drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "sdma0/sdma0_4_2_offset.h"
  34 #include "sdma0/sdma0_4_2_sh_mask.h"
  35 #include "sdma1/sdma1_4_2_offset.h"
  36 #include "sdma1/sdma1_4_2_sh_mask.h"
  37 #include "sdma2/sdma2_4_2_2_offset.h"
  38 #include "sdma2/sdma2_4_2_2_sh_mask.h"
  39 #include "sdma3/sdma3_4_2_2_offset.h"
  40 #include "sdma3/sdma3_4_2_2_sh_mask.h"
  41 #include "sdma4/sdma4_4_2_2_offset.h"
  42 #include "sdma4/sdma4_4_2_2_sh_mask.h"
  43 #include "sdma5/sdma5_4_2_2_offset.h"
  44 #include "sdma5/sdma5_4_2_2_sh_mask.h"
  45 #include "sdma6/sdma6_4_2_2_offset.h"
  46 #include "sdma6/sdma6_4_2_2_sh_mask.h"
  47 #include "sdma7/sdma7_4_2_2_offset.h"
  48 #include "sdma7/sdma7_4_2_2_sh_mask.h"
  49 #include "sdma0/sdma0_4_1_default.h"
  50
  51 #include "soc15_common.h"
  52 #include "soc15.h"
  53 #include "vega10_sdma_pkt_open.h"
  54
  55 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
  56 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
  57
  58 #include "amdgpu_ras.h"
  59
  60 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
  61 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
  62 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
  63 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
  64 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
  65 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
  66 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
  67 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
  68 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
  69 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
  70 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
  71 MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin");
  72 MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin");
  73
  74 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
  75 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
  76
  77 #define WREG32_SDMA(instance, offset, value) \
  78         WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
  79 #define RREG32_SDMA(instance, offset) \
  80         RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
  81
  82 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
  83 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
  84 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  85 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  86 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev);
  87
  88 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
  89         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
  90         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
  91         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
  92         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  93         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
  94         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  95         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
  96         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
  97         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  98         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
  99         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 100         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 101         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
 102         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
 103         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
 104         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 105         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
 106         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 107         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
 108         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
 109         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 110         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
 111         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 112         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 113         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
 114 };
 115
 116 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
 117         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 118         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 119         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 120         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 121         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 122         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 123         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 124 };
 125
 126 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
 127         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
 128         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
 129         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 130         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 131         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
 132         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
 133         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 134 };
 135
 136 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
 137         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 138         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 139         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
 140         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 141         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
 142         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
 143         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 144         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
 145         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 146         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 147         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
 148 };
 149
 150 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
 151         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 152 };
 153
 154 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
 155 {
 156         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 157         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 158         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 159         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 160         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 161         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 162         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 163         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 164         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
 165         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 166         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 167         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 168         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 169         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 170         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 171         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 172         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 173         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 174         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 175         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 176         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 177         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 178         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 179         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 180         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 181         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 182         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 183 };
 184
 185 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
 186         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 187         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
 188         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 189         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 190         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 191         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 192         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 193         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 194         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
 195         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 196         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 197         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 198         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 199         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 200         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 201         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 202         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 203         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 204         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 205         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 206         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 207         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 208         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 209         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 210         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 211         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 212         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 213 };
 214
 215 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
 216 {
 217         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
 218         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
 219 };
 220
 221 static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
 222 {
 223         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
 224         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
 225 };
 226
 227 static const struct soc15_reg_golden golden_settings_sdma_arct[] =
 228 {
 229         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 230         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 231         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 232         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 233         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 234         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 235         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 236         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 237         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 238         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 239         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 240         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 241         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 242         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 243         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 244         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 245         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 246         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 247         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 248         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 249         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 250         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 251         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 252         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 253         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 254         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 255         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 256         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 257         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 258         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 259         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 260         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001)
 261 };
 262
 263 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
 264         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 265         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 266         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
 267         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
 268         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 269         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
 270         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 271         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 272         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 273         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe)
 274 };
 275
 276 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = {
 277         { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 278         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED),
 279         0, 0,
 280         },
 281         { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 282         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED),
 283         0, 0,
 284         },
 285         { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 286         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED),
 287         0, 0,
 288         },
 289         { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 290         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED),
 291         0, 0,
 292         },
 293         { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 294         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED),
 295         0, 0,
 296         },
 297         { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 298         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED),
 299         0, 0,
 300         },
 301         { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 302         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED),
 303         0, 0,
 304         },
 305         { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 306         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED),
 307         0, 0,
 308         },
 309         { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 310         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED),
 311         0, 0,
 312         },
 313         { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 314         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED),
 315         0, 0,
 316         },
 317         { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 318         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED),
 319         0, 0,
 320         },
 321         { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 322         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED),
 323         0, 0,
 324         },
 325         { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 326         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED),
 327         0, 0,
 328         },
 329         { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 330         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED),
 331         0, 0,
 332         },
 333         { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 334         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED),
 335         0, 0,
 336         },
 337         { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 338         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED),
 339         0, 0,
 340         },
 341         { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 342         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED),
 343         0, 0,
 344         },
 345         { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 346         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED),
 347         0, 0,
 348         },
 349         { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 350         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED),
 351         0, 0,
 352         },
 353         { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 354         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED),
 355         0, 0,
 356         },
 357         { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 358         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED),
 359         0, 0,
 360         },
 361         { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 362         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED),
 363         0, 0,
 364         },
 365         { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 366         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED),
 367         0, 0,
 368         },
 369         { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 370         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED),
 371         0, 0,
 372         },
 373 };
 374
 375 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
 376                 u32 instance, u32 offset)
 377 {
 378         switch (instance) {
 379         case 0:
 380                 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
 381         case 1:
 382                 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
 383         case 2:
 384                 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
 385         case 3:
 386                 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
 387         case 4:
 388                 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
 389         case 5:
 390                 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
 391         case 6:
 392                 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
 393         case 7:
 394                 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
 395         default:
 396                 break;
 397         }
 398         return 0;
 399 }
 400
 401 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
 402 {
 403         switch (seq_num) {
 404         case 0:
 405                 return SOC15_IH_CLIENTID_SDMA0;
 406         case 1:
 407                 return SOC15_IH_CLIENTID_SDMA1;
 408         case 2:
 409                 return SOC15_IH_CLIENTID_SDMA2;
 410         case 3:
 411                 return SOC15_IH_CLIENTID_SDMA3;
 412         case 4:
 413                 return SOC15_IH_CLIENTID_SDMA4;
 414         case 5:
 415                 return SOC15_IH_CLIENTID_SDMA5;
 416         case 6:
 417                 return SOC15_IH_CLIENTID_SDMA6;
 418         case 7:
 419                 return SOC15_IH_CLIENTID_SDMA7;
 420         default:
 421                 break;
 422         }
 423         return -EINVAL;
 424 }
 425
 426 static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
 427 {
 428         switch (client_id) {
 429         case SOC15_IH_CLIENTID_SDMA0:
 430                 return 0;
 431         case SOC15_IH_CLIENTID_SDMA1:
 432                 return 1;
 433         case SOC15_IH_CLIENTID_SDMA2:
 434                 return 2;
 435         case SOC15_IH_CLIENTID_SDMA3:
 436                 return 3;
 437         case SOC15_IH_CLIENTID_SDMA4:
 438                 return 4;
 439         case SOC15_IH_CLIENTID_SDMA5:
 440                 return 5;
 441         case SOC15_IH_CLIENTID_SDMA6:
 442                 return 6;
 443         case SOC15_IH_CLIENTID_SDMA7:
 444                 return 7;
 445         default:
 446                 break;
 447         }
 448         return -EINVAL;
 449 }
 450
 451 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 452 {
 453         switch (adev->asic_type) {
 454         case CHIP_VEGA10:
 455                 soc15_program_register_sequence(adev,
 456                                                 golden_settings_sdma_4,
 457                                                 ARRAY_SIZE(golden_settings_sdma_4));
 458                 soc15_program_register_sequence(adev,
 459                                                 golden_settings_sdma_vg10,
 460                                                 ARRAY_SIZE(golden_settings_sdma_vg10));
 461                 break;
 462         case CHIP_VEGA12:
 463                 soc15_program_register_sequence(adev,
 464                                                 golden_settings_sdma_4,
 465                                                 ARRAY_SIZE(golden_settings_sdma_4));
 466                 soc15_program_register_sequence(adev,
 467                                                 golden_settings_sdma_vg12,
 468                                                 ARRAY_SIZE(golden_settings_sdma_vg12));
 469                 break;
 470         case CHIP_VEGA20:
 471                 soc15_program_register_sequence(adev,
 472                                                 golden_settings_sdma0_4_2_init,
 473                                                 ARRAY_SIZE(golden_settings_sdma0_4_2_init));
 474                 soc15_program_register_sequence(adev,
 475                                                 golden_settings_sdma0_4_2,
 476                                                 ARRAY_SIZE(golden_settings_sdma0_4_2));
 477                 soc15_program_register_sequence(adev,
 478                                                 golden_settings_sdma1_4_2,
 479                                                 ARRAY_SIZE(golden_settings_sdma1_4_2));
 480                 break;
 481         case CHIP_ARCTURUS:
 482                 soc15_program_register_sequence(adev,
 483                                                 golden_settings_sdma_arct,
 484                                                 ARRAY_SIZE(golden_settings_sdma_arct));
 485                 break;
 486         case CHIP_RAVEN:
 487                 soc15_program_register_sequence(adev,
 488                                                 golden_settings_sdma_4_1,
 489                                                 ARRAY_SIZE(golden_settings_sdma_4_1));
 490                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
 491                         soc15_program_register_sequence(adev,
 492                                                         golden_settings_sdma_rv2,
 493                                                         ARRAY_SIZE(golden_settings_sdma_rv2));
 494                 else
 495                         soc15_program_register_sequence(adev,
 496                                                         golden_settings_sdma_rv1,
 497                                                         ARRAY_SIZE(golden_settings_sdma_rv1));
 498                 break;
 499         case CHIP_RENOIR:
 500                 soc15_program_register_sequence(adev,
 501                                                 golden_settings_sdma_4_3,
 502                                                 ARRAY_SIZE(golden_settings_sdma_4_3));
 503                 break;
 504         default:
 505                 break;
 506         }
 507 }
 508
 509 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
 510 {
 511         int i;
 512
 513         /*
 514          * The only chips with SDMAv4 and ULV are VG10 and VG20.
 515          * Server SKUs take a different hysteresis setting from other SKUs.
 516          */
 517         switch (adev->asic_type) {
 518         case CHIP_VEGA10:
 519                 if (adev->pdev->device == 0x6860)
 520                         break;
 521                 return;
 522         case CHIP_VEGA20:
 523                 if (adev->pdev->device == 0x66a1)
 524                         break;
 525                 return;
 526         default:
 527                 return;
 528         }
 529
 530         for (i = 0; i < adev->sdma.num_instances; i++) {
 531                 uint32_t temp;
 532
 533                 temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL);
 534                 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0);
 535                 WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp);
 536         }
 537 }
 538
 539 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
 540 {
 541         int err = 0;
 542         const struct sdma_firmware_header_v1_0 *hdr;
 543
 544         err = amdgpu_ucode_validate(sdma_inst->fw);
 545         if (err)
 546                 return err;
 547
 548         hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
 549         sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
 550         sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
 551
 552         if (sdma_inst->feature_version >= 20)
 553                 sdma_inst->burst_nop = true;
 554
 555         return 0;
 556 }
 557
 558 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
 559 {
 560         int i;
 561
 562         for (i = 0; i < adev->sdma.num_instances; i++) {
 563                 release_firmware(adev->sdma.instance[i].fw);
 564                 adev->sdma.instance[i].fw = NULL;
 565
 566                 /* arcturus shares the same FW memory across
 567                    all SDMA isntances */
 568                 if (adev->asic_type == CHIP_ARCTURUS ||
 569                     adev->asic_type == CHIP_ALDEBARAN)
 570                         break;
 571         }
 572
 573         memset((void *)adev->sdma.instance, 0,
 574                 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 575 }
 576
 577 /**
 578  * sdma_v4_0_init_microcode - load ucode images from disk
 579  *
 580  * @adev: amdgpu_device pointer
 581  *
 582  * Use the firmware interface to load the ucode images into
 583  * the driver (not loaded into hw).
 584  * Returns 0 on success, error on failure.
 585  */
 586
 587 // emulation only, won't work on real chip
 588 // vega10 real chip need to use PSP to load firmware
 589 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 590 {
 591         const char *chip_name;
 592         char fw_name[30];
 593         int err = 0, i;
 594         struct amdgpu_firmware_info *info = NULL;
 595         const struct common_firmware_header *header = NULL;
 596
 597         DRM_DEBUG("\n");
 598
 599         switch (adev->asic_type) {
 600         case CHIP_VEGA10:
 601                 chip_name = "vega10";
 602                 break;
 603         case CHIP_VEGA12:
 604                 chip_name = "vega12";
 605                 break;
 606         case CHIP_VEGA20:
 607                 chip_name = "vega20";
 608                 break;
 609         case CHIP_RAVEN:
 610                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
 611                         chip_name = "raven2";
 612                 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
 613                         chip_name = "picasso";
 614                 else
 615                         chip_name = "raven";
 616                 break;
 617         case CHIP_ARCTURUS:
 618                 chip_name = "arcturus";
 619                 break;
 620         case CHIP_RENOIR:
 621                 if (adev->apu_flags & AMD_APU_IS_RENOIR)
 622                         chip_name = "renoir";
 623                 else
 624                         chip_name = "green_sardine";
 625                 break;
 626         case CHIP_ALDEBARAN:
 627                 chip_name = "aldebaran";
 628                 break;
 629         default:
 630                 BUG();
 631         }
 632
 633         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 634
 635         err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
 636         if (err)
 637                 goto out;
 638
 639         err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]);
 640         if (err)
 641                 goto out;
 642
 643         for (i = 1; i < adev->sdma.num_instances; i++) {
 644                 if (adev->asic_type == CHIP_ARCTURUS ||
 645                     adev->asic_type == CHIP_ALDEBARAN) {
 646                         /* Acturus & Aldebaran will leverage the same FW memory
 647                            for every SDMA instance */
 648                         memcpy((void *)&adev->sdma.instance[i],
 649                                (void *)&adev->sdma.instance[0],
 650                                sizeof(struct amdgpu_sdma_instance));
 651                 }
 652                 else {
 653                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
 654
 655                         err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 656                         if (err)
 657                                 goto out;
 658
 659                         err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]);
 660                         if (err)
 661                                 goto out;
 662                 }
 663         }
 664
 665         DRM_DEBUG("psp_load == '%s'\n",
 666                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 667
 668         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 669                 for (i = 0; i < adev->sdma.num_instances; i++) {
 670                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 671                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 672                         info->fw = adev->sdma.instance[i].fw;
 673                         header = (const struct common_firmware_header *)info->fw->data;
 674                         adev->firmware.fw_size +=
 675                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 676                 }
 677         }
 678
 679 out:
 680         if (err) {
 681                 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
 682                 sdma_v4_0_destroy_inst_ctx(adev);
 683         }
 684         return err;
 685 }
 686
 687 /**
 688  * sdma_v4_0_ring_get_rptr - get the current read pointer
 689  *
 690  * @ring: amdgpu ring pointer
 691  *
 692  * Get the current rptr from the hardware (VEGA10+).
 693  */
 694 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
 695 {
 696         u64 *rptr;
 697
 698         /* XXX check if swapping is necessary on BE */
 699         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 700
 701         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 702         return ((*rptr) >> 2);
 703 }
 704
 705 /**
 706  * sdma_v4_0_ring_get_wptr - get the current write pointer
 707  *
 708  * @ring: amdgpu ring pointer
 709  *
 710  * Get the current wptr from the hardware (VEGA10+).
 711  */
 712 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 713 {
 714         struct amdgpu_device *adev = ring->adev;
 715         u64 wptr;
 716
 717         if (ring->use_doorbell) {
 718                 /* XXX check if swapping is necessary on BE */
 719                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 720                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 721         } else {
 722                 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
 723                 wptr = wptr << 32;
 724                 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
 725                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
 726                                 ring->me, wptr);
 727         }
 728
 729         return wptr >> 2;
 730 }
 731
 732 /**
 733  * sdma_v4_0_page_ring_set_wptr - commit the write pointer
 734  *
 735  * @ring: amdgpu ring pointer
 736  *
 737  * Write the wptr back to the hardware (VEGA10+).
 738  */
 739 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 740 {
 741         struct amdgpu_device *adev = ring->adev;
 742
 743         DRM_DEBUG("Setting write pointer\n");
 744         if (ring->use_doorbell) {
 745                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 746
 747                 DRM_DEBUG("Using doorbell -- "
 748                                 "wptr_offs == 0x%08x "
 749                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 750                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 751                                 ring->wptr_offs,
 752                                 lower_32_bits(ring->wptr << 2),
 753                                 upper_32_bits(ring->wptr << 2));
 754                 /* XXX check if swapping is necessary on BE */
 755                 WRITE_ONCE(*wb, (ring->wptr << 2));
 756                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 757                                 ring->doorbell_index, ring->wptr << 2);
 758                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 759         } else {
 760                 DRM_DEBUG("Not using doorbell -- "
 761                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 762                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 763                                 ring->me,
 764                                 lower_32_bits(ring->wptr << 2),
 765                                 ring->me,
 766                                 upper_32_bits(ring->wptr << 2));
 767                 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
 768                             lower_32_bits(ring->wptr << 2));
 769                 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
 770                             upper_32_bits(ring->wptr << 2));
 771         }
 772 }
 773
 774 /**
 775  * sdma_v4_0_page_ring_get_wptr - get the current write pointer
 776  *
 777  * @ring: amdgpu ring pointer
 778  *
 779  * Get the current wptr from the hardware (VEGA10+).
 780  */
 781 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
 782 {
 783         struct amdgpu_device *adev = ring->adev;
 784         u64 wptr;
 785
 786         if (ring->use_doorbell) {
 787                 /* XXX check if swapping is necessary on BE */
 788                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 789         } else {
 790                 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
 791                 wptr = wptr << 32;
 792                 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
 793         }
 794
 795         return wptr >> 2;
 796 }
 797
 798 /**
 799  * sdma_v4_0_ring_set_wptr - commit the write pointer
 800  *
 801  * @ring: amdgpu ring pointer
 802  *
 803  * Write the wptr back to the hardware (VEGA10+).
 804  */
 805 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
 806 {
 807         struct amdgpu_device *adev = ring->adev;
 808
 809         if (ring->use_doorbell) {
 810                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 811
 812                 /* XXX check if swapping is necessary on BE */
 813                 WRITE_ONCE(*wb, (ring->wptr << 2));
 814                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 815         } else {
 816                 uint64_t wptr = ring->wptr << 2;
 817
 818                 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
 819                             lower_32_bits(wptr));
 820                 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
 821                             upper_32_bits(wptr));
 822         }
 823 }
 824
 825 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 826 {
 827         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 828         int i;
 829
 830         for (i = 0; i < count; i++)
 831                 if (sdma && sdma->burst_nop && (i == 0))
 832                         amdgpu_ring_write(ring, ring->funcs->nop |
 833                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 834                 else
 835                         amdgpu_ring_write(ring, ring->funcs->nop);
 836 }
 837
 838 /**
 839  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
 840  *
 841  * @ring: amdgpu ring pointer
 842  * @job: job to retrieve vmid from
 843  * @ib: IB object to schedule
 844  * @flags: unused
 845  *
 846  * Schedule an IB in the DMA ring (VEGA10).
 847  */
 848 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
 849                                    struct amdgpu_job *job,
 850                                    struct amdgpu_ib *ib,
 851                                    uint32_t flags)
 852 {
 853         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 854
 855         /* IB packet must end on a 8 DW boundary */
 856         sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 857
 858         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 859                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 860         /* base must be 32 byte aligned */
 861         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 862         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 863         amdgpu_ring_write(ring, ib->length_dw);
 864         amdgpu_ring_write(ring, 0);
 865         amdgpu_ring_write(ring, 0);
 866
 867 }
 868
 869 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
 870                                    int mem_space, int hdp,
 871                                    uint32_t addr0, uint32_t addr1,
 872                                    uint32_t ref, uint32_t mask,
 873                                    uint32_t inv)
 874 {
 875         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 876                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
 877                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
 878                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 879         if (mem_space) {
 880                 /* memory */
 881                 amdgpu_ring_write(ring, addr0);
 882                 amdgpu_ring_write(ring, addr1);
 883         } else {
 884                 /* registers */
 885                 amdgpu_ring_write(ring, addr0 << 2);
 886                 amdgpu_ring_write(ring, addr1 << 2);
 887         }
 888         amdgpu_ring_write(ring, ref); /* reference */
 889         amdgpu_ring_write(ring, mask); /* mask */
 890         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 891                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
 892 }
 893
 894 /**
 895  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 896  *
 897  * @ring: amdgpu ring pointer
 898  *
 899  * Emit an hdp flush packet on the requested DMA ring.
 900  */
 901 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 902 {
 903         struct amdgpu_device *adev = ring->adev;
 904         u32 ref_and_mask = 0;
 905         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 906
 907         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 908
 909         sdma_v4_0_wait_reg_mem(ring, 0, 1,
 910                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
 911                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
 912                                ref_and_mask, ref_and_mask, 10);
 913 }
 914
 915 /**
 916  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
 917  *
 918  * @ring: amdgpu ring pointer
 919  * @addr: address
 920  * @seq: sequence number
 921  * @flags: fence related flags
 922  *
 923  * Add a DMA fence packet to the ring to write
 924  * the fence seq number and DMA trap packet to generate
 925  * an interrupt if needed (VEGA10).
 926  */
 927 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 928                                       unsigned flags)
 929 {
 930         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 931         /* write the fence */
 932         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 933         /* zero in first two bits */
 934         BUG_ON(addr & 0x3);
 935         amdgpu_ring_write(ring, lower_32_bits(addr));
 936         amdgpu_ring_write(ring, upper_32_bits(addr));
 937         amdgpu_ring_write(ring, lower_32_bits(seq));
 938
 939         /* optionally write high bits as well */
 940         if (write64bit) {
 941                 addr += 4;
 942                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 943                 /* zero in first two bits */
 944                 BUG_ON(addr & 0x3);
 945                 amdgpu_ring_write(ring, lower_32_bits(addr));
 946                 amdgpu_ring_write(ring, upper_32_bits(addr));
 947                 amdgpu_ring_write(ring, upper_32_bits(seq));
 948         }
 949
 950         /* generate an interrupt */
 951         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 952         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 953 }
 954
 955
 956 /**
 957  * sdma_v4_0_gfx_stop - stop the gfx async dma engines
 958  *
 959  * @adev: amdgpu_device pointer
 960  *
 961  * Stop the gfx async dma ring buffers (VEGA10).
 962  */
 963 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
 964 {
 965         struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
 966         u32 rb_cntl, ib_cntl;
 967         int i, unset = 0;
 968
 969         for (i = 0; i < adev->sdma.num_instances; i++) {
 970                 sdma[i] = &adev->sdma.instance[i].ring;
 971
 972                 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
 973                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 974                         unset = 1;
 975                 }
 976
 977                 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
 978                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 979                 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
 980                 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
 981                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 982                 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
 983         }
 984 }
 985
 986 /**
 987  * sdma_v4_0_rlc_stop - stop the compute async dma engines
 988  *
 989  * @adev: amdgpu_device pointer
 990  *
 991  * Stop the compute async dma queues (VEGA10).
 992  */
 993 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
 994 {
 995         /* XXX todo */
 996 }
 997
 998 /**
 999  * sdma_v4_0_page_stop - stop the page async dma engines
1000  *
1001  * @adev: amdgpu_device pointer
1002  *
1003  * Stop the page async dma ring buffers (VEGA10).
1004  */
1005 static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
1006 {
1007         struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
1008         u32 rb_cntl, ib_cntl;
1009         int i;
1010         bool unset = false;
1011
1012         for (i = 0; i < adev->sdma.num_instances; i++) {
1013                 sdma[i] = &adev->sdma.instance[i].page;
1014
1015                 if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
1016                         (!unset)) {
1017                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1018                         unset = true;
1019                 }
1020
1021                 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1022                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1023                                         RB_ENABLE, 0);
1024                 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1025                 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1026                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
1027                                         IB_ENABLE, 0);
1028                 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1029         }
1030 }
1031
1032 /**
1033  * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch
1034  *
1035  * @adev: amdgpu_device pointer
1036  * @enable: enable/disable the DMA MEs context switch.
1037  *
1038  * Halt or unhalt the async dma engines context switch (VEGA10).
1039  */
1040 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
1041 {
1042         u32 f32_cntl, phase_quantum = 0;
1043         int i;
1044
1045         if (amdgpu_sdma_phase_quantum) {
1046                 unsigned value = amdgpu_sdma_phase_quantum;
1047                 unsigned unit = 0;
1048
1049                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1050                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
1051                         value = (value + 1) >> 1;
1052                         unit++;
1053                 }
1054                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1055                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
1056                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1057                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
1058                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1059                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
1060                         WARN_ONCE(1,
1061                         "clamping sdma_phase_quantum to %uK clock cycles\n",
1062                                   value << unit);
1063                 }
1064                 phase_quantum =
1065                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
1066                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
1067         }
1068
1069         for (i = 0; i < adev->sdma.num_instances; i++) {
1070                 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
1071                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
1072                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
1073                 if (enable && amdgpu_sdma_phase_quantum) {
1074                         WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
1075                         WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
1076                         WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
1077                 }
1078                 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
1079
1080                 /*
1081                  * Enable SDMA utilization. Its only supported on
1082                  * Arcturus for the moment and firmware version 14
1083                  * and above.
1084                  */
1085                 if (adev->asic_type == CHIP_ARCTURUS &&
1086                     adev->sdma.instance[i].fw_version >= 14)
1087                         WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
1088         }
1089
1090 }
1091
1092 /**
1093  * sdma_v4_0_enable - stop the async dma engines
1094  *
1095  * @adev: amdgpu_device pointer
1096  * @enable: enable/disable the DMA MEs.
1097  *
1098  * Halt or unhalt the async dma engines (VEGA10).
1099  */
1100 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
1101 {
1102         u32 f32_cntl;
1103         int i;
1104
1105         if (!enable) {
1106                 sdma_v4_0_gfx_stop(adev);
1107                 sdma_v4_0_rlc_stop(adev);
1108                 if (adev->sdma.has_page_queue)
1109                         sdma_v4_0_page_stop(adev);
1110         }
1111
1112         for (i = 0; i < adev->sdma.num_instances; i++) {
1113                 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1114                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
1115                 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
1116         }
1117 }
1118
1119 /*
1120  * sdma_v4_0_rb_cntl - get parameters for rb_cntl
1121  */
1122 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
1123 {
1124         /* Set ring buffer size in dwords */
1125         uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
1126
1127         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
1128 #ifdef __BIG_ENDIAN
1129         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
1130         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1131                                 RPTR_WRITEBACK_SWAP_ENABLE, 1);
1132 #endif
1133         return rb_cntl;
1134 }
1135
1136 /**
1137  * sdma_v4_0_gfx_resume - setup and start the async dma engines
1138  *
1139  * @adev: amdgpu_device pointer
1140  * @i: instance to resume
1141  *
1142  * Set up the gfx DMA ring buffers and enable them (VEGA10).
1143  * Returns 0 for success, error for failure.
1144  */
1145 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
1146 {
1147         struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
1148         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1149         u32 wb_offset;
1150         u32 doorbell;
1151         u32 doorbell_offset;
1152         u64 wptr_gpu_addr;
1153
1154         wb_offset = (ring->rptr_offs * 4);
1155
1156         rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1157         rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1158         WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1159
1160         /* Initialize the ring buffer's read and write pointers */
1161         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
1162         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
1163         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
1164         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
1165
1166         /* set the wb address whether it's enabled or not */
1167         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
1168                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1169         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
1170                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1171
1172         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1173                                 RPTR_WRITEBACK_ENABLE, 1);
1174
1175         WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
1176         WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
1177
1178         ring->wptr = 0;
1179
1180         /* before programing wptr to a less value, need set minor_ptr_update first */
1181         WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
1182
1183         doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
1184         doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
1185
1186         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
1187                                  ring->use_doorbell);
1188         doorbell_offset = REG_SET_FIELD(doorbell_offset,
1189                                         SDMA0_GFX_DOORBELL_OFFSET,
1190                                         OFFSET, ring->doorbell_index);
1191         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
1192         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
1193
1194         sdma_v4_0_ring_set_wptr(ring);
1195
1196         /* set minor_ptr_update to 0 after wptr programed */
1197         WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
1198
1199         /* setup the wptr shadow polling */
1200         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1201         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
1202                     lower_32_bits(wptr_gpu_addr));
1203         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
1204                     upper_32_bits(wptr_gpu_addr));
1205         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
1206         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1207                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
1208                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1209         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1210
1211         /* enable DMA RB */
1212         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
1213         WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1214
1215         ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1216         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
1217 #ifdef __BIG_ENDIAN
1218         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
1219 #endif
1220         /* enable DMA IBs */
1221         WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1222
1223         ring->sched.ready = true;
1224 }
1225
1226 /**
1227  * sdma_v4_0_page_resume - setup and start the async dma engines
1228  *
1229  * @adev: amdgpu_device pointer
1230  * @i: instance to resume
1231  *
1232  * Set up the page DMA ring buffers and enable them (VEGA10).
1233  * Returns 0 for success, error for failure.
1234  */
1235 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
1236 {
1237         struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
1238         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1239         u32 wb_offset;
1240         u32 doorbell;
1241         u32 doorbell_offset;
1242         u64 wptr_gpu_addr;
1243
1244         wb_offset = (ring->rptr_offs * 4);
1245
1246         rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1247         rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1248         WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1249
1250         /* Initialize the ring buffer's read and write pointers */
1251         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
1252         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
1253         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
1254         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
1255
1256         /* set the wb address whether it's enabled or not */
1257         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
1258                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1259         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
1260                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1261
1262         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1263                                 RPTR_WRITEBACK_ENABLE, 1);
1264
1265         WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
1266         WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
1267
1268         ring->wptr = 0;
1269
1270         /* before programing wptr to a less value, need set minor_ptr_update first */
1271         WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
1272
1273         doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
1274         doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
1275
1276         doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
1277                                  ring->use_doorbell);
1278         doorbell_offset = REG_SET_FIELD(doorbell_offset,
1279                                         SDMA0_PAGE_DOORBELL_OFFSET,
1280                                         OFFSET, ring->doorbell_index);
1281         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
1282         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
1283
1284         /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
1285         sdma_v4_0_page_ring_set_wptr(ring);
1286
1287         /* set minor_ptr_update to 0 after wptr programed */
1288         WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
1289
1290         /* setup the wptr shadow polling */
1291         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1292         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
1293                     lower_32_bits(wptr_gpu_addr));
1294         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
1295                     upper_32_bits(wptr_gpu_addr));
1296         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
1297         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1298                                        SDMA0_PAGE_RB_WPTR_POLL_CNTL,
1299                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1300         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1301
1302         /* enable DMA RB */
1303         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
1304         WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1305
1306         ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1307         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
1308 #ifdef __BIG_ENDIAN
1309         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
1310 #endif
1311         /* enable DMA IBs */
1312         WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1313
1314         ring->sched.ready = true;
1315 }
1316
1317 static void
1318 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
1319 {
1320         uint32_t def, data;
1321
1322         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
1323                 /* enable idle interrupt */
1324                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1325                 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1326
1327                 if (data != def)
1328                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1329         } else {
1330                 /* disable idle interrupt */
1331                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1332                 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1333                 if (data != def)
1334                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1335         }
1336 }
1337
1338 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
1339 {
1340         uint32_t def, data;
1341
1342         /* Enable HW based PG. */
1343         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1344         data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
1345         if (data != def)
1346                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1347
1348         /* enable interrupt */
1349         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1350         data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1351         if (data != def)
1352                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1353
1354         /* Configure hold time to filter in-valid power on/off request. Use default right now */
1355         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1356         data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1357         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1358         /* Configure switch time for hysteresis purpose. Use default right now */
1359         data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1360         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1361         if(data != def)
1362                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1363 }
1364
1365 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1366 {
1367         if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1368                 return;
1369
1370         switch (adev->asic_type) {
1371         case CHIP_RAVEN:
1372         case CHIP_RENOIR:
1373                 sdma_v4_1_init_power_gating(adev);
1374                 sdma_v4_1_update_power_gating(adev, true);
1375                 break;
1376         default:
1377                 break;
1378         }
1379 }
1380
1381 /**
1382  * sdma_v4_0_rlc_resume - setup and start the async dma engines
1383  *
1384  * @adev: amdgpu_device pointer
1385  *
1386  * Set up the compute DMA queues and enable them (VEGA10).
1387  * Returns 0 for success, error for failure.
1388  */
1389 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1390 {
1391         sdma_v4_0_init_pg(adev);
1392
1393         return 0;
1394 }
1395
1396 /**
1397  * sdma_v4_0_load_microcode - load the sDMA ME ucode
1398  *
1399  * @adev: amdgpu_device pointer
1400  *
1401  * Loads the sDMA0/1 ucode.
1402  * Returns 0 for success, -EINVAL if the ucode is not available.
1403  */
1404 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1405 {
1406         const struct sdma_firmware_header_v1_0 *hdr;
1407         const __le32 *fw_data;
1408         u32 fw_size;
1409         int i, j;
1410
1411         /* halt the MEs */
1412         sdma_v4_0_enable(adev, false);
1413
1414         for (i = 0; i < adev->sdma.num_instances; i++) {
1415                 if (!adev->sdma.instance[i].fw)
1416                         return -EINVAL;
1417
1418                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1419                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
1420                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1421
1422                 fw_data = (const __le32 *)
1423                         (adev->sdma.instance[i].fw->data +
1424                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1425
1426                 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1427
1428                 for (j = 0; j < fw_size; j++)
1429                         WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1430                                     le32_to_cpup(fw_data++));
1431
1432                 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1433                             adev->sdma.instance[i].fw_version);
1434         }
1435
1436         return 0;
1437 }
1438
1439 /**
1440  * sdma_v4_0_start - setup and start the async dma engines
1441  *
1442  * @adev: amdgpu_device pointer
1443  *
1444  * Set up the DMA engines and enable them (VEGA10).
1445  * Returns 0 for success, error for failure.
1446  */
1447 static int sdma_v4_0_start(struct amdgpu_device *adev)
1448 {
1449         struct amdgpu_ring *ring;
1450         int i, r = 0;
1451
1452         if (amdgpu_sriov_vf(adev)) {
1453                 sdma_v4_0_ctx_switch_enable(adev, false);
1454                 sdma_v4_0_enable(adev, false);
1455         } else {
1456
1457                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1458                         r = sdma_v4_0_load_microcode(adev);
1459                         if (r)
1460                                 return r;
1461                 }
1462
1463                 /* unhalt the MEs */
1464                 sdma_v4_0_enable(adev, true);
1465                 /* enable sdma ring preemption */
1466                 sdma_v4_0_ctx_switch_enable(adev, true);
1467         }
1468
1469         /* start the gfx rings and rlc compute queues */
1470         for (i = 0; i < adev->sdma.num_instances; i++) {
1471                 uint32_t temp;
1472
1473                 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1474                 sdma_v4_0_gfx_resume(adev, i);
1475                 if (adev->sdma.has_page_queue)
1476                         sdma_v4_0_page_resume(adev, i);
1477
1478                 /* set utc l1 enable flag always to 1 */
1479                 temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1480                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1481                 WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1482
1483                 if (!amdgpu_sriov_vf(adev)) {
1484                         /* unhalt engine */
1485                         temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1486                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1487                         WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1488                 }
1489         }
1490
1491         if (amdgpu_sriov_vf(adev)) {
1492                 sdma_v4_0_ctx_switch_enable(adev, true);
1493                 sdma_v4_0_enable(adev, true);
1494         } else {
1495                 r = sdma_v4_0_rlc_resume(adev);
1496                 if (r)
1497                         return r;
1498         }
1499
1500         for (i = 0; i < adev->sdma.num_instances; i++) {
1501                 ring = &adev->sdma.instance[i].ring;
1502
1503                 r = amdgpu_ring_test_helper(ring);
1504                 if (r)
1505                         return r;
1506
1507                 if (adev->sdma.has_page_queue) {
1508                         struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1509
1510                         r = amdgpu_ring_test_helper(page);
1511                         if (r)
1512                                 return r;
1513
1514                         if (adev->mman.buffer_funcs_ring == page)
1515                                 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1516                 }
1517
1518                 if (adev->mman.buffer_funcs_ring == ring)
1519                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
1520         }
1521
1522         return r;
1523 }
1524
1525 /**
1526  * sdma_v4_0_ring_test_ring - simple async dma engine test
1527  *
1528  * @ring: amdgpu_ring structure holding ring information
1529  *
1530  * Test the DMA engine by writing using it to write an
1531  * value to memory. (VEGA10).
1532  * Returns 0 for success, error for failure.
1533  */
1534 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1535 {
1536         struct amdgpu_device *adev = ring->adev;
1537         unsigned i;
1538         unsigned index;
1539         int r;
1540         u32 tmp;
1541         u64 gpu_addr;
1542
1543         r = amdgpu_device_wb_get(adev, &index);
1544         if (r)
1545                 return r;
1546
1547         gpu_addr = adev->wb.gpu_addr + (index * 4);
1548         tmp = 0xCAFEDEAD;
1549         adev->wb.wb[index] = cpu_to_le32(tmp);
1550
1551         r = amdgpu_ring_alloc(ring, 5);
1552         if (r)
1553                 goto error_free_wb;
1554
1555         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1556                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1557         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1558         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1559         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1560         amdgpu_ring_write(ring, 0xDEADBEEF);
1561         amdgpu_ring_commit(ring);
1562
1563         for (i = 0; i < adev->usec_timeout; i++) {
1564                 tmp = le32_to_cpu(adev->wb.wb[index]);
1565                 if (tmp == 0xDEADBEEF)
1566                         break;
1567                 udelay(1);
1568         }
1569
1570         if (i >= adev->usec_timeout)
1571                 r = -ETIMEDOUT;
1572
1573 error_free_wb:
1574         amdgpu_device_wb_free(adev, index);
1575         return r;
1576 }
1577
1578 /**
1579  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1580  *
1581  * @ring: amdgpu_ring structure holding ring information
1582  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1583  *
1584  * Test a simple IB in the DMA ring (VEGA10).
1585  * Returns 0 on success, error on failure.
1586  */
1587 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1588 {
1589         struct amdgpu_device *adev = ring->adev;
1590         struct amdgpu_ib ib;
1591         struct dma_fence *f = NULL;
1592         unsigned index;
1593         long r;
1594         u32 tmp = 0;
1595         u64 gpu_addr;
1596
1597         r = amdgpu_device_wb_get(adev, &index);
1598         if (r)
1599                 return r;
1600
1601         gpu_addr = adev->wb.gpu_addr + (index * 4);
1602         tmp = 0xCAFEDEAD;
1603         adev->wb.wb[index] = cpu_to_le32(tmp);
1604         memset(&ib, 0, sizeof(ib));
1605         r = amdgpu_ib_get(adev, NULL, 256,
1606                                         AMDGPU_IB_POOL_DIRECT, &ib);
1607         if (r)
1608                 goto err0;
1609
1610         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1611                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1612         ib.ptr[1] = lower_32_bits(gpu_addr);
1613         ib.ptr[2] = upper_32_bits(gpu_addr);
1614         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1615         ib.ptr[4] = 0xDEADBEEF;
1616         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1617         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1618         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1619         ib.length_dw = 8;
1620
1621         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1622         if (r)
1623                 goto err1;
1624
1625         r = dma_fence_wait_timeout(f, false, timeout);
1626         if (r == 0) {
1627                 r = -ETIMEDOUT;
1628                 goto err1;
1629         } else if (r < 0) {
1630                 goto err1;
1631         }
1632         tmp = le32_to_cpu(adev->wb.wb[index]);
1633         if (tmp == 0xDEADBEEF)
1634                 r = 0;
1635         else
1636                 r = -EINVAL;
1637
1638 err1:
1639         amdgpu_ib_free(adev, &ib, NULL);
1640         dma_fence_put(f);
1641 err0:
1642         amdgpu_device_wb_free(adev, index);
1643         return r;
1644 }
1645
1646
1647 /**
1648  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1649  *
1650  * @ib: indirect buffer to fill with commands
1651  * @pe: addr of the page entry
1652  * @src: src addr to copy from
1653  * @count: number of page entries to update
1654  *
1655  * Update PTEs by copying them from the GART using sDMA (VEGA10).
1656  */
1657 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1658                                   uint64_t pe, uint64_t src,
1659                                   unsigned count)
1660 {
1661         unsigned bytes = count * 8;
1662
1663         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1664                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1665         ib->ptr[ib->length_dw++] = bytes - 1;
1666         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1667         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1668         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1669         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1670         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1671
1672 }
1673
1674 /**
1675  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1676  *
1677  * @ib: indirect buffer to fill with commands
1678  * @pe: addr of the page entry
1679  * @value: dst addr to write into pe
1680  * @count: number of page entries to update
1681  * @incr: increase next addr by incr bytes
1682  *
1683  * Update PTEs by writing them manually using sDMA (VEGA10).
1684  */
1685 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1686                                    uint64_t value, unsigned count,
1687                                    uint32_t incr)
1688 {
1689         unsigned ndw = count * 2;
1690
1691         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1692                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1693         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1694         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1695         ib->ptr[ib->length_dw++] = ndw - 1;
1696         for (; ndw > 0; ndw -= 2) {
1697                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1698                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1699                 value += incr;
1700         }
1701 }
1702
1703 /**
1704  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1705  *
1706  * @ib: indirect buffer to fill with commands
1707  * @pe: addr of the page entry
1708  * @addr: dst addr to write into pe
1709  * @count: number of page entries to update
1710  * @incr: increase next addr by incr bytes
1711  * @flags: access flags
1712  *
1713  * Update the page tables using sDMA (VEGA10).
1714  */
1715 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1716                                      uint64_t pe,
1717                                      uint64_t addr, unsigned count,
1718                                      uint32_t incr, uint64_t flags)
1719 {
1720         /* for physically contiguous pages (vram) */
1721         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1722         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1723         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1724         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1725         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1726         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1727         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1728         ib->ptr[ib->length_dw++] = incr; /* increment size */
1729         ib->ptr[ib->length_dw++] = 0;
1730         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1731 }
1732
1733 /**
1734  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1735  *
1736  * @ring: amdgpu_ring structure holding ring information
1737  * @ib: indirect buffer to fill with padding
1738  */
1739 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1740 {
1741         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1742         u32 pad_count;
1743         int i;
1744
1745         pad_count = (-ib->length_dw) & 7;
1746         for (i = 0; i < pad_count; i++)
1747                 if (sdma && sdma->burst_nop && (i == 0))
1748                         ib->ptr[ib->length_dw++] =
1749                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1750                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1751                 else
1752                         ib->ptr[ib->length_dw++] =
1753                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1754 }
1755
1756
1757 /**
1758  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1759  *
1760  * @ring: amdgpu_ring pointer
1761  *
1762  * Make sure all previous operations are completed (CIK).
1763  */
1764 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1765 {
1766         uint32_t seq = ring->fence_drv.sync_seq;
1767         uint64_t addr = ring->fence_drv.gpu_addr;
1768
1769         /* wait for idle */
1770         sdma_v4_0_wait_reg_mem(ring, 1, 0,
1771                                addr & 0xfffffffc,
1772                                upper_32_bits(addr) & 0xffffffff,
1773                                seq, 0xffffffff, 4);
1774 }
1775
1776
1777 /**
1778  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1779  *
1780  * @ring: amdgpu_ring pointer
1781  * @vmid: vmid number to use
1782  * @pd_addr: address
1783  *
1784  * Update the page table base and flush the VM TLB
1785  * using sDMA (VEGA10).
1786  */
1787 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1788                                          unsigned vmid, uint64_t pd_addr)
1789 {
1790         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1791 }
1792
1793 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1794                                      uint32_t reg, uint32_t val)
1795 {
1796         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1797                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1798         amdgpu_ring_write(ring, reg);
1799         amdgpu_ring_write(ring, val);
1800 }
1801
1802 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1803                                          uint32_t val, uint32_t mask)
1804 {
1805         sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1806 }
1807
1808 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
1809 {
1810         uint fw_version = adev->sdma.instance[0].fw_version;
1811
1812         switch (adev->asic_type) {
1813         case CHIP_VEGA10:
1814                 return fw_version >= 430;
1815         case CHIP_VEGA12:
1816                 /*return fw_version >= 31;*/
1817                 return false;
1818         case CHIP_VEGA20:
1819                 return fw_version >= 123;
1820         default:
1821                 return false;
1822         }
1823 }
1824
1825 static int sdma_v4_0_early_init(void *handle)
1826 {
1827         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1828         int r;
1829
1830         if (adev->flags & AMD_IS_APU)
1831                 adev->sdma.num_instances = 1;
1832         else if (adev->asic_type == CHIP_ARCTURUS)
1833                 adev->sdma.num_instances = 8;
1834         else if (adev->asic_type == CHIP_ALDEBARAN)
1835                 adev->sdma.num_instances = 5;
1836         else
1837                 adev->sdma.num_instances = 2;
1838
1839         r = sdma_v4_0_init_microcode(adev);
1840         if (r) {
1841                 DRM_ERROR("Failed to load sdma firmware!\n");
1842                 return r;
1843         }
1844
1845         /* TODO: Page queue breaks driver reload under SRIOV */
1846         if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev)))
1847                 adev->sdma.has_page_queue = false;
1848         else if (sdma_v4_0_fw_support_paging_queue(adev))
1849                 adev->sdma.has_page_queue = true;
1850
1851         sdma_v4_0_set_ring_funcs(adev);
1852         sdma_v4_0_set_buffer_funcs(adev);
1853         sdma_v4_0_set_vm_pte_funcs(adev);
1854         sdma_v4_0_set_irq_funcs(adev);
1855         sdma_v4_0_set_ras_funcs(adev);
1856
1857         return 0;
1858 }
1859
1860 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1861                 void *err_data,
1862                 struct amdgpu_iv_entry *entry);
1863
1864 static int sdma_v4_0_late_init(void *handle)
1865 {
1866         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1867         struct ras_ih_if ih_info = {
1868                 .cb = sdma_v4_0_process_ras_data_cb,
1869         };
1870
1871         sdma_v4_0_setup_ulv(adev);
1872
1873         if (adev->sdma.funcs && adev->sdma.funcs->reset_ras_error_count)
1874                 adev->sdma.funcs->reset_ras_error_count(adev);
1875
1876         if (adev->sdma.funcs && adev->sdma.funcs->ras_late_init)
1877                 return adev->sdma.funcs->ras_late_init(adev, &ih_info);
1878         else
1879                 return 0;
1880 }
1881
1882 static int sdma_v4_0_sw_init(void *handle)
1883 {
1884         struct amdgpu_ring *ring;
1885         int r, i;
1886         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1887
1888         /* SDMA trap event */
1889         for (i = 0; i < adev->sdma.num_instances; i++) {
1890                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1891                                       SDMA0_4_0__SRCID__SDMA_TRAP,
1892                                       &adev->sdma.trap_irq);
1893                 if (r)
1894                         return r;
1895         }
1896
1897         /* SDMA SRAM ECC event */
1898         for (i = 0; i < adev->sdma.num_instances; i++) {
1899                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1900                                       SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1901                                       &adev->sdma.ecc_irq);
1902                 if (r)
1903                         return r;
1904         }
1905
1906         /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1907         for (i = 0; i < adev->sdma.num_instances; i++) {
1908                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1909                                       SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1910                                       &adev->sdma.vm_hole_irq);
1911                 if (r)
1912                         return r;
1913
1914                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1915                                       SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1916                                       &adev->sdma.doorbell_invalid_irq);
1917                 if (r)
1918                         return r;
1919
1920                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1921                                       SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1922                                       &adev->sdma.pool_timeout_irq);
1923                 if (r)
1924                         return r;
1925
1926                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1927                                       SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1928                                       &adev->sdma.srbm_write_irq);
1929                 if (r)
1930                         return r;
1931         }
1932
1933         for (i = 0; i < adev->sdma.num_instances; i++) {
1934                 ring = &adev->sdma.instance[i].ring;
1935                 ring->ring_obj = NULL;
1936                 ring->use_doorbell = true;
1937
1938                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1939                                 ring->use_doorbell?"true":"false");
1940
1941                 /* doorbell size is 2 dwords, get DWORD offset */
1942                 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1943
1944                 sprintf(ring->name, "sdma%d", i);
1945                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1946                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1947                                      AMDGPU_RING_PRIO_DEFAULT);
1948                 if (r)
1949                         return r;
1950
1951                 if (adev->sdma.has_page_queue) {
1952                         ring = &adev->sdma.instance[i].page;
1953                         ring->ring_obj = NULL;
1954                         ring->use_doorbell = true;
1955
1956                         /* paging queue use same doorbell index/routing as gfx queue
1957                          * with 0x400 (4096 dwords) offset on second doorbell page
1958                          */
1959                         ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1960                         ring->doorbell_index += 0x400;
1961
1962                         sprintf(ring->name, "page%d", i);
1963                         r = amdgpu_ring_init(adev, ring, 1024,
1964                                              &adev->sdma.trap_irq,
1965                                              AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1966                                              AMDGPU_RING_PRIO_DEFAULT);
1967                         if (r)
1968                                 return r;
1969                 }
1970         }
1971
1972         return r;
1973 }
1974
1975 static int sdma_v4_0_sw_fini(void *handle)
1976 {
1977         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1978         int i;
1979
1980         if (adev->sdma.funcs && adev->sdma.funcs->ras_fini)
1981                 adev->sdma.funcs->ras_fini(adev);
1982
1983         for (i = 0; i < adev->sdma.num_instances; i++) {
1984                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1985                 if (adev->sdma.has_page_queue)
1986                         amdgpu_ring_fini(&adev->sdma.instance[i].page);
1987         }
1988
1989         sdma_v4_0_destroy_inst_ctx(adev);
1990
1991         return 0;
1992 }
1993
1994 static int sdma_v4_0_hw_init(void *handle)
1995 {
1996         int r;
1997         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1998
1999         if (adev->flags & AMD_IS_APU)
2000                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
2001
2002         if (!amdgpu_sriov_vf(adev))
2003                 sdma_v4_0_init_golden_registers(adev);
2004
2005         r = sdma_v4_0_start(adev);
2006
2007         return r;
2008 }
2009
2010 static int sdma_v4_0_hw_fini(void *handle)
2011 {
2012         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2013         int i;
2014
2015         if (amdgpu_sriov_vf(adev))
2016                 return 0;
2017
2018         for (i = 0; i < adev->sdma.num_instances; i++) {
2019                 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2020                                AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2021         }
2022
2023         sdma_v4_0_ctx_switch_enable(adev, false);
2024         sdma_v4_0_enable(adev, false);
2025
2026         if (adev->flags & AMD_IS_APU)
2027                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
2028
2029         return 0;
2030 }
2031
2032 static int sdma_v4_0_suspend(void *handle)
2033 {
2034         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2035
2036         return sdma_v4_0_hw_fini(adev);
2037 }
2038
2039 static int sdma_v4_0_resume(void *handle)
2040 {
2041         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2042
2043         return sdma_v4_0_hw_init(adev);
2044 }
2045
2046 static bool sdma_v4_0_is_idle(void *handle)
2047 {
2048         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2049         u32 i;
2050
2051         for (i = 0; i < adev->sdma.num_instances; i++) {
2052                 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
2053
2054                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
2055                         return false;
2056         }
2057
2058         return true;
2059 }
2060
2061 static int sdma_v4_0_wait_for_idle(void *handle)
2062 {
2063         unsigned i, j;
2064         u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
2065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2066
2067         for (i = 0; i < adev->usec_timeout; i++) {
2068                 for (j = 0; j < adev->sdma.num_instances; j++) {
2069                         sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
2070                         if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK))
2071                                 break;
2072                 }
2073                 if (j == adev->sdma.num_instances)
2074                         return 0;
2075                 udelay(1);
2076         }
2077         return -ETIMEDOUT;
2078 }
2079
2080 static int sdma_v4_0_soft_reset(void *handle)
2081 {
2082         /* todo */
2083
2084         return 0;
2085 }
2086
2087 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
2088                                         struct amdgpu_irq_src *source,
2089                                         unsigned type,
2090                                         enum amdgpu_interrupt_state state)
2091 {
2092         u32 sdma_cntl;
2093
2094         sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);
2095         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
2096                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2097         WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
2098
2099         return 0;
2100 }
2101
2102 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
2103                                       struct amdgpu_irq_src *source,
2104                                       struct amdgpu_iv_entry *entry)
2105 {
2106         uint32_t instance;
2107
2108         DRM_DEBUG("IH: SDMA trap\n");
2109         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2110         switch (entry->ring_id) {
2111         case 0:
2112                 amdgpu_fence_process(&adev->sdma.instance[instance].ring);
2113                 break;
2114         case 1:
2115                 if (adev->asic_type == CHIP_VEGA20)
2116                         amdgpu_fence_process(&adev->sdma.instance[instance].page);
2117                 break;
2118         case 2:
2119                 /* XXX compute */
2120                 break;
2121         case 3:
2122                 if (adev->asic_type != CHIP_VEGA20)
2123                         amdgpu_fence_process(&adev->sdma.instance[instance].page);
2124                 break;
2125         }
2126         return 0;
2127 }
2128
2129 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
2130                 void *err_data,
2131                 struct amdgpu_iv_entry *entry)
2132 {
2133         int instance;
2134
2135         /* When “Full RAS” is enabled, the per-IP interrupt sources should
2136          * be disabled and the driver should only look for the aggregated
2137          * interrupt via sync flood
2138          */
2139         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
2140                 goto out;
2141
2142         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2143         if (instance < 0)
2144                 goto out;
2145
2146         amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
2147
2148 out:
2149         return AMDGPU_RAS_SUCCESS;
2150 }
2151
2152 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
2153                                               struct amdgpu_irq_src *source,
2154                                               struct amdgpu_iv_entry *entry)
2155 {
2156         int instance;
2157
2158         DRM_ERROR("Illegal instruction in SDMA command stream\n");
2159
2160         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2161         if (instance < 0)
2162                 return 0;
2163
2164         switch (entry->ring_id) {
2165         case 0:
2166                 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
2167                 break;
2168         }
2169         return 0;
2170 }
2171
2172 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
2173                                         struct amdgpu_irq_src *source,
2174                                         unsigned type,
2175                                         enum amdgpu_interrupt_state state)
2176 {
2177         u32 sdma_edc_config;
2178
2179         sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);
2180         sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
2181                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2182         WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
2183
2184         return 0;
2185 }
2186
2187 static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev,
2188                                               struct amdgpu_iv_entry *entry)
2189 {
2190         int instance;
2191         struct amdgpu_task_info task_info;
2192         u64 addr;
2193
2194         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2195         if (instance < 0 || instance >= adev->sdma.num_instances) {
2196                 dev_err(adev->dev, "sdma instance invalid %d\n", instance);
2197                 return -EINVAL;
2198         }
2199
2200         addr = (u64)entry->src_data[0] << 12;
2201         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
2202
2203         memset(&task_info, 0, sizeof(struct amdgpu_task_info));
2204         amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
2205
2206         dev_info(adev->dev,
2207                    "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
2208                    "pasid:%u, for process %s pid %d thread %s pid %d\n",
2209                    instance, addr, entry->src_id, entry->ring_id, entry->vmid,
2210                    entry->pasid, task_info.process_name, task_info.tgid,
2211                    task_info.task_name, task_info.pid);
2212         return 0;
2213 }
2214
2215 static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev,
2216                                               struct amdgpu_irq_src *source,
2217                                               struct amdgpu_iv_entry *entry)
2218 {
2219         dev_err(adev->dev, "MC or SEM address in VM hole\n");
2220         sdma_v4_0_print_iv_entry(adev, entry);
2221         return 0;
2222 }
2223
2224 static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev,
2225                                               struct amdgpu_irq_src *source,
2226                                               struct amdgpu_iv_entry *entry)
2227 {
2228         dev_err(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
2229         sdma_v4_0_print_iv_entry(adev, entry);
2230         return 0;
2231 }
2232
2233 static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev,
2234                                               struct amdgpu_irq_src *source,
2235                                               struct amdgpu_iv_entry *entry)
2236 {
2237         dev_err(adev->dev,
2238                 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
2239         sdma_v4_0_print_iv_entry(adev, entry);
2240         return 0;
2241 }
2242
2243 static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev,
2244                                               struct amdgpu_irq_src *source,
2245                                               struct amdgpu_iv_entry *entry)
2246 {
2247         dev_err(adev->dev,
2248                 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
2249         sdma_v4_0_print_iv_entry(adev, entry);
2250         return 0;
2251 }
2252
2253 static void sdma_v4_0_update_medium_grain_clock_gating(
2254                 struct amdgpu_device *adev,
2255                 bool enable)
2256 {
2257         uint32_t data, def;
2258         int i;
2259
2260         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
2261                 for (i = 0; i < adev->sdma.num_instances; i++) {
2262                         def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2263                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2264                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2265                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2266                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2267                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2268                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2269                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2270                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2271                         if (def != data)
2272                                 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2273                 }
2274         } else {
2275                 for (i = 0; i < adev->sdma.num_instances; i++) {
2276                         def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2277                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2278                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2279                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2280                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2281                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2282                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2283                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2284                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2285                         if (def != data)
2286                                 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2287                 }
2288         }
2289 }
2290
2291
2292 static void sdma_v4_0_update_medium_grain_light_sleep(
2293                 struct amdgpu_device *adev,
2294                 bool enable)
2295 {
2296         uint32_t data, def;
2297         int i;
2298
2299         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
2300                 for (i = 0; i < adev->sdma.num_instances; i++) {
2301                         /* 1-not override: enable sdma mem light sleep */
2302                         def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2303                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2304                         if (def != data)
2305                                 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2306                 }
2307         } else {
2308                 for (i = 0; i < adev->sdma.num_instances; i++) {
2309                 /* 0-override:disable sdma mem light sleep */
2310                         def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2311                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2312                         if (def != data)
2313                                 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2314                 }
2315         }
2316 }
2317
2318 static int sdma_v4_0_set_clockgating_state(void *handle,
2319                                           enum amd_clockgating_state state)
2320 {
2321         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2322
2323         if (amdgpu_sriov_vf(adev))
2324                 return 0;
2325
2326         sdma_v4_0_update_medium_grain_clock_gating(adev,
2327                         state == AMD_CG_STATE_GATE);
2328         sdma_v4_0_update_medium_grain_light_sleep(adev,
2329                         state == AMD_CG_STATE_GATE);
2330         return 0;
2331 }
2332
2333 static int sdma_v4_0_set_powergating_state(void *handle,
2334                                           enum amd_powergating_state state)
2335 {
2336         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2337
2338         switch (adev->asic_type) {
2339         case CHIP_RAVEN:
2340         case CHIP_RENOIR:
2341                 sdma_v4_1_update_power_gating(adev,
2342                                 state == AMD_PG_STATE_GATE);
2343                 break;
2344         default:
2345                 break;
2346         }
2347
2348         return 0;
2349 }
2350
2351 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
2352 {
2353         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2354         int data;
2355
2356         if (amdgpu_sriov_vf(adev))
2357                 *flags = 0;
2358
2359         /* AMD_CG_SUPPORT_SDMA_MGCG */
2360         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
2361         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
2362                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2363
2364         /* AMD_CG_SUPPORT_SDMA_LS */
2365         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2366         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2367                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
2368 }
2369
2370 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
2371         .name = "sdma_v4_0",
2372         .early_init = sdma_v4_0_early_init,
2373         .late_init = sdma_v4_0_late_init,
2374         .sw_init = sdma_v4_0_sw_init,
2375         .sw_fini = sdma_v4_0_sw_fini,
2376         .hw_init = sdma_v4_0_hw_init,
2377         .hw_fini = sdma_v4_0_hw_fini,
2378         .suspend = sdma_v4_0_suspend,
2379         .resume = sdma_v4_0_resume,
2380         .is_idle = sdma_v4_0_is_idle,
2381         .wait_for_idle = sdma_v4_0_wait_for_idle,
2382         .soft_reset = sdma_v4_0_soft_reset,
2383         .set_clockgating_state = sdma_v4_0_set_clockgating_state,
2384         .set_powergating_state = sdma_v4_0_set_powergating_state,
2385         .get_clockgating_state = sdma_v4_0_get_clockgating_state,
2386 };
2387
2388 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2389         .type = AMDGPU_RING_TYPE_SDMA,
2390         .align_mask = 0xf,
2391         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2392         .support_64bit_ptrs = true,
2393         .vmhub = AMDGPU_MMHUB_0,
2394         .get_rptr = sdma_v4_0_ring_get_rptr,
2395         .get_wptr = sdma_v4_0_ring_get_wptr,
2396         .set_wptr = sdma_v4_0_ring_set_wptr,
2397         .emit_frame_size =
2398                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2399                 3 + /* hdp invalidate */
2400                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2401                 /* sdma_v4_0_ring_emit_vm_flush */
2402                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2403                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2404                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2405         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2406         .emit_ib = sdma_v4_0_ring_emit_ib,
2407         .emit_fence = sdma_v4_0_ring_emit_fence,
2408         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2409         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2410         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2411         .test_ring = sdma_v4_0_ring_test_ring,
2412         .test_ib = sdma_v4_0_ring_test_ib,
2413         .insert_nop = sdma_v4_0_ring_insert_nop,
2414         .pad_ib = sdma_v4_0_ring_pad_ib,
2415         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2416         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2417         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2418 };
2419
2420 /*
2421  * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1).
2422  * So create a individual constant ring_funcs for those instances.
2423  */
2424 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
2425         .type = AMDGPU_RING_TYPE_SDMA,
2426         .align_mask = 0xf,
2427         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2428         .support_64bit_ptrs = true,
2429         .vmhub = AMDGPU_MMHUB_1,
2430         .get_rptr = sdma_v4_0_ring_get_rptr,
2431         .get_wptr = sdma_v4_0_ring_get_wptr,
2432         .set_wptr = sdma_v4_0_ring_set_wptr,
2433         .emit_frame_size =
2434                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2435                 3 + /* hdp invalidate */
2436                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2437                 /* sdma_v4_0_ring_emit_vm_flush */
2438                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2439                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2440                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2441         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2442         .emit_ib = sdma_v4_0_ring_emit_ib,
2443         .emit_fence = sdma_v4_0_ring_emit_fence,
2444         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2445         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2446         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2447         .test_ring = sdma_v4_0_ring_test_ring,
2448         .test_ib = sdma_v4_0_ring_test_ib,
2449         .insert_nop = sdma_v4_0_ring_insert_nop,
2450         .pad_ib = sdma_v4_0_ring_pad_ib,
2451         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2452         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2453         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2454 };
2455
2456 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2457         .type = AMDGPU_RING_TYPE_SDMA,
2458         .align_mask = 0xf,
2459         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2460         .support_64bit_ptrs = true,
2461         .vmhub = AMDGPU_MMHUB_0,
2462         .get_rptr = sdma_v4_0_ring_get_rptr,
2463         .get_wptr = sdma_v4_0_page_ring_get_wptr,
2464         .set_wptr = sdma_v4_0_page_ring_set_wptr,
2465         .emit_frame_size =
2466                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2467                 3 + /* hdp invalidate */
2468                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2469                 /* sdma_v4_0_ring_emit_vm_flush */
2470                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2471                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2472                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2473         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2474         .emit_ib = sdma_v4_0_ring_emit_ib,
2475         .emit_fence = sdma_v4_0_ring_emit_fence,
2476         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2477         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2478         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2479         .test_ring = sdma_v4_0_ring_test_ring,
2480         .test_ib = sdma_v4_0_ring_test_ib,
2481         .insert_nop = sdma_v4_0_ring_insert_nop,
2482         .pad_ib = sdma_v4_0_ring_pad_ib,
2483         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2484         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2485         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2486 };
2487
2488 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = {
2489         .type = AMDGPU_RING_TYPE_SDMA,
2490         .align_mask = 0xf,
2491         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2492         .support_64bit_ptrs = true,
2493         .vmhub = AMDGPU_MMHUB_1,
2494         .get_rptr = sdma_v4_0_ring_get_rptr,
2495         .get_wptr = sdma_v4_0_page_ring_get_wptr,
2496         .set_wptr = sdma_v4_0_page_ring_set_wptr,
2497         .emit_frame_size =
2498                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2499                 3 + /* hdp invalidate */
2500                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2501                 /* sdma_v4_0_ring_emit_vm_flush */
2502                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2503                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2504                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2505         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2506         .emit_ib = sdma_v4_0_ring_emit_ib,
2507         .emit_fence = sdma_v4_0_ring_emit_fence,
2508         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2509         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2510         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2511         .test_ring = sdma_v4_0_ring_test_ring,
2512         .test_ib = sdma_v4_0_ring_test_ib,
2513         .insert_nop = sdma_v4_0_ring_insert_nop,
2514         .pad_ib = sdma_v4_0_ring_pad_ib,
2515         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2516         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2517         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2518 };
2519
2520 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
2521 {
2522         int i;
2523
2524         for (i = 0; i < adev->sdma.num_instances; i++) {
2525                 if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2526                         adev->sdma.instance[i].ring.funcs =
2527                                         &sdma_v4_0_ring_funcs_2nd_mmhub;
2528                 else
2529                         adev->sdma.instance[i].ring.funcs =
2530                                         &sdma_v4_0_ring_funcs;
2531                 adev->sdma.instance[i].ring.me = i;
2532                 if (adev->sdma.has_page_queue) {
2533                         if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2534                                 adev->sdma.instance[i].page.funcs =
2535                                         &sdma_v4_0_page_ring_funcs_2nd_mmhub;
2536                         else
2537                                 adev->sdma.instance[i].page.funcs =
2538                                         &sdma_v4_0_page_ring_funcs;
2539                         adev->sdma.instance[i].page.me = i;
2540                 }
2541         }
2542 }
2543
2544 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2545         .set = sdma_v4_0_set_trap_irq_state,
2546         .process = sdma_v4_0_process_trap_irq,
2547 };
2548
2549 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2550         .process = sdma_v4_0_process_illegal_inst_irq,
2551 };
2552
2553 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
2554         .set = sdma_v4_0_set_ecc_irq_state,
2555         .process = amdgpu_sdma_process_ecc_irq,
2556 };
2557
2558 static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = {
2559         .process = sdma_v4_0_process_vm_hole_irq,
2560 };
2561
2562 static const struct amdgpu_irq_src_funcs sdma_v4_0_doorbell_invalid_irq_funcs = {
2563         .process = sdma_v4_0_process_doorbell_invalid_irq,
2564 };
2565
2566 static const struct amdgpu_irq_src_funcs sdma_v4_0_pool_timeout_irq_funcs = {
2567         .process = sdma_v4_0_process_pool_timeout_irq,
2568 };
2569
2570 static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = {
2571         .process = sdma_v4_0_process_srbm_write_irq,
2572 };
2573
2574 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2575 {
2576         switch (adev->sdma.num_instances) {
2577         case 1:
2578                 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2579                 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2580                 break;
2581         case 5:
2582                 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5;
2583                 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5;
2584                 break;
2585         case 8:
2586                 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2587                 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2588                 adev->sdma.vm_hole_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5;
2589                 adev->sdma.doorbell_invalid_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2590                 adev->sdma.pool_timeout_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2591                 adev->sdma.srbm_write_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2592                 break;
2593         case 2:
2594         default:
2595                 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2596                 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2597                 break;
2598         }
2599         adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2600         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2601         adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2602         adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs;
2603         adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs;
2604         adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs;
2605         adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs;
2606 }
2607
2608 /**
2609  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2610  *
2611  * @ib: indirect buffer to copy to
2612  * @src_offset: src GPU address
2613  * @dst_offset: dst GPU address
2614  * @byte_count: number of bytes to xfer
2615  * @tmz: if a secure copy should be used
2616  *
2617  * Copy GPU buffers using the DMA engine (VEGA10/12).
2618  * Used by the amdgpu ttm implementation to move pages if
2619  * registered as the asic copy callback.
2620  */
2621 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2622                                        uint64_t src_offset,
2623                                        uint64_t dst_offset,
2624                                        uint32_t byte_count,
2625                                        bool tmz)
2626 {
2627         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2628                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
2629                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
2630         ib->ptr[ib->length_dw++] = byte_count - 1;
2631         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2632         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2633         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2634         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2635         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2636 }
2637
2638 /**
2639  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2640  *
2641  * @ib: indirect buffer to copy to
2642  * @src_data: value to write to buffer
2643  * @dst_offset: dst GPU address
2644  * @byte_count: number of bytes to xfer
2645  *
2646  * Fill GPU buffers using the DMA engine (VEGA10/12).
2647  */
2648 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2649                                        uint32_t src_data,
2650                                        uint64_t dst_offset,
2651                                        uint32_t byte_count)
2652 {
2653         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2654         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2655         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2656         ib->ptr[ib->length_dw++] = src_data;
2657         ib->ptr[ib->length_dw++] = byte_count - 1;
2658 }
2659
2660 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2661         .copy_max_bytes = 0x400000,
2662         .copy_num_dw = 7,
2663         .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2664
2665         .fill_max_bytes = 0x400000,
2666         .fill_num_dw = 5,
2667         .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2668 };
2669
2670 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2671 {
2672         adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2673         if (adev->sdma.has_page_queue)
2674                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2675         else
2676                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2677 }
2678
2679 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2680         .copy_pte_num_dw = 7,
2681         .copy_pte = sdma_v4_0_vm_copy_pte,
2682
2683         .write_pte = sdma_v4_0_vm_write_pte,
2684         .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2685 };
2686
2687 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2688 {
2689         struct drm_gpu_scheduler *sched;
2690         unsigned i;
2691
2692         adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2693         for (i = 0; i < adev->sdma.num_instances; i++) {
2694                 if (adev->sdma.has_page_queue)
2695                         sched = &adev->sdma.instance[i].page.sched;
2696                 else
2697                         sched = &adev->sdma.instance[i].ring.sched;
2698                 adev->vm_manager.vm_pte_scheds[i] = sched;
2699         }
2700         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2701 }
2702
2703 static void sdma_v4_0_get_ras_error_count(uint32_t value,
2704                                         uint32_t instance,
2705                                         uint32_t *sec_count)
2706 {
2707         uint32_t i;
2708         uint32_t sec_cnt;
2709
2710         /* double bits error (multiple bits) error detection is not supported */
2711         for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) {
2712                 /* the SDMA_EDC_COUNTER register in each sdma instance
2713                  * shares the same sed shift_mask
2714                  * */
2715                 sec_cnt = (value &
2716                         sdma_v4_0_ras_fields[i].sec_count_mask) >>
2717                         sdma_v4_0_ras_fields[i].sec_count_shift;
2718                 if (sec_cnt) {
2719                         DRM_INFO("Detected %s in SDMA%d, SED %d\n",
2720                                 sdma_v4_0_ras_fields[i].name,
2721                                 instance, sec_cnt);
2722                         *sec_count += sec_cnt;
2723                 }
2724         }
2725 }
2726
2727 static int sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev,
2728                         uint32_t instance, void *ras_error_status)
2729 {
2730         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
2731         uint32_t sec_count = 0;
2732         uint32_t reg_value = 0;
2733
2734         reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);
2735         /* double bit error is not supported */
2736         if (reg_value)
2737                 sdma_v4_0_get_ras_error_count(reg_value,
2738                                 instance, &sec_count);
2739         /* err_data->ce_count should be initialized to 0
2740          * before calling into this function */
2741         err_data->ce_count += sec_count;
2742         /* double bit error is not supported
2743          * set ue count to 0 */
2744         err_data->ue_count = 0;
2745
2746         return 0;
2747 };
2748
2749 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
2750 {
2751         int i;
2752
2753         /* read back edc counter registers to clear the counters */
2754         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2755                 for (i = 0; i < adev->sdma.num_instances; i++)
2756                         RREG32_SDMA(i, mmSDMA0_EDC_COUNTER);
2757         }
2758 }
2759
2760 static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
2761         .ras_late_init = amdgpu_sdma_ras_late_init,
2762         .ras_fini = amdgpu_sdma_ras_fini,
2763         .query_ras_error_count = sdma_v4_0_query_ras_error_count,
2764         .reset_ras_error_count = sdma_v4_0_reset_ras_error_count,
2765 };
2766
2767 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2768 {
2769         switch (adev->asic_type) {
2770         case CHIP_VEGA20:
2771         case CHIP_ARCTURUS:
2772                 adev->sdma.funcs = &sdma_v4_0_ras_funcs;
2773                 break;
2774         default:
2775                 break;
2776         }
2777 }
2778
2779 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2780         .type = AMD_IP_BLOCK_TYPE_SDMA,
2781         .major = 4,
2782         .minor = 0,
2783         .rev = 0,
2784         .funcs = &sdma_v4_0_ip_funcs,
2785 };