drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/amdgpu_drm.h>
  25 #include "amdgpu.h"
  26 #include "atomfirmware.h"
  27 #include "amdgpu_atomfirmware.h"
  28 #include "atom.h"
  29 #include "atombios.h"
  30 #include "soc15_hw_ip.h"
  31
  32 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
  33 {
  34         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  35                                                 firmwareinfo);
  36         uint16_t data_offset;
  37
  38         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  39                                           NULL, NULL, &data_offset)) {
  40                 struct atom_firmware_info_v3_1 *firmware_info =
  41                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  42                                                            data_offset);
  43
  44                 if (le32_to_cpu(firmware_info->firmware_capability) &
  45                     ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
  46                         return true;
  47         }
  48         return false;
  49 }
  50
  51 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
  52 {
  53         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  54                                                 firmwareinfo);
  55         uint16_t data_offset;
  56
  57         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  58                                           NULL, NULL, &data_offset)) {
  59                 struct atom_firmware_info_v3_1 *firmware_info =
  60                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  61                                                            data_offset);
  62
  63                 adev->bios_scratch_reg_offset =
  64                         le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
  65         }
  66 }
  67
  68 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
  69 {
  70         struct atom_context *ctx = adev->mode_info.atom_context;
  71         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  72                                                 vram_usagebyfirmware);
  73         struct vram_usagebyfirmware_v2_1 *firmware_usage;
  74         uint32_t start_addr, size;
  75         uint16_t data_offset;
  76         int usage_bytes = 0;
  77
  78         if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
  79                 firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
  80                 DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
  81                           le32_to_cpu(firmware_usage->start_address_in_kb),
  82                           le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
  83                           le16_to_cpu(firmware_usage->used_by_driver_in_kb));
  84
  85                 start_addr = le32_to_cpu(firmware_usage->start_address_in_kb);
  86                 size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb);
  87
  88                 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
  89                         (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
  90                         ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
  91                         /* Firmware request VRAM reservation for SR-IOV */
  92                         adev->mman.fw_vram_usage_start_offset = (start_addr &
  93                                 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
  94                         adev->mman.fw_vram_usage_size = size << 10;
  95                         /* Use the default scratch size */
  96                         usage_bytes = 0;
  97                 } else {
  98                         usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10;
  99                 }
 100         }
 101         ctx->scratch_size_bytes = 0;
 102         if (usage_bytes == 0)
 103                 usage_bytes = 20 * 1024;
 104         /* allocate some scratch memory */
 105         ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
 106         if (!ctx->scratch)
 107                 return -ENOMEM;
 108         ctx->scratch_size_bytes = usage_bytes;
 109         return 0;
 110 }
 111
 112 union igp_info {
 113         struct atom_integrated_system_info_v1_11 v11;
 114         struct atom_integrated_system_info_v1_12 v12;
 115         struct atom_integrated_system_info_v2_1 v21;
 116 };
 117
 118 union umc_info {
 119         struct atom_umc_info_v3_1 v31;
 120 };
 121
 122 union vram_info {
 123         struct atom_vram_info_header_v2_3 v23;
 124         struct atom_vram_info_header_v2_4 v24;
 125         struct atom_vram_info_header_v2_5 v25;
 126         struct atom_vram_info_header_v2_5 v26;
 127 };
 128
 129 union vram_module {
 130         struct atom_vram_module_v9 v9;
 131         struct atom_vram_module_v10 v10;
 132         struct atom_vram_module_v11 v11;
 133 };
 134
 135 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
 136                                               int atom_mem_type)
 137 {
 138         int vram_type;
 139
 140         if (adev->flags & AMD_IS_APU) {
 141                 switch (atom_mem_type) {
 142                 case Ddr2MemType:
 143                 case LpDdr2MemType:
 144                         vram_type = AMDGPU_VRAM_TYPE_DDR2;
 145                         break;
 146                 case Ddr3MemType:
 147                 case LpDdr3MemType:
 148                         vram_type = AMDGPU_VRAM_TYPE_DDR3;
 149                         break;
 150                 case Ddr4MemType:
 151                 case LpDdr4MemType:
 152                         vram_type = AMDGPU_VRAM_TYPE_DDR4;
 153                         break;
 154                 case Ddr5MemType:
 155                 case LpDdr5MemType:
 156                         vram_type = AMDGPU_VRAM_TYPE_DDR5;
 157                         break;
 158                 default:
 159                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 160                         break;
 161                 }
 162         } else {
 163                 switch (atom_mem_type) {
 164                 case ATOM_DGPU_VRAM_TYPE_GDDR5:
 165                         vram_type = AMDGPU_VRAM_TYPE_GDDR5;
 166                         break;
 167                 case ATOM_DGPU_VRAM_TYPE_HBM2:
 168                         vram_type = AMDGPU_VRAM_TYPE_HBM;
 169                         break;
 170                 case ATOM_DGPU_VRAM_TYPE_GDDR6:
 171                         vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 172                         break;
 173                 default:
 174                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 175                         break;
 176                 }
 177         }
 178
 179         return vram_type;
 180 }
 181
 182
 183 int
 184 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
 185                                   int *vram_width, int *vram_type,
 186                                   int *vram_vendor)
 187 {
 188         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 189         int index, i = 0;
 190         u16 data_offset, size;
 191         union igp_info *igp_info;
 192         union vram_info *vram_info;
 193         union vram_module *vram_module;
 194         u8 frev, crev;
 195         u8 mem_type;
 196         u8 mem_vendor;
 197         u32 mem_channel_number;
 198         u32 mem_channel_width;
 199         u32 module_id;
 200
 201         if (adev->flags & AMD_IS_APU)
 202                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 203                                                     integratedsysteminfo);
 204         else
 205                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 206                                                     vram_info);
 207
 208         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 209                                           index, &size,
 210                                           &frev, &crev, &data_offset)) {
 211                 if (adev->flags & AMD_IS_APU) {
 212                         igp_info = (union igp_info *)
 213                                 (mode_info->atom_context->bios + data_offset);
 214                         switch (frev) {
 215                         case 1:
 216                                 switch (crev) {
 217                                 case 11:
 218                                 case 12:
 219                                         mem_channel_number = igp_info->v11.umachannelnumber;
 220                                         if (!mem_channel_number)
 221                                                 mem_channel_number = 1;
 222                                         /* channel width is 64 */
 223                                         if (vram_width)
 224                                                 *vram_width = mem_channel_number * 64;
 225                                         mem_type = igp_info->v11.memorytype;
 226                                         if (vram_type)
 227                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 228                                         break;
 229                                 default:
 230                                         return -EINVAL;
 231                                 }
 232                                 break;
 233                         case 2:
 234                                 switch (crev) {
 235                                 case 1:
 236                                 case 2:
 237                                         mem_channel_number = igp_info->v21.umachannelnumber;
 238                                         if (!mem_channel_number)
 239                                                 mem_channel_number = 1;
 240                                         /* channel width is 64 */
 241                                         if (vram_width)
 242                                                 *vram_width = mem_channel_number * 64;
 243                                         mem_type = igp_info->v21.memorytype;
 244                                         if (vram_type)
 245                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 246                                         break;
 247                                 default:
 248                                         return -EINVAL;
 249                                 }
 250                                 break;
 251                         default:
 252                                 return -EINVAL;
 253                         }
 254                 } else {
 255                         vram_info = (union vram_info *)
 256                                 (mode_info->atom_context->bios + data_offset);
 257                         module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
 258                         switch (crev) {
 259                         case 3:
 260                                 if (module_id > vram_info->v23.vram_module_num)
 261                                         module_id = 0;
 262                                 vram_module = (union vram_module *)vram_info->v23.vram_module;
 263                                 while (i < module_id) {
 264                                         vram_module = (union vram_module *)
 265                                                 ((u8 *)vram_module + vram_module->v9.vram_module_size);
 266                                         i++;
 267                                 }
 268                                 mem_type = vram_module->v9.memory_type;
 269                                 if (vram_type)
 270                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 271                                 mem_channel_number = vram_module->v9.channel_num;
 272                                 mem_channel_width = vram_module->v9.channel_width;
 273                                 if (vram_width)
 274                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 275                                 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 276                                 if (vram_vendor)
 277                                         *vram_vendor = mem_vendor;
 278                                 break;
 279                         case 4:
 280                                 if (module_id > vram_info->v24.vram_module_num)
 281                                         module_id = 0;
 282                                 vram_module = (union vram_module *)vram_info->v24.vram_module;
 283                                 while (i < module_id) {
 284                                         vram_module = (union vram_module *)
 285                                                 ((u8 *)vram_module + vram_module->v10.vram_module_size);
 286                                         i++;
 287                                 }
 288                                 mem_type = vram_module->v10.memory_type;
 289                                 if (vram_type)
 290                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 291                                 mem_channel_number = vram_module->v10.channel_num;
 292                                 mem_channel_width = vram_module->v10.channel_width;
 293                                 if (vram_width)
 294                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 295                                 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
 296                                 if (vram_vendor)
 297                                         *vram_vendor = mem_vendor;
 298                                 break;
 299                         case 5:
 300                                 if (module_id > vram_info->v25.vram_module_num)
 301                                         module_id = 0;
 302                                 vram_module = (union vram_module *)vram_info->v25.vram_module;
 303                                 while (i < module_id) {
 304                                         vram_module = (union vram_module *)
 305                                                 ((u8 *)vram_module + vram_module->v11.vram_module_size);
 306                                         i++;
 307                                 }
 308                                 mem_type = vram_module->v11.memory_type;
 309                                 if (vram_type)
 310                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 311                                 mem_channel_number = vram_module->v11.channel_num;
 312                                 mem_channel_width = vram_module->v11.channel_width;
 313                                 if (vram_width)
 314                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 315                                 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
 316                                 if (vram_vendor)
 317                                         *vram_vendor = mem_vendor;
 318                                 break;
 319                         case 6:
 320                                 if (module_id > vram_info->v26.vram_module_num)
 321                                         module_id = 0;
 322                                 vram_module = (union vram_module *)vram_info->v26.vram_module;
 323                                 while (i < module_id) {
 324                                         vram_module = (union vram_module *)
 325                                                 ((u8 *)vram_module + vram_module->v11.vram_module_size);
 326                                         i++;
 327                                 }
 328                                 mem_type = vram_module->v9.memory_type;
 329                                 if (vram_type)
 330                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 331                                 mem_channel_number = vram_module->v9.channel_num;
 332                                 mem_channel_width = vram_module->v9.channel_width;
 333                                 if (vram_width)
 334                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 335                                 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 336                                 if (vram_vendor)
 337                                         *vram_vendor = mem_vendor;
 338                                 break;
 339                         default:
 340                                 return -EINVAL;
 341                         }
 342                 }
 343
 344         }
 345
 346         return 0;
 347 }
 348
 349 /*
 350  * Return true if vbios enabled ecc by default, if umc info table is available
 351  * or false if ecc is not enabled or umc info table is not available
 352  */
 353 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 354 {
 355         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 356         int index;
 357         u16 data_offset, size;
 358         union umc_info *umc_info;
 359         u8 frev, crev;
 360         bool ecc_default_enabled = false;
 361
 362         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 363                         umc_info);
 364
 365         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 366                                 index, &size, &frev, &crev, &data_offset)) {
 367                 /* support umc_info 3.1+ */
 368                 if ((frev == 3 && crev >= 1) || (frev > 3)) {
 369                         umc_info = (union umc_info *)
 370                                 (mode_info->atom_context->bios + data_offset);
 371                         ecc_default_enabled =
 372                                 (le32_to_cpu(umc_info->v31.umc_config) &
 373                                  UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 374                 }
 375         }
 376
 377         return ecc_default_enabled;
 378 }
 379
 380 union firmware_info {
 381         struct atom_firmware_info_v3_1 v31;
 382         struct atom_firmware_info_v3_2 v32;
 383         struct atom_firmware_info_v3_3 v33;
 384         struct atom_firmware_info_v3_4 v34;
 385 };
 386
 387 /*
 388  * Return true if vbios supports sram ecc or false if not
 389  */
 390 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
 391 {
 392         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 393         int index;
 394         u16 data_offset, size;
 395         union firmware_info *firmware_info;
 396         u8 frev, crev;
 397         bool sram_ecc_supported = false;
 398
 399         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 400                         firmwareinfo);
 401
 402         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
 403                                 index, &size, &frev, &crev, &data_offset)) {
 404                 /* support firmware_info 3.1 + */
 405                 if ((frev == 3 && crev >=1) || (frev > 3)) {
 406                         firmware_info = (union firmware_info *)
 407                                 (mode_info->atom_context->bios + data_offset);
 408                         sram_ecc_supported =
 409                                 (le32_to_cpu(firmware_info->v31.firmware_capability) &
 410                                  ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
 411                 }
 412         }
 413
 414         return sram_ecc_supported;
 415 }
 416
 417 union smu_info {
 418         struct atom_smu_info_v3_1 v31;
 419 };
 420
 421 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 422 {
 423         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 424         struct amdgpu_pll *spll = &adev->clock.spll;
 425         struct amdgpu_pll *mpll = &adev->clock.mpll;
 426         uint8_t frev, crev;
 427         uint16_t data_offset;
 428         int ret = -EINVAL, index;
 429
 430         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 431                                             firmwareinfo);
 432         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 433                                    &frev, &crev, &data_offset)) {
 434                 union firmware_info *firmware_info =
 435                         (union firmware_info *)(mode_info->atom_context->bios +
 436                                                 data_offset);
 437
 438                 adev->clock.default_sclk =
 439                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 440                 adev->clock.default_mclk =
 441                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 442
 443                 adev->pm.current_sclk = adev->clock.default_sclk;
 444                 adev->pm.current_mclk = adev->clock.default_mclk;
 445
 446                 /* not technically a clock, but... */
 447                 adev->mode_info.firmware_flags =
 448                         le32_to_cpu(firmware_info->v31.firmware_capability);
 449
 450                 ret = 0;
 451         }
 452
 453         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 454                                             smu_info);
 455         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 456                                    &frev, &crev, &data_offset)) {
 457                 union smu_info *smu_info =
 458                         (union smu_info *)(mode_info->atom_context->bios +
 459                                            data_offset);
 460
 461                 /* system clock */
 462                 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
 463
 464                 spll->reference_div = 0;
 465                 spll->min_post_div = 1;
 466                 spll->max_post_div = 1;
 467                 spll->min_ref_div = 2;
 468                 spll->max_ref_div = 0xff;
 469                 spll->min_feedback_div = 4;
 470                 spll->max_feedback_div = 0xff;
 471                 spll->best_vco = 0;
 472
 473                 ret = 0;
 474         }
 475
 476         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 477                                             umc_info);
 478         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 479                                    &frev, &crev, &data_offset)) {
 480                 union umc_info *umc_info =
 481                         (union umc_info *)(mode_info->atom_context->bios +
 482                                            data_offset);
 483
 484                 /* memory clock */
 485                 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
 486
 487                 mpll->reference_div = 0;
 488                 mpll->min_post_div = 1;
 489                 mpll->max_post_div = 1;
 490                 mpll->min_ref_div = 2;
 491                 mpll->max_ref_div = 0xff;
 492                 mpll->min_feedback_div = 4;
 493                 mpll->max_feedback_div = 0xff;
 494                 mpll->best_vco = 0;
 495
 496                 ret = 0;
 497         }
 498
 499         return ret;
 500 }
 501
 502 union gfx_info {
 503         struct  atom_gfx_info_v2_4 v24;
 504 };
 505
 506 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
 507 {
 508         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 509         int index;
 510         uint8_t frev, crev;
 511         uint16_t data_offset;
 512
 513         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 514                                             gfx_info);
 515         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 516                                    &frev, &crev, &data_offset)) {
 517                 union gfx_info *gfx_info = (union gfx_info *)
 518                         (mode_info->atom_context->bios + data_offset);
 519                 switch (crev) {
 520                 case 4:
 521                         adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
 522                         adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
 523                         adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
 524                         adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
 525                         adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
 526                         adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
 527                         adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
 528                         adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
 529                         adev->gfx.config.gs_prim_buffer_depth =
 530                                 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
 531                         adev->gfx.config.double_offchip_lds_buf =
 532                                 gfx_info->v24.gc_double_offchip_lds_buffer;
 533                         adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
 534                         adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
 535                         adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
 536                         adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
 537                         return 0;
 538                 default:
 539                         return -EINVAL;
 540                 }
 541
 542         }
 543         return -EINVAL;
 544 }
 545
 546 /*
 547  * Check if VBIOS supports GDDR6 training data save/restore
 548  */
 549 static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev)
 550 {
 551         uint16_t data_offset;
 552         int index;
 553
 554         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 555                                             firmwareinfo);
 556         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
 557                                           NULL, NULL, &data_offset)) {
 558                 struct atom_firmware_info_v3_1 *firmware_info =
 559                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
 560                                                            data_offset);
 561
 562                 DRM_DEBUG("atom firmware capability:0x%08x.\n",
 563                           le32_to_cpu(firmware_info->firmware_capability));
 564
 565                 if (le32_to_cpu(firmware_info->firmware_capability) &
 566                     ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING)
 567                         return true;
 568         }
 569
 570         return false;
 571 }
 572
 573 int amdgpu_mem_train_support(struct amdgpu_device *adev)
 574 {
 575         int ret;
 576         uint32_t major, minor, revision, hw_v;
 577
 578         if (gddr6_mem_train_vbios_support(adev)) {
 579                 amdgpu_discovery_get_ip_version(adev, MP0_HWID, &major, &minor, &revision);
 580                 hw_v = HW_REV(major, minor, revision);
 581                 /*
 582                  * treat 0 revision as a special case since register for MP0 and MMHUB is missing
 583                  * for some Navi10 A0, preventing driver from discovering the hwip information since
 584                  * none of the functions will be initialized, it should not cause any problems
 585                  */
 586                 switch (hw_v) {
 587                 case HW_REV(11, 0, 0):
 588                 case HW_REV(11, 0, 5):
 589                 case HW_REV(11, 0, 7):
 590                 case HW_REV(11, 0, 11):
 591                 case HW_REV(11, 0, 12):
 592                         ret = 1;
 593                         break;
 594                 default:
 595                         DRM_ERROR("memory training vbios supports but psp hw(%08x)"
 596                                   " doesn't support!\n", hw_v);
 597                         ret = -1;
 598                         break;
 599                 }
 600         } else {
 601                 ret = 0;
 602                 hw_v = -1;
 603         }
 604
 605
 606         DRM_DEBUG("mp0 hw_v %08x, ret:%d.\n", hw_v, ret);
 607         return ret;
 608 }
 609
 610 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
 611 {
 612         struct atom_context *ctx = adev->mode_info.atom_context;
 613         union firmware_info *firmware_info;
 614         int index;
 615         u16 data_offset, size;
 616         u8 frev, crev;
 617         int fw_reserved_fb_size;
 618
 619         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 620                         firmwareinfo);
 621
 622         if (!amdgpu_atom_parse_data_header(ctx, index, &size,
 623                                 &frev, &crev, &data_offset))
 624                 /* fail to parse data_header */
 625                 return 0;
 626
 627         firmware_info = (union firmware_info *)(ctx->bios + data_offset);
 628
 629         if (frev !=3)
 630                 return -EINVAL;
 631
 632         switch (crev) {
 633         case 4:
 634                 fw_reserved_fb_size =
 635                         (firmware_info->v34.fw_reserved_size_in_kb << 10);
 636                 break;
 637         default:
 638                 fw_reserved_fb_size = 0;
 639                 break;
 640         }
 641
 642         return fw_reserved_fb_size;
 643 }