drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25
  26 #include <drm/drm_drv.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_ras.h"
  30
  31 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
  32 {
  33         /* By now all MMIO pages except mailbox are blocked */
  34         /* if blocking is enabled in hypervisor. Choose the */
  35         /* SCRATCH_REG0 to test. */
  36         return RREG32_NO_KIQ(0xc040) == 0xffffffff;
  37 }
  38
  39 void amdgpu_virt_init_setting(struct amdgpu_device *adev)
  40 {
  41         /* enable virtual display */
  42         if (adev->mode_info.num_crtc == 0)
  43                 adev->mode_info.num_crtc = 1;
  44         adev->enable_virtual_display = true;
  45         adev->ddev->driver->driver_features &= ~DRIVER_ATOMIC;
  46         adev->cg_flags = 0;
  47         adev->pg_flags = 0;
  48 }
  49
  50 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
  51                                         uint32_t reg0, uint32_t reg1,
  52                                         uint32_t ref, uint32_t mask)
  53 {
  54         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
  55         struct amdgpu_ring *ring = &kiq->ring;
  56         signed long r, cnt = 0;
  57         unsigned long flags;
  58         uint32_t seq;
  59
  60         spin_lock_irqsave(&kiq->ring_lock, flags);
  61         amdgpu_ring_alloc(ring, 32);
  62         amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
  63                                             ref, mask);
  64         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
  65         if (r)
  66                 goto failed_undo;
  67
  68         amdgpu_ring_commit(ring);
  69         spin_unlock_irqrestore(&kiq->ring_lock, flags);
  70
  71         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
  72
  73         /* don't wait anymore for IRQ context */
  74         if (r < 1 && in_interrupt())
  75                 goto failed_kiq;
  76
  77         might_sleep();
  78         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
  79
  80                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
  81                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
  82         }
  83
  84         if (cnt > MAX_KIQ_REG_TRY)
  85                 goto failed_kiq;
  86
  87         return;
  88
  89 failed_undo:
  90         amdgpu_ring_undo(ring);
  91         spin_unlock_irqrestore(&kiq->ring_lock, flags);
  92 failed_kiq:
  93         pr_err("failed to write reg %x wait reg %x\n", reg0, reg1);
  94 }
  95
  96 /**
  97  * amdgpu_virt_request_full_gpu() - request full gpu access
  98  * @amdgpu:     amdgpu device.
  99  * @init:       is driver init time.
 100  * When start to init/fini driver, first need to request full gpu access.
 101  * Return: Zero if request success, otherwise will return error.
 102  */
 103 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
 104 {
 105         struct amdgpu_virt *virt = &adev->virt;
 106         int r;
 107
 108         if (virt->ops && virt->ops->req_full_gpu) {
 109                 r = virt->ops->req_full_gpu(adev, init);
 110                 if (r)
 111                         return r;
 112
 113                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 114         }
 115
 116         return 0;
 117 }
 118
 119 /**
 120  * amdgpu_virt_release_full_gpu() - release full gpu access
 121  * @amdgpu:     amdgpu device.
 122  * @init:       is driver init time.
 123  * When finishing driver init/fini, need to release full gpu access.
 124  * Return: Zero if release success, otherwise will returen error.
 125  */
 126 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
 127 {
 128         struct amdgpu_virt *virt = &adev->virt;
 129         int r;
 130
 131         if (virt->ops && virt->ops->rel_full_gpu) {
 132                 r = virt->ops->rel_full_gpu(adev, init);
 133                 if (r)
 134                         return r;
 135
 136                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
 137         }
 138         return 0;
 139 }
 140
 141 /**
 142  * amdgpu_virt_reset_gpu() - reset gpu
 143  * @amdgpu:     amdgpu device.
 144  * Send reset command to GPU hypervisor to reset GPU that VM is using
 145  * Return: Zero if reset success, otherwise will return error.
 146  */
 147 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
 148 {
 149         struct amdgpu_virt *virt = &adev->virt;
 150         int r;
 151
 152         if (virt->ops && virt->ops->reset_gpu) {
 153                 r = virt->ops->reset_gpu(adev);
 154                 if (r)
 155                         return r;
 156
 157                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 158         }
 159
 160         return 0;
 161 }
 162
 163 void amdgpu_virt_request_init_data(struct amdgpu_device *adev)
 164 {
 165         struct amdgpu_virt *virt = &adev->virt;
 166
 167         if (virt->ops && virt->ops->req_init_data)
 168                 virt->ops->req_init_data(adev);
 169
 170         if (adev->virt.req_init_data_ver > 0)
 171                 DRM_INFO("host supports REQ_INIT_DATA handshake\n");
 172         else
 173                 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n");
 174 }
 175
 176 /**
 177  * amdgpu_virt_wait_reset() - wait for reset gpu completed
 178  * @amdgpu:     amdgpu device.
 179  * Wait for GPU reset completed.
 180  * Return: Zero if reset success, otherwise will return error.
 181  */
 182 int amdgpu_virt_wait_reset(struct amdgpu_device *adev)
 183 {
 184         struct amdgpu_virt *virt = &adev->virt;
 185
 186         if (!virt->ops || !virt->ops->wait_reset)
 187                 return -EINVAL;
 188
 189         return virt->ops->wait_reset(adev);
 190 }
 191
 192 /**
 193  * amdgpu_virt_alloc_mm_table() - alloc memory for mm table
 194  * @amdgpu:     amdgpu device.
 195  * MM table is used by UVD and VCE for its initialization
 196  * Return: Zero if allocate success.
 197  */
 198 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)
 199 {
 200         int r;
 201
 202         if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)
 203                 return 0;
 204
 205         r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
 206                                     AMDGPU_GEM_DOMAIN_VRAM,
 207                                     &adev->virt.mm_table.bo,
 208                                     &adev->virt.mm_table.gpu_addr,
 209                                     (void *)&adev->virt.mm_table.cpu_addr);
 210         if (r) {
 211                 DRM_ERROR("failed to alloc mm table and error = %d.\n", r);
 212                 return r;
 213         }
 214
 215         memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);
 216         DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n",
 217                  adev->virt.mm_table.gpu_addr,
 218                  adev->virt.mm_table.cpu_addr);
 219         return 0;
 220 }
 221
 222 /**
 223  * amdgpu_virt_free_mm_table() - free mm table memory
 224  * @amdgpu:     amdgpu device.
 225  * Free MM table memory
 226  */
 227 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
 228 {
 229         if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)
 230                 return;
 231
 232         amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,
 233                               &adev->virt.mm_table.gpu_addr,
 234                               (void *)&adev->virt.mm_table.cpu_addr);
 235         adev->virt.mm_table.gpu_addr = 0;
 236 }
 237
 238
 239 int amdgpu_virt_fw_reserve_get_checksum(void *obj,
 240                                         unsigned long obj_size,
 241                                         unsigned int key,
 242                                         unsigned int chksum)
 243 {
 244         unsigned int ret = key;
 245         unsigned long i = 0;
 246         unsigned char *pos;
 247
 248         pos = (char *)obj;
 249         /* calculate checksum */
 250         for (i = 0; i < obj_size; ++i)
 251                 ret += *(pos + i);
 252         /* minus the chksum itself */
 253         pos = (char *)&chksum;
 254         for (i = 0; i < sizeof(chksum); ++i)
 255                 ret -= *(pos + i);
 256         return ret;
 257 }
 258
 259 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev)
 260 {
 261         struct amdgpu_virt *virt = &adev->virt;
 262         struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data;
 263         /* GPU will be marked bad on host if bp count more then 10,
 264          * so alloc 512 is enough.
 265          */
 266         unsigned int align_space = 512;
 267         void *bps = NULL;
 268         struct amdgpu_bo **bps_bo = NULL;
 269
 270         *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL);
 271         if (!*data)
 272                 return -ENOMEM;
 273
 274         bps = kmalloc(align_space * sizeof((*data)->bps), GFP_KERNEL);
 275         bps_bo = kmalloc(align_space * sizeof((*data)->bps_bo), GFP_KERNEL);
 276
 277         if (!bps || !bps_bo) {
 278                 kfree(bps);
 279                 kfree(bps_bo);
 280                 kfree(*data);
 281                 return -ENOMEM;
 282         }
 283
 284         (*data)->bps = bps;
 285         (*data)->bps_bo = bps_bo;
 286         (*data)->count = 0;
 287         (*data)->last_reserved = 0;
 288
 289         virt->ras_init_done = true;
 290
 291         return 0;
 292 }
 293
 294 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev)
 295 {
 296         struct amdgpu_virt *virt = &adev->virt;
 297         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 298         struct amdgpu_bo *bo;
 299         int i;
 300
 301         if (!data)
 302                 return;
 303
 304         for (i = data->last_reserved - 1; i >= 0; i--) {
 305                 bo = data->bps_bo[i];
 306                 amdgpu_bo_free_kernel(&bo, NULL, NULL);
 307                 data->bps_bo[i] = bo;
 308                 data->last_reserved = i;
 309         }
 310 }
 311
 312 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev)
 313 {
 314         struct amdgpu_virt *virt = &adev->virt;
 315         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 316
 317         virt->ras_init_done = false;
 318
 319         if (!data)
 320                 return;
 321
 322         amdgpu_virt_ras_release_bp(adev);
 323
 324         kfree(data->bps);
 325         kfree(data->bps_bo);
 326         kfree(data);
 327         virt->virt_eh_data = NULL;
 328 }
 329
 330 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev,
 331                 struct eeprom_table_record *bps, int pages)
 332 {
 333         struct amdgpu_virt *virt = &adev->virt;
 334         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 335
 336         if (!data)
 337                 return;
 338
 339         memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps));
 340         data->count += pages;
 341 }
 342
 343 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev)
 344 {
 345         struct amdgpu_virt *virt = &adev->virt;
 346         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 347         struct amdgpu_bo *bo = NULL;
 348         uint64_t bp;
 349         int i;
 350
 351         if (!data)
 352                 return;
 353
 354         for (i = data->last_reserved; i < data->count; i++) {
 355                 bp = data->bps[i].retired_page;
 356
 357                 /* There are two cases of reserve error should be ignored:
 358                  * 1) a ras bad page has been allocated (used by someone);
 359                  * 2) a ras bad page has been reserved (duplicate error injection
 360                  *    for one page);
 361                  */
 362                 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,
 363                                                AMDGPU_GPU_PAGE_SIZE,
 364                                                AMDGPU_GEM_DOMAIN_VRAM,
 365                                                &bo, NULL))
 366                         DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp);
 367
 368                 data->bps_bo[i] = bo;
 369                 data->last_reserved = i + 1;
 370                 bo = NULL;
 371         }
 372 }
 373
 374 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev,
 375                 uint64_t retired_page)
 376 {
 377         struct amdgpu_virt *virt = &adev->virt;
 378         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 379         int i;
 380
 381         if (!data)
 382                 return true;
 383
 384         for (i = 0; i < data->count; i++)
 385                 if (retired_page == data->bps[i].retired_page)
 386                         return true;
 387
 388         return false;
 389 }
 390
 391 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev,
 392                 uint64_t bp_block_offset, uint32_t bp_block_size)
 393 {
 394         struct eeprom_table_record bp;
 395         uint64_t retired_page;
 396         uint32_t bp_idx, bp_cnt;
 397
 398         if (bp_block_size) {
 399                 bp_cnt = bp_block_size / sizeof(uint64_t);
 400                 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) {
 401                         retired_page = *(uint64_t *)(adev->fw_vram_usage.va +
 402                                         bp_block_offset + bp_idx * sizeof(uint64_t));
 403                         bp.retired_page = retired_page;
 404
 405                         if (amdgpu_virt_ras_check_bad_page(adev, retired_page))
 406                                 continue;
 407
 408                         amdgpu_virt_ras_add_bps(adev, &bp, 1);
 409
 410                         amdgpu_virt_ras_reserve_bps(adev);
 411                 }
 412         }
 413 }
 414
 415 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
 416 {
 417         uint32_t pf2vf_size = 0;
 418         uint32_t checksum = 0;
 419         uint32_t checkval;
 420         char *str;
 421         uint64_t bp_block_offset = 0;
 422         uint32_t bp_block_size = 0;
 423         struct amdgim_pf2vf_info_v2 *pf2vf_v2 = NULL;
 424
 425         adev->virt.fw_reserve.p_pf2vf = NULL;
 426         adev->virt.fw_reserve.p_vf2pf = NULL;
 427
 428         if (adev->fw_vram_usage.va != NULL) {
 429                 adev->virt.fw_reserve.p_pf2vf =
 430                         (struct amd_sriov_msg_pf2vf_info_header *)(
 431                         adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET);
 432                 AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size);
 433                 AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum);
 434                 AMDGPU_FW_VRAM_PF2VF_READ(adev, feature_flags, &adev->virt.gim_feature);
 435
 436                 /* pf2vf message must be in 4K */
 437                 if (pf2vf_size > 0 && pf2vf_size < 4096) {
 438                         if (adev->virt.fw_reserve.p_pf2vf->version == 2) {
 439                                 pf2vf_v2 = (struct amdgim_pf2vf_info_v2 *)adev->virt.fw_reserve.p_pf2vf;
 440                                 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_L & 0xFFFFFFFF) |
 441                                                 ((((uint64_t)pf2vf_v2->bp_block_offset_H) << 32) & 0xFFFFFFFF00000000);
 442                                 bp_block_size = pf2vf_v2->bp_block_size;
 443
 444                                 if (bp_block_size && !adev->virt.ras_init_done)
 445                                         amdgpu_virt_init_ras_err_handler_data(adev);
 446
 447                                 if (adev->virt.ras_init_done)
 448                                         amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);
 449                         }
 450
 451                         checkval = amdgpu_virt_fw_reserve_get_checksum(
 452                                 adev->virt.fw_reserve.p_pf2vf, pf2vf_size,
 453                                 adev->virt.fw_reserve.checksum_key, checksum);
 454                         if (checkval == checksum) {
 455                                 adev->virt.fw_reserve.p_vf2pf =
 456                                         ((void *)adev->virt.fw_reserve.p_pf2vf +
 457                                         pf2vf_size);
 458                                 memset((void *)adev->virt.fw_reserve.p_vf2pf, 0,
 459                                         sizeof(amdgim_vf2pf_info));
 460                                 AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.version,
 461                                         AMDGPU_FW_VRAM_VF2PF_VER);
 462                                 AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.size,
 463                                         sizeof(amdgim_vf2pf_info));
 464                                 AMDGPU_FW_VRAM_VF2PF_READ(adev, driver_version,
 465                                         &str);
 466 #ifdef MODULE
 467                                 if (THIS_MODULE->version != NULL)
 468                                         strcpy(str, THIS_MODULE->version);
 469                                 else
 470 #endif
 471                                         strcpy(str, "N/A");
 472                                 AMDGPU_FW_VRAM_VF2PF_WRITE(adev, driver_cert,
 473                                         0);
 474                                 AMDGPU_FW_VRAM_VF2PF_WRITE(adev, checksum,
 475                                         amdgpu_virt_fw_reserve_get_checksum(
 476                                         adev->virt.fw_reserve.p_vf2pf,
 477                                         pf2vf_size,
 478                                         adev->virt.fw_reserve.checksum_key, 0));
 479                         }
 480                 }
 481         }
 482 }
 483
 484 void amdgpu_detect_virtualization(struct amdgpu_device *adev)
 485 {
 486         uint32_t reg;
 487
 488         switch (adev->asic_type) {
 489         case CHIP_TONGA:
 490         case CHIP_FIJI:
 491                 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
 492                 break;
 493         case CHIP_VEGA10:
 494         case CHIP_VEGA20:
 495         case CHIP_NAVI10:
 496         case CHIP_NAVI12:
 497         case CHIP_SIENNA_CICHLID:
 498         case CHIP_ARCTURUS:
 499                 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
 500                 break;
 501         default: /* other chip doesn't support SRIOV */
 502                 reg = 0;
 503                 break;
 504         }
 505
 506         if (reg & 1)
 507                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
 508
 509         if (reg & 0x80000000)
 510                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
 511
 512         if (!reg) {
 513                 if (is_virtual_machine())       /* passthrough mode exclus sriov mod */
 514                         adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 515         }
 516 }
 517
 518 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
 519 {
 520         return amdgpu_sriov_is_debug(adev) ? true : false;
 521 }
 522
 523 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
 524 {
 525         return amdgpu_sriov_is_normal(adev) ? true : false;
 526 }
 527
 528 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev)
 529 {
 530         if (!amdgpu_sriov_vf(adev) ||
 531             amdgpu_virt_access_debugfs_is_kiq(adev))
 532                 return 0;
 533
 534         if (amdgpu_virt_access_debugfs_is_mmio(adev))
 535                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 536         else
 537                 return -EPERM;
 538
 539         return 0;
 540 }
 541
 542 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev)
 543 {
 544         if (amdgpu_sriov_vf(adev))
 545                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
 546 }
 547
 548 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev)
 549 {
 550         enum amdgpu_sriov_vf_mode mode;
 551
 552         if (amdgpu_sriov_vf(adev)) {
 553                 if (amdgpu_sriov_is_pp_one_vf(adev))
 554                         mode = SRIOV_VF_MODE_ONE_VF;
 555                 else
 556                         mode = SRIOV_VF_MODE_MULTI_VF;
 557         } else {
 558                 mode = SRIOV_VF_MODE_BARE_METAL;
 559         }
 560
 561         return mode;
 562 }