drivers/staging/rtl8192e/rtl819x_HT.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   4  *
   5  * Contact Information: wlanfae <[email protected]>
   6  */
   7 #ifndef _RTL819XU_HTTYPE_H_
   8 #define _RTL819XU_HTTYPE_H_
   9
  10 #define MIMO_PS_STATIC                          0
  11
  12 #define sHTCLng 4
  13
  14 enum ht_channel_width {
  15         HT_CHANNEL_WIDTH_20 = 0,
  16         HT_CHANNEL_WIDTH_20_40 = 1,
  17 };
  18
  19 enum ht_extchnl_offset {
  20         HT_EXTCHNL_OFFSET_NO_EXT = 0,
  21         HT_EXTCHNL_OFFSET_UPPER = 1,
  22         HT_EXTCHNL_OFFSET_NO_DEF = 2,
  23         HT_EXTCHNL_OFFSET_LOWER = 3,
  24 };
  25
  26 struct ht_capab_ele {
  27         u8      AdvCoding:1;
  28         u8      ChlWidth:1;
  29         u8      MimoPwrSave:2;
  30         u8      GreenField:1;
  31         u8      ShortGI20Mhz:1;
  32         u8      ShortGI40Mhz:1;
  33         u8      TxSTBC:1;
  34         u8      RxSTBC:2;
  35         u8      DelayBA:1;
  36         u8      MaxAMSDUSize:1;
  37         u8      DssCCk:1;
  38         u8      PSMP:1;
  39         u8      Rsvd1:1;
  40         u8      LSigTxopProtect:1;
  41
  42         u8      MaxRxAMPDUFactor:2;
  43         u8      MPDUDensity:3;
  44         u8      Rsvd2:3;
  45
  46         u8      MCS[16];
  47
  48         u16     ExtHTCapInfo;
  49
  50         u8      TxBFCap[4];
  51
  52         u8      ASCap;
  53
  54 } __packed;
  55
  56 struct ht_info_ele {
  57         u8      ControlChl;
  58
  59         u8      ExtChlOffset:2;
  60         u8      RecommemdedTxWidth:1;
  61         u8      RIFS:1;
  62         u8      PSMPAccessOnly:1;
  63         u8      SrvIntGranularity:3;
  64
  65         u8      OptMode:2;
  66         u8      NonGFDevPresent:1;
  67         u8      Revd1:5;
  68         u8      Revd2:8;
  69
  70         u8      Rsvd3:6;
  71         u8      DualBeacon:1;
  72         u8      DualCTSProtect:1;
  73
  74         u8      SecondaryBeacon:1;
  75         u8      LSigTxopProtectFull:1;
  76         u8      PcoActive:1;
  77         u8      PcoPhase:1;
  78         u8      Rsvd4:4;
  79
  80         u8      BasicMSC[16];
  81 } __packed;
  82
  83 enum ht_spec_ver {
  84         HT_SPEC_VER_IEEE = 0,
  85         HT_SPEC_VER_EWC = 1,
  86 };
  87
  88 enum ht_aggre_mode {
  89         HT_AGG_AUTO = 0,
  90         HT_AGG_FORCE_ENABLE = 1,
  91         HT_AGG_FORCE_DISABLE = 2,
  92 };
  93
  94 struct rt_hi_throughput {
  95         u8 enable_ht;
  96         u8 current_ht_support;
  97         u8 bRegBW40MHz;
  98         u8 bCurBW40MHz;
  99         u8 bRegShortGI40MHz;
 100         u8 bCurShortGI40MHz;
 101         u8 bRegShortGI20MHz;
 102         u8 bCurShortGI20MHz;
 103         u8 bRegSuppCCK;
 104         u8 bCurSuppCCK;
 105         enum ht_spec_ver ePeerHTSpecVer;
 106         struct ht_capab_ele SelfHTCap;
 107         struct ht_info_ele SelfHTInfo;
 108         u8 PeerHTCapBuf[32];
 109         u8 PeerHTInfoBuf[32];
 110         u8 bAMSDU_Support;
 111         u16 nAMSDU_MaxSize;
 112         u8 bCurrent_AMSDU_Support;
 113         u16 nCurrent_AMSDU_MaxSize;
 114         u8 bAMPDUEnable;
 115         u8 bCurrentAMPDUEnable;
 116         u8 AMPDU_Factor;
 117         u8 CurrentAMPDUFactor;
 118         u8 MPDU_Density;
 119         u8 current_mpdu_density;
 120         enum ht_aggre_mode ForcedAMPDUMode;
 121         u8 forced_ampdu_factor;
 122         u8 forced_mpdu_density;
 123         enum ht_aggre_mode ForcedAMSDUMode;
 124         u8 forced_short_gi;
 125         u8 current_op_mode;
 126         u8 self_mimo_ps;
 127         u8 peer_mimo_ps;
 128         enum ht_extchnl_offset CurSTAExtChnlOffset;
 129         u8 cur_tx_bw40mhz;
 130         u8 sw_bw_in_progress;
 131         u8 reg_rt2rt_aggregation;
 132         u8 RT2RT_HT_Mode;
 133         u8 current_rt2rt_aggregation;
 134         u8 current_rt2rt_long_slot_time;
 135         u8 sz_rt2rt_agg_buf[10];
 136         u8 reg_rx_reorder_enable;
 137         u8 cur_rx_reorder_enable;
 138         u8 rx_reorder_win_size;
 139         u8 rx_reorder_pending_time;
 140         u16 rx_reorder_drop_counter;
 141         u8 IOTPeer;
 142         u32 iot_action;
 143         u8 iot_ra_func;
 144 } __packed;
 145
 146 struct bss_ht {
 147         u8 bd_support_ht;
 148
 149         u8 bd_ht_cap_buf[32];
 150         u16 bd_ht_cap_len;
 151         u8 bd_ht_info_buf[32];
 152         u16 bd_ht_info_len;
 153
 154         enum ht_spec_ver bd_ht_spec_ver;
 155         enum ht_channel_width bd_bandwidth;
 156
 157         u8 bd_rt2rt_aggregation;
 158         u8 bd_rt2rt_long_slot_time;
 159         u8 rt2rt_ht_mode;
 160         u8 bd_ht_1r;
 161 };
 162
 163 extern u8 MCS_FILTER_ALL[16];
 164 extern u8 MCS_FILTER_1SS[16];
 165
 166 #define RATE_ADPT_1SS_MASK              0xFF
 167 #define RATE_ADPT_2SS_MASK              0xF0
 168 #define RATE_ADPT_MCS32_MASK            0x01
 169
 170 enum ht_aggre_size {
 171         HT_AGG_SIZE_8K = 0,
 172         HT_AGG_SIZE_16K = 1,
 173         HT_AGG_SIZE_32K = 2,
 174         HT_AGG_SIZE_64K = 3,
 175 };
 176
 177 enum ht_iot_peer {
 178         HT_IOT_PEER_UNKNOWN = 0,
 179         HT_IOT_PEER_REALTEK = 1,
 180         HT_IOT_PEER_REALTEK_92SE = 2,
 181         HT_IOT_PEER_BROADCOM = 3,
 182         HT_IOT_PEER_RALINK = 4,
 183         HT_IOT_PEER_ATHEROS = 5,
 184         HT_IOT_PEER_CISCO = 6,
 185         HT_IOT_PEER_MARVELL = 7,
 186         HT_IOT_PEER_92U_SOFTAP = 8,
 187         HT_IOT_PEER_SELF_SOFTAP = 9,
 188         HT_IOT_PEER_AIRGO = 10,
 189         HT_IOT_PEER_MAX = 11,
 190 };
 191
 192 enum ht_iot_action {
 193         HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
 194         HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,
 195         HT_IOT_ACT_DISABLE_MCS14 = 0x00000004,
 196         HT_IOT_ACT_DISABLE_MCS15 = 0x00000008,
 197         HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010,
 198         HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020,
 199         HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040,
 200         HT_IOT_ACT_CDD_FSYNC = 0x00000080,
 201         HT_IOT_ACT_PURE_N_MODE = 0x00000100,
 202         HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200,
 203         HT_IOT_ACT_FORCED_RTS = 0x00000400,
 204         HT_IOT_ACT_AMSDU_ENABLE = 0x00000800,
 205         HT_IOT_ACT_REJECT_ADDBA_REQ = 0x00001000,
 206         HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT = 0x00002000,
 207         HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00004000,
 208
 209         HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000,
 210         HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000,
 211         HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000,
 212         HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000,
 213         HT_IOT_ACT_TX_NO_AGGREGATION = 0x00100000,
 214         HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000,
 215
 216         HT_IOT_ACT_MID_HIGHPOWER = 0x00400000,
 217         HT_IOT_ACT_NULL_DATA_POWER_SAVING = 0x00800000,
 218
 219         HT_IOT_ACT_DISABLE_CCK_RATE = 0x01000000,
 220         HT_IOT_ACT_FORCED_ENABLE_BE_TXOP = 0x02000000,
 221         HT_IOT_ACT_WA_IOT_Broadcom = 0x04000000,
 222
 223         HT_IOT_ACT_DISABLE_RX_40MHZ_SHORT_GI = 0x08000000,
 224
 225 };
 226
 227 enum ht_iot_rafunc {
 228         HT_IOT_RAFUNC_DISABLE_ALL = 0x00,
 229         HT_IOT_RAFUNC_PEER_1R = 0x01,
 230         HT_IOT_RAFUNC_TX_AMSDU = 0x02,
 231 };
 232
 233 enum rt_ht_capability {
 234         RT_HT_CAP_USE_TURBO_AGGR = 0x01,
 235         RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
 236         RT_HT_CAP_USE_AMPDU = 0x04,
 237         RT_HT_CAP_USE_WOW = 0x8,
 238         RT_HT_CAP_USE_SOFTAP = 0x10,
 239         RT_HT_CAP_USE_92SE = 0x20,
 240 };
 241
 242 #endif