drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright 2023 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef __AMDGPU_UMSCH_MM_H__
  26 #define __AMDGPU_UMSCH_MM_H__
  27
  28 enum UMSCH_SWIP_ENGINE_TYPE {
  29         UMSCH_SWIP_ENGINE_TYPE_VCN0 = 0,
  30         UMSCH_SWIP_ENGINE_TYPE_VCN1 = 1,
  31         UMSCH_SWIP_ENGINE_TYPE_VCN = 2,
  32         UMSCH_SWIP_ENGINE_TYPE_VPE = 3,
  33         UMSCH_SWIP_ENGINE_TYPE_MAX
  34 };
  35
  36 enum UMSCH_CONTEXT_PRIORITY_LEVEL {
  37         CONTEXT_PRIORITY_LEVEL_IDLE = 0,
  38         CONTEXT_PRIORITY_LEVEL_NORMAL = 1,
  39         CONTEXT_PRIORITY_LEVEL_FOCUS = 2,
  40         CONTEXT_PRIORITY_LEVEL_REALTIME = 3,
  41         CONTEXT_PRIORITY_NUM_LEVELS
  42 };
  43
  44 struct umsch_mm_set_resource_input {
  45         uint32_t vmid_mask_mm_vcn;
  46         uint32_t vmid_mask_mm_vpe;
  47         uint32_t collaboration_mask_vpe;
  48         uint32_t logging_vmid;
  49         uint32_t engine_mask;
  50         union {
  51                 struct {
  52                         uint32_t disable_reset : 1;
  53                         uint32_t disable_umsch_mm_log : 1;
  54                         uint32_t use_rs64mem_for_proc_ctx_csa : 1;
  55                         uint32_t reserved : 29;
  56                 };
  57                 uint32_t uint32_all;
  58         };
  59 };
  60
  61 struct amdgpu_umsch_fwlog {
  62         uint32_t rptr;
  63         uint32_t wptr;
  64         uint32_t buffer_size;
  65         uint32_t header_size;
  66         uint32_t wrapped;
  67 };
  68
  69 struct umsch_mm_add_queue_input {
  70         uint32_t process_id;
  71         uint64_t page_table_base_addr;
  72         uint64_t process_va_start;
  73         uint64_t process_va_end;
  74         uint64_t process_quantum;
  75         uint64_t process_csa_addr;
  76         uint64_t context_quantum;
  77         uint64_t context_csa_addr;
  78         uint32_t inprocess_context_priority;
  79         enum UMSCH_CONTEXT_PRIORITY_LEVEL context_global_priority_level;
  80         uint32_t doorbell_offset_0;
  81         uint32_t doorbell_offset_1;
  82         enum UMSCH_SWIP_ENGINE_TYPE engine_type;
  83         uint32_t affinity;
  84         uint64_t mqd_addr;
  85         uint64_t h_context;
  86         uint64_t h_queue;
  87         uint32_t vm_context_cntl;
  88
  89         uint32_t process_csa_array_index;
  90         uint32_t context_csa_array_index;
  91
  92         struct {
  93                 uint32_t is_context_suspended : 1;
  94                 uint32_t collaboration_mode : 1;
  95                 uint32_t reserved : 30;
  96         };
  97 };
  98
  99 struct umsch_mm_remove_queue_input {
 100         uint32_t doorbell_offset_0;
 101         uint32_t doorbell_offset_1;
 102         uint64_t context_csa_addr;
 103         uint32_t context_csa_array_index;
 104 };
 105
 106 struct MQD_INFO {
 107         uint32_t rb_base_hi;
 108         uint32_t rb_base_lo;
 109         uint32_t rb_size;
 110         uint32_t wptr_val;
 111         uint32_t rptr_val;
 112         uint32_t unmapped;
 113         uint32_t vmid;
 114 };
 115
 116 struct amdgpu_umsch_mm;
 117
 118 struct umsch_mm_funcs {
 119         int (*set_hw_resources)(struct amdgpu_umsch_mm *umsch);
 120         int (*add_queue)(struct amdgpu_umsch_mm *umsch,
 121                          struct umsch_mm_add_queue_input *input);
 122         int (*remove_queue)(struct amdgpu_umsch_mm *umsch,
 123                             struct umsch_mm_remove_queue_input *input);
 124         int (*set_regs)(struct amdgpu_umsch_mm *umsch);
 125         int (*init_microcode)(struct amdgpu_umsch_mm *umsch);
 126         int (*load_microcode)(struct amdgpu_umsch_mm *umsch);
 127         int (*ring_init)(struct amdgpu_umsch_mm *umsch);
 128         int (*ring_start)(struct amdgpu_umsch_mm *umsch);
 129         int (*ring_stop)(struct amdgpu_umsch_mm *umsch);
 130         int (*ring_fini)(struct amdgpu_umsch_mm *umsch);
 131 };
 132
 133 struct amdgpu_umsch_mm {
 134         struct amdgpu_ring              ring;
 135
 136         uint32_t                        rb_wptr;
 137         uint32_t                        rb_rptr;
 138
 139         const struct umsch_mm_funcs     *funcs;
 140
 141         const struct firmware           *fw;
 142         uint32_t                        fw_version;
 143         uint32_t                        feature_version;
 144
 145         struct amdgpu_bo                *ucode_fw_obj;
 146         uint64_t                        ucode_fw_gpu_addr;
 147         uint32_t                        *ucode_fw_ptr;
 148         uint64_t                        irq_start_addr;
 149         uint64_t                        uc_start_addr;
 150         uint32_t                        ucode_size;
 151
 152         struct amdgpu_bo                *data_fw_obj;
 153         uint64_t                        data_fw_gpu_addr;
 154         uint32_t                        *data_fw_ptr;
 155         uint64_t                        data_start_addr;
 156         uint32_t                        data_size;
 157
 158         struct amdgpu_bo                *cmd_buf_obj;
 159         uint64_t                        cmd_buf_gpu_addr;
 160         uint32_t                        *cmd_buf_ptr;
 161         uint32_t                        *cmd_buf_curr_ptr;
 162
 163         uint32_t                        wb_index;
 164         uint64_t                        sch_ctx_gpu_addr;
 165         uint32_t                        *sch_ctx_cpu_addr;
 166
 167         uint32_t                        vmid_mask_mm_vcn;
 168         uint32_t                        vmid_mask_mm_vpe;
 169         uint32_t                        engine_mask;
 170         uint32_t                        vcn0_hqd_mask;
 171         uint32_t                        vcn1_hqd_mask;
 172         uint32_t                        vcn_hqd_mask[2];
 173         uint32_t                        vpe_hqd_mask;
 174         uint32_t                        agdb_index[CONTEXT_PRIORITY_NUM_LEVELS];
 175
 176         struct mutex                    mutex_hidden;
 177         struct amdgpu_bo                *dbglog_bo;
 178         void                            *log_cpu_addr;
 179         uint64_t                        log_gpu_addr;
 180         uint32_t                        mem_size;
 181         uint32_t                        log_offset;
 182 };
 183
 184 int amdgpu_umsch_mm_submit_pkt(struct amdgpu_umsch_mm *umsch, void *pkt, int ndws);
 185 int amdgpu_umsch_mm_query_fence(struct amdgpu_umsch_mm *umsch);
 186
 187 int amdgpu_umsch_mm_init_microcode(struct amdgpu_umsch_mm *umsch);
 188 int amdgpu_umsch_mm_allocate_ucode_buffer(struct amdgpu_umsch_mm *umsch);
 189 int amdgpu_umsch_mm_allocate_ucode_data_buffer(struct amdgpu_umsch_mm *umsch);
 190
 191 int amdgpu_umsch_mm_psp_execute_cmd_buf(struct amdgpu_umsch_mm *umsch);
 192
 193 int amdgpu_umsch_mm_ring_init(struct amdgpu_umsch_mm *umsch);
 194
 195 void amdgpu_debugfs_umsch_fwlog_init(struct amdgpu_device *adev,
 196                         struct amdgpu_umsch_mm *umsch);
 197
 198 void amdgpu_umsch_fwlog_init(struct amdgpu_umsch_mm *umsch_mm);
 199
 200 #define WREG32_SOC15_UMSCH(reg, value)                                                          \
 201         do {                                                                                    \
 202                 uint32_t reg_offset = adev->reg_offset[VCN_HWIP][0][reg##_BASE_IDX] + reg;      \
 203                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {                           \
 204                         *adev->umsch_mm.cmd_buf_curr_ptr++ = (reg_offset << 2);                 \
 205                         *adev->umsch_mm.cmd_buf_curr_ptr++ = value;                             \
 206                 } else  {                                                                       \
 207                         WREG32(reg_offset, value);                                              \
 208                 }                                                                               \
 209         } while (0)
 210
 211 #define umsch_mm_set_hw_resources(umsch) \
 212         ((umsch)->funcs->set_hw_resources ? (umsch)->funcs->set_hw_resources((umsch)) : 0)
 213 #define umsch_mm_add_queue(umsch, input) \
 214         ((umsch)->funcs->add_queue ? (umsch)->funcs->add_queue((umsch), (input)) : 0)
 215 #define umsch_mm_remove_queue(umsch, input) \
 216         ((umsch)->funcs->remove_queue ? (umsch)->funcs->remove_queue((umsch), (input)) : 0)
 217
 218 #define umsch_mm_set_regs(umsch) \
 219         ((umsch)->funcs->set_regs ? (umsch)->funcs->set_regs((umsch)) : 0)
 220 #define umsch_mm_init_microcode(umsch) \
 221         ((umsch)->funcs->init_microcode ? (umsch)->funcs->init_microcode((umsch)) : 0)
 222 #define umsch_mm_load_microcode(umsch) \
 223         ((umsch)->funcs->load_microcode ? (umsch)->funcs->load_microcode((umsch)) : 0)
 224
 225 #define umsch_mm_ring_init(umsch) \
 226         ((umsch)->funcs->ring_init ? (umsch)->funcs->ring_init((umsch)) : 0)
 227 #define umsch_mm_ring_start(umsch) \
 228         ((umsch)->funcs->ring_start ? (umsch)->funcs->ring_start((umsch)) : 0)
 229 #define umsch_mm_ring_stop(umsch) \
 230         ((umsch)->funcs->ring_stop ? (umsch)->funcs->ring_stop((umsch)) : 0)
 231 #define umsch_mm_ring_fini(umsch) \
 232         ((umsch)->funcs->ring_fini ? (umsch)->funcs->ring_fini((umsch)) : 0)
 233
 234 static inline void amdgpu_umsch_mm_lock(struct amdgpu_umsch_mm *umsch)
 235 {
 236         mutex_lock(&umsch->mutex_hidden);
 237 }
 238
 239 static inline void amdgpu_umsch_mm_unlock(struct amdgpu_umsch_mm *umsch)
 240 {
 241         mutex_unlock(&umsch->mutex_hidden);
 242 }
 243
 244 extern const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block;
 245
 246 #endif