drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_i2c.h"
  30 #include "atom.h"
  31 #include "amdgpu_connectors.h"
  32 #include "amdgpu_display.h"
  33 #include "soc15_common.h"
  34 #include "gc/gc_11_0_0_offset.h"
  35 #include "gc/gc_11_0_0_sh_mask.h"
  36 #include "bif/bif_4_1_d.h"
  37 #include <asm/div64.h>
  38
  39 #include <linux/pci.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_damage_helper.h>
  43 #include <drm/drm_drv.h>
  44 #include <drm/drm_edid.h>
  45 #include <drm/drm_fb_helper.h>
  46 #include <drm/drm_gem_framebuffer_helper.h>
  47 #include <drm/drm_fourcc.h>
  48 #include <drm/drm_modeset_helper.h>
  49 #include <drm/drm_vblank.h>
  50
  51 /**
  52  * amdgpu_display_hotplug_work_func - work handler for display hotplug event
  53  *
  54  * @work: work struct pointer
  55  *
  56  * This is the hotplug event work handler (all ASICs).
  57  * The work gets scheduled from the IRQ handler if there
  58  * was a hotplug interrupt.  It walks through the connector table
  59  * and calls hotplug handler for each connector. After this, it sends
  60  * a DRM hotplug event to alert userspace.
  61  *
  62  * This design approach is required in order to defer hotplug event handling
  63  * from the IRQ handler to a work handler because hotplug handler has to use
  64  * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
  65  * sleep).
  66  */
  67 void amdgpu_display_hotplug_work_func(struct work_struct *work)
  68 {
  69         struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
  70                                                   hotplug_work.work);
  71         struct drm_device *dev = adev_to_drm(adev);
  72         struct drm_mode_config *mode_config = &dev->mode_config;
  73         struct drm_connector *connector;
  74         struct drm_connector_list_iter iter;
  75
  76         mutex_lock(&mode_config->mutex);
  77         drm_connector_list_iter_begin(dev, &iter);
  78         drm_for_each_connector_iter(connector, &iter)
  79                 amdgpu_connector_hotplug(connector);
  80         drm_connector_list_iter_end(&iter);
  81         mutex_unlock(&mode_config->mutex);
  82         /* Just fire off a uevent and let userspace tell us what to do */
  83         drm_helper_hpd_irq_event(dev);
  84 }
  85
  86 static int amdgpu_display_framebuffer_init(struct drm_device *dev,
  87                                            struct amdgpu_framebuffer *rfb,
  88                                            const struct drm_mode_fb_cmd2 *mode_cmd,
  89                                            struct drm_gem_object *obj);
  90
  91 static void amdgpu_display_flip_callback(struct dma_fence *f,
  92                                          struct dma_fence_cb *cb)
  93 {
  94         struct amdgpu_flip_work *work =
  95                 container_of(cb, struct amdgpu_flip_work, cb);
  96
  97         dma_fence_put(f);
  98         schedule_work(&work->flip_work.work);
  99 }
 100
 101 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
 102                                              struct dma_fence **f)
 103 {
 104         struct dma_fence *fence = *f;
 105
 106         if (fence == NULL)
 107                 return false;
 108
 109         *f = NULL;
 110
 111         if (!dma_fence_add_callback(fence, &work->cb,
 112                                     amdgpu_display_flip_callback))
 113                 return true;
 114
 115         dma_fence_put(fence);
 116         return false;
 117 }
 118
 119 static void amdgpu_display_flip_work_func(struct work_struct *__work)
 120 {
 121         struct delayed_work *delayed_work =
 122                 container_of(__work, struct delayed_work, work);
 123         struct amdgpu_flip_work *work =
 124                 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
 125         struct amdgpu_device *adev = work->adev;
 126         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
 127
 128         struct drm_crtc *crtc = &amdgpu_crtc->base;
 129         unsigned long flags;
 130         unsigned int i;
 131         int vpos, hpos;
 132
 133         for (i = 0; i < work->shared_count; ++i)
 134                 if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
 135                         return;
 136
 137         /* Wait until we're out of the vertical blank period before the one
 138          * targeted by the flip
 139          */
 140         if (amdgpu_crtc->enabled &&
 141             (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
 142                                                 &vpos, &hpos, NULL, NULL,
 143                                                 &crtc->hwmode)
 144              & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
 145             (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
 146             (int)(work->target_vblank -
 147                   amdgpu_get_vblank_counter_kms(crtc)) > 0) {
 148                 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
 149                 return;
 150         }
 151
 152         /* We borrow the event spin lock for protecting flip_status */
 153         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 154
 155         /* Do the flip (mmio) */
 156         adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
 157
 158         /* Set the flip status */
 159         amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
 160         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 161
 162
 163         drm_dbg_vbl(adev_to_drm(adev),
 164                     "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
 165                     amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 166
 167 }
 168
 169 /*
 170  * Handle unpin events outside the interrupt handler proper.
 171  */
 172 static void amdgpu_display_unpin_work_func(struct work_struct *__work)
 173 {
 174         struct amdgpu_flip_work *work =
 175                 container_of(__work, struct amdgpu_flip_work, unpin_work);
 176         int r;
 177
 178         /* unpin of the old buffer */
 179         r = amdgpu_bo_reserve(work->old_abo, true);
 180         if (likely(r == 0)) {
 181                 amdgpu_bo_unpin(work->old_abo);
 182                 amdgpu_bo_unreserve(work->old_abo);
 183         } else
 184                 DRM_ERROR("failed to reserve buffer after flip\n");
 185
 186         amdgpu_bo_unref(&work->old_abo);
 187         kfree(work->shared);
 188         kfree(work);
 189 }
 190
 191 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
 192                                 struct drm_framebuffer *fb,
 193                                 struct drm_pending_vblank_event *event,
 194                                 uint32_t page_flip_flags, uint32_t target,
 195                                 struct drm_modeset_acquire_ctx *ctx)
 196 {
 197         struct drm_device *dev = crtc->dev;
 198         struct amdgpu_device *adev = drm_to_adev(dev);
 199         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 200         struct drm_gem_object *obj;
 201         struct amdgpu_flip_work *work;
 202         struct amdgpu_bo *new_abo;
 203         unsigned long flags;
 204         u64 tiling_flags;
 205         int i, r;
 206
 207         work = kzalloc(sizeof(*work), GFP_KERNEL);
 208         if (work == NULL)
 209                 return -ENOMEM;
 210
 211         INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
 212         INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
 213
 214         work->event = event;
 215         work->adev = adev;
 216         work->crtc_id = amdgpu_crtc->crtc_id;
 217         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 218
 219         /* schedule unpin of the old buffer */
 220         obj = crtc->primary->fb->obj[0];
 221
 222         /* take a reference to the old object */
 223         work->old_abo = gem_to_amdgpu_bo(obj);
 224         amdgpu_bo_ref(work->old_abo);
 225
 226         obj = fb->obj[0];
 227         new_abo = gem_to_amdgpu_bo(obj);
 228
 229         /* pin the new buffer */
 230         r = amdgpu_bo_reserve(new_abo, false);
 231         if (unlikely(r != 0)) {
 232                 DRM_ERROR("failed to reserve new abo buffer before flip\n");
 233                 goto cleanup;
 234         }
 235
 236         if (!adev->enable_virtual_display) {
 237                 new_abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 238                 r = amdgpu_bo_pin(new_abo,
 239                                   amdgpu_display_supported_domains(adev, new_abo->flags));
 240                 if (unlikely(r != 0)) {
 241                         DRM_ERROR("failed to pin new abo buffer before flip\n");
 242                         goto unreserve;
 243                 }
 244         }
 245
 246         r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
 247         if (unlikely(r != 0)) {
 248                 DRM_ERROR("%p bind failed\n", new_abo);
 249                 goto unpin;
 250         }
 251
 252         r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE,
 253                                 &work->shared_count,
 254                                 &work->shared);
 255         if (unlikely(r != 0)) {
 256                 DRM_ERROR("failed to get fences for buffer\n");
 257                 goto unpin;
 258         }
 259
 260         amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
 261         amdgpu_bo_unreserve(new_abo);
 262
 263         if (!adev->enable_virtual_display)
 264                 work->base = amdgpu_bo_gpu_offset(new_abo);
 265         work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
 266                 amdgpu_get_vblank_counter_kms(crtc);
 267
 268         /* we borrow the event spin lock for protecting flip_wrok */
 269         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 270         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
 271                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 272                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 273                 r = -EBUSY;
 274                 goto pflip_cleanup;
 275         }
 276
 277         amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
 278         amdgpu_crtc->pflip_works = work;
 279
 280
 281         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
 282                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 283         /* update crtc fb */
 284         crtc->primary->fb = fb;
 285         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 286         amdgpu_display_flip_work_func(&work->flip_work.work);
 287         return 0;
 288
 289 pflip_cleanup:
 290         if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
 291                 DRM_ERROR("failed to reserve new abo in error path\n");
 292                 goto cleanup;
 293         }
 294 unpin:
 295         if (!adev->enable_virtual_display)
 296                 amdgpu_bo_unpin(new_abo);
 297
 298 unreserve:
 299         amdgpu_bo_unreserve(new_abo);
 300
 301 cleanup:
 302         amdgpu_bo_unref(&work->old_abo);
 303         for (i = 0; i < work->shared_count; ++i)
 304                 dma_fence_put(work->shared[i]);
 305         kfree(work->shared);
 306         kfree(work);
 307
 308         return r;
 309 }
 310
 311 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
 312                                    struct drm_modeset_acquire_ctx *ctx)
 313 {
 314         struct drm_device *dev;
 315         struct amdgpu_device *adev;
 316         struct drm_crtc *crtc;
 317         bool active = false;
 318         int ret;
 319
 320         if (!set || !set->crtc)
 321                 return -EINVAL;
 322
 323         dev = set->crtc->dev;
 324
 325         ret = pm_runtime_get_sync(dev->dev);
 326         if (ret < 0)
 327                 goto out;
 328
 329         ret = drm_crtc_helper_set_config(set, ctx);
 330
 331         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 332                 if (crtc->enabled)
 333                         active = true;
 334
 335         pm_runtime_mark_last_busy(dev->dev);
 336
 337         adev = drm_to_adev(dev);
 338         /* if we have active crtcs and we don't have a power ref,
 339          * take the current one
 340          */
 341         if (active && !adev->have_disp_power_ref) {
 342                 adev->have_disp_power_ref = true;
 343                 return ret;
 344         }
 345         /* if we have no active crtcs, then go to
 346          * drop the power ref we got before
 347          */
 348         if (!active && adev->have_disp_power_ref)
 349                 adev->have_disp_power_ref = false;
 350 out:
 351         /* drop the power reference we got coming in here */
 352         pm_runtime_put_autosuspend(dev->dev);
 353         return ret;
 354 }
 355
 356 static const char *encoder_names[41] = {
 357         "NONE",
 358         "INTERNAL_LVDS",
 359         "INTERNAL_TMDS1",
 360         "INTERNAL_TMDS2",
 361         "INTERNAL_DAC1",
 362         "INTERNAL_DAC2",
 363         "INTERNAL_SDVOA",
 364         "INTERNAL_SDVOB",
 365         "SI170B",
 366         "CH7303",
 367         "CH7301",
 368         "INTERNAL_DVO1",
 369         "EXTERNAL_SDVOA",
 370         "EXTERNAL_SDVOB",
 371         "TITFP513",
 372         "INTERNAL_LVTM1",
 373         "VT1623",
 374         "HDMI_SI1930",
 375         "HDMI_INTERNAL",
 376         "INTERNAL_KLDSCP_TMDS1",
 377         "INTERNAL_KLDSCP_DVO1",
 378         "INTERNAL_KLDSCP_DAC1",
 379         "INTERNAL_KLDSCP_DAC2",
 380         "SI178",
 381         "MVPU_FPGA",
 382         "INTERNAL_DDI",
 383         "VT1625",
 384         "HDMI_SI1932",
 385         "DP_AN9801",
 386         "DP_DP501",
 387         "INTERNAL_UNIPHY",
 388         "INTERNAL_KLDSCP_LVTMA",
 389         "INTERNAL_UNIPHY1",
 390         "INTERNAL_UNIPHY2",
 391         "NUTMEG",
 392         "TRAVIS",
 393         "INTERNAL_VCE",
 394         "INTERNAL_UNIPHY3",
 395         "HDMI_ANX9805",
 396         "INTERNAL_AMCLK",
 397         "VIRTUAL",
 398 };
 399
 400 static const char *hpd_names[6] = {
 401         "HPD1",
 402         "HPD2",
 403         "HPD3",
 404         "HPD4",
 405         "HPD5",
 406         "HPD6",
 407 };
 408
 409 void amdgpu_display_print_display_setup(struct drm_device *dev)
 410 {
 411         struct drm_connector *connector;
 412         struct amdgpu_connector *amdgpu_connector;
 413         struct drm_encoder *encoder;
 414         struct amdgpu_encoder *amdgpu_encoder;
 415         struct drm_connector_list_iter iter;
 416         uint32_t devices;
 417         int i = 0;
 418
 419         drm_connector_list_iter_begin(dev, &iter);
 420         DRM_INFO("AMDGPU Display Connectors\n");
 421         drm_for_each_connector_iter(connector, &iter) {
 422                 amdgpu_connector = to_amdgpu_connector(connector);
 423                 DRM_INFO("Connector %d:\n", i);
 424                 DRM_INFO("  %s\n", connector->name);
 425                 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
 426                         DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
 427                 if (amdgpu_connector->ddc_bus) {
 428                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 429                                  amdgpu_connector->ddc_bus->rec.mask_clk_reg,
 430                                  amdgpu_connector->ddc_bus->rec.mask_data_reg,
 431                                  amdgpu_connector->ddc_bus->rec.a_clk_reg,
 432                                  amdgpu_connector->ddc_bus->rec.a_data_reg,
 433                                  amdgpu_connector->ddc_bus->rec.en_clk_reg,
 434                                  amdgpu_connector->ddc_bus->rec.en_data_reg,
 435                                  amdgpu_connector->ddc_bus->rec.y_clk_reg,
 436                                  amdgpu_connector->ddc_bus->rec.y_data_reg);
 437                         if (amdgpu_connector->router.ddc_valid)
 438                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 439                                          amdgpu_connector->router.ddc_mux_control_pin,
 440                                          amdgpu_connector->router.ddc_mux_state);
 441                         if (amdgpu_connector->router.cd_valid)
 442                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 443                                          amdgpu_connector->router.cd_mux_control_pin,
 444                                          amdgpu_connector->router.cd_mux_state);
 445                 } else {
 446                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 447                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 448                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 449                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 450                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 451                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 452                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to [email protected]\n");
 453                 }
 454                 DRM_INFO("  Encoders:\n");
 455                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 456                         amdgpu_encoder = to_amdgpu_encoder(encoder);
 457                         devices = amdgpu_encoder->devices & amdgpu_connector->devices;
 458                         if (devices) {
 459                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 460                                         DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 461                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 462                                         DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 463                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 464                                         DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 465                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 466                                         DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 467                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 468                                         DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 469                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 470                                         DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 471                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 472                                         DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 473                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 474                                         DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 475                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 476                                         DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 477                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 478                                         DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 479                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 480                                         DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 481                         }
 482                 }
 483                 i++;
 484         }
 485         drm_connector_list_iter_end(&iter);
 486 }
 487
 488 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
 489                               bool use_aux)
 490 {
 491         u8 out = 0x0;
 492         u8 buf[8];
 493         int ret;
 494         struct i2c_msg msgs[] = {
 495                 {
 496                         .addr = DDC_ADDR,
 497                         .flags = 0,
 498                         .len = 1,
 499                         .buf = &out,
 500                 },
 501                 {
 502                         .addr = DDC_ADDR,
 503                         .flags = I2C_M_RD,
 504                         .len = 8,
 505                         .buf = buf,
 506                 }
 507         };
 508
 509         /* on hw with routers, select right port */
 510         if (amdgpu_connector->router.ddc_valid)
 511                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 512
 513         if (use_aux)
 514                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
 515         else
 516                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
 517
 518         if (ret != 2)
 519                 /* Couldn't find an accessible DDC on this connector */
 520                 return false;
 521         /* Probe also for valid EDID header
 522          * EDID header starts with:
 523          * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
 524          * Only the first 6 bytes must be valid as
 525          * drm_edid_block_valid() can fix the last 2 bytes
 526          */
 527         if (drm_edid_header_is_valid(buf) < 6) {
 528                 /* Couldn't find an accessible EDID on this
 529                  * connector
 530                  */
 531                 return false;
 532         }
 533         return true;
 534 }
 535
 536 static int amdgpu_dirtyfb(struct drm_framebuffer *fb, struct drm_file *file,
 537                           unsigned int flags, unsigned int color,
 538                           struct drm_clip_rect *clips, unsigned int num_clips)
 539 {
 540
 541         if (file)
 542                 return -ENOSYS;
 543
 544         return drm_atomic_helper_dirtyfb(fb, file, flags, color, clips,
 545                                          num_clips);
 546 }
 547
 548 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
 549         .destroy = drm_gem_fb_destroy,
 550         .create_handle = drm_gem_fb_create_handle,
 551 };
 552
 553 static const struct drm_framebuffer_funcs amdgpu_fb_funcs_atomic = {
 554         .destroy = drm_gem_fb_destroy,
 555         .create_handle = drm_gem_fb_create_handle,
 556         .dirty = amdgpu_dirtyfb
 557 };
 558
 559 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
 560                                           uint64_t bo_flags)
 561 {
 562         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 563
 564 #if defined(CONFIG_DRM_AMD_DC)
 565         /*
 566          * if amdgpu_bo_support_uswc returns false it means that USWC mappings
 567          * is not supported for this board. But this mapping is required
 568          * to avoid hang caused by placement of scanout BO in GTT on certain
 569          * APUs. So force the BO placement to VRAM in case this architecture
 570          * will not allow USWC mappings.
 571          * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
 572          */
 573         if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
 574             amdgpu_bo_support_uswc(bo_flags) &&
 575             adev->dc_enabled &&
 576             adev->mode_info.gpu_vm_support)
 577                 domain |= AMDGPU_GEM_DOMAIN_GTT;
 578 #endif
 579
 580         return domain;
 581 }
 582
 583 static const struct drm_format_info dcc_formats[] = {
 584         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 585           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 586          { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
 587           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 588         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
 589           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 590            .has_alpha = true, },
 591         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
 592           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 593           .has_alpha = true, },
 594         { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
 595           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 596           .has_alpha = true, },
 597         { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
 598           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 599         { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
 600           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 601         { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
 602           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 603           .has_alpha = true, },
 604         { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
 605           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 606           .has_alpha = true, },
 607         { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
 608           .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 609 };
 610
 611 static const struct drm_format_info dcc_retile_formats[] = {
 612         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
 613           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 614          { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
 615           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 616         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
 617           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 618            .has_alpha = true, },
 619         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
 620           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 621           .has_alpha = true, },
 622         { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
 623           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 624           .has_alpha = true, },
 625         { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
 626           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 627         { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
 628           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 629         { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
 630           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 631           .has_alpha = true, },
 632         { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
 633           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 634           .has_alpha = true, },
 635         { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
 636           .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 637 };
 638
 639 static const struct drm_format_info *
 640 lookup_format_info(const struct drm_format_info formats[],
 641                   int num_formats, u32 format)
 642 {
 643         int i;
 644
 645         for (i = 0; i < num_formats; i++) {
 646                 if (formats[i].format == format)
 647                         return &formats[i];
 648         }
 649
 650         return NULL;
 651 }
 652
 653 const struct drm_format_info *
 654 amdgpu_lookup_format_info(u32 format, uint64_t modifier)
 655 {
 656         if (!IS_AMD_FMT_MOD(modifier))
 657                 return NULL;
 658
 659         if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) < AMD_FMT_MOD_TILE_VER_GFX9 ||
 660             AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX12)
 661                 return NULL;
 662
 663         if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
 664                 return lookup_format_info(dcc_retile_formats,
 665                                           ARRAY_SIZE(dcc_retile_formats),
 666                                           format);
 667
 668         if (AMD_FMT_MOD_GET(DCC, modifier))
 669                 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
 670                                           format);
 671
 672         /* returning NULL will cause the default format structs to be used. */
 673         return NULL;
 674 }
 675
 676
 677 /*
 678  * Tries to extract the renderable DCC offset from the opaque metadata attached
 679  * to the buffer.
 680  */
 681 static int
 682 extract_render_dcc_offset(struct amdgpu_device *adev,
 683                           struct drm_gem_object *obj,
 684                           uint64_t *offset)
 685 {
 686         struct amdgpu_bo *rbo;
 687         int r = 0;
 688         uint32_t metadata[10]; /* Something that fits a descriptor + header. */
 689         uint32_t size;
 690
 691         rbo = gem_to_amdgpu_bo(obj);
 692         r = amdgpu_bo_reserve(rbo, false);
 693
 694         if (unlikely(r)) {
 695                 /* Don't show error message when returning -ERESTARTSYS */
 696                 if (r != -ERESTARTSYS)
 697                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
 698                 return r;
 699         }
 700
 701         r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
 702         amdgpu_bo_unreserve(rbo);
 703
 704         if (r)
 705                 return r;
 706
 707         /*
 708          * The first word is the metadata version, and we need space for at least
 709          * the version + pci vendor+device id + 8 words for a descriptor.
 710          */
 711         if (size < 40  || metadata[0] != 1)
 712                 return -EINVAL;
 713
 714         if (adev->family >= AMDGPU_FAMILY_NV) {
 715                 /* resource word 6/7 META_DATA_ADDRESS{_LO} */
 716                 *offset = ((u64)metadata[9] << 16u) |
 717                           ((metadata[8] & 0xFF000000u) >> 16);
 718         } else {
 719                 /* resource word 5/7 META_DATA_ADDRESS */
 720                 *offset = ((u64)metadata[9] << 8u) |
 721                           ((u64)(metadata[7] & 0x1FE0000u) << 23);
 722         }
 723
 724         return 0;
 725 }
 726
 727 static int convert_tiling_flags_to_modifier_gfx12(struct amdgpu_framebuffer *afb)
 728 {
 729         u64 modifier = 0;
 730         int swizzle_mode = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE);
 731
 732         if (!swizzle_mode) {
 733                 modifier = DRM_FORMAT_MOD_LINEAR;
 734         } else {
 735                 int max_comp_block =
 736                         AMDGPU_TILING_GET(afb->tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);
 737
 738                 modifier =
 739                         AMD_FMT_MOD |
 740                         AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) |
 741                         AMD_FMT_MOD_SET(TILE, swizzle_mode) |
 742                         AMD_FMT_MOD_SET(DCC, afb->gfx12_dcc) |
 743                         AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_comp_block);
 744         }
 745
 746         afb->base.modifier = modifier;
 747         afb->base.flags |= DRM_MODE_FB_MODIFIERS;
 748         return 0;
 749 }
 750
 751 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 752 {
 753         struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
 754         uint64_t modifier = 0;
 755         int num_pipes = 0;
 756         int num_pkrs = 0;
 757
 758         num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
 759         num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes;
 760
 761         if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
 762                 modifier = DRM_FORMAT_MOD_LINEAR;
 763         } else {
 764                 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
 765                 bool has_xor = swizzle >= 16;
 766                 int block_size_bits;
 767                 int version;
 768                 int pipe_xor_bits = 0;
 769                 int bank_xor_bits = 0;
 770                 int packers = 0;
 771                 int rb = 0;
 772                 int pipes = ilog2(num_pipes);
 773                 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
 774
 775                 switch (swizzle >> 2) {
 776                 case 0: /* 256B */
 777                         block_size_bits = 8;
 778                         break;
 779                 case 1: /* 4KiB */
 780                 case 5: /* 4KiB _X */
 781                         block_size_bits = 12;
 782                         break;
 783                 case 2: /* 64KiB */
 784                 case 4: /* 64 KiB _T */
 785                 case 6: /* 64 KiB _X */
 786                         block_size_bits = 16;
 787                         break;
 788                 case 7: /* 256 KiB */
 789                         block_size_bits = 18;
 790                         break;
 791                 default:
 792                         /* RESERVED or VAR */
 793                         return -EINVAL;
 794                 }
 795
 796                 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0))
 797                         version = AMD_FMT_MOD_TILE_VER_GFX11;
 798                 else if (amdgpu_ip_version(adev, GC_HWIP, 0) >=
 799                          IP_VERSION(10, 3, 0))
 800                         version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 801                 else if (amdgpu_ip_version(adev, GC_HWIP, 0) >=
 802                          IP_VERSION(10, 0, 0))
 803                         version = AMD_FMT_MOD_TILE_VER_GFX10;
 804                 else
 805                         version = AMD_FMT_MOD_TILE_VER_GFX9;
 806
 807                 switch (swizzle & 3) {
 808                 case 0: /* Z microtiling */
 809                         return -EINVAL;
 810                 case 1: /* S microtiling */
 811                         if (amdgpu_ip_version(adev, GC_HWIP, 0) <
 812                             IP_VERSION(11, 0, 0)) {
 813                                 if (!has_xor)
 814                                         version = AMD_FMT_MOD_TILE_VER_GFX9;
 815                         }
 816                         break;
 817                 case 2:
 818                         if (amdgpu_ip_version(adev, GC_HWIP, 0) <
 819                             IP_VERSION(11, 0, 0)) {
 820                                 if (!has_xor && afb->base.format->cpp[0] != 4)
 821                                         version = AMD_FMT_MOD_TILE_VER_GFX9;
 822                         }
 823                         break;
 824                 case 3:
 825                         break;
 826                 }
 827
 828                 if (has_xor) {
 829                         if (num_pipes == num_pkrs && num_pkrs == 0) {
 830                                 DRM_ERROR("invalid number of pipes and packers\n");
 831                                 return -EINVAL;
 832                         }
 833
 834                         switch (version) {
 835                         case AMD_FMT_MOD_TILE_VER_GFX11:
 836                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 837                                 packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
 838                                 break;
 839                         case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
 840                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 841                                 packers = min(block_size_bits - 8 - pipe_xor_bits,
 842                                               ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
 843                                 break;
 844                         case AMD_FMT_MOD_TILE_VER_GFX10:
 845                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 846                                 break;
 847                         case AMD_FMT_MOD_TILE_VER_GFX9:
 848                                 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
 849                                      ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
 850                                 pipe_xor_bits = min(block_size_bits - 8, pipes +
 851                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
 852                                 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
 853                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
 854                                 break;
 855                         }
 856                 }
 857
 858                 modifier = AMD_FMT_MOD |
 859                            AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
 860                            AMD_FMT_MOD_SET(TILE_VERSION, version) |
 861                            AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
 862                            AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
 863                            AMD_FMT_MOD_SET(PACKERS, packers);
 864
 865                 if (dcc_offset != 0) {
 866                         bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
 867                         bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 868                         const struct drm_format_info *format_info;
 869                         u64 render_dcc_offset;
 870
 871                         /* Enable constant encode on RAVEN2 and later. */
 872                         bool dcc_constant_encode =
 873                                 (adev->asic_type > CHIP_RAVEN ||
 874                                  (adev->asic_type == CHIP_RAVEN &&
 875                                   adev->external_rev_id >= 0x81)) &&
 876                                 amdgpu_ip_version(adev, GC_HWIP, 0) <
 877                                         IP_VERSION(11, 0, 0);
 878
 879                         int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
 880                                               dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
 881                                               AMD_FMT_MOD_DCC_BLOCK_256B;
 882
 883                         modifier |= AMD_FMT_MOD_SET(DCC, 1) |
 884                                     AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
 885                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
 886                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
 887                                     AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
 888
 889                         afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
 890                         afb->base.pitches[1] =
 891                                 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
 892
 893                         /*
 894                          * If the userspace driver uses retiling the tiling flags do not contain
 895                          * info on the renderable DCC buffer. Luckily the opaque metadata contains
 896                          * the info so we can try to extract it. The kernel does not use this info
 897                          * but we should convert it to a modifier plane for getfb2, so the
 898                          * userspace driver that gets it doesn't have to juggle around another DCC
 899                          * plane internally.
 900                          */
 901                         if (extract_render_dcc_offset(adev, afb->base.obj[0],
 902                                                       &render_dcc_offset) == 0 &&
 903                             render_dcc_offset != 0 &&
 904                             render_dcc_offset != afb->base.offsets[1] &&
 905                             render_dcc_offset < UINT_MAX) {
 906                                 uint32_t dcc_block_bits;  /* of base surface data */
 907
 908                                 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
 909                                 afb->base.offsets[2] = render_dcc_offset;
 910
 911                                 if (adev->family >= AMDGPU_FAMILY_NV) {
 912                                         int extra_pipe = 0;
 913
 914                                         if ((amdgpu_ip_version(adev, GC_HWIP,
 915                                                                0) >=
 916                                              IP_VERSION(10, 3, 0)) &&
 917                                             pipes == packers && pipes > 1)
 918                                                 extra_pipe = 1;
 919
 920                                         dcc_block_bits = max(20, 16 + pipes + extra_pipe);
 921                                 } else {
 922                                         modifier |= AMD_FMT_MOD_SET(RB, rb) |
 923                                                     AMD_FMT_MOD_SET(PIPE, pipes);
 924                                         dcc_block_bits = max(20, 18 + rb);
 925                                 }
 926
 927                                 dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
 928                                 afb->base.pitches[2] = ALIGN(afb->base.width,
 929                                                              1u << ((dcc_block_bits + 1) / 2));
 930                         }
 931                         format_info = amdgpu_lookup_format_info(afb->base.format->format,
 932                                                                 modifier);
 933                         if (!format_info)
 934                                 return -EINVAL;
 935
 936                         afb->base.format = format_info;
 937                 }
 938         }
 939
 940         afb->base.modifier = modifier;
 941         afb->base.flags |= DRM_MODE_FB_MODIFIERS;
 942         return 0;
 943 }
 944
 945 /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */
 946 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
 947 {
 948         u64 micro_tile_mode;
 949
 950         if (AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) == 1) /* LINEAR_ALIGNED */
 951                 return 0;
 952
 953         micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
 954         switch (micro_tile_mode) {
 955         case 0: /* DISPLAY */
 956         case 3: /* RENDER */
 957                 return 0;
 958         default:
 959                 drm_dbg_kms(afb->base.dev,
 960                             "Micro tile mode %llu not supported for scanout\n",
 961                             micro_tile_mode);
 962                 return -EINVAL;
 963         }
 964 }
 965
 966 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp,
 967                                  unsigned int *width, unsigned int *height)
 968 {
 969         unsigned int cpp_log2 = ilog2(cpp);
 970         unsigned int pixel_log2 = block_log2 - cpp_log2;
 971         unsigned int width_log2 = (pixel_log2 + 1) / 2;
 972         unsigned int height_log2 = pixel_log2 - width_log2;
 973
 974         *width = 1 << width_log2;
 975         *height = 1 << height_log2;
 976 }
 977
 978 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
 979                                        bool pipe_aligned)
 980 {
 981         unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
 982
 983         switch (ver) {
 984         case AMD_FMT_MOD_TILE_VER_GFX9: {
 985                 /*
 986                  * TODO: for pipe aligned we may need to check the alignment of the
 987                  * total size of the surface, which may need to be bigger than the
 988                  * natural alignment due to some HW workarounds
 989                  */
 990                 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
 991         }
 992         case AMD_FMT_MOD_TILE_VER_GFX10:
 993         case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
 994         case AMD_FMT_MOD_TILE_VER_GFX11: {
 995                 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
 996
 997                 if (ver >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
 998                     AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
 999                         ++pipes_log2;
1000
1001                 return max(8 + (pipe_aligned ? pipes_log2 : 0), 12);
1002         }
1003         default:
1004                 return 0;
1005         }
1006 }
1007
1008 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane,
1009                                        const struct drm_format_info *format,
1010                                        unsigned int block_width, unsigned int block_height,
1011                                        unsigned int block_size_log2)
1012 {
1013         unsigned int width = rfb->base.width /
1014                 ((plane && plane < format->num_planes) ? format->hsub : 1);
1015         unsigned int height = rfb->base.height /
1016                 ((plane && plane < format->num_planes) ? format->vsub : 1);
1017         unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1;
1018         unsigned int block_pitch = block_width * cpp;
1019         unsigned int min_pitch = ALIGN(width * cpp, block_pitch);
1020         unsigned int block_size = 1 << block_size_log2;
1021         uint64_t size;
1022
1023         if (rfb->base.pitches[plane] % block_pitch) {
1024                 drm_dbg_kms(rfb->base.dev,
1025                             "pitch %d for plane %d is not a multiple of block pitch %d\n",
1026                             rfb->base.pitches[plane], plane, block_pitch);
1027                 return -EINVAL;
1028         }
1029         if (rfb->base.pitches[plane] < min_pitch) {
1030                 drm_dbg_kms(rfb->base.dev,
1031                             "pitch %d for plane %d is less than minimum pitch %d\n",
1032                             rfb->base.pitches[plane], plane, min_pitch);
1033                 return -EINVAL;
1034         }
1035
1036         /* Force at least natural alignment. */
1037         if (rfb->base.offsets[plane] % block_size) {
1038                 drm_dbg_kms(rfb->base.dev,
1039                             "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n",
1040                             rfb->base.offsets[plane], plane, block_size);
1041                 return -EINVAL;
1042         }
1043
1044         size = rfb->base.offsets[plane] +
1045                 (uint64_t)rfb->base.pitches[plane] / block_pitch *
1046                 block_size * DIV_ROUND_UP(height, block_height);
1047
1048         if (rfb->base.obj[0]->size < size) {
1049                 drm_dbg_kms(rfb->base.dev,
1050                             "BO size 0x%zx is less than 0x%llx required for plane %d\n",
1051                             rfb->base.obj[0]->size, size, plane);
1052                 return -EINVAL;
1053         }
1054
1055         return 0;
1056 }
1057
1058
1059 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
1060 {
1061         const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format);
1062         uint64_t modifier = rfb->base.modifier;
1063         int ret;
1064         unsigned int i, block_width, block_height, block_size_log2;
1065
1066         if (rfb->base.dev->mode_config.fb_modifiers_not_supported)
1067                 return 0;
1068
1069         for (i = 0; i < format_info->num_planes; ++i) {
1070                 if (modifier == DRM_FORMAT_MOD_LINEAR) {
1071                         block_width = 256 / format_info->cpp[i];
1072                         block_height = 1;
1073                         block_size_log2 = 8;
1074                 } else if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX12) {
1075                         int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
1076
1077                         switch (swizzle) {
1078                         case AMD_FMT_MOD_TILE_GFX12_256B_2D:
1079                                 block_size_log2 = 8;
1080                                 break;
1081                         case AMD_FMT_MOD_TILE_GFX12_4K_2D:
1082                                 block_size_log2 = 12;
1083                                 break;
1084                         case AMD_FMT_MOD_TILE_GFX12_64K_2D:
1085                                 block_size_log2 = 16;
1086                                 break;
1087                         case AMD_FMT_MOD_TILE_GFX12_256K_2D:
1088                                 block_size_log2 = 18;
1089                                 break;
1090                         default:
1091                                 drm_dbg_kms(rfb->base.dev,
1092                                             "Gfx12 swizzle mode with unknown block size: %d\n", swizzle);
1093                                 return -EINVAL;
1094                         }
1095
1096                         get_block_dimensions(block_size_log2, format_info->cpp[i],
1097                                              &block_width, &block_height);
1098                 } else {
1099                         int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
1100
1101                         switch ((swizzle & ~3) + 1) {
1102                         case DC_SW_256B_S:
1103                                 block_size_log2 = 8;
1104                                 break;
1105                         case DC_SW_4KB_S:
1106                         case DC_SW_4KB_S_X:
1107                                 block_size_log2 = 12;
1108                                 break;
1109                         case DC_SW_64KB_S:
1110                         case DC_SW_64KB_S_T:
1111                         case DC_SW_64KB_S_X:
1112                                 block_size_log2 = 16;
1113                                 break;
1114                         case DC_SW_VAR_S_X:
1115                                 block_size_log2 = 18;
1116                                 break;
1117                         default:
1118                                 drm_dbg_kms(rfb->base.dev,
1119                                             "Swizzle mode with unknown block size: %d\n", swizzle);
1120                                 return -EINVAL;
1121                         }
1122
1123                         get_block_dimensions(block_size_log2, format_info->cpp[i],
1124                                              &block_width, &block_height);
1125                 }
1126
1127                 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1128                                                   block_width, block_height, block_size_log2);
1129                 if (ret)
1130                         return ret;
1131         }
1132
1133         if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) <= AMD_FMT_MOD_TILE_VER_GFX11 &&
1134             AMD_FMT_MOD_GET(DCC, modifier)) {
1135                 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
1136                         block_size_log2 = get_dcc_block_size(modifier, false, false);
1137                         get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1138                                              &block_width, &block_height);
1139                         ret = amdgpu_display_verify_plane(rfb, i, format_info,
1140                                                           block_width, block_height,
1141                                                           block_size_log2);
1142                         if (ret)
1143                                 return ret;
1144
1145                         ++i;
1146                         block_size_log2 = get_dcc_block_size(modifier, true, true);
1147                 } else {
1148                         bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
1149
1150                         block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);
1151                 }
1152                 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1153                                      &block_width, &block_height);
1154                 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1155                                                   block_width, block_height, block_size_log2);
1156                 if (ret)
1157                         return ret;
1158         }
1159
1160         return 0;
1161 }
1162
1163 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1164                                       uint64_t *tiling_flags, bool *tmz_surface,
1165                                       bool *gfx12_dcc)
1166 {
1167         struct amdgpu_bo *rbo;
1168         int r;
1169
1170         if (!amdgpu_fb) {
1171                 *tiling_flags = 0;
1172                 *tmz_surface = false;
1173                 *gfx12_dcc = false;
1174                 return 0;
1175         }
1176
1177         rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1178         r = amdgpu_bo_reserve(rbo, false);
1179
1180         if (unlikely(r)) {
1181                 /* Don't show error message when returning -ERESTARTSYS */
1182                 if (r != -ERESTARTSYS)
1183                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
1184                 return r;
1185         }
1186
1187         amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1188         *tmz_surface = amdgpu_bo_encrypted(rbo);
1189         *gfx12_dcc = rbo->flags & AMDGPU_GEM_CREATE_GFX12_DCC;
1190
1191         amdgpu_bo_unreserve(rbo);
1192
1193         return r;
1194 }
1195
1196 static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev,
1197                                                  struct amdgpu_framebuffer *rfb,
1198                                                  struct drm_file *file_priv,
1199                                                  const struct drm_mode_fb_cmd2 *mode_cmd,
1200                                                  struct drm_gem_object *obj)
1201 {
1202         int ret;
1203
1204         rfb->base.obj[0] = obj;
1205         drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1206         /* Verify that the modifier is supported. */
1207         if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
1208                                       mode_cmd->modifier[0])) {
1209                 drm_dbg_kms(dev,
1210                             "unsupported pixel format %p4cc / modifier 0x%llx\n",
1211                             &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1212
1213                 ret = -EINVAL;
1214                 goto err;
1215         }
1216
1217         ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1218         if (ret)
1219                 goto err;
1220
1221         if (drm_drv_uses_atomic_modeset(dev))
1222                 ret = drm_framebuffer_init(dev, &rfb->base,
1223                                            &amdgpu_fb_funcs_atomic);
1224         else
1225                 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1226
1227         if (ret)
1228                 goto err;
1229
1230         return 0;
1231 err:
1232         drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
1233         rfb->base.obj[0] = NULL;
1234         return ret;
1235 }
1236
1237 static int amdgpu_display_framebuffer_init(struct drm_device *dev,
1238                                            struct amdgpu_framebuffer *rfb,
1239                                            const struct drm_mode_fb_cmd2 *mode_cmd,
1240                                            struct drm_gem_object *obj)
1241 {
1242         struct amdgpu_device *adev = drm_to_adev(dev);
1243         int ret, i;
1244
1245         /*
1246          * This needs to happen before modifier conversion as that might change
1247          * the number of planes.
1248          */
1249         for (i = 1; i < rfb->base.format->num_planes; ++i) {
1250                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1251                         drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
1252                                     i, mode_cmd->handles[0], mode_cmd->handles[i]);
1253                         ret = -EINVAL;
1254                         return ret;
1255                 }
1256         }
1257
1258         ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface,
1259                                          &rfb->gfx12_dcc);
1260         if (ret)
1261                 return ret;
1262
1263         if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) {
1264                 drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
1265                               "GFX9+ requires FB check based on format modifier\n");
1266                 ret = check_tiling_flags_gfx6(rfb);
1267                 if (ret)
1268                         return ret;
1269         }
1270
1271         if (!dev->mode_config.fb_modifiers_not_supported &&
1272             !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
1273                 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0))
1274                         ret = convert_tiling_flags_to_modifier_gfx12(rfb);
1275                 else
1276                         ret = convert_tiling_flags_to_modifier(rfb);
1277
1278                 if (ret) {
1279                         drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
1280                                     rfb->tiling_flags);
1281                         return ret;
1282                 }
1283         }
1284
1285         ret = amdgpu_display_verify_sizes(rfb);
1286         if (ret)
1287                 return ret;
1288
1289         for (i = 0; i < rfb->base.format->num_planes; ++i) {
1290                 drm_gem_object_get(rfb->base.obj[0]);
1291                 rfb->base.obj[i] = rfb->base.obj[0];
1292         }
1293
1294         return 0;
1295 }
1296
1297 struct drm_framebuffer *
1298 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
1299                                        struct drm_file *file_priv,
1300                                        const struct drm_mode_fb_cmd2 *mode_cmd)
1301 {
1302         struct amdgpu_framebuffer *amdgpu_fb;
1303         struct drm_gem_object *obj;
1304         struct amdgpu_bo *bo;
1305         uint32_t domains;
1306         int ret;
1307
1308         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1309         if (obj ==  NULL) {
1310                 drm_dbg_kms(dev,
1311                             "No GEM object associated to handle 0x%08X, can't create framebuffer\n",
1312                             mode_cmd->handles[0]);
1313
1314                 return ERR_PTR(-ENOENT);
1315         }
1316
1317         /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1318         bo = gem_to_amdgpu_bo(obj);
1319         domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
1320         if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
1321                 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
1322                 drm_gem_object_put(obj);
1323                 return ERR_PTR(-EINVAL);
1324         }
1325
1326         amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
1327         if (amdgpu_fb == NULL) {
1328                 drm_gem_object_put(obj);
1329                 return ERR_PTR(-ENOMEM);
1330         }
1331
1332         ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv,
1333                                                     mode_cmd, obj);
1334         if (ret) {
1335                 kfree(amdgpu_fb);
1336                 drm_gem_object_put(obj);
1337                 return ERR_PTR(ret);
1338         }
1339
1340         drm_gem_object_put(obj);
1341         return &amdgpu_fb->base;
1342 }
1343
1344 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
1345         .fb_create = amdgpu_display_user_framebuffer_create,
1346 };
1347
1348 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = {
1349         { UNDERSCAN_OFF, "off" },
1350         { UNDERSCAN_ON, "on" },
1351         { UNDERSCAN_AUTO, "auto" },
1352 };
1353
1354 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = {
1355         { AMDGPU_AUDIO_DISABLE, "off" },
1356         { AMDGPU_AUDIO_ENABLE, "on" },
1357         { AMDGPU_AUDIO_AUTO, "auto" },
1358 };
1359
1360 /* XXX support different dither options? spatial, temporal, both, etc. */
1361 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = {
1362         { AMDGPU_FMT_DITHER_DISABLE, "off" },
1363         { AMDGPU_FMT_DITHER_ENABLE, "on" },
1364 };
1365
1366 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
1367 {
1368         int sz;
1369
1370         adev->mode_info.coherent_mode_property =
1371                 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
1372         if (!adev->mode_info.coherent_mode_property)
1373                 return -ENOMEM;
1374
1375         adev->mode_info.load_detect_property =
1376                 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
1377         if (!adev->mode_info.load_detect_property)
1378                 return -ENOMEM;
1379
1380         drm_mode_create_scaling_mode_property(adev_to_drm(adev));
1381
1382         sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
1383         adev->mode_info.underscan_property =
1384                 drm_property_create_enum(adev_to_drm(adev), 0,
1385                                          "underscan",
1386                                          amdgpu_underscan_enum_list, sz);
1387
1388         adev->mode_info.underscan_hborder_property =
1389                 drm_property_create_range(adev_to_drm(adev), 0,
1390                                           "underscan hborder", 0, 128);
1391         if (!adev->mode_info.underscan_hborder_property)
1392                 return -ENOMEM;
1393
1394         adev->mode_info.underscan_vborder_property =
1395                 drm_property_create_range(adev_to_drm(adev), 0,
1396                                           "underscan vborder", 0, 128);
1397         if (!adev->mode_info.underscan_vborder_property)
1398                 return -ENOMEM;
1399
1400         sz = ARRAY_SIZE(amdgpu_audio_enum_list);
1401         adev->mode_info.audio_property =
1402                 drm_property_create_enum(adev_to_drm(adev), 0,
1403                                          "audio",
1404                                          amdgpu_audio_enum_list, sz);
1405
1406         sz = ARRAY_SIZE(amdgpu_dither_enum_list);
1407         adev->mode_info.dither_property =
1408                 drm_property_create_enum(adev_to_drm(adev), 0,
1409                                          "dither",
1410                                          amdgpu_dither_enum_list, sz);
1411
1412         return 0;
1413 }
1414
1415 void amdgpu_display_update_priority(struct amdgpu_device *adev)
1416 {
1417         /* adjustment options for the display watermarks */
1418         if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
1419                 adev->mode_info.disp_priority = 0;
1420         else
1421                 adev->mode_info.disp_priority = amdgpu_disp_priority;
1422
1423 }
1424
1425 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
1426 {
1427         /* try and guess if this is a tv or a monitor */
1428         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1429             (mode->vdisplay == 576) || /* 576p */
1430             (mode->vdisplay == 720) || /* 720p */
1431             (mode->vdisplay == 1080)) /* 1080p */
1432                 return true;
1433         else
1434                 return false;
1435 }
1436
1437 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1438                                         const struct drm_display_mode *mode,
1439                                         struct drm_display_mode *adjusted_mode)
1440 {
1441         struct drm_device *dev = crtc->dev;
1442         struct drm_encoder *encoder;
1443         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1444         struct amdgpu_encoder *amdgpu_encoder;
1445         struct drm_connector *connector;
1446         u32 src_v = 1, dst_v = 1;
1447         u32 src_h = 1, dst_h = 1;
1448
1449         amdgpu_crtc->h_border = 0;
1450         amdgpu_crtc->v_border = 0;
1451
1452         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1453                 if (encoder->crtc != crtc)
1454                         continue;
1455                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1456                 connector = amdgpu_get_connector_for_encoder(encoder);
1457
1458                 /* set scaling */
1459                 if (amdgpu_encoder->rmx_type == RMX_OFF)
1460                         amdgpu_crtc->rmx_type = RMX_OFF;
1461                 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
1462                          mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
1463                         amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
1464                 else
1465                         amdgpu_crtc->rmx_type = RMX_OFF;
1466                 /* copy native mode */
1467                 memcpy(&amdgpu_crtc->native_mode,
1468                        &amdgpu_encoder->native_mode,
1469                        sizeof(struct drm_display_mode));
1470                 src_v = crtc->mode.vdisplay;
1471                 dst_v = amdgpu_crtc->native_mode.vdisplay;
1472                 src_h = crtc->mode.hdisplay;
1473                 dst_h = amdgpu_crtc->native_mode.hdisplay;
1474
1475                 /* fix up for overscan on hdmi */
1476                 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1477                     ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
1478                      ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
1479                       connector && connector->display_info.is_hdmi &&
1480                       amdgpu_display_is_hdtv_mode(mode)))) {
1481                         if (amdgpu_encoder->underscan_hborder != 0)
1482                                 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
1483                         else
1484                                 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
1485                         if (amdgpu_encoder->underscan_vborder != 0)
1486                                 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
1487                         else
1488                                 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
1489                         amdgpu_crtc->rmx_type = RMX_FULL;
1490                         src_v = crtc->mode.vdisplay;
1491                         dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
1492                         src_h = crtc->mode.hdisplay;
1493                         dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
1494                 }
1495         }
1496         if (amdgpu_crtc->rmx_type != RMX_OFF) {
1497                 fixed20_12 a, b;
1498
1499                 a.full = dfixed_const(src_v);
1500                 b.full = dfixed_const(dst_v);
1501                 amdgpu_crtc->vsc.full = dfixed_div(a, b);
1502                 a.full = dfixed_const(src_h);
1503                 b.full = dfixed_const(dst_h);
1504                 amdgpu_crtc->hsc.full = dfixed_div(a, b);
1505         } else {
1506                 amdgpu_crtc->vsc.full = dfixed_const(1);
1507                 amdgpu_crtc->hsc.full = dfixed_const(1);
1508         }
1509         return true;
1510 }
1511
1512 /*
1513  * Retrieve current video scanout position of crtc on a given gpu, and
1514  * an optional accurate timestamp of when query happened.
1515  *
1516  * \param dev Device to query.
1517  * \param pipe Crtc to query.
1518  * \param flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1519  *              For driver internal use only also supports these flags:
1520  *
1521  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1522  *              of a fudged earlier start of vblank.
1523  *
1524  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1525  *              fudged earlier start of vblank in *vpos and the distance
1526  *              to true start of vblank in *hpos.
1527  *
1528  * \param *vpos Location where vertical scanout position should be stored.
1529  * \param *hpos Location where horizontal scanout position should go.
1530  * \param *stime Target location for timestamp taken immediately before
1531  *               scanout position query. Can be NULL to skip timestamp.
1532  * \param *etime Target location for timestamp taken immediately after
1533  *               scanout position query. Can be NULL to skip timestamp.
1534  *
1535  * Returns vpos as a positive number while in active scanout area.
1536  * Returns vpos as a negative number inside vblank, counting the number
1537  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1538  * until start of active scanout / end of vblank."
1539  *
1540  * \return Flags, or'ed together as follows:
1541  *
1542  * DRM_SCANOUTPOS_VALID = Query successful.
1543  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1544  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1545  * this flag means that returned position may be offset by a constant but
1546  * unknown small number of scanlines wrt. real scanout position.
1547  *
1548  */
1549 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
1550                         unsigned int pipe, unsigned int flags, int *vpos,
1551                         int *hpos, ktime_t *stime, ktime_t *etime,
1552                         const struct drm_display_mode *mode)
1553 {
1554         u32 vbl = 0, position = 0;
1555         int vbl_start, vbl_end, vtotal, ret = 0;
1556         bool in_vbl = true;
1557
1558         struct amdgpu_device *adev = drm_to_adev(dev);
1559
1560         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1561
1562         /* Get optional system timestamp before query. */
1563         if (stime)
1564                 *stime = ktime_get();
1565
1566         if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
1567                 ret |= DRM_SCANOUTPOS_VALID;
1568
1569         /* Get optional system timestamp after query. */
1570         if (etime)
1571                 *etime = ktime_get();
1572
1573         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1574
1575         /* Decode into vertical and horizontal scanout position. */
1576         *vpos = position & 0x1fff;
1577         *hpos = (position >> 16) & 0x1fff;
1578
1579         /* Valid vblank area boundaries from gpu retrieved? */
1580         if (vbl > 0) {
1581                 /* Yes: Decode. */
1582                 ret |= DRM_SCANOUTPOS_ACCURATE;
1583                 vbl_start = vbl & 0x1fff;
1584                 vbl_end = (vbl >> 16) & 0x1fff;
1585         } else {
1586                 /* No: Fake something reasonable which gives at least ok results. */
1587                 vbl_start = mode->crtc_vdisplay;
1588                 vbl_end = 0;
1589         }
1590
1591         /* Called from driver internal vblank counter query code? */
1592         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1593                 /* Caller wants distance from real vbl_start in *hpos */
1594                 *hpos = *vpos - vbl_start;
1595         }
1596
1597         /* Fudge vblank to start a few scanlines earlier to handle the
1598          * problem that vblank irqs fire a few scanlines before start
1599          * of vblank. Some driver internal callers need the true vblank
1600          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1601          *
1602          * The cause of the "early" vblank irq is that the irq is triggered
1603          * by the line buffer logic when the line buffer read position enters
1604          * the vblank, whereas our crtc scanout position naturally lags the
1605          * line buffer read position.
1606          */
1607         if (!(flags & USE_REAL_VBLANKSTART))
1608                 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1609
1610         /* Test scanout position against vblank region. */
1611         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1612                 in_vbl = false;
1613
1614         /* In vblank? */
1615         if (in_vbl)
1616                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1617
1618         /* Called from driver internal vblank counter query code? */
1619         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1620                 /* Caller wants distance from fudged earlier vbl_start */
1621                 *vpos -= vbl_start;
1622                 return ret;
1623         }
1624
1625         /* Check if inside vblank area and apply corrective offsets:
1626          * vpos will then be >=0 in video scanout area, but negative
1627          * within vblank area, counting down the number of lines until
1628          * start of scanout.
1629          */
1630
1631         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1632         if (in_vbl && (*vpos >= vbl_start)) {
1633                 vtotal = mode->crtc_vtotal;
1634
1635                 /* With variable refresh rate displays the vpos can exceed
1636                  * the vtotal value. Clamp to 0 to return -vbl_end instead
1637                  * of guessing the remaining number of lines until scanout.
1638                  */
1639                 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1640         }
1641
1642         /* Correct for shifted end of vbl at vbl_end. */
1643         *vpos = *vpos - vbl_end;
1644
1645         return ret;
1646 }
1647
1648 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1649 {
1650         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1651                 return AMDGPU_CRTC_IRQ_NONE;
1652
1653         switch (crtc) {
1654         case 0:
1655                 return AMDGPU_CRTC_IRQ_VBLANK1;
1656         case 1:
1657                 return AMDGPU_CRTC_IRQ_VBLANK2;
1658         case 2:
1659                 return AMDGPU_CRTC_IRQ_VBLANK3;
1660         case 3:
1661                 return AMDGPU_CRTC_IRQ_VBLANK4;
1662         case 4:
1663                 return AMDGPU_CRTC_IRQ_VBLANK5;
1664         case 5:
1665                 return AMDGPU_CRTC_IRQ_VBLANK6;
1666         default:
1667                 return AMDGPU_CRTC_IRQ_NONE;
1668         }
1669 }
1670
1671 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1672                         bool in_vblank_irq, int *vpos,
1673                         int *hpos, ktime_t *stime, ktime_t *etime,
1674                         const struct drm_display_mode *mode)
1675 {
1676         struct drm_device *dev = crtc->dev;
1677         unsigned int pipe = crtc->index;
1678
1679         return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1680                                                   stime, etime, mode);
1681 }
1682
1683 static bool
1684 amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
1685 {
1686         struct drm_device *dev = adev_to_drm(adev);
1687         struct drm_fb_helper *fb_helper = dev->fb_helper;
1688
1689         if (!fb_helper || !fb_helper->buffer)
1690                 return false;
1691
1692         if (gem_to_amdgpu_bo(fb_helper->buffer->gem) != robj)
1693                 return false;
1694
1695         return true;
1696 }
1697
1698 int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
1699 {
1700         struct drm_device *dev = adev_to_drm(adev);
1701         struct drm_crtc *crtc;
1702         struct drm_connector *connector;
1703         struct drm_connector_list_iter iter;
1704         int r;
1705
1706         drm_kms_helper_poll_disable(dev);
1707
1708         /* turn off display hw */
1709         drm_modeset_lock_all(dev);
1710         drm_connector_list_iter_begin(dev, &iter);
1711         drm_for_each_connector_iter(connector, &iter)
1712                 drm_helper_connector_dpms(connector,
1713                                           DRM_MODE_DPMS_OFF);
1714         drm_connector_list_iter_end(&iter);
1715         drm_modeset_unlock_all(dev);
1716         /* unpin the front buffers and cursors */
1717         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1718                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1719                 struct drm_framebuffer *fb = crtc->primary->fb;
1720                 struct amdgpu_bo *robj;
1721
1722                 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1723                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1724
1725                         r = amdgpu_bo_reserve(aobj, true);
1726                         if (r == 0) {
1727                                 amdgpu_bo_unpin(aobj);
1728                                 amdgpu_bo_unreserve(aobj);
1729                         }
1730                 }
1731
1732                 if (!fb || !fb->obj[0])
1733                         continue;
1734
1735                 robj = gem_to_amdgpu_bo(fb->obj[0]);
1736                 if (!amdgpu_display_robj_is_fb(adev, robj)) {
1737                         r = amdgpu_bo_reserve(robj, true);
1738                         if (r == 0) {
1739                                 amdgpu_bo_unpin(robj);
1740                                 amdgpu_bo_unreserve(robj);
1741                         }
1742                 }
1743         }
1744         return 0;
1745 }
1746
1747 int amdgpu_display_resume_helper(struct amdgpu_device *adev)
1748 {
1749         struct drm_device *dev = adev_to_drm(adev);
1750         struct drm_connector *connector;
1751         struct drm_connector_list_iter iter;
1752         struct drm_crtc *crtc;
1753         int r;
1754
1755         /* pin cursors */
1756         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1757                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1758
1759                 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1760                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1761
1762                         r = amdgpu_bo_reserve(aobj, true);
1763                         if (r == 0) {
1764                                 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1765                                 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
1766                                 if (r != 0)
1767                                         dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
1768                                 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
1769                                 amdgpu_bo_unreserve(aobj);
1770                         }
1771                 }
1772         }
1773
1774         drm_helper_resume_force_mode(dev);
1775
1776         /* turn on display hw */
1777         drm_modeset_lock_all(dev);
1778
1779         drm_connector_list_iter_begin(dev, &iter);
1780         drm_for_each_connector_iter(connector, &iter)
1781                 drm_helper_connector_dpms(connector,
1782                                           DRM_MODE_DPMS_ON);
1783         drm_connector_list_iter_end(&iter);
1784
1785         drm_modeset_unlock_all(dev);
1786
1787         drm_kms_helper_poll_enable(dev);
1788
1789         return 0;
1790 }
1791
1792 /* panic_bo is set in amdgpu_dm_plane_get_scanout_buffer() and only used in amdgpu_dm_set_pixel()
1793  * they are called from the panic handler, and protected by the drm_panic spinlock.
1794  */
1795 static struct amdgpu_bo *panic_abo;
1796
1797 /* Use the indirect MMIO to write each pixel to the GPU VRAM,
1798  * This is a simplified version of amdgpu_device_mm_access()
1799  */
1800 static void amdgpu_display_set_pixel(struct drm_scanout_buffer *sb,
1801                                      unsigned int x,
1802                                      unsigned int y,
1803                                      u32 color)
1804 {
1805         struct amdgpu_res_cursor cursor;
1806         unsigned long offset;
1807         struct amdgpu_bo *abo = panic_abo;
1808         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1809         uint32_t tmp;
1810
1811         offset = x * 4 + y * sb->pitch[0];
1812         amdgpu_res_first(abo->tbo.resource, offset, 4, &cursor);
1813
1814         tmp = cursor.start >> 31;
1815         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t) cursor.start) | 0x80000000);
1816         if (tmp != 0xffffffff)
1817                 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
1818         WREG32_NO_KIQ(mmMM_DATA, color);
1819 }
1820
1821 int amdgpu_display_get_scanout_buffer(struct drm_plane *plane,
1822                                       struct drm_scanout_buffer *sb)
1823 {
1824         struct amdgpu_bo *abo;
1825         struct drm_framebuffer *fb = plane->state->fb;
1826
1827         if (!fb)
1828                 return -EINVAL;
1829
1830         DRM_DEBUG_KMS("Framebuffer %dx%d %p4cc\n", fb->width, fb->height, &fb->format->format);
1831
1832         abo = gem_to_amdgpu_bo(fb->obj[0]);
1833         if (!abo)
1834                 return -EINVAL;
1835
1836         sb->width = fb->width;
1837         sb->height = fb->height;
1838         /* Use the generic linear format, because tiling will be disabled in panic_flush() */
1839         sb->format = drm_format_info(fb->format->format);
1840         if (!sb->format)
1841                 return -EINVAL;
1842
1843         sb->pitch[0] = fb->pitches[0];
1844
1845         if (abo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) {
1846                 if (abo->tbo.resource->mem_type != TTM_PL_VRAM) {
1847                         drm_warn(plane->dev, "amdgpu panic, framebuffer not in VRAM\n");
1848                         return -EINVAL;
1849                 }
1850                 /* Only handle 32bits format, to simplify mmio access */
1851                 if (fb->format->cpp[0] != 4) {
1852                         drm_warn(plane->dev, "amdgpu panic, pixel format is not 32bits\n");
1853                         return -EINVAL;
1854                 }
1855                 sb->set_pixel = amdgpu_display_set_pixel;
1856                 panic_abo = abo;
1857                 return 0;
1858         }
1859         if (!abo->kmap.virtual &&
1860             ttm_bo_kmap(&abo->tbo, 0, PFN_UP(abo->tbo.base.size), &abo->kmap)) {
1861                 drm_warn(plane->dev, "amdgpu bo map failed, panic won't be displayed\n");
1862                 return -ENOMEM;
1863         }
1864         if (abo->kmap.bo_kmap_type & TTM_BO_MAP_IOMEM_MASK)
1865                 iosys_map_set_vaddr_iomem(&sb->map[0], abo->kmap.virtual);
1866         else
1867                 iosys_map_set_vaddr(&sb->map[0], abo->kmap.virtual);
1868
1869         return 0;
1870 }