drivers/firewire/core-iso.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Isochronous I/O functionality:
   4  *   - Isochronous DMA context management
   5  *   - Isochronous bus resource management (channels, bandwidth), client side
   6  *
   7  * Copyright (C) 2006 Kristian Hoegsberg <[email protected]>
   8  */
   9
  10 #include <linux/dma-mapping.h>
  11 #include <linux/errno.h>
  12 #include <linux/firewire.h>
  13 #include <linux/firewire-constants.h>
  14 #include <linux/kernel.h>
  15 #include <linux/mm.h>
  16 #include <linux/slab.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/byteorder.h>
  22
  23 #include "core.h"
  24
  25 #include <trace/events/firewire.h>
  26
  27 /*
  28  * Isochronous DMA context management
  29  */
  30
  31 int fw_iso_buffer_alloc(struct fw_iso_buffer *buffer, int page_count)
  32 {
  33         int i;
  34
  35         buffer->page_count = 0;
  36         buffer->page_count_mapped = 0;
  37         buffer->pages = kmalloc_array(page_count, sizeof(buffer->pages[0]),
  38                                       GFP_KERNEL);
  39         if (buffer->pages == NULL)
  40                 return -ENOMEM;
  41
  42         for (i = 0; i < page_count; i++) {
  43                 buffer->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
  44                 if (buffer->pages[i] == NULL)
  45                         break;
  46         }
  47         buffer->page_count = i;
  48         if (i < page_count) {
  49                 fw_iso_buffer_destroy(buffer, NULL);
  50                 return -ENOMEM;
  51         }
  52
  53         return 0;
  54 }
  55
  56 int fw_iso_buffer_map_dma(struct fw_iso_buffer *buffer, struct fw_card *card,
  57                           enum dma_data_direction direction)
  58 {
  59         dma_addr_t address;
  60         int i;
  61
  62         buffer->direction = direction;
  63
  64         for (i = 0; i < buffer->page_count; i++) {
  65                 address = dma_map_page(card->device, buffer->pages[i],
  66                                        0, PAGE_SIZE, direction);
  67                 if (dma_mapping_error(card->device, address))
  68                         break;
  69
  70                 set_page_private(buffer->pages[i], address);
  71         }
  72         buffer->page_count_mapped = i;
  73         if (i < buffer->page_count)
  74                 return -ENOMEM;
  75
  76         return 0;
  77 }
  78
  79 int fw_iso_buffer_init(struct fw_iso_buffer *buffer, struct fw_card *card,
  80                        int page_count, enum dma_data_direction direction)
  81 {
  82         int ret;
  83
  84         ret = fw_iso_buffer_alloc(buffer, page_count);
  85         if (ret < 0)
  86                 return ret;
  87
  88         ret = fw_iso_buffer_map_dma(buffer, card, direction);
  89         if (ret < 0)
  90                 fw_iso_buffer_destroy(buffer, card);
  91
  92         return ret;
  93 }
  94 EXPORT_SYMBOL(fw_iso_buffer_init);
  95
  96 void fw_iso_buffer_destroy(struct fw_iso_buffer *buffer,
  97                            struct fw_card *card)
  98 {
  99         int i;
 100         dma_addr_t address;
 101
 102         for (i = 0; i < buffer->page_count_mapped; i++) {
 103                 address = page_private(buffer->pages[i]);
 104                 dma_unmap_page(card->device, address,
 105                                PAGE_SIZE, buffer->direction);
 106         }
 107         for (i = 0; i < buffer->page_count; i++)
 108                 __free_page(buffer->pages[i]);
 109
 110         kfree(buffer->pages);
 111         buffer->pages = NULL;
 112         buffer->page_count = 0;
 113         buffer->page_count_mapped = 0;
 114 }
 115 EXPORT_SYMBOL(fw_iso_buffer_destroy);
 116
 117 /* Convert DMA address to offset into virtually contiguous buffer. */
 118 size_t fw_iso_buffer_lookup(struct fw_iso_buffer *buffer, dma_addr_t completed)
 119 {
 120         size_t i;
 121         dma_addr_t address;
 122         ssize_t offset;
 123
 124         for (i = 0; i < buffer->page_count; i++) {
 125                 address = page_private(buffer->pages[i]);
 126                 offset = (ssize_t)completed - (ssize_t)address;
 127                 if (offset > 0 && offset <= PAGE_SIZE)
 128                         return (i << PAGE_SHIFT) + offset;
 129         }
 130
 131         return 0;
 132 }
 133
 134 struct fw_iso_context *fw_iso_context_create(struct fw_card *card,
 135                 int type, int channel, int speed, size_t header_size,
 136                 fw_iso_callback_t callback, void *callback_data)
 137 {
 138         struct fw_iso_context *ctx;
 139
 140         ctx = card->driver->allocate_iso_context(card,
 141                                                  type, channel, header_size);
 142         if (IS_ERR(ctx))
 143                 return ctx;
 144
 145         ctx->card = card;
 146         ctx->type = type;
 147         ctx->channel = channel;
 148         ctx->speed = speed;
 149         ctx->header_size = header_size;
 150         ctx->callback.sc = callback;
 151         ctx->callback_data = callback_data;
 152
 153         trace_isoc_outbound_allocate(ctx, channel, speed);
 154         trace_isoc_inbound_single_allocate(ctx, channel, header_size);
 155         trace_isoc_inbound_multiple_allocate(ctx);
 156
 157         return ctx;
 158 }
 159 EXPORT_SYMBOL(fw_iso_context_create);
 160
 161 void fw_iso_context_destroy(struct fw_iso_context *ctx)
 162 {
 163         trace_isoc_outbound_destroy(ctx);
 164         trace_isoc_inbound_single_destroy(ctx);
 165         trace_isoc_inbound_multiple_destroy(ctx);
 166
 167         ctx->card->driver->free_iso_context(ctx);
 168 }
 169 EXPORT_SYMBOL(fw_iso_context_destroy);
 170
 171 int fw_iso_context_start(struct fw_iso_context *ctx,
 172                          int cycle, int sync, int tags)
 173 {
 174         trace_isoc_outbound_start(ctx, cycle);
 175         trace_isoc_inbound_single_start(ctx, cycle, sync, tags);
 176         trace_isoc_inbound_multiple_start(ctx, cycle, sync, tags);
 177
 178         return ctx->card->driver->start_iso(ctx, cycle, sync, tags);
 179 }
 180 EXPORT_SYMBOL(fw_iso_context_start);
 181
 182 int fw_iso_context_set_channels(struct fw_iso_context *ctx, u64 *channels)
 183 {
 184         trace_isoc_inbound_multiple_channels(ctx, *channels);
 185
 186         return ctx->card->driver->set_iso_channels(ctx, channels);
 187 }
 188
 189 int fw_iso_context_queue(struct fw_iso_context *ctx,
 190                          struct fw_iso_packet *packet,
 191                          struct fw_iso_buffer *buffer,
 192                          unsigned long payload)
 193 {
 194         trace_isoc_outbound_queue(ctx, payload, packet);
 195         trace_isoc_inbound_single_queue(ctx, payload, packet);
 196         trace_isoc_inbound_multiple_queue(ctx, payload, packet);
 197
 198         return ctx->card->driver->queue_iso(ctx, packet, buffer, payload);
 199 }
 200 EXPORT_SYMBOL(fw_iso_context_queue);
 201
 202 void fw_iso_context_queue_flush(struct fw_iso_context *ctx)
 203 {
 204         trace_isoc_outbound_flush(ctx);
 205         trace_isoc_inbound_single_flush(ctx);
 206         trace_isoc_inbound_multiple_flush(ctx);
 207
 208         ctx->card->driver->flush_queue_iso(ctx);
 209 }
 210 EXPORT_SYMBOL(fw_iso_context_queue_flush);
 211
 212 int fw_iso_context_flush_completions(struct fw_iso_context *ctx)
 213 {
 214         trace_isoc_outbound_flush_completions(ctx);
 215         trace_isoc_inbound_single_flush_completions(ctx);
 216         trace_isoc_inbound_multiple_flush_completions(ctx);
 217
 218         return ctx->card->driver->flush_iso_completions(ctx);
 219 }
 220 EXPORT_SYMBOL(fw_iso_context_flush_completions);
 221
 222 int fw_iso_context_stop(struct fw_iso_context *ctx)
 223 {
 224         trace_isoc_outbound_stop(ctx);
 225         trace_isoc_inbound_single_stop(ctx);
 226         trace_isoc_inbound_multiple_stop(ctx);
 227
 228         return ctx->card->driver->stop_iso(ctx);
 229 }
 230 EXPORT_SYMBOL(fw_iso_context_stop);
 231
 232 /*
 233  * Isochronous bus resource management (channels, bandwidth), client side
 234  */
 235
 236 static int manage_bandwidth(struct fw_card *card, int irm_id, int generation,
 237                             int bandwidth, bool allocate)
 238 {
 239         int try, new, old = allocate ? BANDWIDTH_AVAILABLE_INITIAL : 0;
 240         __be32 data[2];
 241
 242         /*
 243          * On a 1394a IRM with low contention, try < 1 is enough.
 244          * On a 1394-1995 IRM, we need at least try < 2.
 245          * Let's just do try < 5.
 246          */
 247         for (try = 0; try < 5; try++) {
 248                 new = allocate ? old - bandwidth : old + bandwidth;
 249                 if (new < 0 || new > BANDWIDTH_AVAILABLE_INITIAL)
 250                         return -EBUSY;
 251
 252                 data[0] = cpu_to_be32(old);
 253                 data[1] = cpu_to_be32(new);
 254                 switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP,
 255                                 irm_id, generation, SCODE_100,
 256                                 CSR_REGISTER_BASE + CSR_BANDWIDTH_AVAILABLE,
 257                                 data, 8)) {
 258                 case RCODE_GENERATION:
 259                         /* A generation change frees all bandwidth. */
 260                         return allocate ? -EAGAIN : bandwidth;
 261
 262                 case RCODE_COMPLETE:
 263                         if (be32_to_cpup(data) == old)
 264                                 return bandwidth;
 265
 266                         old = be32_to_cpup(data);
 267                         /* Fall through. */
 268                 }
 269         }
 270
 271         return -EIO;
 272 }
 273
 274 static int manage_channel(struct fw_card *card, int irm_id, int generation,
 275                 u32 channels_mask, u64 offset, bool allocate)
 276 {
 277         __be32 bit, all, old;
 278         __be32 data[2];
 279         int channel, ret = -EIO, retry = 5;
 280
 281         old = all = allocate ? cpu_to_be32(~0) : 0;
 282
 283         for (channel = 0; channel < 32; channel++) {
 284                 if (!(channels_mask & 1 << channel))
 285                         continue;
 286
 287                 ret = -EBUSY;
 288
 289                 bit = cpu_to_be32(1 << (31 - channel));
 290                 if ((old & bit) != (all & bit))
 291                         continue;
 292
 293                 data[0] = old;
 294                 data[1] = old ^ bit;
 295                 switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP,
 296                                            irm_id, generation, SCODE_100,
 297                                            offset, data, 8)) {
 298                 case RCODE_GENERATION:
 299                         /* A generation change frees all channels. */
 300                         return allocate ? -EAGAIN : channel;
 301
 302                 case RCODE_COMPLETE:
 303                         if (data[0] == old)
 304                                 return channel;
 305
 306                         old = data[0];
 307
 308                         /* Is the IRM 1394a-2000 compliant? */
 309                         if ((data[0] & bit) == (data[1] & bit))
 310                                 continue;
 311
 312                         fallthrough;    /* It's a 1394-1995 IRM, retry */
 313                 default:
 314                         if (retry) {
 315                                 retry--;
 316                                 channel--;
 317                         } else {
 318                                 ret = -EIO;
 319                         }
 320                 }
 321         }
 322
 323         return ret;
 324 }
 325
 326 static void deallocate_channel(struct fw_card *card, int irm_id,
 327                                int generation, int channel)
 328 {
 329         u32 mask;
 330         u64 offset;
 331
 332         mask = channel < 32 ? 1 << channel : 1 << (channel - 32);
 333         offset = channel < 32 ? CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI :
 334                                 CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO;
 335
 336         manage_channel(card, irm_id, generation, mask, offset, false);
 337 }
 338
 339 /**
 340  * fw_iso_resource_manage() - Allocate or deallocate a channel and/or bandwidth
 341  * @card: card interface for this action
 342  * @generation: bus generation
 343  * @channels_mask: bitmask for channel allocation
 344  * @channel: pointer for returning channel allocation result
 345  * @bandwidth: pointer for returning bandwidth allocation result
 346  * @allocate: whether to allocate (true) or deallocate (false)
 347  *
 348  * In parameters: card, generation, channels_mask, bandwidth, allocate
 349  * Out parameters: channel, bandwidth
 350  *
 351  * This function blocks (sleeps) during communication with the IRM.
 352  *
 353  * Allocates or deallocates at most one channel out of channels_mask.
 354  * channels_mask is a bitfield with MSB for channel 63 and LSB for channel 0.
 355  * (Note, the IRM's CHANNELS_AVAILABLE is a big-endian bitfield with MSB for
 356  * channel 0 and LSB for channel 63.)
 357  * Allocates or deallocates as many bandwidth allocation units as specified.
 358  *
 359  * Returns channel < 0 if no channel was allocated or deallocated.
 360  * Returns bandwidth = 0 if no bandwidth was allocated or deallocated.
 361  *
 362  * If generation is stale, deallocations succeed but allocations fail with
 363  * channel = -EAGAIN.
 364  *
 365  * If channel allocation fails, no bandwidth will be allocated either.
 366  * If bandwidth allocation fails, no channel will be allocated either.
 367  * But deallocations of channel and bandwidth are tried independently
 368  * of each other's success.
 369  */
 370 void fw_iso_resource_manage(struct fw_card *card, int generation,
 371                             u64 channels_mask, int *channel, int *bandwidth,
 372                             bool allocate)
 373 {
 374         u32 channels_hi = channels_mask;        /* channels 31...0 */
 375         u32 channels_lo = channels_mask >> 32;  /* channels 63...32 */
 376         int irm_id, ret, c = -EINVAL;
 377
 378         spin_lock_irq(&card->lock);
 379         irm_id = card->irm_node->node_id;
 380         spin_unlock_irq(&card->lock);
 381
 382         if (channels_hi)
 383                 c = manage_channel(card, irm_id, generation, channels_hi,
 384                                 CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI,
 385                                 allocate);
 386         if (channels_lo && c < 0) {
 387                 c = manage_channel(card, irm_id, generation, channels_lo,
 388                                 CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO,
 389                                 allocate);
 390                 if (c >= 0)
 391                         c += 32;
 392         }
 393         *channel = c;
 394
 395         if (allocate && channels_mask != 0 && c < 0)
 396                 *bandwidth = 0;
 397
 398         if (*bandwidth == 0)
 399                 return;
 400
 401         ret = manage_bandwidth(card, irm_id, generation, *bandwidth, allocate);
 402         if (ret < 0)
 403                 *bandwidth = 0;
 404
 405         if (allocate && ret < 0) {
 406                 if (c >= 0)
 407                         deallocate_channel(card, irm_id, generation, c);
 408                 *channel = ret;
 409         }
 410 }
 411 EXPORT_SYMBOL(fw_iso_resource_manage);