drivers/base/regmap/regmap-irq.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // regmap based irq_chip
   4 //
   5 // Copyright 2011 Wolfson Microelectronics plc
   6 //
   7 // Author: Mark Brown <[email protected]>
   8
   9 #include <linux/device.h>
  10 #include <linux/export.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/irq.h>
  13 #include <linux/irqdomain.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regmap.h>
  16 #include <linux/slab.h>
  17
  18 #include "internal.h"
  19
  20 struct regmap_irq_chip_data {
  21         struct mutex lock;
  22         struct irq_chip irq_chip;
  23
  24         struct regmap *map;
  25         const struct regmap_irq_chip *chip;
  26
  27         int irq_base;
  28         struct irq_domain *domain;
  29
  30         int irq;
  31         int wake_count;
  32
  33         void *status_reg_buf;
  34         unsigned int *main_status_buf;
  35         unsigned int *status_buf;
  36         unsigned int *mask_buf;
  37         unsigned int *mask_buf_def;
  38         unsigned int *wake_buf;
  39         unsigned int *type_buf;
  40         unsigned int *type_buf_def;
  41
  42         unsigned int irq_reg_stride;
  43         unsigned int type_reg_stride;
  44
  45         bool clear_status:1;
  46 };
  47
  48 static inline const
  49 struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
  50                                      int irq)
  51 {
  52         return &data->chip->irqs[irq];
  53 }
  54
  55 static void regmap_irq_lock(struct irq_data *data)
  56 {
  57         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  58
  59         mutex_lock(&d->lock);
  60 }
  61
  62 static int regmap_irq_update_bits(struct regmap_irq_chip_data *d,
  63                                   unsigned int reg, unsigned int mask,
  64                                   unsigned int val)
  65 {
  66         if (d->chip->mask_writeonly)
  67                 return regmap_write_bits(d->map, reg, mask, val);
  68         else
  69                 return regmap_update_bits(d->map, reg, mask, val);
  70 }
  71
  72 static void regmap_irq_sync_unlock(struct irq_data *data)
  73 {
  74         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  75         struct regmap *map = d->map;
  76         int i, ret;
  77         u32 reg;
  78         u32 unmask_offset;
  79         u32 val;
  80
  81         if (d->chip->runtime_pm) {
  82                 ret = pm_runtime_get_sync(map->dev);
  83                 if (ret < 0)
  84                         dev_err(map->dev, "IRQ sync failed to resume: %d\n",
  85                                 ret);
  86         }
  87
  88         if (d->clear_status) {
  89                 for (i = 0; i < d->chip->num_regs; i++) {
  90                         reg = d->chip->status_base +
  91                                 (i * map->reg_stride * d->irq_reg_stride);
  92
  93                         ret = regmap_read(map, reg, &val);
  94                         if (ret)
  95                                 dev_err(d->map->dev,
  96                                         "Failed to clear the interrupt status bits\n");
  97                 }
  98
  99                 d->clear_status = false;
 100         }
 101
 102         /*
 103          * If there's been a change in the mask write it back to the
 104          * hardware.  We rely on the use of the regmap core cache to
 105          * suppress pointless writes.
 106          */
 107         for (i = 0; i < d->chip->num_regs; i++) {
 108                 if (!d->chip->mask_base)
 109                         continue;
 110
 111                 reg = d->chip->mask_base +
 112                         (i * map->reg_stride * d->irq_reg_stride);
 113                 if (d->chip->mask_invert) {
 114                         ret = regmap_irq_update_bits(d, reg,
 115                                          d->mask_buf_def[i], ~d->mask_buf[i]);
 116                 } else if (d->chip->unmask_base) {
 117                         /* set mask with mask_base register */
 118                         ret = regmap_irq_update_bits(d, reg,
 119                                         d->mask_buf_def[i], ~d->mask_buf[i]);
 120                         if (ret < 0)
 121                                 dev_err(d->map->dev,
 122                                         "Failed to sync unmasks in %x\n",
 123                                         reg);
 124                         unmask_offset = d->chip->unmask_base -
 125                                                         d->chip->mask_base;
 126                         /* clear mask with unmask_base register */
 127                         ret = regmap_irq_update_bits(d,
 128                                         reg + unmask_offset,
 129                                         d->mask_buf_def[i],
 130                                         d->mask_buf[i]);
 131                 } else {
 132                         ret = regmap_irq_update_bits(d, reg,
 133                                          d->mask_buf_def[i], d->mask_buf[i]);
 134                 }
 135                 if (ret != 0)
 136                         dev_err(d->map->dev, "Failed to sync masks in %x\n",
 137                                 reg);
 138
 139                 reg = d->chip->wake_base +
 140                         (i * map->reg_stride * d->irq_reg_stride);
 141                 if (d->wake_buf) {
 142                         if (d->chip->wake_invert)
 143                                 ret = regmap_irq_update_bits(d, reg,
 144                                                          d->mask_buf_def[i],
 145                                                          ~d->wake_buf[i]);
 146                         else
 147                                 ret = regmap_irq_update_bits(d, reg,
 148                                                          d->mask_buf_def[i],
 149                                                          d->wake_buf[i]);
 150                         if (ret != 0)
 151                                 dev_err(d->map->dev,
 152                                         "Failed to sync wakes in %x: %d\n",
 153                                         reg, ret);
 154                 }
 155
 156                 if (!d->chip->init_ack_masked)
 157                         continue;
 158                 /*
 159                  * Ack all the masked interrupts unconditionally,
 160                  * OR if there is masked interrupt which hasn't been Acked,
 161                  * it'll be ignored in irq handler, then may introduce irq storm
 162                  */
 163                 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
 164                         reg = d->chip->ack_base +
 165                                 (i * map->reg_stride * d->irq_reg_stride);
 166                         /* some chips ack by write 0 */
 167                         if (d->chip->ack_invert)
 168                                 ret = regmap_write(map, reg, ~d->mask_buf[i]);
 169                         else
 170                                 ret = regmap_write(map, reg, d->mask_buf[i]);
 171                         if (ret != 0)
 172                                 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
 173                                         reg, ret);
 174                 }
 175         }
 176
 177         /* Don't update the type bits if we're using mask bits for irq type. */
 178         if (!d->chip->type_in_mask) {
 179                 for (i = 0; i < d->chip->num_type_reg; i++) {
 180                         if (!d->type_buf_def[i])
 181                                 continue;
 182                         reg = d->chip->type_base +
 183                                 (i * map->reg_stride * d->type_reg_stride);
 184                         if (d->chip->type_invert)
 185                                 ret = regmap_irq_update_bits(d, reg,
 186                                         d->type_buf_def[i], ~d->type_buf[i]);
 187                         else
 188                                 ret = regmap_irq_update_bits(d, reg,
 189                                         d->type_buf_def[i], d->type_buf[i]);
 190                         if (ret != 0)
 191                                 dev_err(d->map->dev, "Failed to sync type in %x\n",
 192                                         reg);
 193                 }
 194         }
 195
 196         if (d->chip->runtime_pm)
 197                 pm_runtime_put(map->dev);
 198
 199         /* If we've changed our wakeup count propagate it to the parent */
 200         if (d->wake_count < 0)
 201                 for (i = d->wake_count; i < 0; i++)
 202                         irq_set_irq_wake(d->irq, 0);
 203         else if (d->wake_count > 0)
 204                 for (i = 0; i < d->wake_count; i++)
 205                         irq_set_irq_wake(d->irq, 1);
 206
 207         d->wake_count = 0;
 208
 209         mutex_unlock(&d->lock);
 210 }
 211
 212 static void regmap_irq_enable(struct irq_data *data)
 213 {
 214         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 215         struct regmap *map = d->map;
 216         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 217         unsigned int mask, type;
 218
 219         type = irq_data->type.type_falling_val | irq_data->type.type_rising_val;
 220
 221         /*
 222          * The type_in_mask flag means that the underlying hardware uses
 223          * separate mask bits for rising and falling edge interrupts, but
 224          * we want to make them into a single virtual interrupt with
 225          * configurable edge.
 226          *
 227          * If the interrupt we're enabling defines the falling or rising
 228          * masks then instead of using the regular mask bits for this
 229          * interrupt, use the value previously written to the type buffer
 230          * at the corresponding offset in regmap_irq_set_type().
 231          */
 232         if (d->chip->type_in_mask && type)
 233                 mask = d->type_buf[irq_data->reg_offset / map->reg_stride];
 234         else
 235                 mask = irq_data->mask;
 236
 237         if (d->chip->clear_on_unmask)
 238                 d->clear_status = true;
 239
 240         d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask;
 241 }
 242
 243 static void regmap_irq_disable(struct irq_data *data)
 244 {
 245         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 246         struct regmap *map = d->map;
 247         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 248
 249         d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
 250 }
 251
 252 static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
 253 {
 254         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 255         struct regmap *map = d->map;
 256         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 257         int reg;
 258         const struct regmap_irq_type *t = &irq_data->type;
 259
 260         if ((t->types_supported & type) != type)
 261                 return 0;
 262
 263         reg = t->type_reg_offset / map->reg_stride;
 264
 265         if (t->type_reg_mask)
 266                 d->type_buf[reg] &= ~t->type_reg_mask;
 267         else
 268                 d->type_buf[reg] &= ~(t->type_falling_val |
 269                                       t->type_rising_val |
 270                                       t->type_level_low_val |
 271                                       t->type_level_high_val);
 272         switch (type) {
 273         case IRQ_TYPE_EDGE_FALLING:
 274                 d->type_buf[reg] |= t->type_falling_val;
 275                 break;
 276
 277         case IRQ_TYPE_EDGE_RISING:
 278                 d->type_buf[reg] |= t->type_rising_val;
 279                 break;
 280
 281         case IRQ_TYPE_EDGE_BOTH:
 282                 d->type_buf[reg] |= (t->type_falling_val |
 283                                         t->type_rising_val);
 284                 break;
 285
 286         case IRQ_TYPE_LEVEL_HIGH:
 287                 d->type_buf[reg] |= t->type_level_high_val;
 288                 break;
 289
 290         case IRQ_TYPE_LEVEL_LOW:
 291                 d->type_buf[reg] |= t->type_level_low_val;
 292                 break;
 293         default:
 294                 return -EINVAL;
 295         }
 296         return 0;
 297 }
 298
 299 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
 300 {
 301         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 302         struct regmap *map = d->map;
 303         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 304
 305         if (on) {
 306                 if (d->wake_buf)
 307                         d->wake_buf[irq_data->reg_offset / map->reg_stride]
 308                                 &= ~irq_data->mask;
 309                 d->wake_count++;
 310         } else {
 311                 if (d->wake_buf)
 312                         d->wake_buf[irq_data->reg_offset / map->reg_stride]
 313                                 |= irq_data->mask;
 314                 d->wake_count--;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static const struct irq_chip regmap_irq_chip = {
 321         .irq_bus_lock           = regmap_irq_lock,
 322         .irq_bus_sync_unlock    = regmap_irq_sync_unlock,
 323         .irq_disable            = regmap_irq_disable,
 324         .irq_enable             = regmap_irq_enable,
 325         .irq_set_type           = regmap_irq_set_type,
 326         .irq_set_wake           = regmap_irq_set_wake,
 327 };
 328
 329 static inline int read_sub_irq_data(struct regmap_irq_chip_data *data,
 330                                            unsigned int b)
 331 {
 332         const struct regmap_irq_chip *chip = data->chip;
 333         struct regmap *map = data->map;
 334         struct regmap_irq_sub_irq_map *subreg;
 335         int i, ret = 0;
 336
 337         if (!chip->sub_reg_offsets) {
 338                 /* Assume linear mapping */
 339                 ret = regmap_read(map, chip->status_base +
 340                                   (b * map->reg_stride * data->irq_reg_stride),
 341                                    &data->status_buf[b]);
 342         } else {
 343                 subreg = &chip->sub_reg_offsets[b];
 344                 for (i = 0; i < subreg->num_regs; i++) {
 345                         unsigned int offset = subreg->offset[i];
 346
 347                         ret = regmap_read(map, chip->status_base + offset,
 348                                           &data->status_buf[offset]);
 349                         if (ret)
 350                                 break;
 351                 }
 352         }
 353         return ret;
 354 }
 355
 356 static irqreturn_t regmap_irq_thread(int irq, void *d)
 357 {
 358         struct regmap_irq_chip_data *data = d;
 359         const struct regmap_irq_chip *chip = data->chip;
 360         struct regmap *map = data->map;
 361         int ret, i;
 362         bool handled = false;
 363         u32 reg;
 364
 365         if (chip->handle_pre_irq)
 366                 chip->handle_pre_irq(chip->irq_drv_data);
 367
 368         if (chip->runtime_pm) {
 369                 ret = pm_runtime_get_sync(map->dev);
 370                 if (ret < 0) {
 371                         dev_err(map->dev, "IRQ thread failed to resume: %d\n",
 372                                 ret);
 373                         pm_runtime_put(map->dev);
 374                         goto exit;
 375                 }
 376         }
 377
 378         /*
 379          * Read only registers with active IRQs if the chip has 'main status
 380          * register'. Else read in the statuses, using a single bulk read if
 381          * possible in order to reduce the I/O overheads.
 382          */
 383
 384         if (chip->num_main_regs) {
 385                 unsigned int max_main_bits;
 386                 unsigned long size;
 387
 388                 size = chip->num_regs * sizeof(unsigned int);
 389
 390                 max_main_bits = (chip->num_main_status_bits) ?
 391                                  chip->num_main_status_bits : chip->num_regs;
 392                 /* Clear the status buf as we don't read all status regs */
 393                 memset(data->status_buf, 0, size);
 394
 395                 /* We could support bulk read for main status registers
 396                  * but I don't expect to see devices with really many main
 397                  * status registers so let's only support single reads for the
 398                  * sake of simplicity. and add bulk reads only if needed
 399                  */
 400                 for (i = 0; i < chip->num_main_regs; i++) {
 401                         ret = regmap_read(map, chip->main_status +
 402                                   (i * map->reg_stride
 403                                    * data->irq_reg_stride),
 404                                   &data->main_status_buf[i]);
 405                         if (ret) {
 406                                 dev_err(map->dev,
 407                                         "Failed to read IRQ status %d\n",
 408                                         ret);
 409                                 goto exit;
 410                         }
 411                 }
 412
 413                 /* Read sub registers with active IRQs */
 414                 for (i = 0; i < chip->num_main_regs; i++) {
 415                         unsigned int b;
 416                         const unsigned long mreg = data->main_status_buf[i];
 417
 418                         for_each_set_bit(b, &mreg, map->format.val_bytes * 8) {
 419                                 if (i * map->format.val_bytes * 8 + b >
 420                                     max_main_bits)
 421                                         break;
 422                                 ret = read_sub_irq_data(data, b);
 423
 424                                 if (ret != 0) {
 425                                         dev_err(map->dev,
 426                                                 "Failed to read IRQ status %d\n",
 427                                                 ret);
 428                                         if (chip->runtime_pm)
 429                                                 pm_runtime_put(map->dev);
 430                                         goto exit;
 431                                 }
 432                         }
 433
 434                 }
 435         } else if (!map->use_single_read && map->reg_stride == 1 &&
 436                    data->irq_reg_stride == 1) {
 437
 438                 u8 *buf8 = data->status_reg_buf;
 439                 u16 *buf16 = data->status_reg_buf;
 440                 u32 *buf32 = data->status_reg_buf;
 441
 442                 BUG_ON(!data->status_reg_buf);
 443
 444                 ret = regmap_bulk_read(map, chip->status_base,
 445                                        data->status_reg_buf,
 446                                        chip->num_regs);
 447                 if (ret != 0) {
 448                         dev_err(map->dev, "Failed to read IRQ status: %d\n",
 449                                 ret);
 450                         goto exit;
 451                 }
 452
 453                 for (i = 0; i < data->chip->num_regs; i++) {
 454                         switch (map->format.val_bytes) {
 455                         case 1:
 456                                 data->status_buf[i] = buf8[i];
 457                                 break;
 458                         case 2:
 459                                 data->status_buf[i] = buf16[i];
 460                                 break;
 461                         case 4:
 462                                 data->status_buf[i] = buf32[i];
 463                                 break;
 464                         default:
 465                                 BUG();
 466                                 goto exit;
 467                         }
 468                 }
 469
 470         } else {
 471                 for (i = 0; i < data->chip->num_regs; i++) {
 472                         ret = regmap_read(map, chip->status_base +
 473                                           (i * map->reg_stride
 474                                            * data->irq_reg_stride),
 475                                           &data->status_buf[i]);
 476
 477                         if (ret != 0) {
 478                                 dev_err(map->dev,
 479                                         "Failed to read IRQ status: %d\n",
 480                                         ret);
 481                                 if (chip->runtime_pm)
 482                                         pm_runtime_put(map->dev);
 483                                 goto exit;
 484                         }
 485                 }
 486         }
 487
 488         /*
 489          * Ignore masked IRQs and ack if we need to; we ack early so
 490          * there is no race between handling and acknowleding the
 491          * interrupt.  We assume that typically few of the interrupts
 492          * will fire simultaneously so don't worry about overhead from
 493          * doing a write per register.
 494          */
 495         for (i = 0; i < data->chip->num_regs; i++) {
 496                 data->status_buf[i] &= ~data->mask_buf[i];
 497
 498                 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
 499                         reg = chip->ack_base +
 500                                 (i * map->reg_stride * data->irq_reg_stride);
 501                         ret = regmap_write(map, reg, data->status_buf[i]);
 502                         if (ret != 0)
 503                                 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 504                                         reg, ret);
 505                 }
 506         }
 507
 508         for (i = 0; i < chip->num_irqs; i++) {
 509                 if (data->status_buf[chip->irqs[i].reg_offset /
 510                                      map->reg_stride] & chip->irqs[i].mask) {
 511                         handle_nested_irq(irq_find_mapping(data->domain, i));
 512                         handled = true;
 513                 }
 514         }
 515
 516         if (chip->runtime_pm)
 517                 pm_runtime_put(map->dev);
 518
 519 exit:
 520         if (chip->handle_post_irq)
 521                 chip->handle_post_irq(chip->irq_drv_data);
 522
 523         if (handled)
 524                 return IRQ_HANDLED;
 525         else
 526                 return IRQ_NONE;
 527 }
 528
 529 static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
 530                           irq_hw_number_t hw)
 531 {
 532         struct regmap_irq_chip_data *data = h->host_data;
 533
 534         irq_set_chip_data(virq, data);
 535         irq_set_chip(virq, &data->irq_chip);
 536         irq_set_nested_thread(virq, 1);
 537         irq_set_parent(virq, data->irq);
 538         irq_set_noprobe(virq);
 539
 540         return 0;
 541 }
 542
 543 static const struct irq_domain_ops regmap_domain_ops = {
 544         .map    = regmap_irq_map,
 545         .xlate  = irq_domain_xlate_onetwocell,
 546 };
 547
 548 /**
 549  * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
 550  *
 551  * @map: The regmap for the device.
 552  * @irq: The IRQ the device uses to signal interrupts.
 553  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
 554  * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 555  * @chip: Configuration for the interrupt controller.
 556  * @data: Runtime data structure for the controller, allocated on success.
 557  *
 558  * Returns 0 on success or an errno on failure.
 559  *
 560  * In order for this to be efficient the chip really should use a
 561  * register cache.  The chip driver is responsible for restoring the
 562  * register values used by the IRQ controller over suspend and resume.
 563  */
 564 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 565                         int irq_base, const struct regmap_irq_chip *chip,
 566                         struct regmap_irq_chip_data **data)
 567 {
 568         struct regmap_irq_chip_data *d;
 569         int i;
 570         int ret = -ENOMEM;
 571         int num_type_reg;
 572         u32 reg;
 573         u32 unmask_offset;
 574
 575         if (chip->num_regs <= 0)
 576                 return -EINVAL;
 577
 578         if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack))
 579                 return -EINVAL;
 580
 581         for (i = 0; i < chip->num_irqs; i++) {
 582                 if (chip->irqs[i].reg_offset % map->reg_stride)
 583                         return -EINVAL;
 584                 if (chip->irqs[i].reg_offset / map->reg_stride >=
 585                     chip->num_regs)
 586                         return -EINVAL;
 587         }
 588
 589         if (irq_base) {
 590                 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
 591                 if (irq_base < 0) {
 592                         dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
 593                                  irq_base);
 594                         return irq_base;
 595                 }
 596         }
 597
 598         d = kzalloc(sizeof(*d), GFP_KERNEL);
 599         if (!d)
 600                 return -ENOMEM;
 601
 602         if (chip->num_main_regs) {
 603                 d->main_status_buf = kcalloc(chip->num_main_regs,
 604                                              sizeof(unsigned int),
 605                                              GFP_KERNEL);
 606
 607                 if (!d->main_status_buf)
 608                         goto err_alloc;
 609         }
 610
 611         d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
 612                                 GFP_KERNEL);
 613         if (!d->status_buf)
 614                 goto err_alloc;
 615
 616         d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
 617                               GFP_KERNEL);
 618         if (!d->mask_buf)
 619                 goto err_alloc;
 620
 621         d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int),
 622                                   GFP_KERNEL);
 623         if (!d->mask_buf_def)
 624                 goto err_alloc;
 625
 626         if (chip->wake_base) {
 627                 d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
 628                                       GFP_KERNEL);
 629                 if (!d->wake_buf)
 630                         goto err_alloc;
 631         }
 632
 633         num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg;
 634         if (num_type_reg) {
 635                 d->type_buf_def = kcalloc(num_type_reg,
 636                                           sizeof(unsigned int), GFP_KERNEL);
 637                 if (!d->type_buf_def)
 638                         goto err_alloc;
 639
 640                 d->type_buf = kcalloc(num_type_reg, sizeof(unsigned int),
 641                                       GFP_KERNEL);
 642                 if (!d->type_buf)
 643                         goto err_alloc;
 644         }
 645
 646         d->irq_chip = regmap_irq_chip;
 647         d->irq_chip.name = chip->name;
 648         d->irq = irq;
 649         d->map = map;
 650         d->chip = chip;
 651         d->irq_base = irq_base;
 652
 653         if (chip->irq_reg_stride)
 654                 d->irq_reg_stride = chip->irq_reg_stride;
 655         else
 656                 d->irq_reg_stride = 1;
 657
 658         if (chip->type_reg_stride)
 659                 d->type_reg_stride = chip->type_reg_stride;
 660         else
 661                 d->type_reg_stride = 1;
 662
 663         if (!map->use_single_read && map->reg_stride == 1 &&
 664             d->irq_reg_stride == 1) {
 665                 d->status_reg_buf = kmalloc_array(chip->num_regs,
 666                                                   map->format.val_bytes,
 667                                                   GFP_KERNEL);
 668                 if (!d->status_reg_buf)
 669                         goto err_alloc;
 670         }
 671
 672         mutex_init(&d->lock);
 673
 674         for (i = 0; i < chip->num_irqs; i++)
 675                 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
 676                         |= chip->irqs[i].mask;
 677
 678         /* Mask all the interrupts by default */
 679         for (i = 0; i < chip->num_regs; i++) {
 680                 d->mask_buf[i] = d->mask_buf_def[i];
 681                 if (!chip->mask_base)
 682                         continue;
 683
 684                 reg = chip->mask_base +
 685                         (i * map->reg_stride * d->irq_reg_stride);
 686                 if (chip->mask_invert)
 687                         ret = regmap_irq_update_bits(d, reg,
 688                                          d->mask_buf[i], ~d->mask_buf[i]);
 689                 else if (d->chip->unmask_base) {
 690                         unmask_offset = d->chip->unmask_base -
 691                                         d->chip->mask_base;
 692                         ret = regmap_irq_update_bits(d,
 693                                         reg + unmask_offset,
 694                                         d->mask_buf[i],
 695                                         d->mask_buf[i]);
 696                 } else
 697                         ret = regmap_irq_update_bits(d, reg,
 698                                          d->mask_buf[i], d->mask_buf[i]);
 699                 if (ret != 0) {
 700                         dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 701                                 reg, ret);
 702                         goto err_alloc;
 703                 }
 704
 705                 if (!chip->init_ack_masked)
 706                         continue;
 707
 708                 /* Ack masked but set interrupts */
 709                 reg = chip->status_base +
 710                         (i * map->reg_stride * d->irq_reg_stride);
 711                 ret = regmap_read(map, reg, &d->status_buf[i]);
 712                 if (ret != 0) {
 713                         dev_err(map->dev, "Failed to read IRQ status: %d\n",
 714                                 ret);
 715                         goto err_alloc;
 716                 }
 717
 718                 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
 719                         reg = chip->ack_base +
 720                                 (i * map->reg_stride * d->irq_reg_stride);
 721                         if (chip->ack_invert)
 722                                 ret = regmap_write(map, reg,
 723                                         ~(d->status_buf[i] & d->mask_buf[i]));
 724                         else
 725                                 ret = regmap_write(map, reg,
 726                                         d->status_buf[i] & d->mask_buf[i]);
 727                         if (ret != 0) {
 728                                 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 729                                         reg, ret);
 730                                 goto err_alloc;
 731                         }
 732                 }
 733         }
 734
 735         /* Wake is disabled by default */
 736         if (d->wake_buf) {
 737                 for (i = 0; i < chip->num_regs; i++) {
 738                         d->wake_buf[i] = d->mask_buf_def[i];
 739                         reg = chip->wake_base +
 740                                 (i * map->reg_stride * d->irq_reg_stride);
 741
 742                         if (chip->wake_invert)
 743                                 ret = regmap_irq_update_bits(d, reg,
 744                                                          d->mask_buf_def[i],
 745                                                          0);
 746                         else
 747                                 ret = regmap_irq_update_bits(d, reg,
 748                                                          d->mask_buf_def[i],
 749                                                          d->wake_buf[i]);
 750                         if (ret != 0) {
 751                                 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 752                                         reg, ret);
 753                                 goto err_alloc;
 754                         }
 755                 }
 756         }
 757
 758         if (chip->num_type_reg && !chip->type_in_mask) {
 759                 for (i = 0; i < chip->num_type_reg; ++i) {
 760                         reg = chip->type_base +
 761                                 (i * map->reg_stride * d->type_reg_stride);
 762
 763                         ret = regmap_read(map, reg, &d->type_buf_def[i]);
 764
 765                         if (d->chip->type_invert)
 766                                 d->type_buf_def[i] = ~d->type_buf_def[i];
 767
 768                         if (ret) {
 769                                 dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n",
 770                                         reg, ret);
 771                                 goto err_alloc;
 772                         }
 773                 }
 774         }
 775
 776         if (irq_base)
 777                 d->domain = irq_domain_add_legacy(map->dev->of_node,
 778                                                   chip->num_irqs, irq_base, 0,
 779                                                   &regmap_domain_ops, d);
 780         else
 781                 d->domain = irq_domain_add_linear(map->dev->of_node,
 782                                                   chip->num_irqs,
 783                                                   &regmap_domain_ops, d);
 784         if (!d->domain) {
 785                 dev_err(map->dev, "Failed to create IRQ domain\n");
 786                 ret = -ENOMEM;
 787                 goto err_alloc;
 788         }
 789
 790         ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
 791                                    irq_flags | IRQF_ONESHOT,
 792                                    chip->name, d);
 793         if (ret != 0) {
 794                 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
 795                         irq, chip->name, ret);
 796                 goto err_domain;
 797         }
 798
 799         *data = d;
 800
 801         return 0;
 802
 803 err_domain:
 804         /* Should really dispose of the domain but... */
 805 err_alloc:
 806         kfree(d->type_buf);
 807         kfree(d->type_buf_def);
 808         kfree(d->wake_buf);
 809         kfree(d->mask_buf_def);
 810         kfree(d->mask_buf);
 811         kfree(d->status_buf);
 812         kfree(d->status_reg_buf);
 813         kfree(d);
 814         return ret;
 815 }
 816 EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
 817
 818 /**
 819  * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
 820  *
 821  * @irq: Primary IRQ for the device
 822  * @d: &regmap_irq_chip_data allocated by regmap_add_irq_chip()
 823  *
 824  * This function also disposes of all mapped IRQs on the chip.
 825  */
 826 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
 827 {
 828         unsigned int virq;
 829         int hwirq;
 830
 831         if (!d)
 832                 return;
 833
 834         free_irq(irq, d);
 835
 836         /* Dispose all virtual irq from irq domain before removing it */
 837         for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) {
 838                 /* Ignore hwirq if holes in the IRQ list */
 839                 if (!d->chip->irqs[hwirq].mask)
 840                         continue;
 841
 842                 /*
 843                  * Find the virtual irq of hwirq on chip and if it is
 844                  * there then dispose it
 845                  */
 846                 virq = irq_find_mapping(d->domain, hwirq);
 847                 if (virq)
 848                         irq_dispose_mapping(virq);
 849         }
 850
 851         irq_domain_remove(d->domain);
 852         kfree(d->type_buf);
 853         kfree(d->type_buf_def);
 854         kfree(d->wake_buf);
 855         kfree(d->mask_buf_def);
 856         kfree(d->mask_buf);
 857         kfree(d->status_reg_buf);
 858         kfree(d->status_buf);
 859         kfree(d);
 860 }
 861 EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
 862
 863 static void devm_regmap_irq_chip_release(struct device *dev, void *res)
 864 {
 865         struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res;
 866
 867         regmap_del_irq_chip(d->irq, d);
 868 }
 869
 870 static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data)
 871
 872 {
 873         struct regmap_irq_chip_data **r = res;
 874
 875         if (!r || !*r) {
 876                 WARN_ON(!r || !*r);
 877                 return 0;
 878         }
 879         return *r == data;
 880 }
 881
 882 /**
 883  * devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip()
 884  *
 885  * @dev: The device pointer on which irq_chip belongs to.
 886  * @map: The regmap for the device.
 887  * @irq: The IRQ the device uses to signal interrupts
 888  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
 889  * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 890  * @chip: Configuration for the interrupt controller.
 891  * @data: Runtime data structure for the controller, allocated on success
 892  *
 893  * Returns 0 on success or an errno on failure.
 894  *
 895  * The &regmap_irq_chip_data will be automatically released when the device is
 896  * unbound.
 897  */
 898 int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
 899                              int irq_flags, int irq_base,
 900                              const struct regmap_irq_chip *chip,
 901                              struct regmap_irq_chip_data **data)
 902 {
 903         struct regmap_irq_chip_data **ptr, *d;
 904         int ret;
 905
 906         ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr),
 907                            GFP_KERNEL);
 908         if (!ptr)
 909                 return -ENOMEM;
 910
 911         ret = regmap_add_irq_chip(map, irq, irq_flags, irq_base,
 912                                   chip, &d);
 913         if (ret < 0) {
 914                 devres_free(ptr);
 915                 return ret;
 916         }
 917
 918         *ptr = d;
 919         devres_add(dev, ptr);
 920         *data = d;
 921         return 0;
 922 }
 923 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip);
 924
 925 /**
 926  * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
 927  *
 928  * @dev: Device for which which resource was allocated.
 929  * @irq: Primary IRQ for the device.
 930  * @data: &regmap_irq_chip_data allocated by regmap_add_irq_chip().
 931  *
 932  * A resource managed version of regmap_del_irq_chip().
 933  */
 934 void devm_regmap_del_irq_chip(struct device *dev, int irq,
 935                               struct regmap_irq_chip_data *data)
 936 {
 937         int rc;
 938
 939         WARN_ON(irq != data->irq);
 940         rc = devres_release(dev, devm_regmap_irq_chip_release,
 941                             devm_regmap_irq_chip_match, data);
 942
 943         if (rc != 0)
 944                 WARN_ON(rc);
 945 }
 946 EXPORT_SYMBOL_GPL(devm_regmap_del_irq_chip);
 947
 948 /**
 949  * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
 950  *
 951  * @data: regmap irq controller to operate on.
 952  *
 953  * Useful for drivers to request their own IRQs.
 954  */
 955 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
 956 {
 957         WARN_ON(!data->irq_base);
 958         return data->irq_base;
 959 }
 960 EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
 961
 962 /**
 963  * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
 964  *
 965  * @data: regmap irq controller to operate on.
 966  * @irq: index of the interrupt requested in the chip IRQs.
 967  *
 968  * Useful for drivers to request their own IRQs.
 969  */
 970 int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
 971 {
 972         /* Handle holes in the IRQ list */
 973         if (!data->chip->irqs[irq].mask)
 974                 return -EINVAL;
 975
 976         return irq_create_mapping(data->domain, irq);
 977 }
 978 EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
 979
 980 /**
 981  * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
 982  *
 983  * @data: regmap_irq controller to operate on.
 984  *
 985  * Useful for drivers to request their own IRQs and for integration
 986  * with subsystems.  For ease of integration NULL is accepted as a
 987  * domain, allowing devices to just call this even if no domain is
 988  * allocated.
 989  */
 990 struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
 991 {
 992         if (data)
 993                 return data->domain;
 994         else
 995                 return NULL;
 996 }
 997 EXPORT_SYMBOL_GPL(regmap_irq_get_domain);