drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26
  27 #include <linux/firmware.h>
  28 #include <linux/module.h>
  29 #include <drm/drmP.h>
  30 #include <drm/drm.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_pm.h"
  34 #include "amdgpu_vcn.h"
  35 #include "soc15d.h"
  36 #include "soc15_common.h"
  37
  38 #include "vcn/vcn_1_0_offset.h"
  39
  40 /* 1 second timeout */
  41 #define VCN_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  42
  43 /* Firmware Names */
  44 #define FIRMWARE_RAVEN          "amdgpu/raven_vcn.bin"
  45
  46 MODULE_FIRMWARE(FIRMWARE_RAVEN);
  47
  48 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
  49
  50 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
  51 {
  52         unsigned long bo_size;
  53         const char *fw_name;
  54         const struct common_firmware_header *hdr;
  55         unsigned char fw_check;
  56         int r;
  57
  58         INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
  59
  60         switch (adev->asic_type) {
  61         case CHIP_RAVEN:
  62                 fw_name = FIRMWARE_RAVEN;
  63                 break;
  64         default:
  65                 return -EINVAL;
  66         }
  67
  68         r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
  69         if (r) {
  70                 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
  71                         fw_name);
  72                 return r;
  73         }
  74
  75         r = amdgpu_ucode_validate(adev->vcn.fw);
  76         if (r) {
  77                 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
  78                         fw_name);
  79                 release_firmware(adev->vcn.fw);
  80                 adev->vcn.fw = NULL;
  81                 return r;
  82         }
  83
  84         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
  85         adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
  86
  87         /* Bit 20-23, it is encode major and non-zero for new naming convention.
  88          * This field is part of version minor and DRM_DISABLED_FLAG in old naming
  89          * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
  90          * is zero in old naming convention, this field is always zero so far.
  91          * These four bits are used to tell which naming convention is present.
  92          */
  93         fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
  94         if (fw_check) {
  95                 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
  96
  97                 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
  98                 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
  99                 enc_major = fw_check;
 100                 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
 101                 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
 102                 DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n",
 103                         enc_major, enc_minor, dec_ver, vep, fw_rev);
 104         } else {
 105                 unsigned int version_major, version_minor, family_id;
 106
 107                 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 108                 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 109                 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 110                 DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
 111                         version_major, version_minor, family_id);
 112         }
 113
 114         bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
 115                   +  AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
 116                   +  AMDGPU_VCN_SESSION_SIZE * 40;
 117         r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 118                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
 119                                     &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
 120         if (r) {
 121                 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
 122                 return r;
 123         }
 124
 125         return 0;
 126 }
 127
 128 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 129 {
 130         int i;
 131
 132         kfree(adev->vcn.saved_bo);
 133
 134         amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo,
 135                               &adev->vcn.gpu_addr,
 136                               (void **)&adev->vcn.cpu_addr);
 137
 138         amdgpu_ring_fini(&adev->vcn.ring_dec);
 139
 140         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 141                 amdgpu_ring_fini(&adev->vcn.ring_enc[i]);
 142
 143         amdgpu_ring_fini(&adev->vcn.ring_jpeg);
 144
 145         release_firmware(adev->vcn.fw);
 146
 147         return 0;
 148 }
 149
 150 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 151 {
 152         unsigned size;
 153         void *ptr;
 154
 155         if (adev->vcn.vcpu_bo == NULL)
 156                 return 0;
 157
 158         cancel_delayed_work_sync(&adev->vcn.idle_work);
 159
 160         size = amdgpu_bo_size(adev->vcn.vcpu_bo);
 161         ptr = adev->vcn.cpu_addr;
 162
 163         adev->vcn.saved_bo = kmalloc(size, GFP_KERNEL);
 164         if (!adev->vcn.saved_bo)
 165                 return -ENOMEM;
 166
 167         memcpy_fromio(adev->vcn.saved_bo, ptr, size);
 168
 169         return 0;
 170 }
 171
 172 int amdgpu_vcn_resume(struct amdgpu_device *adev)
 173 {
 174         unsigned size;
 175         void *ptr;
 176
 177         if (adev->vcn.vcpu_bo == NULL)
 178                 return -EINVAL;
 179
 180         size = amdgpu_bo_size(adev->vcn.vcpu_bo);
 181         ptr = adev->vcn.cpu_addr;
 182
 183         if (adev->vcn.saved_bo != NULL) {
 184                 memcpy_toio(ptr, adev->vcn.saved_bo, size);
 185                 kfree(adev->vcn.saved_bo);
 186                 adev->vcn.saved_bo = NULL;
 187         } else {
 188                 const struct common_firmware_header *hdr;
 189                 unsigned offset;
 190
 191                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 192                 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 193                 memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
 194                             le32_to_cpu(hdr->ucode_size_bytes));
 195                 size -= le32_to_cpu(hdr->ucode_size_bytes);
 196                 ptr += le32_to_cpu(hdr->ucode_size_bytes);
 197                 memset_io(ptr, 0, size);
 198         }
 199
 200         return 0;
 201 }
 202
 203 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 204 {
 205         struct amdgpu_device *adev =
 206                 container_of(work, struct amdgpu_device, vcn.idle_work.work);
 207         unsigned fences = amdgpu_fence_count_emitted(&adev->vcn.ring_dec);
 208         unsigned i;
 209
 210         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 211                 fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
 212         }
 213
 214         if (fences == 0) {
 215                 if (adev->pm.dpm_enabled)
 216                         amdgpu_dpm_enable_uvd(adev, false);
 217                 else
 218                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 219                                                                AMD_PG_STATE_GATE);
 220         } else {
 221                 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 222         }
 223 }
 224
 225 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 226 {
 227         struct amdgpu_device *adev = ring->adev;
 228         bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
 229
 230         if (set_clocks && adev->pm.dpm_enabled) {
 231                 if (adev->pm.dpm_enabled)
 232                         amdgpu_dpm_enable_uvd(adev, true);
 233                 else
 234                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 235                                                                AMD_PG_STATE_UNGATE);
 236         }
 237 }
 238
 239 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
 240 {
 241         schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 242 }
 243
 244 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
 245 {
 246         struct amdgpu_device *adev = ring->adev;
 247         uint32_t tmp = 0;
 248         unsigned i;
 249         int r;
 250
 251         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
 252         r = amdgpu_ring_alloc(ring, 3);
 253         if (r) {
 254                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 255                           ring->idx, r);
 256                 return r;
 257         }
 258         amdgpu_ring_write(ring,
 259                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
 260         amdgpu_ring_write(ring, 0xDEADBEEF);
 261         amdgpu_ring_commit(ring);
 262         for (i = 0; i < adev->usec_timeout; i++) {
 263                 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
 264                 if (tmp == 0xDEADBEEF)
 265                         break;
 266                 DRM_UDELAY(1);
 267         }
 268
 269         if (i < adev->usec_timeout) {
 270                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 271                          ring->idx, i);
 272         } else {
 273                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 274                           ring->idx, tmp);
 275                 r = -EINVAL;
 276         }
 277         return r;
 278 }
 279
 280 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
 281                                    struct amdgpu_bo *bo,
 282                                    struct dma_fence **fence)
 283 {
 284         struct amdgpu_device *adev = ring->adev;
 285         struct dma_fence *f = NULL;
 286         struct amdgpu_job *job;
 287         struct amdgpu_ib *ib;
 288         uint64_t addr;
 289         int i, r;
 290
 291         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
 292         if (r)
 293                 goto err;
 294
 295         ib = &job->ibs[0];
 296         addr = amdgpu_bo_gpu_offset(bo);
 297         ib->ptr[0] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0);
 298         ib->ptr[1] = addr;
 299         ib->ptr[2] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0);
 300         ib->ptr[3] = addr >> 32;
 301         ib->ptr[4] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0);
 302         ib->ptr[5] = 0;
 303         for (i = 6; i < 16; i += 2) {
 304                 ib->ptr[i] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0);
 305                 ib->ptr[i+1] = 0;
 306         }
 307         ib->length_dw = 16;
 308
 309         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 310         job->fence = dma_fence_get(f);
 311         if (r)
 312                 goto err_free;
 313
 314         amdgpu_job_free(job);
 315
 316         amdgpu_bo_fence(bo, f, false);
 317         amdgpu_bo_unreserve(bo);
 318         amdgpu_bo_unref(&bo);
 319
 320         if (fence)
 321                 *fence = dma_fence_get(f);
 322         dma_fence_put(f);
 323
 324         return 0;
 325
 326 err_free:
 327         amdgpu_job_free(job);
 328
 329 err:
 330         amdgpu_bo_unreserve(bo);
 331         amdgpu_bo_unref(&bo);
 332         return r;
 333 }
 334
 335 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 336                               struct dma_fence **fence)
 337 {
 338         struct amdgpu_device *adev = ring->adev;
 339         struct amdgpu_bo *bo = NULL;
 340         uint32_t *msg;
 341         int r, i;
 342
 343         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 344                                       AMDGPU_GEM_DOMAIN_VRAM,
 345                                       &bo, NULL, (void **)&msg);
 346         if (r)
 347                 return r;
 348
 349         msg[0] = cpu_to_le32(0x00000028);
 350         msg[1] = cpu_to_le32(0x00000038);
 351         msg[2] = cpu_to_le32(0x00000001);
 352         msg[3] = cpu_to_le32(0x00000000);
 353         msg[4] = cpu_to_le32(handle);
 354         msg[5] = cpu_to_le32(0x00000000);
 355         msg[6] = cpu_to_le32(0x00000001);
 356         msg[7] = cpu_to_le32(0x00000028);
 357         msg[8] = cpu_to_le32(0x00000010);
 358         msg[9] = cpu_to_le32(0x00000000);
 359         msg[10] = cpu_to_le32(0x00000007);
 360         msg[11] = cpu_to_le32(0x00000000);
 361         msg[12] = cpu_to_le32(0x00000780);
 362         msg[13] = cpu_to_le32(0x00000440);
 363         for (i = 14; i < 1024; ++i)
 364                 msg[i] = cpu_to_le32(0x0);
 365
 366         return amdgpu_vcn_dec_send_msg(ring, bo, fence);
 367 }
 368
 369 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 370                                struct dma_fence **fence)
 371 {
 372         struct amdgpu_device *adev = ring->adev;
 373         struct amdgpu_bo *bo = NULL;
 374         uint32_t *msg;
 375         int r, i;
 376
 377         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 378                                       AMDGPU_GEM_DOMAIN_VRAM,
 379                                       &bo, NULL, (void **)&msg);
 380         if (r)
 381                 return r;
 382
 383         msg[0] = cpu_to_le32(0x00000028);
 384         msg[1] = cpu_to_le32(0x00000018);
 385         msg[2] = cpu_to_le32(0x00000000);
 386         msg[3] = cpu_to_le32(0x00000002);
 387         msg[4] = cpu_to_le32(handle);
 388         msg[5] = cpu_to_le32(0x00000000);
 389         for (i = 6; i < 1024; ++i)
 390                 msg[i] = cpu_to_le32(0x0);
 391
 392         return amdgpu_vcn_dec_send_msg(ring, bo, fence);
 393 }
 394
 395 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 396 {
 397         struct dma_fence *fence;
 398         long r;
 399
 400         r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
 401         if (r) {
 402                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
 403                 goto error;
 404         }
 405
 406         r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
 407         if (r) {
 408                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
 409                 goto error;
 410         }
 411
 412         r = dma_fence_wait_timeout(fence, false, timeout);
 413         if (r == 0) {
 414                 DRM_ERROR("amdgpu: IB test timed out.\n");
 415                 r = -ETIMEDOUT;
 416         } else if (r < 0) {
 417                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 418         } else {
 419                 DRM_DEBUG("ib test on ring %d succeeded\n",  ring->idx);
 420                 r = 0;
 421         }
 422
 423         dma_fence_put(fence);
 424
 425 error:
 426         return r;
 427 }
 428
 429 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
 430 {
 431         struct amdgpu_device *adev = ring->adev;
 432         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 433         unsigned i;
 434         int r;
 435
 436         r = amdgpu_ring_alloc(ring, 16);
 437         if (r) {
 438                 DRM_ERROR("amdgpu: vcn enc failed to lock ring %d (%d).\n",
 439                           ring->idx, r);
 440                 return r;
 441         }
 442         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
 443         amdgpu_ring_commit(ring);
 444
 445         for (i = 0; i < adev->usec_timeout; i++) {
 446                 if (amdgpu_ring_get_rptr(ring) != rptr)
 447                         break;
 448                 DRM_UDELAY(1);
 449         }
 450
 451         if (i < adev->usec_timeout) {
 452                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 453                          ring->idx, i);
 454         } else {
 455                 DRM_ERROR("amdgpu: ring %d test failed\n",
 456                           ring->idx);
 457                 r = -ETIMEDOUT;
 458         }
 459
 460         return r;
 461 }
 462
 463 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 464                               struct dma_fence **fence)
 465 {
 466         const unsigned ib_size_dw = 16;
 467         struct amdgpu_job *job;
 468         struct amdgpu_ib *ib;
 469         struct dma_fence *f = NULL;
 470         uint64_t dummy;
 471         int i, r;
 472
 473         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 474         if (r)
 475                 return r;
 476
 477         ib = &job->ibs[0];
 478         dummy = ib->gpu_addr + 1024;
 479
 480         ib->length_dw = 0;
 481         ib->ptr[ib->length_dw++] = 0x00000018;
 482         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 483         ib->ptr[ib->length_dw++] = handle;
 484         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 485         ib->ptr[ib->length_dw++] = dummy;
 486         ib->ptr[ib->length_dw++] = 0x0000000b;
 487
 488         ib->ptr[ib->length_dw++] = 0x00000014;
 489         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 490         ib->ptr[ib->length_dw++] = 0x0000001c;
 491         ib->ptr[ib->length_dw++] = 0x00000000;
 492         ib->ptr[ib->length_dw++] = 0x00000000;
 493
 494         ib->ptr[ib->length_dw++] = 0x00000008;
 495         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 496
 497         for (i = ib->length_dw; i < ib_size_dw; ++i)
 498                 ib->ptr[i] = 0x0;
 499
 500         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 501         job->fence = dma_fence_get(f);
 502         if (r)
 503                 goto err;
 504
 505         amdgpu_job_free(job);
 506         if (fence)
 507                 *fence = dma_fence_get(f);
 508         dma_fence_put(f);
 509
 510         return 0;
 511
 512 err:
 513         amdgpu_job_free(job);
 514         return r;
 515 }
 516
 517 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 518                                 struct dma_fence **fence)
 519 {
 520         const unsigned ib_size_dw = 16;
 521         struct amdgpu_job *job;
 522         struct amdgpu_ib *ib;
 523         struct dma_fence *f = NULL;
 524         uint64_t dummy;
 525         int i, r;
 526
 527         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 528         if (r)
 529                 return r;
 530
 531         ib = &job->ibs[0];
 532         dummy = ib->gpu_addr + 1024;
 533
 534         ib->length_dw = 0;
 535         ib->ptr[ib->length_dw++] = 0x00000018;
 536         ib->ptr[ib->length_dw++] = 0x00000001;
 537         ib->ptr[ib->length_dw++] = handle;
 538         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 539         ib->ptr[ib->length_dw++] = dummy;
 540         ib->ptr[ib->length_dw++] = 0x0000000b;
 541
 542         ib->ptr[ib->length_dw++] = 0x00000014;
 543         ib->ptr[ib->length_dw++] = 0x00000002;
 544         ib->ptr[ib->length_dw++] = 0x0000001c;
 545         ib->ptr[ib->length_dw++] = 0x00000000;
 546         ib->ptr[ib->length_dw++] = 0x00000000;
 547
 548         ib->ptr[ib->length_dw++] = 0x00000008;
 549         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 550
 551         for (i = ib->length_dw; i < ib_size_dw; ++i)
 552                 ib->ptr[i] = 0x0;
 553
 554         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 555         job->fence = dma_fence_get(f);
 556         if (r)
 557                 goto err;
 558
 559         amdgpu_job_free(job);
 560         if (fence)
 561                 *fence = dma_fence_get(f);
 562         dma_fence_put(f);
 563
 564         return 0;
 565
 566 err:
 567         amdgpu_job_free(job);
 568         return r;
 569 }
 570
 571 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 572 {
 573         struct dma_fence *fence = NULL;
 574         long r;
 575
 576         r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL);
 577         if (r) {
 578                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
 579                 goto error;
 580         }
 581
 582         r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence);
 583         if (r) {
 584                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
 585                 goto error;
 586         }
 587
 588         r = dma_fence_wait_timeout(fence, false, timeout);
 589         if (r == 0) {
 590                 DRM_ERROR("amdgpu: IB test timed out.\n");
 591                 r = -ETIMEDOUT;
 592         } else if (r < 0) {
 593                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 594         } else {
 595                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 596                 r = 0;
 597         }
 598 error:
 599         dma_fence_put(fence);
 600         return r;
 601 }
 602
 603 int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
 604 {
 605         struct amdgpu_device *adev = ring->adev;
 606         uint32_t tmp = 0;
 607         unsigned i;
 608         int r;
 609
 610         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
 611         r = amdgpu_ring_alloc(ring, 3);
 612
 613         if (r) {
 614                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 615                                   ring->idx, r);
 616                 return r;
 617         }
 618
 619         amdgpu_ring_write(ring,
 620                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0, 0, 0));
 621         amdgpu_ring_write(ring, 0xDEADBEEF);
 622         amdgpu_ring_commit(ring);
 623
 624         for (i = 0; i < adev->usec_timeout; i++) {
 625                 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
 626                 if (tmp == 0xDEADBEEF)
 627                         break;
 628                 DRM_UDELAY(1);
 629         }
 630
 631         if (i < adev->usec_timeout) {
 632                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 633                                   ring->idx, i);
 634         } else {
 635                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 636                                   ring->idx, tmp);
 637                 r = -EINVAL;
 638         }
 639
 640         return r;
 641 }
 642
 643 static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle,
 644                 struct dma_fence **fence)
 645 {
 646         struct amdgpu_device *adev = ring->adev;
 647         struct amdgpu_job *job;
 648         struct amdgpu_ib *ib;
 649         struct dma_fence *f = NULL;
 650         const unsigned ib_size_dw = 16;
 651         int i, r;
 652
 653         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 654         if (r)
 655                 return r;
 656
 657         ib = &job->ibs[0];
 658
 659         ib->ptr[0] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH), 0, 0, PACKETJ_TYPE0);
 660         ib->ptr[1] = 0xDEADBEEF;
 661         for (i = 2; i < 16; i += 2) {
 662                 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
 663                 ib->ptr[i+1] = 0;
 664         }
 665         ib->length_dw = 16;
 666
 667         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 668         job->fence = dma_fence_get(f);
 669         if (r)
 670                 goto err;
 671
 672         amdgpu_job_free(job);
 673         if (fence)
 674                 *fence = dma_fence_get(f);
 675         dma_fence_put(f);
 676
 677         return 0;
 678
 679 err:
 680         amdgpu_job_free(job);
 681         return r;
 682 }
 683
 684 int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 685 {
 686         struct amdgpu_device *adev = ring->adev;
 687         uint32_t tmp = 0;
 688         unsigned i;
 689         struct dma_fence *fence = NULL;
 690         long r = 0;
 691
 692         r = amdgpu_vcn_jpeg_set_reg(ring, 1, &fence);
 693         if (r) {
 694                 DRM_ERROR("amdgpu: failed to set jpeg register (%ld).\n", r);
 695                 goto error;
 696         }
 697
 698         r = dma_fence_wait_timeout(fence, false, timeout);
 699         if (r == 0) {
 700                 DRM_ERROR("amdgpu: IB test timed out.\n");
 701                 r = -ETIMEDOUT;
 702                 goto error;
 703         } else if (r < 0) {
 704                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 705                 goto error;
 706         } else
 707                 r = 0;
 708
 709         for (i = 0; i < adev->usec_timeout; i++) {
 710                 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH));
 711                 if (tmp == 0xDEADBEEF)
 712                         break;
 713                 DRM_UDELAY(1);
 714         }
 715
 716         if (i < adev->usec_timeout)
 717                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 718         else {
 719                 DRM_ERROR("ib test failed (0x%08X)\n", tmp);
 720                 r = -EINVAL;
 721         }
 722
 723         dma_fence_put(fence);
 724
 725 error:
 726         return r;
 727 }