drivers/usb/dwc2/params.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) 2004-2016 Synopsys, Inc.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions, and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. The names of the above-listed copyright holders may not be used
  15  *    to endorse or promote products derived from this software without
  16  *    specific prior written permission.
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation; either version 2 of the License, or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  24  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  25  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  26  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  27  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  28  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  29  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  30  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  31  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  32  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  33  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/of_device.h>
  39
  40 #include "core.h"
  41
  42 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
  43 {
  44         struct dwc2_core_params *p = &hsotg->params;
  45
  46         p->host_rx_fifo_size = 774;
  47         p->max_transfer_size = 65535;
  48         p->max_packet_count = 511;
  49         p->ahbcfg = 0x10;
  50 }
  51
  52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
  53 {
  54         struct dwc2_core_params *p = &hsotg->params;
  55
  56         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
  57         p->speed = DWC2_SPEED_PARAM_HIGH;
  58         p->host_rx_fifo_size = 512;
  59         p->host_nperio_tx_fifo_size = 512;
  60         p->host_perio_tx_fifo_size = 512;
  61         p->max_transfer_size = 65535;
  62         p->max_packet_count = 511;
  63         p->host_channels = 16;
  64         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
  65         p->phy_utmi_width = 8;
  66         p->i2c_enable = false;
  67         p->reload_ctl = false;
  68         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  69                 GAHBCFG_HBSTLEN_SHIFT;
  70         p->change_speed_quirk = true;
  71         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
  72 }
  73
  74 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
  75 {
  76         struct dwc2_core_params *p = &hsotg->params;
  77
  78         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
  79         p->phy_utmi_width = 8;
  80 }
  81
  82 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
  83 {
  84         struct dwc2_core_params *p = &hsotg->params;
  85
  86         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
  87         p->host_rx_fifo_size = 525;
  88         p->host_nperio_tx_fifo_size = 128;
  89         p->host_perio_tx_fifo_size = 256;
  90         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  91                 GAHBCFG_HBSTLEN_SHIFT;
  92         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
  93 }
  94
  95 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
  96 {
  97         struct dwc2_core_params *p = &hsotg->params;
  98
  99         p->otg_cap = 2;
 100         p->host_rx_fifo_size = 288;
 101         p->host_nperio_tx_fifo_size = 128;
 102         p->host_perio_tx_fifo_size = 96;
 103         p->max_transfer_size = 65535;
 104         p->max_packet_count = 511;
 105         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
 106                 GAHBCFG_HBSTLEN_SHIFT;
 107 }
 108
 109 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
 110 {
 111         struct dwc2_core_params *p = &hsotg->params;
 112
 113         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 114         p->speed = DWC2_SPEED_PARAM_HIGH;
 115         p->host_rx_fifo_size = 512;
 116         p->host_nperio_tx_fifo_size = 500;
 117         p->host_perio_tx_fifo_size = 500;
 118         p->host_channels = 16;
 119         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
 120         p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
 121                 GAHBCFG_HBSTLEN_SHIFT;
 122         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 123 }
 124
 125 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
 126 {
 127         struct dwc2_core_params *p = &hsotg->params;
 128
 129         p->lpm = false;
 130         p->lpm_clock_gating = false;
 131         p->besl = false;
 132         p->hird_threshold_en = false;
 133 }
 134
 135 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
 136 {
 137         struct dwc2_core_params *p = &hsotg->params;
 138
 139         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 140 }
 141
 142 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
 143 {
 144         struct dwc2_core_params *p = &hsotg->params;
 145
 146         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 147         p->speed = DWC2_SPEED_PARAM_FULL;
 148         p->host_rx_fifo_size = 128;
 149         p->host_nperio_tx_fifo_size = 96;
 150         p->host_perio_tx_fifo_size = 96;
 151         p->max_packet_count = 256;
 152         p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
 153         p->i2c_enable = false;
 154         p->activate_stm_fs_transceiver = true;
 155 }
 156
 157 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
 158 {
 159         struct dwc2_core_params *p = &hsotg->params;
 160
 161         p->host_rx_fifo_size = 622;
 162         p->host_nperio_tx_fifo_size = 128;
 163         p->host_perio_tx_fifo_size = 256;
 164 }
 165
 166 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
 167 {
 168         struct dwc2_core_params *p = &hsotg->params;
 169
 170         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 171         p->speed = DWC2_SPEED_PARAM_FULL;
 172         p->host_rx_fifo_size = 128;
 173         p->host_nperio_tx_fifo_size = 96;
 174         p->host_perio_tx_fifo_size = 96;
 175         p->max_packet_count = 256;
 176         p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
 177         p->i2c_enable = false;
 178         p->activate_stm_fs_transceiver = true;
 179         p->activate_stm_id_vb_detection = true;
 180         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 181 }
 182
 183 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
 184 {
 185         struct dwc2_core_params *p = &hsotg->params;
 186
 187         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 188         p->activate_stm_id_vb_detection = true;
 189         p->host_rx_fifo_size = 440;
 190         p->host_nperio_tx_fifo_size = 256;
 191         p->host_perio_tx_fifo_size = 256;
 192         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 193 }
 194
 195 const struct of_device_id dwc2_of_match_table[] = {
 196         { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
 197         { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },
 198         { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
 199         { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
 200         { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
 201         { .compatible = "snps,dwc2" },
 202         { .compatible = "samsung,s3c6400-hsotg",
 203           .data = dwc2_set_s3c6400_params },
 204         { .compatible = "amlogic,meson8-usb",
 205           .data = dwc2_set_amlogic_params },
 206         { .compatible = "amlogic,meson8b-usb",
 207           .data = dwc2_set_amlogic_params },
 208         { .compatible = "amlogic,meson-gxbb-usb",
 209           .data = dwc2_set_amlogic_params },
 210         { .compatible = "amlogic,meson-g12a-usb",
 211           .data = dwc2_set_amlogic_g12a_params },
 212         { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
 213         { .compatible = "st,stm32f4x9-fsotg",
 214           .data = dwc2_set_stm32f4x9_fsotg_params },
 215         { .compatible = "st,stm32f4x9-hsotg" },
 216         { .compatible = "st,stm32f7-hsotg",
 217           .data = dwc2_set_stm32f7_hsotg_params },
 218         { .compatible = "st,stm32mp15-fsotg",
 219           .data = dwc2_set_stm32mp15_fsotg_params },
 220         { .compatible = "st,stm32mp15-hsotg",
 221           .data = dwc2_set_stm32mp15_hsotg_params },
 222         {},
 223 };
 224 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 225
 226 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
 227 {
 228         u8 val;
 229
 230         switch (hsotg->hw_params.op_mode) {
 231         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 232                 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
 233                 break;
 234         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 235         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 236         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 237                 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
 238                 break;
 239         default:
 240                 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 241                 break;
 242         }
 243
 244         hsotg->params.otg_cap = val;
 245 }
 246
 247 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
 248 {
 249         int val;
 250         u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
 251
 252         val = DWC2_PHY_TYPE_PARAM_FS;
 253         if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
 254                 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
 255                     hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
 256                         val = DWC2_PHY_TYPE_PARAM_UTMI;
 257                 else
 258                         val = DWC2_PHY_TYPE_PARAM_ULPI;
 259         }
 260
 261         if (dwc2_is_fs_iot(hsotg))
 262                 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
 263
 264         hsotg->params.phy_type = val;
 265 }
 266
 267 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
 268 {
 269         int val;
 270
 271         val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
 272                 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
 273
 274         if (dwc2_is_fs_iot(hsotg))
 275                 val = DWC2_SPEED_PARAM_FULL;
 276
 277         if (dwc2_is_hs_iot(hsotg))
 278                 val = DWC2_SPEED_PARAM_HIGH;
 279
 280         hsotg->params.speed = val;
 281 }
 282
 283 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 284 {
 285         int val;
 286
 287         val = (hsotg->hw_params.utmi_phy_data_width ==
 288                GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
 289
 290         if (hsotg->phy) {
 291                 /*
 292                  * If using the generic PHY framework, check if the PHY bus
 293                  * width is 8-bit and set the phyif appropriately.
 294                  */
 295                 if (phy_get_bus_width(hsotg->phy) == 8)
 296                         val = 8;
 297         }
 298
 299         hsotg->params.phy_utmi_width = val;
 300 }
 301
 302 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 303 {
 304         struct dwc2_core_params *p = &hsotg->params;
 305         int depth_average;
 306         int fifo_count;
 307         int i;
 308
 309         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 310
 311         memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
 312         depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
 313         for (i = 1; i <= fifo_count; i++)
 314                 p->g_tx_fifo_size[i] = depth_average;
 315 }
 316
 317 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
 318 {
 319         int val;
 320
 321         if (hsotg->hw_params.hibernation)
 322                 val = DWC2_POWER_DOWN_PARAM_HIBERNATION;
 323         else if (hsotg->hw_params.power_optimized)
 324                 val = DWC2_POWER_DOWN_PARAM_PARTIAL;
 325         else
 326                 val = DWC2_POWER_DOWN_PARAM_NONE;
 327
 328         hsotg->params.power_down = val;
 329 }
 330
 331 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
 332 {
 333         struct dwc2_core_params *p = &hsotg->params;
 334
 335         p->lpm = hsotg->hw_params.lpm_mode;
 336         if (p->lpm) {
 337                 p->lpm_clock_gating = true;
 338                 p->besl = true;
 339                 p->hird_threshold_en = true;
 340                 p->hird_threshold = 4;
 341         } else {
 342                 p->lpm_clock_gating = false;
 343                 p->besl = false;
 344                 p->hird_threshold_en = false;
 345         }
 346 }
 347
 348 /**
 349  * dwc2_set_default_params() - Set all core parameters to their
 350  * auto-detected default values.
 351  *
 352  * @hsotg: Programming view of the DWC_otg controller
 353  *
 354  */
 355 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
 356 {
 357         struct dwc2_hw_params *hw = &hsotg->hw_params;
 358         struct dwc2_core_params *p = &hsotg->params;
 359         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 360
 361         dwc2_set_param_otg_cap(hsotg);
 362         dwc2_set_param_phy_type(hsotg);
 363         dwc2_set_param_speed(hsotg);
 364         dwc2_set_param_phy_utmi_width(hsotg);
 365         dwc2_set_param_power_down(hsotg);
 366         dwc2_set_param_lpm(hsotg);
 367         p->phy_ulpi_ddr = false;
 368         p->phy_ulpi_ext_vbus = false;
 369
 370         p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
 371         p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
 372         p->i2c_enable = hw->i2c_enable;
 373         p->acg_enable = hw->acg_enable;
 374         p->ulpi_fs_ls = false;
 375         p->ts_dline = false;
 376         p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
 377         p->uframe_sched = true;
 378         p->external_id_pin_ctl = false;
 379         p->ipg_isoc_en = false;
 380         p->service_interval = false;
 381         p->max_packet_count = hw->max_packet_count;
 382         p->max_transfer_size = hw->max_transfer_size;
 383         p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
 384         p->ref_clk_per = 33333;
 385         p->sof_cnt_wkup_alert = 100;
 386
 387         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 388             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 389                 p->host_dma = dma_capable;
 390                 p->dma_desc_enable = false;
 391                 p->dma_desc_fs_enable = false;
 392                 p->host_support_fs_ls_low_power = false;
 393                 p->host_ls_low_power_phy_clk = false;
 394                 p->host_channels = hw->host_channels;
 395                 p->host_rx_fifo_size = hw->rx_fifo_size;
 396                 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
 397                 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
 398         }
 399
 400         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 401             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 402                 p->g_dma = dma_capable;
 403                 p->g_dma_desc = hw->dma_desc_enable;
 404
 405                 /*
 406                  * The values for g_rx_fifo_size (2048) and
 407                  * g_np_tx_fifo_size (1024) come from the legacy s3c
 408                  * gadget driver. These defaults have been hard-coded
 409                  * for some time so many platforms depend on these
 410                  * values. Leave them as defaults for now and only
 411                  * auto-detect if the hardware does not support the
 412                  * default.
 413                  */
 414                 p->g_rx_fifo_size = 2048;
 415                 p->g_np_tx_fifo_size = 1024;
 416                 dwc2_set_param_tx_fifo_sizes(hsotg);
 417         }
 418 }
 419
 420 /**
 421  * dwc2_get_device_properties() - Read in device properties.
 422  *
 423  * @hsotg: Programming view of the DWC_otg controller
 424  *
 425  * Read in the device properties and adjust core parameters if needed.
 426  */
 427 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
 428 {
 429         struct dwc2_core_params *p = &hsotg->params;
 430         int num;
 431
 432         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 433             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 434                 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
 435                                          &p->g_rx_fifo_size);
 436
 437                 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
 438                                          &p->g_np_tx_fifo_size);
 439
 440                 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size");
 441                 if (num > 0) {
 442                         num = min(num, 15);
 443                         memset(p->g_tx_fifo_size, 0,
 444                                sizeof(p->g_tx_fifo_size));
 445                         device_property_read_u32_array(hsotg->dev,
 446                                                        "g-tx-fifo-size",
 447                                                        &p->g_tx_fifo_size[1],
 448                                                        num);
 449                 }
 450         }
 451
 452         if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
 453                 p->oc_disable = true;
 454 }
 455
 456 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
 457 {
 458         int valid = 1;
 459
 460         switch (hsotg->params.otg_cap) {
 461         case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
 462                 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
 463                         valid = 0;
 464                 break;
 465         case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
 466                 switch (hsotg->hw_params.op_mode) {
 467                 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 468                 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 469                 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 470                 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 471                         break;
 472                 default:
 473                         valid = 0;
 474                         break;
 475                 }
 476                 break;
 477         case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
 478                 /* always valid */
 479                 break;
 480         default:
 481                 valid = 0;
 482                 break;
 483         }
 484
 485         if (!valid)
 486                 dwc2_set_param_otg_cap(hsotg);
 487 }
 488
 489 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
 490 {
 491         int valid = 0;
 492         u32 hs_phy_type;
 493         u32 fs_phy_type;
 494
 495         hs_phy_type = hsotg->hw_params.hs_phy_type;
 496         fs_phy_type = hsotg->hw_params.fs_phy_type;
 497
 498         switch (hsotg->params.phy_type) {
 499         case DWC2_PHY_TYPE_PARAM_FS:
 500                 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
 501                         valid = 1;
 502                 break;
 503         case DWC2_PHY_TYPE_PARAM_UTMI:
 504                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 505                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 506                         valid = 1;
 507                 break;
 508         case DWC2_PHY_TYPE_PARAM_ULPI:
 509                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 510                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 511                         valid = 1;
 512                 break;
 513         default:
 514                 break;
 515         }
 516
 517         if (!valid)
 518                 dwc2_set_param_phy_type(hsotg);
 519 }
 520
 521 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
 522 {
 523         int valid = 1;
 524         int phy_type = hsotg->params.phy_type;
 525         int speed = hsotg->params.speed;
 526
 527         switch (speed) {
 528         case DWC2_SPEED_PARAM_HIGH:
 529                 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
 530                     (phy_type == DWC2_PHY_TYPE_PARAM_FS))
 531                         valid = 0;
 532                 break;
 533         case DWC2_SPEED_PARAM_FULL:
 534         case DWC2_SPEED_PARAM_LOW:
 535                 break;
 536         default:
 537                 valid = 0;
 538                 break;
 539         }
 540
 541         if (!valid)
 542                 dwc2_set_param_speed(hsotg);
 543 }
 544
 545 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 546 {
 547         int valid = 0;
 548         int param = hsotg->params.phy_utmi_width;
 549         int width = hsotg->hw_params.utmi_phy_data_width;
 550
 551         switch (width) {
 552         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
 553                 valid = (param == 8);
 554                 break;
 555         case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
 556                 valid = (param == 16);
 557                 break;
 558         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
 559                 valid = (param == 8 || param == 16);
 560                 break;
 561         }
 562
 563         if (!valid)
 564                 dwc2_set_param_phy_utmi_width(hsotg);
 565 }
 566
 567 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
 568 {
 569         int param = hsotg->params.power_down;
 570
 571         switch (param) {
 572         case DWC2_POWER_DOWN_PARAM_NONE:
 573                 break;
 574         case DWC2_POWER_DOWN_PARAM_PARTIAL:
 575                 if (hsotg->hw_params.power_optimized)
 576                         break;
 577                 dev_dbg(hsotg->dev,
 578                         "Partial power down isn't supported by HW\n");
 579                 param = DWC2_POWER_DOWN_PARAM_NONE;
 580                 break;
 581         case DWC2_POWER_DOWN_PARAM_HIBERNATION:
 582                 if (hsotg->hw_params.hibernation)
 583                         break;
 584                 dev_dbg(hsotg->dev,
 585                         "Hibernation isn't supported by HW\n");
 586                 param = DWC2_POWER_DOWN_PARAM_NONE;
 587                 break;
 588         default:
 589                 dev_err(hsotg->dev,
 590                         "%s: Invalid parameter power_down=%d\n",
 591                         __func__, param);
 592                 param = DWC2_POWER_DOWN_PARAM_NONE;
 593                 break;
 594         }
 595
 596         hsotg->params.power_down = param;
 597 }
 598
 599 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 600 {
 601         int fifo_count;
 602         int fifo;
 603         int min;
 604         u32 total = 0;
 605         u32 dptxfszn;
 606
 607         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 608         min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
 609
 610         for (fifo = 1; fifo <= fifo_count; fifo++)
 611                 total += hsotg->params.g_tx_fifo_size[fifo];
 612
 613         if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
 614                 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
 615                          __func__);
 616                 dwc2_set_param_tx_fifo_sizes(hsotg);
 617         }
 618
 619         for (fifo = 1; fifo <= fifo_count; fifo++) {
 620                 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
 621
 622                 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
 623                     hsotg->params.g_tx_fifo_size[fifo] >  dptxfszn) {
 624                         dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
 625                                  __func__, fifo,
 626                                  hsotg->params.g_tx_fifo_size[fifo]);
 627                         hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
 628                 }
 629         }
 630 }
 631
 632 #define CHECK_RANGE(_param, _min, _max, _def) do {                      \
 633                 if ((int)(hsotg->params._param) < (_min) ||             \
 634                     (hsotg->params._param) > (_max)) {                  \
 635                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 636                                  __func__, #_param, hsotg->params._param); \
 637                         hsotg->params._param = (_def);                  \
 638                 }                                                       \
 639         } while (0)
 640
 641 #define CHECK_BOOL(_param, _check) do {                                 \
 642                 if (hsotg->params._param && !(_check)) {                \
 643                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 644                                  __func__, #_param, hsotg->params._param); \
 645                         hsotg->params._param = false;                   \
 646                 }                                                       \
 647         } while (0)
 648
 649 static void dwc2_check_params(struct dwc2_hsotg *hsotg)
 650 {
 651         struct dwc2_hw_params *hw = &hsotg->hw_params;
 652         struct dwc2_core_params *p = &hsotg->params;
 653         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 654
 655         dwc2_check_param_otg_cap(hsotg);
 656         dwc2_check_param_phy_type(hsotg);
 657         dwc2_check_param_speed(hsotg);
 658         dwc2_check_param_phy_utmi_width(hsotg);
 659         dwc2_check_param_power_down(hsotg);
 660         CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
 661         CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
 662         CHECK_BOOL(i2c_enable, hw->i2c_enable);
 663         CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
 664         CHECK_BOOL(acg_enable, hw->acg_enable);
 665         CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
 666         CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
 667         CHECK_BOOL(lpm, hw->lpm_mode);
 668         CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
 669         CHECK_BOOL(besl, hsotg->params.lpm);
 670         CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
 671         CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
 672         CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
 673         CHECK_BOOL(service_interval, hw->service_interval_mode);
 674         CHECK_RANGE(max_packet_count,
 675                     15, hw->max_packet_count,
 676                     hw->max_packet_count);
 677         CHECK_RANGE(max_transfer_size,
 678                     2047, hw->max_transfer_size,
 679                     hw->max_transfer_size);
 680
 681         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 682             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 683                 CHECK_BOOL(host_dma, dma_capable);
 684                 CHECK_BOOL(dma_desc_enable, p->host_dma);
 685                 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
 686                 CHECK_BOOL(host_ls_low_power_phy_clk,
 687                            p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
 688                 CHECK_RANGE(host_channels,
 689                             1, hw->host_channels,
 690                             hw->host_channels);
 691                 CHECK_RANGE(host_rx_fifo_size,
 692                             16, hw->rx_fifo_size,
 693                             hw->rx_fifo_size);
 694                 CHECK_RANGE(host_nperio_tx_fifo_size,
 695                             16, hw->host_nperio_tx_fifo_size,
 696                             hw->host_nperio_tx_fifo_size);
 697                 CHECK_RANGE(host_perio_tx_fifo_size,
 698                             16, hw->host_perio_tx_fifo_size,
 699                             hw->host_perio_tx_fifo_size);
 700         }
 701
 702         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 703             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 704                 CHECK_BOOL(g_dma, dma_capable);
 705                 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
 706                 CHECK_RANGE(g_rx_fifo_size,
 707                             16, hw->rx_fifo_size,
 708                             hw->rx_fifo_size);
 709                 CHECK_RANGE(g_np_tx_fifo_size,
 710                             16, hw->dev_nperio_tx_fifo_size,
 711                             hw->dev_nperio_tx_fifo_size);
 712                 dwc2_check_param_tx_fifo_sizes(hsotg);
 713         }
 714 }
 715
 716 /*
 717  * Gets host hardware parameters. Forces host mode if not currently in
 718  * host mode. Should be called immediately after a core soft reset in
 719  * order to get the reset values.
 720  */
 721 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
 722 {
 723         struct dwc2_hw_params *hw = &hsotg->hw_params;
 724         u32 gnptxfsiz;
 725         u32 hptxfsiz;
 726
 727         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 728                 return;
 729
 730         dwc2_force_mode(hsotg, true);
 731
 732         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 733         hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
 734
 735         hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 736                                        FIFOSIZE_DEPTH_SHIFT;
 737         hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 738                                       FIFOSIZE_DEPTH_SHIFT;
 739 }
 740
 741 /*
 742  * Gets device hardware parameters. Forces device mode if not
 743  * currently in device mode. Should be called immediately after a core
 744  * soft reset in order to get the reset values.
 745  */
 746 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
 747 {
 748         struct dwc2_hw_params *hw = &hsotg->hw_params;
 749         u32 gnptxfsiz;
 750         int fifo, fifo_count;
 751
 752         if (hsotg->dr_mode == USB_DR_MODE_HOST)
 753                 return;
 754
 755         dwc2_force_mode(hsotg, false);
 756
 757         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 758
 759         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 760
 761         for (fifo = 1; fifo <= fifo_count; fifo++) {
 762                 hw->g_tx_fifo_size[fifo] =
 763                         (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
 764                          FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
 765         }
 766
 767         hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 768                                        FIFOSIZE_DEPTH_SHIFT;
 769 }
 770
 771 /**
 772  * During device initialization, read various hardware configuration
 773  * registers and interpret the contents.
 774  *
 775  * @hsotg: Programming view of the DWC_otg controller
 776  *
 777  */
 778 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
 779 {
 780         struct dwc2_hw_params *hw = &hsotg->hw_params;
 781         unsigned int width;
 782         u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
 783         u32 grxfsiz;
 784
 785         hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
 786         hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
 787         hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
 788         hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
 789         grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
 790
 791         /* hwcfg1 */
 792         hw->dev_ep_dirs = hwcfg1;
 793
 794         /* hwcfg2 */
 795         hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
 796                       GHWCFG2_OP_MODE_SHIFT;
 797         hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
 798                    GHWCFG2_ARCHITECTURE_SHIFT;
 799         hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
 800         hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
 801                                 GHWCFG2_NUM_HOST_CHAN_SHIFT);
 802         hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
 803                           GHWCFG2_HS_PHY_TYPE_SHIFT;
 804         hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
 805                           GHWCFG2_FS_PHY_TYPE_SHIFT;
 806         hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
 807                          GHWCFG2_NUM_DEV_EP_SHIFT;
 808         hw->nperio_tx_q_depth =
 809                 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
 810                 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
 811         hw->host_perio_tx_q_depth =
 812                 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
 813                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
 814         hw->dev_token_q_depth =
 815                 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
 816                 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
 817
 818         /* hwcfg3 */
 819         width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
 820                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
 821         hw->max_transfer_size = (1 << (width + 11)) - 1;
 822         width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
 823                 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
 824         hw->max_packet_count = (1 << (width + 4)) - 1;
 825         hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
 826         hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
 827                               GHWCFG3_DFIFO_DEPTH_SHIFT;
 828         hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
 829
 830         /* hwcfg4 */
 831         hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
 832         hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
 833                                   GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
 834         hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
 835                              GHWCFG4_NUM_IN_EPS_SHIFT;
 836         hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
 837         hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
 838         hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
 839         hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
 840                                   GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
 841         hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
 842         hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
 843         hw->service_interval_mode = !!(hwcfg4 &
 844                                        GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
 845
 846         /* fifo sizes */
 847         hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
 848                                 GRXFSIZ_DEPTH_SHIFT;
 849         /*
 850          * Host specific hardware parameters. Reading these parameters
 851          * requires the controller to be in host mode. The mode will
 852          * be forced, if necessary, to read these values.
 853          */
 854         dwc2_get_host_hwparams(hsotg);
 855         dwc2_get_dev_hwparams(hsotg);
 856
 857         return 0;
 858 }
 859
 860 int dwc2_init_params(struct dwc2_hsotg *hsotg)
 861 {
 862         const struct of_device_id *match;
 863         void (*set_params)(void *data);
 864
 865         dwc2_set_default_params(hsotg);
 866         dwc2_get_device_properties(hsotg);
 867
 868         match = of_match_device(dwc2_of_match_table, hsotg->dev);
 869         if (match && match->data) {
 870                 set_params = match->data;
 871                 set_params(hsotg);
 872         }
 873
 874         dwc2_check_params(hsotg);
 875
 876         return 0;
 877 }