drivers/net/wireless/ath/ath11k/dp.h

   1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
   2 /*
   3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef ATH11K_DP_H
   7 #define ATH11K_DP_H
   8
   9 #include "hal_rx.h"
  10
  11 struct ath11k_base;
  12 struct ath11k_peer;
  13 struct ath11k_dp;
  14 struct ath11k_vif;
  15 struct hal_tcl_status_ring;
  16 struct ath11k_ext_irq_grp;
  17
  18 struct dp_rx_tid {
  19         u8 tid;
  20         u32 *vaddr;
  21         dma_addr_t paddr;
  22         u32 size;
  23         u32 ba_win_sz;
  24         bool active;
  25
  26         /* Info related to rx fragments */
  27         u32 cur_sn;
  28         u16 last_frag_no;
  29         u16 rx_frag_bitmap;
  30
  31         struct sk_buff_head rx_frags;
  32         struct hal_reo_dest_ring *dst_ring_desc;
  33
  34         /* Timer info related to fragments */
  35         struct timer_list frag_timer;
  36         struct ath11k_base *ab;
  37 };
  38
  39 #define DP_REO_DESC_FREE_THRESHOLD  64
  40 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000
  41
  42 struct dp_reo_cache_flush_elem {
  43         struct list_head list;
  44         struct dp_rx_tid data;
  45         unsigned long ts;
  46 };
  47
  48 struct dp_reo_cmd {
  49         struct list_head list;
  50         struct dp_rx_tid data;
  51         int cmd_num;
  52         void (*handler)(struct ath11k_dp *, void *,
  53                         enum hal_reo_cmd_status status);
  54 };
  55
  56 struct dp_srng {
  57         u32 *vaddr_unaligned;
  58         u32 *vaddr;
  59         dma_addr_t paddr_unaligned;
  60         dma_addr_t paddr;
  61         int size;
  62         u32 ring_id;
  63 };
  64
  65 struct dp_rxdma_ring {
  66         struct dp_srng refill_buf_ring;
  67         struct idr bufs_idr;
  68         /* Protects bufs_idr */
  69         spinlock_t idr_lock;
  70         int bufs_max;
  71 };
  72
  73 #define ATH11K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE)
  74
  75 struct dp_tx_ring {
  76         u8 tcl_data_ring_id;
  77         struct dp_srng tcl_data_ring;
  78         struct dp_srng tcl_comp_ring;
  79         struct idr txbuf_idr;
  80         /* Protects txbuf_idr and num_pending */
  81         spinlock_t tx_idr_lock;
  82         struct hal_wbm_release_ring *tx_status;
  83         int tx_status_head;
  84         int tx_status_tail;
  85 };
  86
  87 struct ath11k_pdev_mon_stats {
  88         u32 status_ppdu_state;
  89         u32 status_ppdu_start;
  90         u32 status_ppdu_end;
  91         u32 status_ppdu_compl;
  92         u32 status_ppdu_start_mis;
  93         u32 status_ppdu_end_mis;
  94         u32 status_ppdu_done;
  95         u32 dest_ppdu_done;
  96         u32 dest_mpdu_done;
  97         u32 dest_mpdu_drop;
  98         u32 dup_mon_linkdesc_cnt;
  99         u32 dup_mon_buf_cnt;
 100 };
 101
 102 struct dp_link_desc_bank {
 103         void *vaddr_unaligned;
 104         void *vaddr;
 105         dma_addr_t paddr_unaligned;
 106         dma_addr_t paddr;
 107         u32 size;
 108 };
 109
 110 /* Size to enforce scatter idle list mode */
 111 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000
 112 #define DP_LINK_DESC_BANKS_MAX 8
 113
 114 #define DP_RX_DESC_COOKIE_INDEX_MAX             0x3ffff
 115 #define DP_RX_DESC_COOKIE_POOL_ID_MAX           0x1c0000
 116 #define DP_RX_DESC_COOKIE_MAX   \
 117         (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX)
 118 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000
 119
 120 enum ath11k_dp_ppdu_state {
 121         DP_PPDU_STATUS_START,
 122         DP_PPDU_STATUS_DONE,
 123 };
 124
 125 struct ath11k_mon_data {
 126         struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
 127         struct hal_rx_mon_ppdu_info mon_ppdu_info;
 128
 129         u32 mon_ppdu_status;
 130         u32 mon_last_buf_cookie;
 131         u64 mon_last_linkdesc_paddr;
 132         u16 chan_noise_floor;
 133
 134         struct ath11k_pdev_mon_stats rx_mon_stats;
 135         /* lock for monitor data */
 136         spinlock_t mon_lock;
 137         struct sk_buff_head rx_status_q;
 138 };
 139
 140 struct ath11k_pdev_dp {
 141         u32 mac_id;
 142         atomic_t num_tx_pending;
 143         wait_queue_head_t tx_empty_waitq;
 144         struct dp_rxdma_ring rx_refill_buf_ring;
 145         struct dp_srng rxdma_err_dst_ring;
 146         struct dp_srng rxdma_mon_dst_ring;
 147         struct dp_srng rxdma_mon_desc_ring;
 148
 149         struct dp_rxdma_ring rxdma_mon_buf_ring;
 150         struct dp_rxdma_ring rx_mon_status_refill_ring;
 151         struct ieee80211_rx_status rx_status;
 152         struct ath11k_mon_data mon_data;
 153 };
 154
 155 #define DP_NUM_CLIENTS_MAX 64
 156 #define DP_AVG_TIDS_PER_CLIENT 2
 157 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT)
 158 #define DP_AVG_MSDUS_PER_FLOW 128
 159 #define DP_AVG_FLOWS_PER_TID 2
 160 #define DP_AVG_MPDUS_PER_TID_MAX 128
 161 #define DP_AVG_MSDUS_PER_MPDU 4
 162
 163 #define DP_RX_HASH_ENABLE       1 /* Enable hash based Rx steering */
 164
 165 #define DP_BA_WIN_SZ_MAX        256
 166
 167 #define DP_TCL_NUM_RING_MAX     3
 168
 169 #define DP_IDLE_SCATTER_BUFS_MAX 16
 170
 171 #define DP_WBM_RELEASE_RING_SIZE        64
 172 #define DP_TCL_DATA_RING_SIZE           512
 173 #define DP_TX_COMP_RING_SIZE            32768
 174 #define DP_TX_IDR_SIZE                  DP_TX_COMP_RING_SIZE
 175 #define DP_TCL_CMD_RING_SIZE            32
 176 #define DP_TCL_STATUS_RING_SIZE         32
 177 #define DP_REO_DST_RING_MAX             4
 178 #define DP_REO_DST_RING_SIZE            2048
 179 #define DP_REO_REINJECT_RING_SIZE       32
 180 #define DP_RX_RELEASE_RING_SIZE         1024
 181 #define DP_REO_EXCEPTION_RING_SIZE      128
 182 #define DP_REO_CMD_RING_SIZE            128
 183 #define DP_REO_STATUS_RING_SIZE         2048
 184 #define DP_RXDMA_BUF_RING_SIZE          4096
 185 #define DP_RXDMA_REFILL_RING_SIZE       2048
 186 #define DP_RXDMA_ERR_DST_RING_SIZE      1024
 187 #define DP_RXDMA_MON_STATUS_RING_SIZE   1024
 188 #define DP_RXDMA_MONITOR_BUF_RING_SIZE  4096
 189 #define DP_RXDMA_MONITOR_DST_RING_SIZE  2048
 190 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096
 191
 192 #define DP_RX_BUFFER_SIZE       2048
 193 #define DP_RX_BUFFER_ALIGN_SIZE 128
 194
 195 #define DP_RXDMA_BUF_COOKIE_BUF_ID      GENMASK(17, 0)
 196 #define DP_RXDMA_BUF_COOKIE_PDEV_ID     GENMASK(20, 18)
 197
 198 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0)
 199 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1)
 200
 201 #define DP_TX_DESC_ID_MAC_ID  GENMASK(1, 0)
 202 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
 203 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
 204
 205 struct ath11k_dp {
 206         struct ath11k_base *ab;
 207         enum ath11k_htc_ep_id eid;
 208         struct completion htt_tgt_version_received;
 209         u8 htt_tgt_ver_major;
 210         u8 htt_tgt_ver_minor;
 211         struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
 212         struct dp_srng wbm_idle_ring;
 213         struct dp_srng wbm_desc_rel_ring;
 214         struct dp_srng tcl_cmd_ring;
 215         struct dp_srng tcl_status_ring;
 216         struct dp_srng reo_reinject_ring;
 217         struct dp_srng rx_rel_ring;
 218         struct dp_srng reo_except_ring;
 219         struct dp_srng reo_cmd_ring;
 220         struct dp_srng reo_status_ring;
 221         struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX];
 222         struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];
 223         struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX];
 224         struct list_head reo_cmd_list;
 225         struct list_head reo_cmd_cache_flush_list;
 226         u32 reo_cmd_cache_flush_count;
 227         /**
 228          * protects access to below fields,
 229          * - reo_cmd_list
 230          * - reo_cmd_cache_flush_list
 231          * - reo_cmd_cache_flush_count
 232          */
 233         spinlock_t reo_cmd_lock;
 234 };
 235
 236 /* HTT definitions */
 237
 238 #define HTT_TCL_META_DATA_TYPE                  BIT(0)
 239 #define HTT_TCL_META_DATA_VALID_HTT             BIT(1)
 240
 241 /* vdev meta data */
 242 #define HTT_TCL_META_DATA_VDEV_ID               GENMASK(9, 2)
 243 #define HTT_TCL_META_DATA_PDEV_ID               GENMASK(11, 10)
 244 #define HTT_TCL_META_DATA_HOST_INSPECTED        BIT(12)
 245
 246 /* peer meta data */
 247 #define HTT_TCL_META_DATA_PEER_ID               GENMASK(15, 2)
 248
 249 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8
 250
 251 /* HTT tx completion is overlayed in wbm_release_ring */
 252 #define HTT_TX_WBM_COMP_INFO0_STATUS            GENMASK(12, 9)
 253 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON   GENMASK(16, 13)
 254 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON   GENMASK(16, 13)
 255
 256 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI          GENMASK(31, 24)
 257
 258 struct htt_tx_wbm_completion {
 259         u32 info0;
 260         u32 info1;
 261         u32 info2;
 262         u32 info3;
 263 } __packed;
 264
 265 enum htt_h2t_msg_type {
 266         HTT_H2T_MSG_TYPE_VERSION_REQ            = 0,
 267         HTT_H2T_MSG_TYPE_SRING_SETUP            = 0xb,
 268         HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG  = 0xc,
 269         HTT_H2T_MSG_TYPE_EXT_STATS_CFG          = 0x10,
 270         HTT_H2T_MSG_TYPE_PPDU_STATS_CFG         = 0x11,
 271 };
 272
 273 #define HTT_VER_REQ_INFO_MSG_ID         GENMASK(7, 0)
 274
 275 struct htt_ver_req_cmd {
 276         u32 ver_reg_info;
 277 } __packed;
 278
 279 enum htt_srng_ring_type {
 280         HTT_HW_TO_SW_RING,
 281         HTT_SW_TO_HW_RING,
 282         HTT_SW_TO_SW_RING,
 283 };
 284
 285 enum htt_srng_ring_id {
 286         HTT_RXDMA_HOST_BUF_RING,
 287         HTT_RXDMA_MONITOR_STATUS_RING,
 288         HTT_RXDMA_MONITOR_BUF_RING,
 289         HTT_RXDMA_MONITOR_DESC_RING,
 290         HTT_RXDMA_MONITOR_DEST_RING,
 291         HTT_HOST1_TO_FW_RXBUF_RING,
 292         HTT_HOST2_TO_FW_RXBUF_RING,
 293         HTT_RXDMA_NON_MONITOR_DEST_RING,
 294 };
 295
 296 /* host -> target  HTT_SRING_SETUP message
 297  *
 298  * After target is booted up, Host can send SRING setup message for
 299  * each host facing LMAC SRING. Target setups up HW registers based
 300  * on setup message and confirms back to Host if response_required is set.
 301  * Host should wait for confirmation message before sending new SRING
 302  * setup message
 303  *
 304  * The message would appear as follows:
 305  *
 306  * |31            24|23    20|19|18 16|15|14          8|7                0|
 307  * |--------------- +-----------------+----------------+------------------|
 308  * |    ring_type   |      ring_id    |    pdev_id     |     msg_type     |
 309  * |----------------------------------------------------------------------|
 310  * |                          ring_base_addr_lo                           |
 311  * |----------------------------------------------------------------------|
 312  * |                         ring_base_addr_hi                            |
 313  * |----------------------------------------------------------------------|
 314  * |ring_misc_cfg_flag|ring_entry_size|            ring_size              |
 315  * |----------------------------------------------------------------------|
 316  * |                         ring_head_offset32_remote_addr_lo            |
 317  * |----------------------------------------------------------------------|
 318  * |                         ring_head_offset32_remote_addr_hi            |
 319  * |----------------------------------------------------------------------|
 320  * |                         ring_tail_offset32_remote_addr_lo            |
 321  * |----------------------------------------------------------------------|
 322  * |                         ring_tail_offset32_remote_addr_hi            |
 323  * |----------------------------------------------------------------------|
 324  * |                          ring_msi_addr_lo                            |
 325  * |----------------------------------------------------------------------|
 326  * |                          ring_msi_addr_hi                            |
 327  * |----------------------------------------------------------------------|
 328  * |                          ring_msi_data                               |
 329  * |----------------------------------------------------------------------|
 330  * |         intr_timer_th            |IM|      intr_batch_counter_th     |
 331  * |----------------------------------------------------------------------|
 332  * |          reserved        |RR|PTCF|        intr_low_threshold         |
 333  * |----------------------------------------------------------------------|
 334  * Where
 335  *     IM = sw_intr_mode
 336  *     RR = response_required
 337  *     PTCF = prefetch_timer_cfg
 338  *
 339  * The message is interpreted as follows:
 340  * dword0  - b'0:7   - msg_type: This will be set to
 341  *                     HTT_H2T_MSG_TYPE_SRING_SETUP
 342  *           b'8:15  - pdev_id:
 343  *                     0 (for rings at SOC/UMAC level),
 344  *                     1/2/3 mac id (for rings at LMAC level)
 345  *           b'16:23 - ring_id: identify which ring is to setup,
 346  *                     more details can be got from enum htt_srng_ring_id
 347  *           b'24:31 - ring_type: identify type of host rings,
 348  *                     more details can be got from enum htt_srng_ring_type
 349  * dword1  - b'0:31  - ring_base_addr_lo: Lower 32bits of ring base address
 350  * dword2  - b'0:31  - ring_base_addr_hi: Upper 32bits of ring base address
 351  * dword3  - b'0:15  - ring_size: size of the ring in unit of 4-bytes words
 352  *           b'16:23 - ring_entry_size: Size of each entry in 4-byte word units
 353  *           b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and
 354  *                     SW_TO_HW_RING.
 355  *                     Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs.
 356  * dword4  - b'0:31  - ring_head_off32_remote_addr_lo:
 357  *                     Lower 32 bits of memory address of the remote variable
 358  *                     storing the 4-byte word offset that identifies the head
 359  *                     element within the ring.
 360  *                     (The head offset variable has type u32.)
 361  *                     Valid for HW_TO_SW and SW_TO_SW rings.
 362  * dword5  - b'0:31  - ring_head_off32_remote_addr_hi:
 363  *                     Upper 32 bits of memory address of the remote variable
 364  *                     storing the 4-byte word offset that identifies the head
 365  *                     element within the ring.
 366  *                     (The head offset variable has type u32.)
 367  *                     Valid for HW_TO_SW and SW_TO_SW rings.
 368  * dword6  - b'0:31  - ring_tail_off32_remote_addr_lo:
 369  *                     Lower 32 bits of memory address of the remote variable
 370  *                     storing the 4-byte word offset that identifies the tail
 371  *                     element within the ring.
 372  *                     (The tail offset variable has type u32.)
 373  *                     Valid for HW_TO_SW and SW_TO_SW rings.
 374  * dword7  - b'0:31  - ring_tail_off32_remote_addr_hi:
 375  *                     Upper 32 bits of memory address of the remote variable
 376  *                     storing the 4-byte word offset that identifies the tail
 377  *                     element within the ring.
 378  *                     (The tail offset variable has type u32.)
 379  *                     Valid for HW_TO_SW and SW_TO_SW rings.
 380  * dword8  - b'0:31  - ring_msi_addr_lo: Lower 32bits of MSI cfg address
 381  *                     valid only for HW_TO_SW_RING and SW_TO_HW_RING
 382  * dword9  - b'0:31  - ring_msi_addr_hi: Upper 32bits of MSI cfg address
 383  *                     valid only for HW_TO_SW_RING and SW_TO_HW_RING
 384  * dword10 - b'0:31  - ring_msi_data: MSI data
 385  *                     Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs
 386  *                     valid only for HW_TO_SW_RING and SW_TO_HW_RING
 387  * dword11 - b'0:14  - intr_batch_counter_th:
 388  *                     batch counter threshold is in units of 4-byte words.
 389  *                     HW internally maintains and increments batch count.
 390  *                     (see SRING spec for detail description).
 391  *                     When batch count reaches threshold value, an interrupt
 392  *                     is generated by HW.
 393  *           b'15    - sw_intr_mode:
 394  *                     This configuration shall be static.
 395  *                     Only programmed at power up.
 396  *                     0: generate pulse style sw interrupts
 397  *                     1: generate level style sw interrupts
 398  *           b'16:31 - intr_timer_th:
 399  *                     The timer init value when timer is idle or is
 400  *                     initialized to start downcounting.
 401  *                     In 8us units (to cover a range of 0 to 524 ms)
 402  * dword12 - b'0:15  - intr_low_threshold:
 403  *                     Used only by Consumer ring to generate ring_sw_int_p.
 404  *                     Ring entries low threshold water mark, that is used
 405  *                     in combination with the interrupt timer as well as
 406  *                     the the clearing of the level interrupt.
 407  *           b'16:18 - prefetch_timer_cfg:
 408  *                     Used only by Consumer ring to set timer mode to
 409  *                     support Application prefetch handling.
 410  *                     The external tail offset/pointer will be updated
 411  *                     at following intervals:
 412  *                     3'b000: (Prefetch feature disabled; used only for debug)
 413  *                     3'b001: 1 usec
 414  *                     3'b010: 4 usec
 415  *                     3'b011: 8 usec (default)
 416  *                     3'b100: 16 usec
 417  *                     Others: Reserverd
 418  *           b'19    - response_required:
 419  *                     Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
 420  *           b'20:31 - reserved:  reserved for future use
 421  */
 422
 423 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE       GENMASK(7, 0)
 424 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID        GENMASK(15, 8)
 425 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID        GENMASK(23, 16)
 426 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE      GENMASK(31, 24)
 427
 428 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE                      GENMASK(15, 0)
 429 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE                GENMASK(23, 16)
 430 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS              BIT(25)
 431 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP            BIT(27)
 432 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP        BIT(28)
 433 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP            BIT(29)
 434
 435 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH       GENMASK(14, 0)
 436 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE               BIT(15)
 437 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH          GENMASK(31, 16)
 438
 439 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH        GENMASK(15, 0)
 440 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG    BIT(16)
 441 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED      BIT(19)
 442
 443 struct htt_srng_setup_cmd {
 444         u32 info0;
 445         u32 ring_base_addr_lo;
 446         u32 ring_base_addr_hi;
 447         u32 info1;
 448         u32 ring_head_off32_remote_addr_lo;
 449         u32 ring_head_off32_remote_addr_hi;
 450         u32 ring_tail_off32_remote_addr_lo;
 451         u32 ring_tail_off32_remote_addr_hi;
 452         u32 ring_msi_addr_lo;
 453         u32 ring_msi_addr_hi;
 454         u32 msi_data;
 455         u32 intr_info;
 456         u32 info2;
 457 } __packed;
 458
 459 /* host -> target FW  PPDU_STATS config message
 460  *
 461  * @details
 462  * The following field definitions describe the format of the HTT host
 463  * to target FW for PPDU_STATS_CFG msg.
 464  * The message allows the host to configure the PPDU_STATS_IND messages
 465  * produced by the target.
 466  *
 467  * |31          24|23          16|15           8|7            0|
 468  * |-----------------------------------------------------------|
 469  * |    REQ bit mask             |   pdev_mask  |   msg type   |
 470  * |-----------------------------------------------------------|
 471  * Header fields:
 472  *  - MSG_TYPE
 473  *    Bits 7:0
 474  *    Purpose: identifies this is a req to configure ppdu_stats_ind from target
 475  *    Value: 0x11
 476  *  - PDEV_MASK
 477  *    Bits 8:15
 478  *    Purpose: identifies which pdevs this PPDU stats configuration applies to
 479  *    Value: This is a overloaded field, refer to usage and interpretation of
 480  *           PDEV in interface document.
 481  *           Bit   8    :  Reserved for SOC stats
 482  *           Bit 9 - 15 :  Indicates PDEV_MASK in DBDC
 483  *                         Indicates MACID_MASK in DBS
 484  *  - REQ_TLV_BIT_MASK
 485  *    Bits 16:31
 486  *    Purpose: each set bit indicates the corresponding PPDU stats TLV type
 487  *        needs to be included in the target's PPDU_STATS_IND messages.
 488  *    Value: refer htt_ppdu_stats_tlv_tag_t <<<???
 489  *
 490  */
 491
 492 struct htt_ppdu_stats_cfg_cmd {
 493         u32 msg;
 494 } __packed;
 495
 496 #define HTT_PPDU_STATS_CFG_MSG_TYPE             GENMASK(7, 0)
 497 #define HTT_PPDU_STATS_CFG_PDEV_ID              GENMASK(16, 9)
 498 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK     GENMASK(31, 16)
 499
 500 enum htt_ppdu_stats_tag_type {
 501         HTT_PPDU_STATS_TAG_COMMON,
 502         HTT_PPDU_STATS_TAG_USR_COMMON,
 503         HTT_PPDU_STATS_TAG_USR_RATE,
 504         HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64,
 505         HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256,
 506         HTT_PPDU_STATS_TAG_SCH_CMD_STATUS,
 507         HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON,
 508         HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64,
 509         HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256,
 510         HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS,
 511         HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH,
 512         HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY,
 513         HTT_PPDU_STATS_TAG_INFO,
 514         HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD,
 515
 516         /* New TLV's are added above to this line */
 517         HTT_PPDU_STATS_TAG_MAX,
 518 };
 519
 520 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
 521                                    | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
 522                                    | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
 523                                    | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
 524                                    | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
 525                                    | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
 526                                    | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
 527                                    | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
 528
 529 #define HTT_PPDU_STATS_TAG_PKTLOG  (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
 530                                     BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
 531                                     BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
 532                                     BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
 533                                     BIT(HTT_PPDU_STATS_TAG_INFO) | \
 534                                     BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
 535                                     HTT_PPDU_STATS_TAG_DEFAULT)
 536
 537 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message
 538  *
 539  * details:
 540  *    HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to
 541  *    configure RXDMA rings.
 542  *    The configuration is per ring based and includes both packet subtypes
 543  *    and PPDU/MPDU TLVs.
 544  *
 545  *    The message would appear as follows:
 546  *
 547  *    |31       26|25|24|23            16|15             8|7             0|
 548  *    |-----------------+----------------+----------------+---------------|
 549  *    |   rsvd1   |PS|SS|     ring_id    |     pdev_id    |    msg_type   |
 550  *    |-------------------------------------------------------------------|
 551  *    |              rsvd2               |           ring_buffer_size     |
 552  *    |-------------------------------------------------------------------|
 553  *    |                        packet_type_enable_flags_0                 |
 554  *    |-------------------------------------------------------------------|
 555  *    |                        packet_type_enable_flags_1                 |
 556  *    |-------------------------------------------------------------------|
 557  *    |                        packet_type_enable_flags_2                 |
 558  *    |-------------------------------------------------------------------|
 559  *    |                        packet_type_enable_flags_3                 |
 560  *    |-------------------------------------------------------------------|
 561  *    |                         tlv_filter_in_flags                       |
 562  *    |-------------------------------------------------------------------|
 563  * Where:
 564  *     PS = pkt_swap
 565  *     SS = status_swap
 566  * The message is interpreted as follows:
 567  * dword0 - b'0:7   - msg_type: This will be set to
 568  *                    HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
 569  *          b'8:15  - pdev_id:
 570  *                    0 (for rings at SOC/UMAC level),
 571  *                    1/2/3 mac id (for rings at LMAC level)
 572  *          b'16:23 - ring_id : Identify the ring to configure.
 573  *                    More details can be got from enum htt_srng_ring_id
 574  *          b'24    - status_swap: 1 is to swap status TLV
 575  *          b'25    - pkt_swap:  1 is to swap packet TLV
 576  *          b'26:31 - rsvd1:  reserved for future use
 577  * dword1 - b'0:16  - ring_buffer_size: size of bufferes referenced by rx ring,
 578  *                    in byte units.
 579  *                    Valid only for HW_TO_SW_RING and SW_TO_HW_RING
 580  *        - b'16:31 - rsvd2: Reserved for future use
 581  * dword2 - b'0:31  - packet_type_enable_flags_0:
 582  *                    Enable MGMT packet from 0b0000 to 0b1001
 583  *                    bits from low to high: FP, MD, MO - 3 bits
 584  *                        FP: Filter_Pass
 585  *                        MD: Monitor_Direct
 586  *                        MO: Monitor_Other
 587  *                    10 mgmt subtypes * 3 bits -> 30 bits
 588  *                    Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs
 589  * dword3 - b'0:31  - packet_type_enable_flags_1:
 590  *                    Enable MGMT packet from 0b1010 to 0b1111
 591  *                    bits from low to high: FP, MD, MO - 3 bits
 592  *                    Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs
 593  * dword4 - b'0:31 -  packet_type_enable_flags_2:
 594  *                    Enable CTRL packet from 0b0000 to 0b1001
 595  *                    bits from low to high: FP, MD, MO - 3 bits
 596  *                    Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs
 597  * dword5 - b'0:31  - packet_type_enable_flags_3:
 598  *                    Enable CTRL packet from 0b1010 to 0b1111,
 599  *                    MCAST_DATA, UCAST_DATA, NULL_DATA
 600  *                    bits from low to high: FP, MD, MO - 3 bits
 601  *                    Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs
 602  * dword6 - b'0:31 -  tlv_filter_in_flags:
 603  *                    Filter in Attention/MPDU/PPDU/Header/User tlvs
 604  *                    Refer to CFG_TLV_FILTER_IN_FLAG defs
 605  */
 606
 607 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE    GENMASK(7, 0)
 608 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID     GENMASK(15, 8)
 609 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID     GENMASK(23, 16)
 610 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS          BIT(24)
 611 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS          BIT(25)
 612
 613 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE    GENMASK(15, 0)
 614
 615 enum htt_rx_filter_tlv_flags {
 616         HTT_RX_FILTER_TLV_FLAGS_MPDU_START              = BIT(0),
 617         HTT_RX_FILTER_TLV_FLAGS_MSDU_START              = BIT(1),
 618         HTT_RX_FILTER_TLV_FLAGS_RX_PACKET               = BIT(2),
 619         HTT_RX_FILTER_TLV_FLAGS_MSDU_END                = BIT(3),
 620         HTT_RX_FILTER_TLV_FLAGS_MPDU_END                = BIT(4),
 621         HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER           = BIT(5),
 622         HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER         = BIT(6),
 623         HTT_RX_FILTER_TLV_FLAGS_ATTENTION               = BIT(7),
 624         HTT_RX_FILTER_TLV_FLAGS_PPDU_START              = BIT(8),
 625         HTT_RX_FILTER_TLV_FLAGS_PPDU_END                = BIT(9),
 626         HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS     = BIT(10),
 627         HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11),
 628         HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE    = BIT(12),
 629 };
 630
 631 enum htt_rx_mgmt_pkt_filter_tlv_flags0 {
 632         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ          = BIT(0),
 633         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ          = BIT(1),
 634         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ          = BIT(2),
 635         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP         = BIT(3),
 636         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP         = BIT(4),
 637         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP         = BIT(5),
 638         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ        = BIT(6),
 639         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ        = BIT(7),
 640         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ        = BIT(8),
 641         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP       = BIT(9),
 642         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP       = BIT(10),
 643         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP       = BIT(11),
 644         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ          = BIT(12),
 645         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ          = BIT(13),
 646         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ          = BIT(14),
 647         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP         = BIT(15),
 648         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP         = BIT(16),
 649         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP         = BIT(17),
 650         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV   = BIT(18),
 651         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV   = BIT(19),
 652         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV   = BIT(20),
 653         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7         = BIT(21),
 654         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7         = BIT(22),
 655         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7         = BIT(23),
 656         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON             = BIT(24),
 657         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON             = BIT(25),
 658         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON             = BIT(26),
 659         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM               = BIT(27),
 660         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM               = BIT(28),
 661         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM               = BIT(29),
 662 };
 663
 664 enum htt_rx_mgmt_pkt_filter_tlv_flags1 {
 665         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC           = BIT(0),
 666         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC           = BIT(1),
 667         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC           = BIT(2),
 668         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH               = BIT(3),
 669         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH               = BIT(4),
 670         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH               = BIT(5),
 671         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH             = BIT(6),
 672         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH             = BIT(7),
 673         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH             = BIT(8),
 674         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION             = BIT(9),
 675         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION             = BIT(10),
 676         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION             = BIT(11),
 677         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK       = BIT(12),
 678         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK       = BIT(13),
 679         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK       = BIT(14),
 680         HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15        = BIT(15),
 681         HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15        = BIT(16),
 682         HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15        = BIT(17),
 683 };
 684
 685 enum htt_rx_ctrl_pkt_filter_tlv_flags2 {
 686         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1    = BIT(0),
 687         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1    = BIT(1),
 688         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1    = BIT(2),
 689         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2    = BIT(3),
 690         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2    = BIT(4),
 691         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2    = BIT(5),
 692         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER       = BIT(6),
 693         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER       = BIT(7),
 694         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER       = BIT(8),
 695         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4    = BIT(9),
 696         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4    = BIT(10),
 697         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4    = BIT(11),
 698         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL   = BIT(12),
 699         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL   = BIT(13),
 700         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL   = BIT(14),
 701         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP       = BIT(15),
 702         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP       = BIT(16),
 703         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP       = BIT(17),
 704         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT     = BIT(18),
 705         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT     = BIT(19),
 706         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT     = BIT(20),
 707         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER       = BIT(21),
 708         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER       = BIT(22),
 709         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER       = BIT(23),
 710         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR                = BIT(24),
 711         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR                = BIT(25),
 712         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR                = BIT(26),
 713         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA                 = BIT(27),
 714         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA                 = BIT(28),
 715         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA                 = BIT(29),
 716 };
 717
 718 enum htt_rx_ctrl_pkt_filter_tlv_flags3 {
 719         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL             = BIT(0),
 720         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL             = BIT(1),
 721         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL             = BIT(2),
 722         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS                = BIT(3),
 723         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS                = BIT(4),
 724         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS                = BIT(5),
 725         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS                = BIT(6),
 726         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS                = BIT(7),
 727         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS                = BIT(8),
 728         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK                = BIT(9),
 729         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK                = BIT(10),
 730         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK                = BIT(11),
 731         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND              = BIT(12),
 732         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND              = BIT(13),
 733         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND              = BIT(14),
 734         HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK          = BIT(15),
 735         HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK          = BIT(16),
 736         HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK          = BIT(17),
 737 };
 738
 739 enum htt_rx_data_pkt_filter_tlv_flasg3 {
 740         HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST      = BIT(18),
 741         HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST      = BIT(19),
 742         HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST      = BIT(20),
 743         HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST      = BIT(21),
 744         HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST      = BIT(22),
 745         HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST      = BIT(23),
 746         HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA  = BIT(24),
 747         HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA  = BIT(25),
 748         HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA  = BIT(26),
 749 };
 750
 751 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \
 752         (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
 753         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
 754         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
 755         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
 756         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
 757         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
 758         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
 759         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
 760         | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
 761
 762 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \
 763         (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
 764         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
 765         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
 766         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
 767         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
 768         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
 769         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
 770         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
 771         | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
 772
 773 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \
 774         (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
 775         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
 776         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
 777         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
 778         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
 779         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
 780         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
 781         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
 782         | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
 783
 784 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
 785                                      | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
 786                                      | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
 787                                      | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
 788                                      | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
 789
 790 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
 791                                      | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
 792                                      | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
 793                                      | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
 794                                      | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
 795
 796 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
 797                                      | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
 798                                      | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
 799                                      | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
 800                                      | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
 801
 802 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
 803                                      | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
 804                                      | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
 805
 806 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
 807                                      | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
 808                                      | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
 809
 810 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
 811                                      | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
 812                                      | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
 813
 814 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
 815                                      | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
 816                                      | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
 817                                      | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
 818                                      | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
 819                                      | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
 820
 821 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
 822                                      | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
 823                                      | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
 824                                      | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
 825                                      | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
 826                                      | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
 827
 828 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
 829                                      | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
 830                                      | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
 831                                      | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
 832                                      | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
 833                                      | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
 834
 835 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
 836                                      | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
 837                                      | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
 838
 839 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
 840                                      | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
 841                                      | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
 842
 843 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
 844                                      | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
 845                                      | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
 846
 847 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \
 848                 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \
 849                 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
 850
 851 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \
 852                 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \
 853                 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
 854
 855 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \
 856                 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \
 857                 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
 858
 859 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \
 860                 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \
 861                 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
 862
 863 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \
 864                 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \
 865                 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
 866                 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
 867                 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
 868                 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
 869                 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
 870                 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
 871                 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
 872
 873 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \
 874                 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \
 875                 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
 876                 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
 877                 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
 878                 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
 879                 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
 880                 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
 881                 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
 882
 883 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3
 884
 885 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3
 886
 887 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3
 888
 889 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3
 890
 891 #define HTT_RX_MON_FILTER_TLV_FLAGS \
 892                 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
 893                 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
 894                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
 895                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
 896                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
 897                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
 898
 899 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \
 900                 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
 901                 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
 902                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
 903                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
 904                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
 905                 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
 906
 907 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \
 908                 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
 909                 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \
 910                 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
 911                 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \
 912                 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \
 913                 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \
 914                 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
 915                 HTT_RX_FILTER_TLV_FLAGS_ATTENTION)
 916
 917 struct htt_rx_ring_selection_cfg_cmd {
 918         u32 info0;
 919         u32 info1;
 920         u32 pkt_type_en_flags0;
 921         u32 pkt_type_en_flags1;
 922         u32 pkt_type_en_flags2;
 923         u32 pkt_type_en_flags3;
 924         u32 rx_filter_tlv;
 925 } __packed;
 926
 927 struct htt_rx_ring_tlv_filter {
 928         u32 rx_filter; /* see htt_rx_filter_tlv_flags */
 929         u32 pkt_filter_flags0; /* MGMT */
 930         u32 pkt_filter_flags1; /* MGMT */
 931         u32 pkt_filter_flags2; /* CTRL */
 932         u32 pkt_filter_flags3; /* DATA */
 933 };
 934
 935 /* HTT message target->host */
 936
 937 enum htt_t2h_msg_type {
 938         HTT_T2H_MSG_TYPE_VERSION_CONF,
 939         HTT_T2H_MSG_TYPE_RX_ADDBA       = 0x5,
 940         HTT_T2H_MSG_TYPE_PKTLOG         = 0x8,
 941         HTT_T2H_MSG_TYPE_SEC_IND        = 0xb,
 942         HTT_T2H_MSG_TYPE_PEER_MAP       = 0x1e,
 943         HTT_T2H_MSG_TYPE_PEER_UNMAP     = 0x1f,
 944         HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d,
 945         HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c,
 946         HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,
 947 };
 948
 949 #define HTT_TARGET_VERSION_MAJOR 3
 950
 951 #define HTT_T2H_MSG_TYPE                GENMASK(7, 0)
 952 #define HTT_T2H_VERSION_CONF_MINOR      GENMASK(15, 8)
 953 #define HTT_T2H_VERSION_CONF_MAJOR      GENMASK(23, 16)
 954
 955 struct htt_t2h_version_conf_msg {
 956         u32 version;
 957 } __packed;
 958
 959 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID   GENMASK(15, 8)
 960 #define HTT_T2H_PEER_MAP_INFO_PEER_ID   GENMASK(31, 16)
 961 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16     GENMASK(15, 0)
 962 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID       GENMASK(31, 16)
 963 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL     GENMASK(15, 0)
 964 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M       BIT(16)
 965 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S       16
 966
 967 struct htt_t2h_peer_map_event {
 968         u32 info;
 969         u32 mac_addr_l32;
 970         u32 info1;
 971         u32 info2;
 972 } __packed;
 973
 974 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID
 975 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID
 976 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \
 977                                         HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16
 978 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M
 979 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S
 980
 981 struct htt_t2h_peer_unmap_event {
 982         u32 info;
 983         u32 mac_addr_l32;
 984         u32 info1;
 985 } __packed;
 986
 987 struct htt_resp_msg {
 988         union {
 989                 struct htt_t2h_version_conf_msg version_msg;
 990                 struct htt_t2h_peer_map_event peer_map_ev;
 991                 struct htt_t2h_peer_unmap_event peer_unmap_ev;
 992         };
 993 } __packed;
 994
 995 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8)
 996 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16)
 997 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24)
 998
 999 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0)
1000 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16)
1001
1002 #define HTT_BACKPRESSURE_UMAC_RING_TYPE 0
1003 #define HTT_BACKPRESSURE_LMAC_RING_TYPE 1
1004
1005 enum htt_backpressure_umac_ringid {
1006         HTT_SW_RING_IDX_REO_REO2SW1_RING,
1007         HTT_SW_RING_IDX_REO_REO2SW2_RING,
1008         HTT_SW_RING_IDX_REO_REO2SW3_RING,
1009         HTT_SW_RING_IDX_REO_REO2SW4_RING,
1010         HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING,
1011         HTT_SW_RING_IDX_REO_REO2TCL_RING,
1012         HTT_SW_RING_IDX_REO_REO2FW_RING,
1013         HTT_SW_RING_IDX_REO_REO_RELEASE_RING,
1014         HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING,
1015         HTT_SW_RING_IDX_TCL_TCL2TQM_RING,
1016         HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING,
1017         HTT_SW_RING_IDX_WBM_REO_RELEASE_RING,
1018         HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING,
1019         HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING,
1020         HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING,
1021         HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING,
1022         HTT_SW_RING_IDX_REO_REO_CMD_RING,
1023         HTT_SW_RING_IDX_REO_REO_STATUS_RING,
1024         HTT_SW_UMAC_RING_IDX_MAX,
1025 };
1026
1027 enum htt_backpressure_lmac_ringid {
1028         HTT_SW_RING_IDX_FW2RXDMA_BUF_RING,
1029         HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING,
1030         HTT_SW_RING_IDX_FW2RXDMA_LINK_RING,
1031         HTT_SW_RING_IDX_SW2RXDMA_BUF_RING,
1032         HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING,
1033         HTT_SW_RING_IDX_RXDMA2FW_RING,
1034         HTT_SW_RING_IDX_RXDMA2SW_RING,
1035         HTT_SW_RING_IDX_RXDMA2RELEASE_RING,
1036         HTT_SW_RING_IDX_RXDMA2REO_RING,
1037         HTT_SW_RING_IDX_MONITOR_STATUS_RING,
1038         HTT_SW_RING_IDX_MONITOR_BUF_RING,
1039         HTT_SW_RING_IDX_MONITOR_DESC_RING,
1040         HTT_SW_RING_IDX_MONITOR_DEST_RING,
1041         HTT_SW_LMAC_RING_IDX_MAX,
1042 };
1043
1044 /* ppdu stats
1045  *
1046  * @details
1047  * The following field definitions describe the format of the HTT target
1048  * to host ppdu stats indication message.
1049  *
1050  *
1051  * |31                         16|15   12|11   10|9      8|7            0 |
1052  * |----------------------------------------------------------------------|
1053  * |    payload_size             | rsvd  |pdev_id|mac_id  |    msg type   |
1054  * |----------------------------------------------------------------------|
1055  * |                          ppdu_id                                     |
1056  * |----------------------------------------------------------------------|
1057  * |                        Timestamp in us                               |
1058  * |----------------------------------------------------------------------|
1059  * |                          reserved                                    |
1060  * |----------------------------------------------------------------------|
1061  * |                    type-specific stats info                          |
1062  * |                     (see htt_ppdu_stats.h)                           |
1063  * |----------------------------------------------------------------------|
1064  * Header fields:
1065  *  - MSG_TYPE
1066  *    Bits 7:0
1067  *    Purpose: Identifies this is a PPDU STATS indication
1068  *             message.
1069  *    Value: 0x1d
1070  *  - mac_id
1071  *    Bits 9:8
1072  *    Purpose: mac_id of this ppdu_id
1073  *    Value: 0-3
1074  *  - pdev_id
1075  *    Bits 11:10
1076  *    Purpose: pdev_id of this ppdu_id
1077  *    Value: 0-3
1078  *     0 (for rings at SOC level),
1079  *     1/2/3 PDEV -> 0/1/2
1080  *  - payload_size
1081  *    Bits 31:16
1082  *    Purpose: total tlv size
1083  *    Value: payload_size in bytes
1084  */
1085
1086 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)
1087 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)
1088
1089 struct ath11k_htt_ppdu_stats_msg {
1090         u32 info;
1091         u32 ppdu_id;
1092         u32 timestamp;
1093         u32 rsvd;
1094         u8 data[0];
1095 } __packed;
1096
1097 struct htt_tlv {
1098         u32 header;
1099         u8 value[0];
1100 } __packed;
1101
1102 #define HTT_TLV_TAG                     GENMASK(11, 0)
1103 #define HTT_TLV_LEN                     GENMASK(23, 12)
1104
1105 enum HTT_PPDU_STATS_BW {
1106         HTT_PPDU_STATS_BANDWIDTH_5MHZ   = 0,
1107         HTT_PPDU_STATS_BANDWIDTH_10MHZ  = 1,
1108         HTT_PPDU_STATS_BANDWIDTH_20MHZ  = 2,
1109         HTT_PPDU_STATS_BANDWIDTH_40MHZ  = 3,
1110         HTT_PPDU_STATS_BANDWIDTH_80MHZ  = 4,
1111         HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */
1112         HTT_PPDU_STATS_BANDWIDTH_DYN    = 6,
1113 };
1114
1115 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M   GENMASK(7, 0)
1116 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M   GENMASK(15, 8)
1117 /* bw - HTT_PPDU_STATS_BW */
1118 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M           GENMASK(19, 16)
1119
1120 struct htt_ppdu_stats_common {
1121         u32 ppdu_id;
1122         u16 sched_cmdid;
1123         u8 ring_id;
1124         u8 num_users;
1125         u32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/
1126         u32 chain_mask;
1127         u32 fes_duration_us; /* frame exchange sequence */
1128         u32 ppdu_sch_eval_start_tstmp_us;
1129         u32 ppdu_sch_end_tstmp_us;
1130         u32 ppdu_start_tstmp_us;
1131         /* BIT [15 :  0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted
1132          * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted
1133          */
1134         u16 phy_mode;
1135         u16 bw_mhz;
1136 } __packed;
1137
1138 enum htt_ppdu_stats_gi {
1139         HTT_PPDU_STATS_SGI_0_8_US,
1140         HTT_PPDU_STATS_SGI_0_4_US,
1141         HTT_PPDU_STATS_SGI_1_6_US,
1142         HTT_PPDU_STATS_SGI_3_2_US,
1143 };
1144
1145 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M       GENMASK(3, 0)
1146 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M    GENMASK(11, 4)
1147
1148 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0)
1149 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M      GENMASK(5, 1)
1150
1151 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M       GENMASK(1, 0)
1152 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M           BIT(2)
1153 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M          BIT(3)
1154 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M           GENMASK(7, 4)
1155 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M             GENMASK(11, 8)
1156 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M            GENMASK(15, 12)
1157 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M            GENMASK(19, 16)
1158 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M       GENMASK(23, 20)
1159 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M             GENMASK(27, 24)
1160 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M            BIT(28)
1161 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M           BIT(29)
1162
1163 #define HTT_USR_RATE_PREAMBLE(_val) \
1164                 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val)
1165 #define HTT_USR_RATE_BW(_val) \
1166                 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val)
1167 #define HTT_USR_RATE_NSS(_val) \
1168                 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val)
1169 #define HTT_USR_RATE_MCS(_val) \
1170                 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val)
1171 #define HTT_USR_RATE_GI(_val) \
1172                 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val)
1173 #define HTT_USR_RATE_DCM(_val) \
1174                 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val)
1175
1176 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M          GENMASK(1, 0)
1177 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M              BIT(2)
1178 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M             BIT(3)
1179 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M              GENMASK(7, 4)
1180 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M                GENMASK(11, 8)
1181 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M               GENMASK(15, 12)
1182 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M               GENMASK(19, 16)
1183 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M          GENMASK(23, 20)
1184 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M                GENMASK(27, 24)
1185 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M               BIT(28)
1186 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M              BIT(29)
1187
1188 struct htt_ppdu_stats_user_rate {
1189         u8 tid_num;
1190         u8 reserved0;
1191         u16 sw_peer_id;
1192         u32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/
1193         u16 ru_end;
1194         u16 ru_start;
1195         u16 resp_ru_end;
1196         u16 resp_ru_start;
1197         u32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */
1198         u32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */
1199         /* Note: resp_rate_info is only valid for if resp_type is UL */
1200         u32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */
1201 } __packed;
1202
1203 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M         GENMASK(7, 0)
1204 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M         BIT(8)
1205 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M    GENMASK(10, 9)
1206 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M               GENMASK(13, 11)
1207 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M              BIT(14)
1208 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M           GENMASK(31, 16)
1209
1210 #define HTT_TX_INFO_IS_AMSDU(_flags) \
1211                         FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags)
1212 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \
1213                         FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags)
1214 #define HTT_TX_INFO_RATECODE(_flags) \
1215                         FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags)
1216 #define HTT_TX_INFO_PEERID(_flags) \
1217                         FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags)
1218
1219 struct htt_tx_ppdu_stats_info {
1220         struct htt_tlv tlv_hdr;
1221         u32 tx_success_bytes;
1222         u32 tx_retry_bytes;
1223         u32 tx_failed_bytes;
1224         u32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */
1225         u16 tx_success_msdus;
1226         u16 tx_retry_msdus;
1227         u16 tx_failed_msdus;
1228         u16 tx_duration; /* united in us */
1229 } __packed;
1230
1231 enum  htt_ppdu_stats_usr_compln_status {
1232         HTT_PPDU_STATS_USER_STATUS_OK,
1233         HTT_PPDU_STATS_USER_STATUS_FILTERED,
1234         HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT,
1235         HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH,
1236         HTT_PPDU_STATS_USER_STATUS_ABORT,
1237 };
1238
1239 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M        GENMASK(3, 0)
1240 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M       GENMASK(7, 4)
1241 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M          BIT(8)
1242 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M         GENMASK(12, 9)
1243
1244 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \
1245             FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val)
1246 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \
1247             FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val)
1248 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \
1249             FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val)
1250
1251 struct htt_ppdu_stats_usr_cmpltn_cmn {
1252         u8 status;
1253         u8 tid_num;
1254         u16 sw_peer_id;
1255         /* RSSI value of last ack packet (units = dB above noise floor) */
1256         u32 ack_rssi;
1257         u16 mpdu_tried;
1258         u16 mpdu_success;
1259         u32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/
1260 } __packed;
1261
1262 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M   GENMASK(8, 0)
1263 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M   GENMASK(24, 9)
1264 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM      GENMASK(31, 25)
1265
1266 #define HTT_PPDU_STATS_NON_QOS_TID      16
1267
1268 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status {
1269         u32 ppdu_id;
1270         u16 sw_peer_id;
1271         u16 reserved0;
1272         u32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */
1273         u16 current_seq;
1274         u16 start_seq;
1275         u32 success_bytes;
1276 } __packed;
1277
1278 struct htt_ppdu_stats_usr_cmn_array {
1279         struct htt_tlv tlv_hdr;
1280         u32 num_ppdu_stats;
1281         /* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info
1282          * elements.
1283          * tx_ppdu_stats_info is variable length, with length =
1284          *     number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info)
1285          */
1286         struct htt_tx_ppdu_stats_info tx_ppdu_info[0];
1287 } __packed;
1288
1289 struct htt_ppdu_user_stats {
1290         u16 peer_id;
1291         u32 tlv_flags;
1292         bool is_valid_peer_id;
1293         struct htt_ppdu_stats_user_rate rate;
1294         struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn;
1295         struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba;
1296 };
1297
1298 #define HTT_PPDU_STATS_MAX_USERS        8
1299 #define HTT_PPDU_DESC_MAX_DEPTH 16
1300
1301 struct htt_ppdu_stats {
1302         struct htt_ppdu_stats_common common;
1303         struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS];
1304 };
1305
1306 struct htt_ppdu_stats_info {
1307         u32 ppdu_id;
1308         struct htt_ppdu_stats ppdu_stats;
1309         struct list_head list;
1310 };
1311
1312 /**
1313  * @brief target -> host packet log message
1314  *
1315  * @details
1316  * The following field definitions describe the format of the packet log
1317  * message sent from the target to the host.
1318  * The message consists of a 4-octet header,followed by a variable number
1319  * of 32-bit character values.
1320  *
1321  * |31                         16|15  12|11   10|9    8|7            0|
1322  * |------------------------------------------------------------------|
1323  * |        payload_size         | rsvd |pdev_id|mac_id|   msg type   |
1324  * |------------------------------------------------------------------|
1325  * |                              payload                             |
1326  * |------------------------------------------------------------------|
1327  *   - MSG_TYPE
1328  *     Bits 7:0
1329  *     Purpose: identifies this as a pktlog message
1330  *     Value: HTT_T2H_MSG_TYPE_PKTLOG
1331  *   - mac_id
1332  *     Bits 9:8
1333  *     Purpose: identifies which MAC/PHY instance generated this pktlog info
1334  *     Value: 0-3
1335  *   - pdev_id
1336  *     Bits 11:10
1337  *     Purpose: pdev_id
1338  *     Value: 0-3
1339  *     0 (for rings at SOC level),
1340  *     1/2/3 PDEV -> 0/1/2
1341  *   - payload_size
1342  *     Bits 31:16
1343  *     Purpose: explicitly specify the payload size
1344  *     Value: payload size in bytes (payload size is a multiple of 4 bytes)
1345  */
1346 struct htt_pktlog_msg {
1347         u32 hdr;
1348         u8 payload[0];
1349 };
1350
1351 /**
1352  * @brief host -> target FW extended statistics retrieve
1353  *
1354  * @details
1355  * The following field definitions describe the format of the HTT host
1356  * to target FW extended stats retrieve message.
1357  * The message specifies the type of stats the host wants to retrieve.
1358  *
1359  * |31          24|23          16|15           8|7            0|
1360  * |-----------------------------------------------------------|
1361  * |   reserved   | stats type   |   pdev_mask  |   msg type   |
1362  * |-----------------------------------------------------------|
1363  * |                   config param [0]                        |
1364  * |-----------------------------------------------------------|
1365  * |                   config param [1]                        |
1366  * |-----------------------------------------------------------|
1367  * |                   config param [2]                        |
1368  * |-----------------------------------------------------------|
1369  * |                   config param [3]                        |
1370  * |-----------------------------------------------------------|
1371  * |                         reserved                          |
1372  * |-----------------------------------------------------------|
1373  * |                        cookie LSBs                        |
1374  * |-----------------------------------------------------------|
1375  * |                        cookie MSBs                        |
1376  * |-----------------------------------------------------------|
1377  * Header fields:
1378  *  - MSG_TYPE
1379  *    Bits 7:0
1380  *    Purpose: identifies this is a extended stats upload request message
1381  *    Value: 0x10
1382  *  - PDEV_MASK
1383  *    Bits 8:15
1384  *    Purpose: identifies the mask of PDEVs to retrieve stats from
1385  *    Value: This is a overloaded field, refer to usage and interpretation of
1386  *           PDEV in interface document.
1387  *           Bit   8    :  Reserved for SOC stats
1388  *           Bit 9 - 15 :  Indicates PDEV_MASK in DBDC
1389  *                         Indicates MACID_MASK in DBS
1390  *  - STATS_TYPE
1391  *    Bits 23:16
1392  *    Purpose: identifies which FW statistics to upload
1393  *    Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)
1394  *  - Reserved
1395  *    Bits 31:24
1396  *  - CONFIG_PARAM [0]
1397  *    Bits 31:0
1398  *    Purpose: give an opaque configuration value to the specified stats type
1399  *    Value: stats-type specific configuration value
1400  *           Refer to htt_stats.h for interpretation for each stats sub_type
1401  *  - CONFIG_PARAM [1]
1402  *    Bits 31:0
1403  *    Purpose: give an opaque configuration value to the specified stats type
1404  *    Value: stats-type specific configuration value
1405  *           Refer to htt_stats.h for interpretation for each stats sub_type
1406  *  - CONFIG_PARAM [2]
1407  *    Bits 31:0
1408  *    Purpose: give an opaque configuration value to the specified stats type
1409  *    Value: stats-type specific configuration value
1410  *           Refer to htt_stats.h for interpretation for each stats sub_type
1411  *  - CONFIG_PARAM [3]
1412  *    Bits 31:0
1413  *    Purpose: give an opaque configuration value to the specified stats type
1414  *    Value: stats-type specific configuration value
1415  *           Refer to htt_stats.h for interpretation for each stats sub_type
1416  *  - Reserved [31:0] for future use.
1417  *  - COOKIE_LSBS
1418  *    Bits 31:0
1419  *    Purpose: Provide a mechanism to match a target->host stats confirmation
1420  *        message with its preceding host->target stats request message.
1421  *    Value: LSBs of the opaque cookie specified by the host-side requestor
1422  *  - COOKIE_MSBS
1423  *    Bits 31:0
1424  *    Purpose: Provide a mechanism to match a target->host stats confirmation
1425  *        message with its preceding host->target stats request message.
1426  *    Value: MSBs of the opaque cookie specified by the host-side requestor
1427  */
1428
1429 struct htt_ext_stats_cfg_hdr {
1430         u8 msg_type;
1431         u8 pdev_mask;
1432         u8 stats_type;
1433         u8 reserved;
1434 } __packed;
1435
1436 struct htt_ext_stats_cfg_cmd {
1437         struct htt_ext_stats_cfg_hdr hdr;
1438         u32 cfg_param0;
1439         u32 cfg_param1;
1440         u32 cfg_param2;
1441         u32 cfg_param3;
1442         u32 reserved;
1443         u32 cookie_lsb;
1444         u32 cookie_msb;
1445 } __packed;
1446
1447 /* htt stats config default params */
1448 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0
1449 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff
1450 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff
1451 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff
1452 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff
1453 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff
1454 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00
1455 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00
1456
1457 /* HTT_DBG_EXT_STATS_PEER_INFO
1458  * PARAMS:
1459  * @config_param0:
1460  *  [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request
1461  *  [Bit15 : Bit 1] htt_peer_stats_req_mode_t
1462  *  [Bit31 : Bit16] sw_peer_id
1463  * @config_param1:
1464  *  peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum)
1465  *   0 bit htt_peer_stats_cmn_tlv
1466  *   1 bit htt_peer_details_tlv
1467  *   2 bit htt_tx_peer_rate_stats_tlv
1468  *   3 bit htt_rx_peer_rate_stats_tlv
1469  *   4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv
1470  *   5 bit htt_rx_tid_stats_tlv
1471  *   6 bit htt_msdu_flow_stats_tlv
1472  * @config_param2: [Bit31 : Bit0] mac_addr31to0
1473  * @config_param3: [Bit15 : Bit0] mac_addr47to32
1474  *                [Bit31 : Bit16] reserved
1475  */
1476 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
1477 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f
1478
1479 /* Used to set different configs to the specified stats type.*/
1480 struct htt_ext_stats_cfg_params {
1481         u32 cfg0;
1482         u32 cfg1;
1483         u32 cfg2;
1484         u32 cfg3;
1485 };
1486
1487 /**
1488  * @brief target -> host extended statistics upload
1489  *
1490  * @details
1491  * The following field definitions describe the format of the HTT target
1492  * to host stats upload confirmation message.
1493  * The message contains a cookie echoed from the HTT host->target stats
1494  * upload request, which identifies which request the confirmation is
1495  * for, and a single stats can span over multiple HTT stats indication
1496  * due to the HTT message size limitation so every HTT ext stats indication
1497  * will have tag-length-value stats information elements.
1498  * The tag-length header for each HTT stats IND message also includes a
1499  * status field, to indicate whether the request for the stat type in
1500  * question was fully met, partially met, unable to be met, or invalid
1501  * (if the stat type in question is disabled in the target).
1502  * A Done bit 1's indicate the end of the of stats info elements.
1503  *
1504  *
1505  * |31                         16|15    12|11|10 8|7   5|4       0|
1506  * |--------------------------------------------------------------|
1507  * |                   reserved                   |    msg type   |
1508  * |--------------------------------------------------------------|
1509  * |                         cookie LSBs                          |
1510  * |--------------------------------------------------------------|
1511  * |                         cookie MSBs                          |
1512  * |--------------------------------------------------------------|
1513  * |      stats entry length     | rsvd   | D|  S |   stat type   |
1514  * |--------------------------------------------------------------|
1515  * |                   type-specific stats info                   |
1516  * |                      (see htt_stats.h)                       |
1517  * |--------------------------------------------------------------|
1518  * Header fields:
1519  *  - MSG_TYPE
1520  *    Bits 7:0
1521  *    Purpose: Identifies this is a extended statistics upload confirmation
1522  *             message.
1523  *    Value: 0x1c
1524  *  - COOKIE_LSBS
1525  *    Bits 31:0
1526  *    Purpose: Provide a mechanism to match a target->host stats confirmation
1527  *        message with its preceding host->target stats request message.
1528  *    Value: LSBs of the opaque cookie specified by the host-side requestor
1529  *  - COOKIE_MSBS
1530  *    Bits 31:0
1531  *    Purpose: Provide a mechanism to match a target->host stats confirmation
1532  *        message with its preceding host->target stats request message.
1533  *    Value: MSBs of the opaque cookie specified by the host-side requestor
1534  *
1535  * Stats Information Element tag-length header fields:
1536  *  - STAT_TYPE
1537  *    Bits 7:0
1538  *    Purpose: identifies the type of statistics info held in the
1539  *        following information element
1540  *    Value: htt_dbg_ext_stats_type
1541  *  - STATUS
1542  *    Bits 10:8
1543  *    Purpose: indicate whether the requested stats are present
1544  *    Value: htt_dbg_ext_stats_status
1545  *  - DONE
1546  *    Bits 11
1547  *    Purpose:
1548  *        Indicates the completion of the stats entry, this will be the last
1549  *        stats conf HTT segment for the requested stats type.
1550  *    Value:
1551  *        0 -> the stats retrieval is ongoing
1552  *        1 -> the stats retrieval is complete
1553  *  - LENGTH
1554  *    Bits 31:16
1555  *    Purpose: indicate the stats information size
1556  *    Value: This field specifies the number of bytes of stats information
1557  *       that follows the element tag-length header.
1558  *       It is expected but not required that this length is a multiple of
1559  *       4 bytes.
1560  */
1561
1562 #define HTT_T2H_EXT_STATS_INFO1_DONE    BIT(11)
1563 #define HTT_T2H_EXT_STATS_INFO1_LENGTH   GENMASK(31, 16)
1564
1565 struct ath11k_htt_extd_stats_msg {
1566         u32 info0;
1567         u64 cookie;
1568         u32 info1;
1569         u8 data[0];
1570 } __packed;
1571
1572 struct htt_mac_addr {
1573         u32 mac_addr_l32;
1574         u32 mac_addr_h16;
1575 };
1576
1577 static inline void ath11k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr)
1578 {
1579         if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
1580                 addr_l32 = swab32(addr_l32);
1581                 addr_h16 = swab16(addr_h16);
1582         }
1583
1584         memcpy(addr, &addr_l32, 4);
1585         memcpy(addr + 4, &addr_h16, ETH_ALEN - 4);
1586 }
1587
1588 int ath11k_dp_service_srng(struct ath11k_base *ab,
1589                            struct ath11k_ext_irq_grp *irq_grp,
1590                            int budget);
1591 int ath11k_dp_htt_connect(struct ath11k_dp *dp);
1592 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif);
1593 void ath11k_dp_free(struct ath11k_base *ab);
1594 int ath11k_dp_alloc(struct ath11k_base *ab);
1595 int ath11k_dp_pdev_alloc(struct ath11k_base *ab);
1596 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab);
1597 void ath11k_dp_pdev_free(struct ath11k_base *ab);
1598 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
1599                                 int mac_id, enum hal_ring_type ring_type);
1600 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr);
1601 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr);
1602 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring);
1603 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring,
1604                          enum hal_ring_type type, int ring_num,
1605                          int mac_id, int num_entries);
1606 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab,
1607                                  struct dp_link_desc_bank *desc_bank,
1608                                  u32 ring_type, struct dp_srng *ring);
1609 int ath11k_dp_link_desc_setup(struct ath11k_base *ab,
1610                               struct dp_link_desc_bank *link_desc_banks,
1611                               u32 ring_type, struct hal_srng *srng,
1612                               u32 n_link_desc);
1613
1614 #endif