drivers/net/ethernet/intel/i40e/i40e_common.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
   3
   4 #include "i40e.h"
   5 #include "i40e_type.h"
   6 #include "i40e_adminq.h"
   7 #include "i40e_prototype.h"
   8 #include <linux/avf/virtchnl.h>
   9
  10 /**
  11  * i40e_set_mac_type - Sets MAC type
  12  * @hw: pointer to the HW structure
  13  *
  14  * This function sets the mac type of the adapter based on the
  15  * vendor ID and device ID stored in the hw structure.
  16  **/
  17 i40e_status i40e_set_mac_type(struct i40e_hw *hw)
  18 {
  19         i40e_status status = 0;
  20
  21         if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
  22                 switch (hw->device_id) {
  23                 case I40E_DEV_ID_SFP_XL710:
  24                 case I40E_DEV_ID_QEMU:
  25                 case I40E_DEV_ID_KX_B:
  26                 case I40E_DEV_ID_KX_C:
  27                 case I40E_DEV_ID_QSFP_A:
  28                 case I40E_DEV_ID_QSFP_B:
  29                 case I40E_DEV_ID_QSFP_C:
  30                 case I40E_DEV_ID_5G_BASE_T_BC:
  31                 case I40E_DEV_ID_10G_BASE_T:
  32                 case I40E_DEV_ID_10G_BASE_T4:
  33                 case I40E_DEV_ID_10G_BASE_T_BC:
  34                 case I40E_DEV_ID_10G_B:
  35                 case I40E_DEV_ID_10G_SFP:
  36                 case I40E_DEV_ID_20G_KR2:
  37                 case I40E_DEV_ID_20G_KR2_A:
  38                 case I40E_DEV_ID_25G_B:
  39                 case I40E_DEV_ID_25G_SFP28:
  40                 case I40E_DEV_ID_X710_N3000:
  41                 case I40E_DEV_ID_XXV710_N3000:
  42                         hw->mac.type = I40E_MAC_XL710;
  43                         break;
  44                 case I40E_DEV_ID_KX_X722:
  45                 case I40E_DEV_ID_QSFP_X722:
  46                 case I40E_DEV_ID_SFP_X722:
  47                 case I40E_DEV_ID_1G_BASE_T_X722:
  48                 case I40E_DEV_ID_10G_BASE_T_X722:
  49                 case I40E_DEV_ID_SFP_I_X722:
  50                         hw->mac.type = I40E_MAC_X722;
  51                         break;
  52                 default:
  53                         hw->mac.type = I40E_MAC_GENERIC;
  54                         break;
  55                 }
  56         } else {
  57                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  58         }
  59
  60         hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
  61                   hw->mac.type, status);
  62         return status;
  63 }
  64
  65 /**
  66  * i40e_aq_str - convert AQ err code to a string
  67  * @hw: pointer to the HW structure
  68  * @aq_err: the AQ error code to convert
  69  **/
  70 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  71 {
  72         switch (aq_err) {
  73         case I40E_AQ_RC_OK:
  74                 return "OK";
  75         case I40E_AQ_RC_EPERM:
  76                 return "I40E_AQ_RC_EPERM";
  77         case I40E_AQ_RC_ENOENT:
  78                 return "I40E_AQ_RC_ENOENT";
  79         case I40E_AQ_RC_ESRCH:
  80                 return "I40E_AQ_RC_ESRCH";
  81         case I40E_AQ_RC_EINTR:
  82                 return "I40E_AQ_RC_EINTR";
  83         case I40E_AQ_RC_EIO:
  84                 return "I40E_AQ_RC_EIO";
  85         case I40E_AQ_RC_ENXIO:
  86                 return "I40E_AQ_RC_ENXIO";
  87         case I40E_AQ_RC_E2BIG:
  88                 return "I40E_AQ_RC_E2BIG";
  89         case I40E_AQ_RC_EAGAIN:
  90                 return "I40E_AQ_RC_EAGAIN";
  91         case I40E_AQ_RC_ENOMEM:
  92                 return "I40E_AQ_RC_ENOMEM";
  93         case I40E_AQ_RC_EACCES:
  94                 return "I40E_AQ_RC_EACCES";
  95         case I40E_AQ_RC_EFAULT:
  96                 return "I40E_AQ_RC_EFAULT";
  97         case I40E_AQ_RC_EBUSY:
  98                 return "I40E_AQ_RC_EBUSY";
  99         case I40E_AQ_RC_EEXIST:
 100                 return "I40E_AQ_RC_EEXIST";
 101         case I40E_AQ_RC_EINVAL:
 102                 return "I40E_AQ_RC_EINVAL";
 103         case I40E_AQ_RC_ENOTTY:
 104                 return "I40E_AQ_RC_ENOTTY";
 105         case I40E_AQ_RC_ENOSPC:
 106                 return "I40E_AQ_RC_ENOSPC";
 107         case I40E_AQ_RC_ENOSYS:
 108                 return "I40E_AQ_RC_ENOSYS";
 109         case I40E_AQ_RC_ERANGE:
 110                 return "I40E_AQ_RC_ERANGE";
 111         case I40E_AQ_RC_EFLUSHED:
 112                 return "I40E_AQ_RC_EFLUSHED";
 113         case I40E_AQ_RC_BAD_ADDR:
 114                 return "I40E_AQ_RC_BAD_ADDR";
 115         case I40E_AQ_RC_EMODE:
 116                 return "I40E_AQ_RC_EMODE";
 117         case I40E_AQ_RC_EFBIG:
 118                 return "I40E_AQ_RC_EFBIG";
 119         }
 120
 121         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 122         return hw->err_str;
 123 }
 124
 125 /**
 126  * i40e_stat_str - convert status err code to a string
 127  * @hw: pointer to the HW structure
 128  * @stat_err: the status error code to convert
 129  **/
 130 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
 131 {
 132         switch (stat_err) {
 133         case 0:
 134                 return "OK";
 135         case I40E_ERR_NVM:
 136                 return "I40E_ERR_NVM";
 137         case I40E_ERR_NVM_CHECKSUM:
 138                 return "I40E_ERR_NVM_CHECKSUM";
 139         case I40E_ERR_PHY:
 140                 return "I40E_ERR_PHY";
 141         case I40E_ERR_CONFIG:
 142                 return "I40E_ERR_CONFIG";
 143         case I40E_ERR_PARAM:
 144                 return "I40E_ERR_PARAM";
 145         case I40E_ERR_MAC_TYPE:
 146                 return "I40E_ERR_MAC_TYPE";
 147         case I40E_ERR_UNKNOWN_PHY:
 148                 return "I40E_ERR_UNKNOWN_PHY";
 149         case I40E_ERR_LINK_SETUP:
 150                 return "I40E_ERR_LINK_SETUP";
 151         case I40E_ERR_ADAPTER_STOPPED:
 152                 return "I40E_ERR_ADAPTER_STOPPED";
 153         case I40E_ERR_INVALID_MAC_ADDR:
 154                 return "I40E_ERR_INVALID_MAC_ADDR";
 155         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 156                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 157         case I40E_ERR_MASTER_REQUESTS_PENDING:
 158                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 159         case I40E_ERR_INVALID_LINK_SETTINGS:
 160                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 161         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 162                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 163         case I40E_ERR_RESET_FAILED:
 164                 return "I40E_ERR_RESET_FAILED";
 165         case I40E_ERR_SWFW_SYNC:
 166                 return "I40E_ERR_SWFW_SYNC";
 167         case I40E_ERR_NO_AVAILABLE_VSI:
 168                 return "I40E_ERR_NO_AVAILABLE_VSI";
 169         case I40E_ERR_NO_MEMORY:
 170                 return "I40E_ERR_NO_MEMORY";
 171         case I40E_ERR_BAD_PTR:
 172                 return "I40E_ERR_BAD_PTR";
 173         case I40E_ERR_RING_FULL:
 174                 return "I40E_ERR_RING_FULL";
 175         case I40E_ERR_INVALID_PD_ID:
 176                 return "I40E_ERR_INVALID_PD_ID";
 177         case I40E_ERR_INVALID_QP_ID:
 178                 return "I40E_ERR_INVALID_QP_ID";
 179         case I40E_ERR_INVALID_CQ_ID:
 180                 return "I40E_ERR_INVALID_CQ_ID";
 181         case I40E_ERR_INVALID_CEQ_ID:
 182                 return "I40E_ERR_INVALID_CEQ_ID";
 183         case I40E_ERR_INVALID_AEQ_ID:
 184                 return "I40E_ERR_INVALID_AEQ_ID";
 185         case I40E_ERR_INVALID_SIZE:
 186                 return "I40E_ERR_INVALID_SIZE";
 187         case I40E_ERR_INVALID_ARP_INDEX:
 188                 return "I40E_ERR_INVALID_ARP_INDEX";
 189         case I40E_ERR_INVALID_FPM_FUNC_ID:
 190                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 191         case I40E_ERR_QP_INVALID_MSG_SIZE:
 192                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 193         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 194                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 195         case I40E_ERR_INVALID_FRAG_COUNT:
 196                 return "I40E_ERR_INVALID_FRAG_COUNT";
 197         case I40E_ERR_QUEUE_EMPTY:
 198                 return "I40E_ERR_QUEUE_EMPTY";
 199         case I40E_ERR_INVALID_ALIGNMENT:
 200                 return "I40E_ERR_INVALID_ALIGNMENT";
 201         case I40E_ERR_FLUSHED_QUEUE:
 202                 return "I40E_ERR_FLUSHED_QUEUE";
 203         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 204                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 205         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 206                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 207         case I40E_ERR_TIMEOUT:
 208                 return "I40E_ERR_TIMEOUT";
 209         case I40E_ERR_OPCODE_MISMATCH:
 210                 return "I40E_ERR_OPCODE_MISMATCH";
 211         case I40E_ERR_CQP_COMPL_ERROR:
 212                 return "I40E_ERR_CQP_COMPL_ERROR";
 213         case I40E_ERR_INVALID_VF_ID:
 214                 return "I40E_ERR_INVALID_VF_ID";
 215         case I40E_ERR_INVALID_HMCFN_ID:
 216                 return "I40E_ERR_INVALID_HMCFN_ID";
 217         case I40E_ERR_BACKING_PAGE_ERROR:
 218                 return "I40E_ERR_BACKING_PAGE_ERROR";
 219         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 220                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 221         case I40E_ERR_INVALID_PBLE_INDEX:
 222                 return "I40E_ERR_INVALID_PBLE_INDEX";
 223         case I40E_ERR_INVALID_SD_INDEX:
 224                 return "I40E_ERR_INVALID_SD_INDEX";
 225         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 226                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 227         case I40E_ERR_INVALID_SD_TYPE:
 228                 return "I40E_ERR_INVALID_SD_TYPE";
 229         case I40E_ERR_MEMCPY_FAILED:
 230                 return "I40E_ERR_MEMCPY_FAILED";
 231         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 232                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 233         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 234                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 235         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 236                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 237         case I40E_ERR_SRQ_ENABLED:
 238                 return "I40E_ERR_SRQ_ENABLED";
 239         case I40E_ERR_ADMIN_QUEUE_ERROR:
 240                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 241         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 242                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 243         case I40E_ERR_BUF_TOO_SHORT:
 244                 return "I40E_ERR_BUF_TOO_SHORT";
 245         case I40E_ERR_ADMIN_QUEUE_FULL:
 246                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 247         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 248                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 249         case I40E_ERR_BAD_IWARP_CQE:
 250                 return "I40E_ERR_BAD_IWARP_CQE";
 251         case I40E_ERR_NVM_BLANK_MODE:
 252                 return "I40E_ERR_NVM_BLANK_MODE";
 253         case I40E_ERR_NOT_IMPLEMENTED:
 254                 return "I40E_ERR_NOT_IMPLEMENTED";
 255         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 256                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 257         case I40E_ERR_DIAG_TEST_FAILED:
 258                 return "I40E_ERR_DIAG_TEST_FAILED";
 259         case I40E_ERR_NOT_READY:
 260                 return "I40E_ERR_NOT_READY";
 261         case I40E_NOT_SUPPORTED:
 262                 return "I40E_NOT_SUPPORTED";
 263         case I40E_ERR_FIRMWARE_API_VERSION:
 264                 return "I40E_ERR_FIRMWARE_API_VERSION";
 265         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 266                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 267         }
 268
 269         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 270         return hw->err_str;
 271 }
 272
 273 /**
 274  * i40e_debug_aq
 275  * @hw: debug mask related to admin queue
 276  * @mask: debug mask
 277  * @desc: pointer to admin queue descriptor
 278  * @buffer: pointer to command buffer
 279  * @buf_len: max length of buffer
 280  *
 281  * Dumps debug log about adminq command with descriptor contents.
 282  **/
 283 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 284                    void *buffer, u16 buf_len)
 285 {
 286         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 287         u32 effective_mask = hw->debug_mask & mask;
 288         char prefix[27];
 289         u16 len;
 290         u8 *buf = (u8 *)buffer;
 291
 292         if (!effective_mask || !desc)
 293                 return;
 294
 295         len = le16_to_cpu(aq_desc->datalen);
 296
 297         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 298                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 299                    le16_to_cpu(aq_desc->opcode),
 300                    le16_to_cpu(aq_desc->flags),
 301                    le16_to_cpu(aq_desc->datalen),
 302                    le16_to_cpu(aq_desc->retval));
 303         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 304                    "\tcookie (h,l) 0x%08X 0x%08X\n",
 305                    le32_to_cpu(aq_desc->cookie_high),
 306                    le32_to_cpu(aq_desc->cookie_low));
 307         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 308                    "\tparam (0,1)  0x%08X 0x%08X\n",
 309                    le32_to_cpu(aq_desc->params.internal.param0),
 310                    le32_to_cpu(aq_desc->params.internal.param1));
 311         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 312                    "\taddr (h,l)   0x%08X 0x%08X\n",
 313                    le32_to_cpu(aq_desc->params.external.addr_high),
 314                    le32_to_cpu(aq_desc->params.external.addr_low));
 315
 316         if (buffer && buf_len != 0 && len != 0 &&
 317             (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
 318                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 319                 if (buf_len < len)
 320                         len = buf_len;
 321
 322                 snprintf(prefix, sizeof(prefix),
 323                          "i40e %02x:%02x.%x: \t0x",
 324                          hw->bus.bus_id,
 325                          hw->bus.device,
 326                          hw->bus.func);
 327
 328                 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
 329                                16, 1, buf, len, false);
 330         }
 331 }
 332
 333 /**
 334  * i40e_check_asq_alive
 335  * @hw: pointer to the hw struct
 336  *
 337  * Returns true if Queue is enabled else false.
 338  **/
 339 bool i40e_check_asq_alive(struct i40e_hw *hw)
 340 {
 341         if (hw->aq.asq.len)
 342                 return !!(rd32(hw, hw->aq.asq.len) &
 343                           I40E_PF_ATQLEN_ATQENABLE_MASK);
 344         else
 345                 return false;
 346 }
 347
 348 /**
 349  * i40e_aq_queue_shutdown
 350  * @hw: pointer to the hw struct
 351  * @unloading: is the driver unloading itself
 352  *
 353  * Tell the Firmware that we're shutting down the AdminQ and whether
 354  * or not the driver is unloading as well.
 355  **/
 356 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
 357                                              bool unloading)
 358 {
 359         struct i40e_aq_desc desc;
 360         struct i40e_aqc_queue_shutdown *cmd =
 361                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 362         i40e_status status;
 363
 364         i40e_fill_default_direct_cmd_desc(&desc,
 365                                           i40e_aqc_opc_queue_shutdown);
 366
 367         if (unloading)
 368                 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
 369         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 370
 371         return status;
 372 }
 373
 374 /**
 375  * i40e_aq_get_set_rss_lut
 376  * @hw: pointer to the hardware structure
 377  * @vsi_id: vsi fw index
 378  * @pf_lut: for PF table set true, for VSI table set false
 379  * @lut: pointer to the lut buffer provided by the caller
 380  * @lut_size: size of the lut buffer
 381  * @set: set true to set the table, false to get the table
 382  *
 383  * Internal function to get or set RSS look up table
 384  **/
 385 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 386                                            u16 vsi_id, bool pf_lut,
 387                                            u8 *lut, u16 lut_size,
 388                                            bool set)
 389 {
 390         i40e_status status;
 391         struct i40e_aq_desc desc;
 392         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 393                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 394
 395         if (set)
 396                 i40e_fill_default_direct_cmd_desc(&desc,
 397                                                   i40e_aqc_opc_set_rss_lut);
 398         else
 399                 i40e_fill_default_direct_cmd_desc(&desc,
 400                                                   i40e_aqc_opc_get_rss_lut);
 401
 402         /* Indirect command */
 403         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
 404         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
 405
 406         cmd_resp->vsi_id =
 407                         cpu_to_le16((u16)((vsi_id <<
 408                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 409                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 410         cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 411
 412         if (pf_lut)
 413                 cmd_resp->flags |= cpu_to_le16((u16)
 414                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 415                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 416                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 417         else
 418                 cmd_resp->flags |= cpu_to_le16((u16)
 419                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 420                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 421                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 422
 423         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 424
 425         return status;
 426 }
 427
 428 /**
 429  * i40e_aq_get_rss_lut
 430  * @hw: pointer to the hardware structure
 431  * @vsi_id: vsi fw index
 432  * @pf_lut: for PF table set true, for VSI table set false
 433  * @lut: pointer to the lut buffer provided by the caller
 434  * @lut_size: size of the lut buffer
 435  *
 436  * get the RSS lookup table, PF or VSI type
 437  **/
 438 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 439                                 bool pf_lut, u8 *lut, u16 lut_size)
 440 {
 441         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 442                                        false);
 443 }
 444
 445 /**
 446  * i40e_aq_set_rss_lut
 447  * @hw: pointer to the hardware structure
 448  * @vsi_id: vsi fw index
 449  * @pf_lut: for PF table set true, for VSI table set false
 450  * @lut: pointer to the lut buffer provided by the caller
 451  * @lut_size: size of the lut buffer
 452  *
 453  * set the RSS lookup table, PF or VSI type
 454  **/
 455 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 456                                 bool pf_lut, u8 *lut, u16 lut_size)
 457 {
 458         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 459 }
 460
 461 /**
 462  * i40e_aq_get_set_rss_key
 463  * @hw: pointer to the hw struct
 464  * @vsi_id: vsi fw index
 465  * @key: pointer to key info struct
 466  * @set: set true to set the key, false to get the key
 467  *
 468  * get the RSS key per VSI
 469  **/
 470 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 471                                       u16 vsi_id,
 472                                       struct i40e_aqc_get_set_rss_key_data *key,
 473                                       bool set)
 474 {
 475         i40e_status status;
 476         struct i40e_aq_desc desc;
 477         struct i40e_aqc_get_set_rss_key *cmd_resp =
 478                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 479         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 480
 481         if (set)
 482                 i40e_fill_default_direct_cmd_desc(&desc,
 483                                                   i40e_aqc_opc_set_rss_key);
 484         else
 485                 i40e_fill_default_direct_cmd_desc(&desc,
 486                                                   i40e_aqc_opc_get_rss_key);
 487
 488         /* Indirect command */
 489         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
 490         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
 491
 492         cmd_resp->vsi_id =
 493                         cpu_to_le16((u16)((vsi_id <<
 494                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 495                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 496         cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 497
 498         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 499
 500         return status;
 501 }
 502
 503 /**
 504  * i40e_aq_get_rss_key
 505  * @hw: pointer to the hw struct
 506  * @vsi_id: vsi fw index
 507  * @key: pointer to key info struct
 508  *
 509  **/
 510 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
 511                                 u16 vsi_id,
 512                                 struct i40e_aqc_get_set_rss_key_data *key)
 513 {
 514         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 515 }
 516
 517 /**
 518  * i40e_aq_set_rss_key
 519  * @hw: pointer to the hw struct
 520  * @vsi_id: vsi fw index
 521  * @key: pointer to key info struct
 522  *
 523  * set the RSS key per VSI
 524  **/
 525 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
 526                                 u16 vsi_id,
 527                                 struct i40e_aqc_get_set_rss_key_data *key)
 528 {
 529         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 530 }
 531
 532 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 533  * hardware to a bit-field that can be used by SW to more easily determine the
 534  * packet type.
 535  *
 536  * Macros are used to shorten the table lines and make this table human
 537  * readable.
 538  *
 539  * We store the PTYPE in the top byte of the bit field - this is just so that
 540  * we can check that the table doesn't have a row missing, as the index into
 541  * the table should be the PTYPE.
 542  *
 543  * Typical work flow:
 544  *
 545  * IF NOT i40e_ptype_lookup[ptype].known
 546  * THEN
 547  *      Packet is unknown
 548  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 549  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 550  * ELSE
 551  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 552  * ENDIF
 553  */
 554
 555 /* macro to make the table lines short */
 556 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 557         {       PTYPE, \
 558                 1, \
 559                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 560                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 561                 I40E_RX_PTYPE_##OUTER_FRAG, \
 562                 I40E_RX_PTYPE_TUNNEL_##T, \
 563                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 564                 I40E_RX_PTYPE_##TEF, \
 565                 I40E_RX_PTYPE_INNER_PROT_##I, \
 566                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 567
 568 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 569                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 570
 571 /* shorter macros makes the table fit but are terse */
 572 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 573 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 574 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 575
 576 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 577 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 578         /* L2 Packet types */
 579         I40E_PTT_UNUSED_ENTRY(0),
 580         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 581         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 582         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 583         I40E_PTT_UNUSED_ENTRY(4),
 584         I40E_PTT_UNUSED_ENTRY(5),
 585         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 586         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 587         I40E_PTT_UNUSED_ENTRY(8),
 588         I40E_PTT_UNUSED_ENTRY(9),
 589         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 590         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 591         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 592         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 593         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 594         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 595         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 596         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 597         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 598         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 599         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 600         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 601
 602         /* Non Tunneled IPv4 */
 603         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 604         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 605         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 606         I40E_PTT_UNUSED_ENTRY(25),
 607         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 608         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 609         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 610
 611         /* IPv4 --> IPv4 */
 612         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 613         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 614         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 615         I40E_PTT_UNUSED_ENTRY(32),
 616         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 617         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 618         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 619
 620         /* IPv4 --> IPv6 */
 621         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 622         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 623         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 624         I40E_PTT_UNUSED_ENTRY(39),
 625         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 626         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 627         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 628
 629         /* IPv4 --> GRE/NAT */
 630         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 631
 632         /* IPv4 --> GRE/NAT --> IPv4 */
 633         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 634         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 635         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 636         I40E_PTT_UNUSED_ENTRY(47),
 637         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 638         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 639         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 640
 641         /* IPv4 --> GRE/NAT --> IPv6 */
 642         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 643         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 644         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 645         I40E_PTT_UNUSED_ENTRY(54),
 646         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 647         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 648         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 649
 650         /* IPv4 --> GRE/NAT --> MAC */
 651         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 652
 653         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 654         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 655         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 656         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 657         I40E_PTT_UNUSED_ENTRY(62),
 658         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 659         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 660         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 661
 662         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 663         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 664         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 665         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 666         I40E_PTT_UNUSED_ENTRY(69),
 667         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 668         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 669         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 670
 671         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 672         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 673
 674         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 675         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 676         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 677         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 678         I40E_PTT_UNUSED_ENTRY(77),
 679         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 680         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 681         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 682
 683         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 684         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 685         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 686         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 687         I40E_PTT_UNUSED_ENTRY(84),
 688         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 689         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 690         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 691
 692         /* Non Tunneled IPv6 */
 693         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 694         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 695         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 696         I40E_PTT_UNUSED_ENTRY(91),
 697         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 698         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 699         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 700
 701         /* IPv6 --> IPv4 */
 702         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 703         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 704         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 705         I40E_PTT_UNUSED_ENTRY(98),
 706         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 707         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 708         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 709
 710         /* IPv6 --> IPv6 */
 711         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 712         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 713         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 714         I40E_PTT_UNUSED_ENTRY(105),
 715         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 716         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 717         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 718
 719         /* IPv6 --> GRE/NAT */
 720         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 721
 722         /* IPv6 --> GRE/NAT -> IPv4 */
 723         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 724         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 725         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 726         I40E_PTT_UNUSED_ENTRY(113),
 727         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 728         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 729         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 730
 731         /* IPv6 --> GRE/NAT -> IPv6 */
 732         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 733         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 734         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 735         I40E_PTT_UNUSED_ENTRY(120),
 736         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 737         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 738         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 739
 740         /* IPv6 --> GRE/NAT -> MAC */
 741         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 742
 743         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 744         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 745         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 746         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 747         I40E_PTT_UNUSED_ENTRY(128),
 748         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 749         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 750         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 751
 752         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 753         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 754         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 755         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 756         I40E_PTT_UNUSED_ENTRY(135),
 757         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 758         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 759         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 760
 761         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 762         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 763
 764         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 765         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 766         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 767         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 768         I40E_PTT_UNUSED_ENTRY(143),
 769         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 770         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 771         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 772
 773         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 774         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 775         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 776         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 777         I40E_PTT_UNUSED_ENTRY(150),
 778         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 779         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 780         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 781
 782         /* unused entries */
 783         I40E_PTT_UNUSED_ENTRY(154),
 784         I40E_PTT_UNUSED_ENTRY(155),
 785         I40E_PTT_UNUSED_ENTRY(156),
 786         I40E_PTT_UNUSED_ENTRY(157),
 787         I40E_PTT_UNUSED_ENTRY(158),
 788         I40E_PTT_UNUSED_ENTRY(159),
 789
 790         I40E_PTT_UNUSED_ENTRY(160),
 791         I40E_PTT_UNUSED_ENTRY(161),
 792         I40E_PTT_UNUSED_ENTRY(162),
 793         I40E_PTT_UNUSED_ENTRY(163),
 794         I40E_PTT_UNUSED_ENTRY(164),
 795         I40E_PTT_UNUSED_ENTRY(165),
 796         I40E_PTT_UNUSED_ENTRY(166),
 797         I40E_PTT_UNUSED_ENTRY(167),
 798         I40E_PTT_UNUSED_ENTRY(168),
 799         I40E_PTT_UNUSED_ENTRY(169),
 800
 801         I40E_PTT_UNUSED_ENTRY(170),
 802         I40E_PTT_UNUSED_ENTRY(171),
 803         I40E_PTT_UNUSED_ENTRY(172),
 804         I40E_PTT_UNUSED_ENTRY(173),
 805         I40E_PTT_UNUSED_ENTRY(174),
 806         I40E_PTT_UNUSED_ENTRY(175),
 807         I40E_PTT_UNUSED_ENTRY(176),
 808         I40E_PTT_UNUSED_ENTRY(177),
 809         I40E_PTT_UNUSED_ENTRY(178),
 810         I40E_PTT_UNUSED_ENTRY(179),
 811
 812         I40E_PTT_UNUSED_ENTRY(180),
 813         I40E_PTT_UNUSED_ENTRY(181),
 814         I40E_PTT_UNUSED_ENTRY(182),
 815         I40E_PTT_UNUSED_ENTRY(183),
 816         I40E_PTT_UNUSED_ENTRY(184),
 817         I40E_PTT_UNUSED_ENTRY(185),
 818         I40E_PTT_UNUSED_ENTRY(186),
 819         I40E_PTT_UNUSED_ENTRY(187),
 820         I40E_PTT_UNUSED_ENTRY(188),
 821         I40E_PTT_UNUSED_ENTRY(189),
 822
 823         I40E_PTT_UNUSED_ENTRY(190),
 824         I40E_PTT_UNUSED_ENTRY(191),
 825         I40E_PTT_UNUSED_ENTRY(192),
 826         I40E_PTT_UNUSED_ENTRY(193),
 827         I40E_PTT_UNUSED_ENTRY(194),
 828         I40E_PTT_UNUSED_ENTRY(195),
 829         I40E_PTT_UNUSED_ENTRY(196),
 830         I40E_PTT_UNUSED_ENTRY(197),
 831         I40E_PTT_UNUSED_ENTRY(198),
 832         I40E_PTT_UNUSED_ENTRY(199),
 833
 834         I40E_PTT_UNUSED_ENTRY(200),
 835         I40E_PTT_UNUSED_ENTRY(201),
 836         I40E_PTT_UNUSED_ENTRY(202),
 837         I40E_PTT_UNUSED_ENTRY(203),
 838         I40E_PTT_UNUSED_ENTRY(204),
 839         I40E_PTT_UNUSED_ENTRY(205),
 840         I40E_PTT_UNUSED_ENTRY(206),
 841         I40E_PTT_UNUSED_ENTRY(207),
 842         I40E_PTT_UNUSED_ENTRY(208),
 843         I40E_PTT_UNUSED_ENTRY(209),
 844
 845         I40E_PTT_UNUSED_ENTRY(210),
 846         I40E_PTT_UNUSED_ENTRY(211),
 847         I40E_PTT_UNUSED_ENTRY(212),
 848         I40E_PTT_UNUSED_ENTRY(213),
 849         I40E_PTT_UNUSED_ENTRY(214),
 850         I40E_PTT_UNUSED_ENTRY(215),
 851         I40E_PTT_UNUSED_ENTRY(216),
 852         I40E_PTT_UNUSED_ENTRY(217),
 853         I40E_PTT_UNUSED_ENTRY(218),
 854         I40E_PTT_UNUSED_ENTRY(219),
 855
 856         I40E_PTT_UNUSED_ENTRY(220),
 857         I40E_PTT_UNUSED_ENTRY(221),
 858         I40E_PTT_UNUSED_ENTRY(222),
 859         I40E_PTT_UNUSED_ENTRY(223),
 860         I40E_PTT_UNUSED_ENTRY(224),
 861         I40E_PTT_UNUSED_ENTRY(225),
 862         I40E_PTT_UNUSED_ENTRY(226),
 863         I40E_PTT_UNUSED_ENTRY(227),
 864         I40E_PTT_UNUSED_ENTRY(228),
 865         I40E_PTT_UNUSED_ENTRY(229),
 866
 867         I40E_PTT_UNUSED_ENTRY(230),
 868         I40E_PTT_UNUSED_ENTRY(231),
 869         I40E_PTT_UNUSED_ENTRY(232),
 870         I40E_PTT_UNUSED_ENTRY(233),
 871         I40E_PTT_UNUSED_ENTRY(234),
 872         I40E_PTT_UNUSED_ENTRY(235),
 873         I40E_PTT_UNUSED_ENTRY(236),
 874         I40E_PTT_UNUSED_ENTRY(237),
 875         I40E_PTT_UNUSED_ENTRY(238),
 876         I40E_PTT_UNUSED_ENTRY(239),
 877
 878         I40E_PTT_UNUSED_ENTRY(240),
 879         I40E_PTT_UNUSED_ENTRY(241),
 880         I40E_PTT_UNUSED_ENTRY(242),
 881         I40E_PTT_UNUSED_ENTRY(243),
 882         I40E_PTT_UNUSED_ENTRY(244),
 883         I40E_PTT_UNUSED_ENTRY(245),
 884         I40E_PTT_UNUSED_ENTRY(246),
 885         I40E_PTT_UNUSED_ENTRY(247),
 886         I40E_PTT_UNUSED_ENTRY(248),
 887         I40E_PTT_UNUSED_ENTRY(249),
 888
 889         I40E_PTT_UNUSED_ENTRY(250),
 890         I40E_PTT_UNUSED_ENTRY(251),
 891         I40E_PTT_UNUSED_ENTRY(252),
 892         I40E_PTT_UNUSED_ENTRY(253),
 893         I40E_PTT_UNUSED_ENTRY(254),
 894         I40E_PTT_UNUSED_ENTRY(255)
 895 };
 896
 897 /**
 898  * i40e_init_shared_code - Initialize the shared code
 899  * @hw: pointer to hardware structure
 900  *
 901  * This assigns the MAC type and PHY code and inits the NVM.
 902  * Does not touch the hardware. This function must be called prior to any
 903  * other function in the shared code. The i40e_hw structure should be
 904  * memset to 0 prior to calling this function.  The following fields in
 905  * hw structure should be filled in prior to calling this function:
 906  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 907  * subsystem_vendor_id, and revision_id
 908  **/
 909 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
 910 {
 911         i40e_status status = 0;
 912         u32 port, ari, func_rid;
 913
 914         i40e_set_mac_type(hw);
 915
 916         switch (hw->mac.type) {
 917         case I40E_MAC_XL710:
 918         case I40E_MAC_X722:
 919                 break;
 920         default:
 921                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
 922         }
 923
 924         hw->phy.get_link_info = true;
 925
 926         /* Determine port number and PF number*/
 927         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
 928                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
 929         hw->port = (u8)port;
 930         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
 931                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
 932         func_rid = rd32(hw, I40E_PF_FUNC_RID);
 933         if (ari)
 934                 hw->pf_id = (u8)(func_rid & 0xff);
 935         else
 936                 hw->pf_id = (u8)(func_rid & 0x7);
 937
 938         status = i40e_init_nvm(hw);
 939         return status;
 940 }
 941
 942 /**
 943  * i40e_aq_mac_address_read - Retrieve the MAC addresses
 944  * @hw: pointer to the hw struct
 945  * @flags: a return indicator of what addresses were added to the addr store
 946  * @addrs: the requestor's mac addr store
 947  * @cmd_details: pointer to command details structure or NULL
 948  **/
 949 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
 950                                    u16 *flags,
 951                                    struct i40e_aqc_mac_address_read_data *addrs,
 952                                    struct i40e_asq_cmd_details *cmd_details)
 953 {
 954         struct i40e_aq_desc desc;
 955         struct i40e_aqc_mac_address_read *cmd_data =
 956                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
 957         i40e_status status;
 958
 959         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
 960         desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
 961
 962         status = i40e_asq_send_command(hw, &desc, addrs,
 963                                        sizeof(*addrs), cmd_details);
 964         *flags = le16_to_cpu(cmd_data->command_flags);
 965
 966         return status;
 967 }
 968
 969 /**
 970  * i40e_aq_mac_address_write - Change the MAC addresses
 971  * @hw: pointer to the hw struct
 972  * @flags: indicates which MAC to be written
 973  * @mac_addr: address to write
 974  * @cmd_details: pointer to command details structure or NULL
 975  **/
 976 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
 977                                     u16 flags, u8 *mac_addr,
 978                                     struct i40e_asq_cmd_details *cmd_details)
 979 {
 980         struct i40e_aq_desc desc;
 981         struct i40e_aqc_mac_address_write *cmd_data =
 982                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
 983         i40e_status status;
 984
 985         i40e_fill_default_direct_cmd_desc(&desc,
 986                                           i40e_aqc_opc_mac_address_write);
 987         cmd_data->command_flags = cpu_to_le16(flags);
 988         cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
 989         cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
 990                                         ((u32)mac_addr[3] << 16) |
 991                                         ((u32)mac_addr[4] << 8) |
 992                                         mac_addr[5]);
 993
 994         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
 995
 996         return status;
 997 }
 998
 999 /**
1000  * i40e_get_mac_addr - get MAC address
1001  * @hw: pointer to the HW structure
1002  * @mac_addr: pointer to MAC address
1003  *
1004  * Reads the adapter's MAC address from register
1005  **/
1006 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1007 {
1008         struct i40e_aqc_mac_address_read_data addrs;
1009         i40e_status status;
1010         u16 flags = 0;
1011
1012         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1013
1014         if (flags & I40E_AQC_LAN_ADDR_VALID)
1015                 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1016
1017         return status;
1018 }
1019
1020 /**
1021  * i40e_get_port_mac_addr - get Port MAC address
1022  * @hw: pointer to the HW structure
1023  * @mac_addr: pointer to Port MAC address
1024  *
1025  * Reads the adapter's Port MAC address
1026  **/
1027 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1028 {
1029         struct i40e_aqc_mac_address_read_data addrs;
1030         i40e_status status;
1031         u16 flags = 0;
1032
1033         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1034         if (status)
1035                 return status;
1036
1037         if (flags & I40E_AQC_PORT_ADDR_VALID)
1038                 ether_addr_copy(mac_addr, addrs.port_mac);
1039         else
1040                 status = I40E_ERR_INVALID_MAC_ADDR;
1041
1042         return status;
1043 }
1044
1045 /**
1046  * i40e_pre_tx_queue_cfg - pre tx queue configure
1047  * @hw: pointer to the HW structure
1048  * @queue: target PF queue index
1049  * @enable: state change request
1050  *
1051  * Handles hw requirement to indicate intention to enable
1052  * or disable target queue.
1053  **/
1054 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1055 {
1056         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1057         u32 reg_block = 0;
1058         u32 reg_val;
1059
1060         if (abs_queue_idx >= 128) {
1061                 reg_block = abs_queue_idx / 128;
1062                 abs_queue_idx %= 128;
1063         }
1064
1065         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1066         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1067         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1068
1069         if (enable)
1070                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1071         else
1072                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1073
1074         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1075 }
1076
1077 /**
1078  *  i40e_read_pba_string - Reads part number string from EEPROM
1079  *  @hw: pointer to hardware structure
1080  *  @pba_num: stores the part number string from the EEPROM
1081  *  @pba_num_size: part number string buffer length
1082  *
1083  *  Reads the part number string from the EEPROM.
1084  **/
1085 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1086                                  u32 pba_num_size)
1087 {
1088         i40e_status status = 0;
1089         u16 pba_word = 0;
1090         u16 pba_size = 0;
1091         u16 pba_ptr = 0;
1092         u16 i = 0;
1093
1094         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1095         if (status || (pba_word != 0xFAFA)) {
1096                 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1097                 return status;
1098         }
1099
1100         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1101         if (status) {
1102                 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1103                 return status;
1104         }
1105
1106         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1107         if (status) {
1108                 hw_dbg(hw, "Failed to read PBA Block size.\n");
1109                 return status;
1110         }
1111
1112         /* Subtract one to get PBA word count (PBA Size word is included in
1113          * total size)
1114          */
1115         pba_size--;
1116         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1117                 hw_dbg(hw, "Buffer too small for PBA data.\n");
1118                 return I40E_ERR_PARAM;
1119         }
1120
1121         for (i = 0; i < pba_size; i++) {
1122                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1123                 if (status) {
1124                         hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1125                         return status;
1126                 }
1127
1128                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1129                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1130         }
1131         pba_num[(pba_size * 2)] = '\0';
1132
1133         return status;
1134 }
1135
1136 /**
1137  * i40e_get_media_type - Gets media type
1138  * @hw: pointer to the hardware structure
1139  **/
1140 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1141 {
1142         enum i40e_media_type media;
1143
1144         switch (hw->phy.link_info.phy_type) {
1145         case I40E_PHY_TYPE_10GBASE_SR:
1146         case I40E_PHY_TYPE_10GBASE_LR:
1147         case I40E_PHY_TYPE_1000BASE_SX:
1148         case I40E_PHY_TYPE_1000BASE_LX:
1149         case I40E_PHY_TYPE_40GBASE_SR4:
1150         case I40E_PHY_TYPE_40GBASE_LR4:
1151         case I40E_PHY_TYPE_25GBASE_LR:
1152         case I40E_PHY_TYPE_25GBASE_SR:
1153                 media = I40E_MEDIA_TYPE_FIBER;
1154                 break;
1155         case I40E_PHY_TYPE_100BASE_TX:
1156         case I40E_PHY_TYPE_1000BASE_T:
1157         case I40E_PHY_TYPE_2_5GBASE_T:
1158         case I40E_PHY_TYPE_5GBASE_T:
1159         case I40E_PHY_TYPE_10GBASE_T:
1160                 media = I40E_MEDIA_TYPE_BASET;
1161                 break;
1162         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1163         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1164         case I40E_PHY_TYPE_10GBASE_CR1:
1165         case I40E_PHY_TYPE_40GBASE_CR4:
1166         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1167         case I40E_PHY_TYPE_40GBASE_AOC:
1168         case I40E_PHY_TYPE_10GBASE_AOC:
1169         case I40E_PHY_TYPE_25GBASE_CR:
1170         case I40E_PHY_TYPE_25GBASE_AOC:
1171         case I40E_PHY_TYPE_25GBASE_ACC:
1172                 media = I40E_MEDIA_TYPE_DA;
1173                 break;
1174         case I40E_PHY_TYPE_1000BASE_KX:
1175         case I40E_PHY_TYPE_10GBASE_KX4:
1176         case I40E_PHY_TYPE_10GBASE_KR:
1177         case I40E_PHY_TYPE_40GBASE_KR4:
1178         case I40E_PHY_TYPE_20GBASE_KR2:
1179         case I40E_PHY_TYPE_25GBASE_KR:
1180                 media = I40E_MEDIA_TYPE_BACKPLANE;
1181                 break;
1182         case I40E_PHY_TYPE_SGMII:
1183         case I40E_PHY_TYPE_XAUI:
1184         case I40E_PHY_TYPE_XFI:
1185         case I40E_PHY_TYPE_XLAUI:
1186         case I40E_PHY_TYPE_XLPPI:
1187         default:
1188                 media = I40E_MEDIA_TYPE_UNKNOWN;
1189                 break;
1190         }
1191
1192         return media;
1193 }
1194
1195 /**
1196  * i40e_poll_globr - Poll for Global Reset completion
1197  * @hw: pointer to the hardware structure
1198  * @retry_limit: how many times to retry before failure
1199  **/
1200 static i40e_status i40e_poll_globr(struct i40e_hw *hw,
1201                                    u32 retry_limit)
1202 {
1203         u32 cnt, reg = 0;
1204
1205         for (cnt = 0; cnt < retry_limit; cnt++) {
1206                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1207                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1208                         return 0;
1209                 msleep(100);
1210         }
1211
1212         hw_dbg(hw, "Global reset failed.\n");
1213         hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg);
1214
1215         return I40E_ERR_RESET_FAILED;
1216 }
1217
1218 #define I40E_PF_RESET_WAIT_COUNT_A0     200
1219 #define I40E_PF_RESET_WAIT_COUNT        200
1220 /**
1221  * i40e_pf_reset - Reset the PF
1222  * @hw: pointer to the hardware structure
1223  *
1224  * Assuming someone else has triggered a global reset,
1225  * assure the global reset is complete and then reset the PF
1226  **/
1227 i40e_status i40e_pf_reset(struct i40e_hw *hw)
1228 {
1229         u32 cnt = 0;
1230         u32 cnt1 = 0;
1231         u32 reg = 0;
1232         u32 grst_del;
1233
1234         /* Poll for Global Reset steady state in case of recent GRST.
1235          * The grst delay value is in 100ms units, and we'll wait a
1236          * couple counts longer to be sure we don't just miss the end.
1237          */
1238         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1239                     I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1240                     I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1241
1242         /* It can take upto 15 secs for GRST steady state.
1243          * Bump it to 16 secs max to be safe.
1244          */
1245         grst_del = grst_del * 20;
1246
1247         for (cnt = 0; cnt < grst_del; cnt++) {
1248                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1249                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1250                         break;
1251                 msleep(100);
1252         }
1253         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1254                 hw_dbg(hw, "Global reset polling failed to complete.\n");
1255                 return I40E_ERR_RESET_FAILED;
1256         }
1257
1258         /* Now Wait for the FW to be ready */
1259         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1260                 reg = rd32(hw, I40E_GLNVM_ULD);
1261                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1262                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1263                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1264                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1265                         hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1266                         break;
1267                 }
1268                 usleep_range(10000, 20000);
1269         }
1270         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1271                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1272                 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1273                 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1274                 return I40E_ERR_RESET_FAILED;
1275         }
1276
1277         /* If there was a Global Reset in progress when we got here,
1278          * we don't need to do the PF Reset
1279          */
1280         if (!cnt) {
1281                 u32 reg2 = 0;
1282                 if (hw->revision_id == 0)
1283                         cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1284                 else
1285                         cnt = I40E_PF_RESET_WAIT_COUNT;
1286                 reg = rd32(hw, I40E_PFGEN_CTRL);
1287                 wr32(hw, I40E_PFGEN_CTRL,
1288                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1289                 for (; cnt; cnt--) {
1290                         reg = rd32(hw, I40E_PFGEN_CTRL);
1291                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1292                                 break;
1293                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1294                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1295                                 break;
1296                         usleep_range(1000, 2000);
1297                 }
1298                 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1299                         if (i40e_poll_globr(hw, grst_del))
1300                                 return I40E_ERR_RESET_FAILED;
1301                 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1302                         hw_dbg(hw, "PF reset polling failed to complete.\n");
1303                         return I40E_ERR_RESET_FAILED;
1304                 }
1305         }
1306
1307         i40e_clear_pxe_mode(hw);
1308
1309         return 0;
1310 }
1311
1312 /**
1313  * i40e_clear_hw - clear out any left over hw state
1314  * @hw: pointer to the hw struct
1315  *
1316  * Clear queues and interrupts, typically called at init time,
1317  * but after the capabilities have been found so we know how many
1318  * queues and msix vectors have been allocated.
1319  **/
1320 void i40e_clear_hw(struct i40e_hw *hw)
1321 {
1322         u32 num_queues, base_queue;
1323         u32 num_pf_int;
1324         u32 num_vf_int;
1325         u32 num_vfs;
1326         u32 i, j;
1327         u32 val;
1328         u32 eol = 0x7ff;
1329
1330         /* get number of interrupts, queues, and VFs */
1331         val = rd32(hw, I40E_GLPCI_CNF2);
1332         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1333                      I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1334         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1335                      I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1336
1337         val = rd32(hw, I40E_PFLAN_QALLOC);
1338         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1339                      I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1340         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1341             I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1342         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1343                 num_queues = (j - base_queue) + 1;
1344         else
1345                 num_queues = 0;
1346
1347         val = rd32(hw, I40E_PF_VT_PFALLOC);
1348         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1349             I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1350         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1351             I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1352         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1353                 num_vfs = (j - i) + 1;
1354         else
1355                 num_vfs = 0;
1356
1357         /* stop all the interrupts */
1358         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1359         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1360         for (i = 0; i < num_pf_int - 2; i++)
1361                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1362
1363         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1364         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1365         wr32(hw, I40E_PFINT_LNKLST0, val);
1366         for (i = 0; i < num_pf_int - 2; i++)
1367                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1368         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1369         for (i = 0; i < num_vfs; i++)
1370                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1371         for (i = 0; i < num_vf_int - 2; i++)
1372                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1373
1374         /* warn the HW of the coming Tx disables */
1375         for (i = 0; i < num_queues; i++) {
1376                 u32 abs_queue_idx = base_queue + i;
1377                 u32 reg_block = 0;
1378
1379                 if (abs_queue_idx >= 128) {
1380                         reg_block = abs_queue_idx / 128;
1381                         abs_queue_idx %= 128;
1382                 }
1383
1384                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1385                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1386                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1387                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1388
1389                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1390         }
1391         udelay(400);
1392
1393         /* stop all the queues */
1394         for (i = 0; i < num_queues; i++) {
1395                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1396                 wr32(hw, I40E_QTX_ENA(i), 0);
1397                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1398                 wr32(hw, I40E_QRX_ENA(i), 0);
1399         }
1400
1401         /* short wait for all queue disables to settle */
1402         udelay(50);
1403 }
1404
1405 /**
1406  * i40e_clear_pxe_mode - clear pxe operations mode
1407  * @hw: pointer to the hw struct
1408  *
1409  * Make sure all PXE mode settings are cleared, including things
1410  * like descriptor fetch/write-back mode.
1411  **/
1412 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1413 {
1414         u32 reg;
1415
1416         if (i40e_check_asq_alive(hw))
1417                 i40e_aq_clear_pxe_mode(hw, NULL);
1418
1419         /* Clear single descriptor fetch/write-back mode */
1420         reg = rd32(hw, I40E_GLLAN_RCTL_0);
1421
1422         if (hw->revision_id == 0) {
1423                 /* As a work around clear PXE_MODE instead of setting it */
1424                 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1425         } else {
1426                 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1427         }
1428 }
1429
1430 /**
1431  * i40e_led_is_mine - helper to find matching led
1432  * @hw: pointer to the hw struct
1433  * @idx: index into GPIO registers
1434  *
1435  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1436  */
1437 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1438 {
1439         u32 gpio_val = 0;
1440         u32 port;
1441
1442         if (!I40E_IS_X710TL_DEVICE(hw->device_id) &&
1443             !hw->func_caps.led[idx])
1444                 return 0;
1445         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1446         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1447                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1448
1449         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1450          * if it is not our port then ignore
1451          */
1452         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1453             (port != hw->port))
1454                 return 0;
1455
1456         return gpio_val;
1457 }
1458
1459 #define I40E_FW_LED BIT(4)
1460 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
1461                              I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
1462
1463 #define I40E_LED0 22
1464
1465 #define I40E_PIN_FUNC_SDP 0x0
1466 #define I40E_PIN_FUNC_LED 0x1
1467
1468 /**
1469  * i40e_led_get - return current on/off mode
1470  * @hw: pointer to the hw struct
1471  *
1472  * The value returned is the 'mode' field as defined in the
1473  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1474  * values are variations of possible behaviors relating to
1475  * blink, link, and wire.
1476  **/
1477 u32 i40e_led_get(struct i40e_hw *hw)
1478 {
1479         u32 mode = 0;
1480         int i;
1481
1482         /* as per the documentation GPIO 22-29 are the LED
1483          * GPIO pins named LED0..LED7
1484          */
1485         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1486                 u32 gpio_val = i40e_led_is_mine(hw, i);
1487
1488                 if (!gpio_val)
1489                         continue;
1490
1491                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1492                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1493                 break;
1494         }
1495
1496         return mode;
1497 }
1498
1499 /**
1500  * i40e_led_set - set new on/off mode
1501  * @hw: pointer to the hw struct
1502  * @mode: 0=off, 0xf=on (else see manual for mode details)
1503  * @blink: true if the LED should blink when on, false if steady
1504  *
1505  * if this function is used to turn on the blink it should
1506  * be used to disable the blink when restoring the original state.
1507  **/
1508 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1509 {
1510         int i;
1511
1512         if (mode & ~I40E_LED_MODE_VALID) {
1513                 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1514                 return;
1515         }
1516
1517         /* as per the documentation GPIO 22-29 are the LED
1518          * GPIO pins named LED0..LED7
1519          */
1520         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1521                 u32 gpio_val = i40e_led_is_mine(hw, i);
1522
1523                 if (!gpio_val)
1524                         continue;
1525
1526                 if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
1527                         u32 pin_func = 0;
1528
1529                         if (mode & I40E_FW_LED)
1530                                 pin_func = I40E_PIN_FUNC_SDP;
1531                         else
1532                                 pin_func = I40E_PIN_FUNC_LED;
1533
1534                         gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;
1535                         gpio_val |= ((pin_func <<
1536                                      I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) &
1537                                      I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK);
1538                 }
1539                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1540                 /* this & is a bit of paranoia, but serves as a range check */
1541                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1542                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1543
1544                 if (blink)
1545                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1546                 else
1547                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1548
1549                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1550                 break;
1551         }
1552 }
1553
1554 /* Admin command wrappers */
1555
1556 /**
1557  * i40e_aq_get_phy_capabilities
1558  * @hw: pointer to the hw struct
1559  * @abilities: structure for PHY capabilities to be filled
1560  * @qualified_modules: report Qualified Modules
1561  * @report_init: report init capabilities (active are default)
1562  * @cmd_details: pointer to command details structure or NULL
1563  *
1564  * Returns the various PHY abilities supported on the Port.
1565  **/
1566 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1567                         bool qualified_modules, bool report_init,
1568                         struct i40e_aq_get_phy_abilities_resp *abilities,
1569                         struct i40e_asq_cmd_details *cmd_details)
1570 {
1571         struct i40e_aq_desc desc;
1572         i40e_status status;
1573         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1574         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1575
1576         if (!abilities)
1577                 return I40E_ERR_PARAM;
1578
1579         do {
1580                 i40e_fill_default_direct_cmd_desc(&desc,
1581                                                i40e_aqc_opc_get_phy_abilities);
1582
1583                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1584                 if (abilities_size > I40E_AQ_LARGE_BUF)
1585                         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1586
1587                 if (qualified_modules)
1588                         desc.params.external.param0 |=
1589                         cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1590
1591                 if (report_init)
1592                         desc.params.external.param0 |=
1593                         cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1594
1595                 status = i40e_asq_send_command(hw, &desc, abilities,
1596                                                abilities_size, cmd_details);
1597
1598                 switch (hw->aq.asq_last_status) {
1599                 case I40E_AQ_RC_EIO:
1600                         status = I40E_ERR_UNKNOWN_PHY;
1601                         break;
1602                 case I40E_AQ_RC_EAGAIN:
1603                         usleep_range(1000, 2000);
1604                         total_delay++;
1605                         status = I40E_ERR_TIMEOUT;
1606                         break;
1607                 /* also covers I40E_AQ_RC_OK */
1608                 default:
1609                         break;
1610                 }
1611
1612         } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1613                 (total_delay < max_delay));
1614
1615         if (status)
1616                 return status;
1617
1618         if (report_init) {
1619                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1620                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1621                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1622                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1623                 } else {
1624                         hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1625                         hw->phy.phy_types |=
1626                                         ((u64)abilities->phy_type_ext << 32);
1627                 }
1628         }
1629
1630         return status;
1631 }
1632
1633 /**
1634  * i40e_aq_set_phy_config
1635  * @hw: pointer to the hw struct
1636  * @config: structure with PHY configuration to be set
1637  * @cmd_details: pointer to command details structure or NULL
1638  *
1639  * Set the various PHY configuration parameters
1640  * supported on the Port.One or more of the Set PHY config parameters may be
1641  * ignored in an MFP mode as the PF may not have the privilege to set some
1642  * of the PHY Config parameters. This status will be indicated by the
1643  * command response.
1644  **/
1645 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1646                                 struct i40e_aq_set_phy_config *config,
1647                                 struct i40e_asq_cmd_details *cmd_details)
1648 {
1649         struct i40e_aq_desc desc;
1650         struct i40e_aq_set_phy_config *cmd =
1651                         (struct i40e_aq_set_phy_config *)&desc.params.raw;
1652         enum i40e_status_code status;
1653
1654         if (!config)
1655                 return I40E_ERR_PARAM;
1656
1657         i40e_fill_default_direct_cmd_desc(&desc,
1658                                           i40e_aqc_opc_set_phy_config);
1659
1660         *cmd = *config;
1661
1662         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1663
1664         return status;
1665 }
1666
1667 static noinline_for_stack enum i40e_status_code
1668 i40e_set_fc_status(struct i40e_hw *hw,
1669                    struct i40e_aq_get_phy_abilities_resp *abilities,
1670                    bool atomic_restart)
1671 {
1672         struct i40e_aq_set_phy_config config;
1673         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1674         u8 pause_mask = 0x0;
1675
1676         switch (fc_mode) {
1677         case I40E_FC_FULL:
1678                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1679                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1680                 break;
1681         case I40E_FC_RX_PAUSE:
1682                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1683                 break;
1684         case I40E_FC_TX_PAUSE:
1685                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1686                 break;
1687         default:
1688                 break;
1689         }
1690
1691         memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1692         /* clear the old pause settings */
1693         config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1694                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1695         /* set the new abilities */
1696         config.abilities |= pause_mask;
1697         /* If the abilities have changed, then set the new config */
1698         if (config.abilities == abilities->abilities)
1699                 return 0;
1700
1701         /* Auto restart link so settings take effect */
1702         if (atomic_restart)
1703                 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1704         /* Copy over all the old settings */
1705         config.phy_type = abilities->phy_type;
1706         config.phy_type_ext = abilities->phy_type_ext;
1707         config.link_speed = abilities->link_speed;
1708         config.eee_capability = abilities->eee_capability;
1709         config.eeer = abilities->eeer_val;
1710         config.low_power_ctrl = abilities->d3_lpan;
1711         config.fec_config = abilities->fec_cfg_curr_mod_ext_info &
1712                             I40E_AQ_PHY_FEC_CONFIG_MASK;
1713
1714         return i40e_aq_set_phy_config(hw, &config, NULL);
1715 }
1716
1717 /**
1718  * i40e_set_fc
1719  * @hw: pointer to the hw struct
1720  * @aq_failures: buffer to return AdminQ failure information
1721  * @atomic_restart: whether to enable atomic link restart
1722  *
1723  * Set the requested flow control mode using set_phy_config.
1724  **/
1725 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1726                                   bool atomic_restart)
1727 {
1728         struct i40e_aq_get_phy_abilities_resp abilities;
1729         enum i40e_status_code status;
1730
1731         *aq_failures = 0x0;
1732
1733         /* Get the current phy config */
1734         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1735                                               NULL);
1736         if (status) {
1737                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1738                 return status;
1739         }
1740
1741         status = i40e_set_fc_status(hw, &abilities, atomic_restart);
1742         if (status)
1743                 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1744
1745         /* Update the link info */
1746         status = i40e_update_link_info(hw);
1747         if (status) {
1748                 /* Wait a little bit (on 40G cards it sometimes takes a really
1749                  * long time for link to come back from the atomic reset)
1750                  * and try once more
1751                  */
1752                 msleep(1000);
1753                 status = i40e_update_link_info(hw);
1754         }
1755         if (status)
1756                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1757
1758         return status;
1759 }
1760
1761 /**
1762  * i40e_aq_clear_pxe_mode
1763  * @hw: pointer to the hw struct
1764  * @cmd_details: pointer to command details structure or NULL
1765  *
1766  * Tell the firmware that the driver is taking over from PXE
1767  **/
1768 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1769                                 struct i40e_asq_cmd_details *cmd_details)
1770 {
1771         i40e_status status;
1772         struct i40e_aq_desc desc;
1773         struct i40e_aqc_clear_pxe *cmd =
1774                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1775
1776         i40e_fill_default_direct_cmd_desc(&desc,
1777                                           i40e_aqc_opc_clear_pxe_mode);
1778
1779         cmd->rx_cnt = 0x2;
1780
1781         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1782
1783         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1784
1785         return status;
1786 }
1787
1788 /**
1789  * i40e_aq_set_link_restart_an
1790  * @hw: pointer to the hw struct
1791  * @enable_link: if true: enable link, if false: disable link
1792  * @cmd_details: pointer to command details structure or NULL
1793  *
1794  * Sets up the link and restarts the Auto-Negotiation over the link.
1795  **/
1796 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1797                                         bool enable_link,
1798                                         struct i40e_asq_cmd_details *cmd_details)
1799 {
1800         struct i40e_aq_desc desc;
1801         struct i40e_aqc_set_link_restart_an *cmd =
1802                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1803         i40e_status status;
1804
1805         i40e_fill_default_direct_cmd_desc(&desc,
1806                                           i40e_aqc_opc_set_link_restart_an);
1807
1808         cmd->command = I40E_AQ_PHY_RESTART_AN;
1809         if (enable_link)
1810                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1811         else
1812                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1813
1814         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1815
1816         return status;
1817 }
1818
1819 /**
1820  * i40e_aq_get_link_info
1821  * @hw: pointer to the hw struct
1822  * @enable_lse: enable/disable LinkStatusEvent reporting
1823  * @link: pointer to link status structure - optional
1824  * @cmd_details: pointer to command details structure or NULL
1825  *
1826  * Returns the link status of the adapter.
1827  **/
1828 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1829                                 bool enable_lse, struct i40e_link_status *link,
1830                                 struct i40e_asq_cmd_details *cmd_details)
1831 {
1832         struct i40e_aq_desc desc;
1833         struct i40e_aqc_get_link_status *resp =
1834                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1835         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1836         i40e_status status;
1837         bool tx_pause, rx_pause;
1838         u16 command_flags;
1839
1840         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1841
1842         if (enable_lse)
1843                 command_flags = I40E_AQ_LSE_ENABLE;
1844         else
1845                 command_flags = I40E_AQ_LSE_DISABLE;
1846         resp->command_flags = cpu_to_le16(command_flags);
1847
1848         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1849
1850         if (status)
1851                 goto aq_get_link_info_exit;
1852
1853         /* save off old link status information */
1854         hw->phy.link_info_old = *hw_link_info;
1855
1856         /* update link status */
1857         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1858         hw->phy.media_type = i40e_get_media_type(hw);
1859         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1860         hw_link_info->link_info = resp->link_info;
1861         hw_link_info->an_info = resp->an_info;
1862         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1863                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1864         hw_link_info->ext_info = resp->ext_info;
1865         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1866         hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1867         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1868
1869         /* update fc info */
1870         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1871         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1872         if (tx_pause & rx_pause)
1873                 hw->fc.current_mode = I40E_FC_FULL;
1874         else if (tx_pause)
1875                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1876         else if (rx_pause)
1877                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1878         else
1879                 hw->fc.current_mode = I40E_FC_NONE;
1880
1881         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1882                 hw_link_info->crc_enable = true;
1883         else
1884                 hw_link_info->crc_enable = false;
1885
1886         if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
1887                 hw_link_info->lse_enable = true;
1888         else
1889                 hw_link_info->lse_enable = false;
1890
1891         if ((hw->mac.type == I40E_MAC_XL710) &&
1892             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1893              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1894                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1895
1896         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
1897             hw->mac.type != I40E_MAC_X722) {
1898                 __le32 tmp;
1899
1900                 memcpy(&tmp, resp->link_type, sizeof(tmp));
1901                 hw->phy.phy_types = le32_to_cpu(tmp);
1902                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
1903         }
1904
1905         /* save link status information */
1906         if (link)
1907                 *link = *hw_link_info;
1908
1909         /* flag cleared so helper functions don't call AQ again */
1910         hw->phy.get_link_info = false;
1911
1912 aq_get_link_info_exit:
1913         return status;
1914 }
1915
1916 /**
1917  * i40e_aq_set_phy_int_mask
1918  * @hw: pointer to the hw struct
1919  * @mask: interrupt mask to be set
1920  * @cmd_details: pointer to command details structure or NULL
1921  *
1922  * Set link interrupt mask.
1923  **/
1924 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1925                                      u16 mask,
1926                                      struct i40e_asq_cmd_details *cmd_details)
1927 {
1928         struct i40e_aq_desc desc;
1929         struct i40e_aqc_set_phy_int_mask *cmd =
1930                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1931         i40e_status status;
1932
1933         i40e_fill_default_direct_cmd_desc(&desc,
1934                                           i40e_aqc_opc_set_phy_int_mask);
1935
1936         cmd->event_mask = cpu_to_le16(mask);
1937
1938         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1939
1940         return status;
1941 }
1942
1943 /**
1944  * i40e_aq_set_phy_debug
1945  * @hw: pointer to the hw struct
1946  * @cmd_flags: debug command flags
1947  * @cmd_details: pointer to command details structure or NULL
1948  *
1949  * Reset the external PHY.
1950  **/
1951 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1952                                   struct i40e_asq_cmd_details *cmd_details)
1953 {
1954         struct i40e_aq_desc desc;
1955         struct i40e_aqc_set_phy_debug *cmd =
1956                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1957         i40e_status status;
1958
1959         i40e_fill_default_direct_cmd_desc(&desc,
1960                                           i40e_aqc_opc_set_phy_debug);
1961
1962         cmd->command_flags = cmd_flags;
1963
1964         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1965
1966         return status;
1967 }
1968
1969 /**
1970  * i40e_aq_add_vsi
1971  * @hw: pointer to the hw struct
1972  * @vsi_ctx: pointer to a vsi context struct
1973  * @cmd_details: pointer to command details structure or NULL
1974  *
1975  * Add a VSI context to the hardware.
1976 **/
1977 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1978                                 struct i40e_vsi_context *vsi_ctx,
1979                                 struct i40e_asq_cmd_details *cmd_details)
1980 {
1981         struct i40e_aq_desc desc;
1982         struct i40e_aqc_add_get_update_vsi *cmd =
1983                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1984         struct i40e_aqc_add_get_update_vsi_completion *resp =
1985                 (struct i40e_aqc_add_get_update_vsi_completion *)
1986                 &desc.params.raw;
1987         i40e_status status;
1988
1989         i40e_fill_default_direct_cmd_desc(&desc,
1990                                           i40e_aqc_opc_add_vsi);
1991
1992         cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1993         cmd->connection_type = vsi_ctx->connection_type;
1994         cmd->vf_id = vsi_ctx->vf_num;
1995         cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1996
1997         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1998
1999         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2000                                     sizeof(vsi_ctx->info), cmd_details);
2001
2002         if (status)
2003                 goto aq_add_vsi_exit;
2004
2005         vsi_ctx->seid = le16_to_cpu(resp->seid);
2006         vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2007         vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2008         vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2009
2010 aq_add_vsi_exit:
2011         return status;
2012 }
2013
2014 /**
2015  * i40e_aq_set_default_vsi
2016  * @hw: pointer to the hw struct
2017  * @seid: vsi number
2018  * @cmd_details: pointer to command details structure or NULL
2019  **/
2020 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw,
2021                                     u16 seid,
2022                                     struct i40e_asq_cmd_details *cmd_details)
2023 {
2024         struct i40e_aq_desc desc;
2025         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2026                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2027                 &desc.params.raw;
2028         i40e_status status;
2029
2030         i40e_fill_default_direct_cmd_desc(&desc,
2031                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2032
2033         cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2034         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2035         cmd->seid = cpu_to_le16(seid);
2036
2037         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2038
2039         return status;
2040 }
2041
2042 /**
2043  * i40e_aq_clear_default_vsi
2044  * @hw: pointer to the hw struct
2045  * @seid: vsi number
2046  * @cmd_details: pointer to command details structure or NULL
2047  **/
2048 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2049                                       u16 seid,
2050                                       struct i40e_asq_cmd_details *cmd_details)
2051 {
2052         struct i40e_aq_desc desc;
2053         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2054                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2055                 &desc.params.raw;
2056         i40e_status status;
2057
2058         i40e_fill_default_direct_cmd_desc(&desc,
2059                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2060
2061         cmd->promiscuous_flags = cpu_to_le16(0);
2062         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2063         cmd->seid = cpu_to_le16(seid);
2064
2065         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2066
2067         return status;
2068 }
2069
2070 /**
2071  * i40e_aq_set_vsi_unicast_promiscuous
2072  * @hw: pointer to the hw struct
2073  * @seid: vsi number
2074  * @set: set unicast promiscuous enable/disable
2075  * @cmd_details: pointer to command details structure or NULL
2076  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2077  **/
2078 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2079                                 u16 seid, bool set,
2080                                 struct i40e_asq_cmd_details *cmd_details,
2081                                 bool rx_only_promisc)
2082 {
2083         struct i40e_aq_desc desc;
2084         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2085                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2086         i40e_status status;
2087         u16 flags = 0;
2088
2089         i40e_fill_default_direct_cmd_desc(&desc,
2090                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2091
2092         if (set) {
2093                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2094                 if (rx_only_promisc &&
2095                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2096                      (hw->aq.api_maj_ver > 1)))
2097                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2098         }
2099
2100         cmd->promiscuous_flags = cpu_to_le16(flags);
2101
2102         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2103         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2104             (hw->aq.api_maj_ver > 1))
2105                 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX);
2106
2107         cmd->seid = cpu_to_le16(seid);
2108         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2109
2110         return status;
2111 }
2112
2113 /**
2114  * i40e_aq_set_vsi_multicast_promiscuous
2115  * @hw: pointer to the hw struct
2116  * @seid: vsi number
2117  * @set: set multicast promiscuous enable/disable
2118  * @cmd_details: pointer to command details structure or NULL
2119  **/
2120 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2121                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2122 {
2123         struct i40e_aq_desc desc;
2124         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2125                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2126         i40e_status status;
2127         u16 flags = 0;
2128
2129         i40e_fill_default_direct_cmd_desc(&desc,
2130                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2131
2132         if (set)
2133                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2134
2135         cmd->promiscuous_flags = cpu_to_le16(flags);
2136
2137         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2138
2139         cmd->seid = cpu_to_le16(seid);
2140         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2141
2142         return status;
2143 }
2144
2145 /**
2146  * i40e_aq_set_vsi_mc_promisc_on_vlan
2147  * @hw: pointer to the hw struct
2148  * @seid: vsi number
2149  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2150  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2151  * @cmd_details: pointer to command details structure or NULL
2152  **/
2153 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2154                                                          u16 seid, bool enable,
2155                                                          u16 vid,
2156                                 struct i40e_asq_cmd_details *cmd_details)
2157 {
2158         struct i40e_aq_desc desc;
2159         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2160                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2161         enum i40e_status_code status;
2162         u16 flags = 0;
2163
2164         i40e_fill_default_direct_cmd_desc(&desc,
2165                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2166
2167         if (enable)
2168                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2169
2170         cmd->promiscuous_flags = cpu_to_le16(flags);
2171         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2172         cmd->seid = cpu_to_le16(seid);
2173         cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2174
2175         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2176
2177         return status;
2178 }
2179
2180 /**
2181  * i40e_aq_set_vsi_uc_promisc_on_vlan
2182  * @hw: pointer to the hw struct
2183  * @seid: vsi number
2184  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2185  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2186  * @cmd_details: pointer to command details structure or NULL
2187  **/
2188 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2189                                                          u16 seid, bool enable,
2190                                                          u16 vid,
2191                                 struct i40e_asq_cmd_details *cmd_details)
2192 {
2193         struct i40e_aq_desc desc;
2194         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2195                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2196         enum i40e_status_code status;
2197         u16 flags = 0;
2198
2199         i40e_fill_default_direct_cmd_desc(&desc,
2200                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2201
2202         if (enable)
2203                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2204
2205         cmd->promiscuous_flags = cpu_to_le16(flags);
2206         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2207         cmd->seid = cpu_to_le16(seid);
2208         cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2209
2210         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2211
2212         return status;
2213 }
2214
2215 /**
2216  * i40e_aq_set_vsi_bc_promisc_on_vlan
2217  * @hw: pointer to the hw struct
2218  * @seid: vsi number
2219  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2220  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2221  * @cmd_details: pointer to command details structure or NULL
2222  **/
2223 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2224                                 u16 seid, bool enable, u16 vid,
2225                                 struct i40e_asq_cmd_details *cmd_details)
2226 {
2227         struct i40e_aq_desc desc;
2228         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2229                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2230         i40e_status status;
2231         u16 flags = 0;
2232
2233         i40e_fill_default_direct_cmd_desc(&desc,
2234                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2235
2236         if (enable)
2237                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2238
2239         cmd->promiscuous_flags = cpu_to_le16(flags);
2240         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2241         cmd->seid = cpu_to_le16(seid);
2242         cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2243
2244         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2245
2246         return status;
2247 }
2248
2249 /**
2250  * i40e_aq_set_vsi_broadcast
2251  * @hw: pointer to the hw struct
2252  * @seid: vsi number
2253  * @set_filter: true to set filter, false to clear filter
2254  * @cmd_details: pointer to command details structure or NULL
2255  *
2256  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2257  **/
2258 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2259                                 u16 seid, bool set_filter,
2260                                 struct i40e_asq_cmd_details *cmd_details)
2261 {
2262         struct i40e_aq_desc desc;
2263         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2264                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2265         i40e_status status;
2266
2267         i40e_fill_default_direct_cmd_desc(&desc,
2268                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2269
2270         if (set_filter)
2271                 cmd->promiscuous_flags
2272                             |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2273         else
2274                 cmd->promiscuous_flags
2275                             &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2276
2277         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2278         cmd->seid = cpu_to_le16(seid);
2279         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2280
2281         return status;
2282 }
2283
2284 /**
2285  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2286  * @hw: pointer to the hw struct
2287  * @seid: vsi number
2288  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2289  * @cmd_details: pointer to command details structure or NULL
2290  **/
2291 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2292                                        u16 seid, bool enable,
2293                                        struct i40e_asq_cmd_details *cmd_details)
2294 {
2295         struct i40e_aq_desc desc;
2296         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2297                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2298         i40e_status status;
2299         u16 flags = 0;
2300
2301         i40e_fill_default_direct_cmd_desc(&desc,
2302                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2303         if (enable)
2304                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2305
2306         cmd->promiscuous_flags = cpu_to_le16(flags);
2307         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2308         cmd->seid = cpu_to_le16(seid);
2309
2310         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2311
2312         return status;
2313 }
2314
2315 /**
2316  * i40e_get_vsi_params - get VSI configuration info
2317  * @hw: pointer to the hw struct
2318  * @vsi_ctx: pointer to a vsi context struct
2319  * @cmd_details: pointer to command details structure or NULL
2320  **/
2321 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2322                                 struct i40e_vsi_context *vsi_ctx,
2323                                 struct i40e_asq_cmd_details *cmd_details)
2324 {
2325         struct i40e_aq_desc desc;
2326         struct i40e_aqc_add_get_update_vsi *cmd =
2327                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2328         struct i40e_aqc_add_get_update_vsi_completion *resp =
2329                 (struct i40e_aqc_add_get_update_vsi_completion *)
2330                 &desc.params.raw;
2331         i40e_status status;
2332
2333         i40e_fill_default_direct_cmd_desc(&desc,
2334                                           i40e_aqc_opc_get_vsi_parameters);
2335
2336         cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2337
2338         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2339
2340         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2341                                     sizeof(vsi_ctx->info), NULL);
2342
2343         if (status)
2344                 goto aq_get_vsi_params_exit;
2345
2346         vsi_ctx->seid = le16_to_cpu(resp->seid);
2347         vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2348         vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2349         vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2350
2351 aq_get_vsi_params_exit:
2352         return status;
2353 }
2354
2355 /**
2356  * i40e_aq_update_vsi_params
2357  * @hw: pointer to the hw struct
2358  * @vsi_ctx: pointer to a vsi context struct
2359  * @cmd_details: pointer to command details structure or NULL
2360  *
2361  * Update a VSI context.
2362  **/
2363 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2364                                 struct i40e_vsi_context *vsi_ctx,
2365                                 struct i40e_asq_cmd_details *cmd_details)
2366 {
2367         struct i40e_aq_desc desc;
2368         struct i40e_aqc_add_get_update_vsi *cmd =
2369                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2370         struct i40e_aqc_add_get_update_vsi_completion *resp =
2371                 (struct i40e_aqc_add_get_update_vsi_completion *)
2372                 &desc.params.raw;
2373         i40e_status status;
2374
2375         i40e_fill_default_direct_cmd_desc(&desc,
2376                                           i40e_aqc_opc_update_vsi_parameters);
2377         cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2378
2379         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2380
2381         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2382                                     sizeof(vsi_ctx->info), cmd_details);
2383
2384         vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2385         vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2386
2387         return status;
2388 }
2389
2390 /**
2391  * i40e_aq_get_switch_config
2392  * @hw: pointer to the hardware structure
2393  * @buf: pointer to the result buffer
2394  * @buf_size: length of input buffer
2395  * @start_seid: seid to start for the report, 0 == beginning
2396  * @cmd_details: pointer to command details structure or NULL
2397  *
2398  * Fill the buf with switch configuration returned from AdminQ command
2399  **/
2400 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2401                                 struct i40e_aqc_get_switch_config_resp *buf,
2402                                 u16 buf_size, u16 *start_seid,
2403                                 struct i40e_asq_cmd_details *cmd_details)
2404 {
2405         struct i40e_aq_desc desc;
2406         struct i40e_aqc_switch_seid *scfg =
2407                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2408         i40e_status status;
2409
2410         i40e_fill_default_direct_cmd_desc(&desc,
2411                                           i40e_aqc_opc_get_switch_config);
2412         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2413         if (buf_size > I40E_AQ_LARGE_BUF)
2414                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2415         scfg->seid = cpu_to_le16(*start_seid);
2416
2417         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2418         *start_seid = le16_to_cpu(scfg->seid);
2419
2420         return status;
2421 }
2422
2423 /**
2424  * i40e_aq_set_switch_config
2425  * @hw: pointer to the hardware structure
2426  * @flags: bit flag values to set
2427  * @mode: cloud filter mode
2428  * @valid_flags: which bit flags to set
2429  * @mode: cloud filter mode
2430  * @cmd_details: pointer to command details structure or NULL
2431  *
2432  * Set switch configuration bits
2433  **/
2434 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2435                                                 u16 flags,
2436                                                 u16 valid_flags, u8 mode,
2437                                 struct i40e_asq_cmd_details *cmd_details)
2438 {
2439         struct i40e_aq_desc desc;
2440         struct i40e_aqc_set_switch_config *scfg =
2441                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2442         enum i40e_status_code status;
2443
2444         i40e_fill_default_direct_cmd_desc(&desc,
2445                                           i40e_aqc_opc_set_switch_config);
2446         scfg->flags = cpu_to_le16(flags);
2447         scfg->valid_flags = cpu_to_le16(valid_flags);
2448         scfg->mode = mode;
2449         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2450                 scfg->switch_tag = cpu_to_le16(hw->switch_tag);
2451                 scfg->first_tag = cpu_to_le16(hw->first_tag);
2452                 scfg->second_tag = cpu_to_le16(hw->second_tag);
2453         }
2454         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2455
2456         return status;
2457 }
2458
2459 /**
2460  * i40e_aq_get_firmware_version
2461  * @hw: pointer to the hw struct
2462  * @fw_major_version: firmware major version
2463  * @fw_minor_version: firmware minor version
2464  * @fw_build: firmware build number
2465  * @api_major_version: major queue version
2466  * @api_minor_version: minor queue version
2467  * @cmd_details: pointer to command details structure or NULL
2468  *
2469  * Get the firmware version from the admin queue commands
2470  **/
2471 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2472                                 u16 *fw_major_version, u16 *fw_minor_version,
2473                                 u32 *fw_build,
2474                                 u16 *api_major_version, u16 *api_minor_version,
2475                                 struct i40e_asq_cmd_details *cmd_details)
2476 {
2477         struct i40e_aq_desc desc;
2478         struct i40e_aqc_get_version *resp =
2479                 (struct i40e_aqc_get_version *)&desc.params.raw;
2480         i40e_status status;
2481
2482         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2483
2484         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2485
2486         if (!status) {
2487                 if (fw_major_version)
2488                         *fw_major_version = le16_to_cpu(resp->fw_major);
2489                 if (fw_minor_version)
2490                         *fw_minor_version = le16_to_cpu(resp->fw_minor);
2491                 if (fw_build)
2492                         *fw_build = le32_to_cpu(resp->fw_build);
2493                 if (api_major_version)
2494                         *api_major_version = le16_to_cpu(resp->api_major);
2495                 if (api_minor_version)
2496                         *api_minor_version = le16_to_cpu(resp->api_minor);
2497         }
2498
2499         return status;
2500 }
2501
2502 /**
2503  * i40e_aq_send_driver_version
2504  * @hw: pointer to the hw struct
2505  * @dv: driver's major, minor version
2506  * @cmd_details: pointer to command details structure or NULL
2507  *
2508  * Send the driver version to the firmware
2509  **/
2510 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2511                                 struct i40e_driver_version *dv,
2512                                 struct i40e_asq_cmd_details *cmd_details)
2513 {
2514         struct i40e_aq_desc desc;
2515         struct i40e_aqc_driver_version *cmd =
2516                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2517         i40e_status status;
2518         u16 len;
2519
2520         if (dv == NULL)
2521                 return I40E_ERR_PARAM;
2522
2523         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2524
2525         desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2526         cmd->driver_major_ver = dv->major_version;
2527         cmd->driver_minor_ver = dv->minor_version;
2528         cmd->driver_build_ver = dv->build_version;
2529         cmd->driver_subbuild_ver = dv->subbuild_version;
2530
2531         len = 0;
2532         while (len < sizeof(dv->driver_string) &&
2533                (dv->driver_string[len] < 0x80) &&
2534                dv->driver_string[len])
2535                 len++;
2536         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2537                                        len, cmd_details);
2538
2539         return status;
2540 }
2541
2542 /**
2543  * i40e_get_link_status - get status of the HW network link
2544  * @hw: pointer to the hw struct
2545  * @link_up: pointer to bool (true/false = linkup/linkdown)
2546  *
2547  * Variable link_up true if link is up, false if link is down.
2548  * The variable link_up is invalid if returned value of status != 0
2549  *
2550  * Side effect: LinkStatusEvent reporting becomes enabled
2551  **/
2552 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2553 {
2554         i40e_status status = 0;
2555
2556         if (hw->phy.get_link_info) {
2557                 status = i40e_update_link_info(hw);
2558
2559                 if (status)
2560                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2561                                    status);
2562         }
2563
2564         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2565
2566         return status;
2567 }
2568
2569 /**
2570  * i40e_updatelink_status - update status of the HW network link
2571  * @hw: pointer to the hw struct
2572  **/
2573 noinline_for_stack i40e_status i40e_update_link_info(struct i40e_hw *hw)
2574 {
2575         struct i40e_aq_get_phy_abilities_resp abilities;
2576         i40e_status status = 0;
2577
2578         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2579         if (status)
2580                 return status;
2581
2582         /* extra checking needed to ensure link info to user is timely */
2583         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2584             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2585              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2586                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2587                                                       &abilities, NULL);
2588                 if (status)
2589                         return status;
2590
2591                 if (abilities.fec_cfg_curr_mod_ext_info &
2592                     I40E_AQ_ENABLE_FEC_AUTO)
2593                         hw->phy.link_info.req_fec_info =
2594                                 (I40E_AQ_REQUEST_FEC_KR |
2595                                  I40E_AQ_REQUEST_FEC_RS);
2596                 else
2597                         hw->phy.link_info.req_fec_info =
2598                                 abilities.fec_cfg_curr_mod_ext_info &
2599                                 (I40E_AQ_REQUEST_FEC_KR |
2600                                  I40E_AQ_REQUEST_FEC_RS);
2601
2602                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2603                        sizeof(hw->phy.link_info.module_type));
2604         }
2605
2606         return status;
2607 }
2608
2609 /**
2610  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2611  * @hw: pointer to the hw struct
2612  * @uplink_seid: the MAC or other gizmo SEID
2613  * @downlink_seid: the VSI SEID
2614  * @enabled_tc: bitmap of TCs to be enabled
2615  * @default_port: true for default port VSI, false for control port
2616  * @veb_seid: pointer to where to put the resulting VEB SEID
2617  * @enable_stats: true to turn on VEB stats
2618  * @cmd_details: pointer to command details structure or NULL
2619  *
2620  * This asks the FW to add a VEB between the uplink and downlink
2621  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2622  **/
2623 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2624                                 u16 downlink_seid, u8 enabled_tc,
2625                                 bool default_port, u16 *veb_seid,
2626                                 bool enable_stats,
2627                                 struct i40e_asq_cmd_details *cmd_details)
2628 {
2629         struct i40e_aq_desc desc;
2630         struct i40e_aqc_add_veb *cmd =
2631                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2632         struct i40e_aqc_add_veb_completion *resp =
2633                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2634         i40e_status status;
2635         u16 veb_flags = 0;
2636
2637         /* SEIDs need to either both be set or both be 0 for floating VEB */
2638         if (!!uplink_seid != !!downlink_seid)
2639                 return I40E_ERR_PARAM;
2640
2641         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2642
2643         cmd->uplink_seid = cpu_to_le16(uplink_seid);
2644         cmd->downlink_seid = cpu_to_le16(downlink_seid);
2645         cmd->enable_tcs = enabled_tc;
2646         if (!uplink_seid)
2647                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2648         if (default_port)
2649                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2650         else
2651                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2652
2653         /* reverse logic here: set the bitflag to disable the stats */
2654         if (!enable_stats)
2655                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2656
2657         cmd->veb_flags = cpu_to_le16(veb_flags);
2658
2659         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2660
2661         if (!status && veb_seid)
2662                 *veb_seid = le16_to_cpu(resp->veb_seid);
2663
2664         return status;
2665 }
2666
2667 /**
2668  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2669  * @hw: pointer to the hw struct
2670  * @veb_seid: the SEID of the VEB to query
2671  * @switch_id: the uplink switch id
2672  * @floating: set to true if the VEB is floating
2673  * @statistic_index: index of the stats counter block for this VEB
2674  * @vebs_used: number of VEB's used by function
2675  * @vebs_free: total VEB's not reserved by any function
2676  * @cmd_details: pointer to command details structure or NULL
2677  *
2678  * This retrieves the parameters for a particular VEB, specified by
2679  * uplink_seid, and returns them to the caller.
2680  **/
2681 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2682                                 u16 veb_seid, u16 *switch_id,
2683                                 bool *floating, u16 *statistic_index,
2684                                 u16 *vebs_used, u16 *vebs_free,
2685                                 struct i40e_asq_cmd_details *cmd_details)
2686 {
2687         struct i40e_aq_desc desc;
2688         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2689                 (struct i40e_aqc_get_veb_parameters_completion *)
2690                 &desc.params.raw;
2691         i40e_status status;
2692
2693         if (veb_seid == 0)
2694                 return I40E_ERR_PARAM;
2695
2696         i40e_fill_default_direct_cmd_desc(&desc,
2697                                           i40e_aqc_opc_get_veb_parameters);
2698         cmd_resp->seid = cpu_to_le16(veb_seid);
2699
2700         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2701         if (status)
2702                 goto get_veb_exit;
2703
2704         if (switch_id)
2705                 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2706         if (statistic_index)
2707                 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2708         if (vebs_used)
2709                 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2710         if (vebs_free)
2711                 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2712         if (floating) {
2713                 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2714
2715                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2716                         *floating = true;
2717                 else
2718                         *floating = false;
2719         }
2720
2721 get_veb_exit:
2722         return status;
2723 }
2724
2725 /**
2726  * i40e_aq_add_macvlan
2727  * @hw: pointer to the hw struct
2728  * @seid: VSI for the mac address
2729  * @mv_list: list of macvlans to be added
2730  * @count: length of the list
2731  * @cmd_details: pointer to command details structure or NULL
2732  *
2733  * Add MAC/VLAN addresses to the HW filtering
2734  **/
2735 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2736                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2737                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2738 {
2739         struct i40e_aq_desc desc;
2740         struct i40e_aqc_macvlan *cmd =
2741                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2742         i40e_status status;
2743         u16 buf_size;
2744         int i;
2745
2746         if (count == 0 || !mv_list || !hw)
2747                 return I40E_ERR_PARAM;
2748
2749         buf_size = count * sizeof(*mv_list);
2750
2751         /* prep the rest of the request */
2752         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2753         cmd->num_addresses = cpu_to_le16(count);
2754         cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2755         cmd->seid[1] = 0;
2756         cmd->seid[2] = 0;
2757
2758         for (i = 0; i < count; i++)
2759                 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2760                         mv_list[i].flags |=
2761                                cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2762
2763         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2764         if (buf_size > I40E_AQ_LARGE_BUF)
2765                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2766
2767         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2768                                        cmd_details);
2769
2770         return status;
2771 }
2772
2773 /**
2774  * i40e_aq_remove_macvlan
2775  * @hw: pointer to the hw struct
2776  * @seid: VSI for the mac address
2777  * @mv_list: list of macvlans to be removed
2778  * @count: length of the list
2779  * @cmd_details: pointer to command details structure or NULL
2780  *
2781  * Remove MAC/VLAN addresses from the HW filtering
2782  **/
2783 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2784                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2785                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2786 {
2787         struct i40e_aq_desc desc;
2788         struct i40e_aqc_macvlan *cmd =
2789                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2790         i40e_status status;
2791         u16 buf_size;
2792
2793         if (count == 0 || !mv_list || !hw)
2794                 return I40E_ERR_PARAM;
2795
2796         buf_size = count * sizeof(*mv_list);
2797
2798         /* prep the rest of the request */
2799         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2800         cmd->num_addresses = cpu_to_le16(count);
2801         cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2802         cmd->seid[1] = 0;
2803         cmd->seid[2] = 0;
2804
2805         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2806         if (buf_size > I40E_AQ_LARGE_BUF)
2807                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2808
2809         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2810                                        cmd_details);
2811
2812         return status;
2813 }
2814
2815 /**
2816  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2817  * @hw: pointer to the hw struct
2818  * @opcode: AQ opcode for add or delete mirror rule
2819  * @sw_seid: Switch SEID (to which rule refers)
2820  * @rule_type: Rule Type (ingress/egress/VLAN)
2821  * @id: Destination VSI SEID or Rule ID
2822  * @count: length of the list
2823  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2824  * @cmd_details: pointer to command details structure or NULL
2825  * @rule_id: Rule ID returned from FW
2826  * @rules_used: Number of rules used in internal switch
2827  * @rules_free: Number of rules free in internal switch
2828  *
2829  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2830  * VEBs/VEPA elements only
2831  **/
2832 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2833                                 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2834                                 u16 count, __le16 *mr_list,
2835                                 struct i40e_asq_cmd_details *cmd_details,
2836                                 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2837 {
2838         struct i40e_aq_desc desc;
2839         struct i40e_aqc_add_delete_mirror_rule *cmd =
2840                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2841         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2842         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2843         i40e_status status;
2844         u16 buf_size;
2845
2846         buf_size = count * sizeof(*mr_list);
2847
2848         /* prep the rest of the request */
2849         i40e_fill_default_direct_cmd_desc(&desc, opcode);
2850         cmd->seid = cpu_to_le16(sw_seid);
2851         cmd->rule_type = cpu_to_le16(rule_type &
2852                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
2853         cmd->num_entries = cpu_to_le16(count);
2854         /* Dest VSI for add, rule_id for delete */
2855         cmd->destination = cpu_to_le16(id);
2856         if (mr_list) {
2857                 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2858                                                 I40E_AQ_FLAG_RD));
2859                 if (buf_size > I40E_AQ_LARGE_BUF)
2860                         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2861         }
2862
2863         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2864                                        cmd_details);
2865         if (!status ||
2866             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2867                 if (rule_id)
2868                         *rule_id = le16_to_cpu(resp->rule_id);
2869                 if (rules_used)
2870                         *rules_used = le16_to_cpu(resp->mirror_rules_used);
2871                 if (rules_free)
2872                         *rules_free = le16_to_cpu(resp->mirror_rules_free);
2873         }
2874         return status;
2875 }
2876
2877 /**
2878  * i40e_aq_add_mirrorrule - add a mirror rule
2879  * @hw: pointer to the hw struct
2880  * @sw_seid: Switch SEID (to which rule refers)
2881  * @rule_type: Rule Type (ingress/egress/VLAN)
2882  * @dest_vsi: SEID of VSI to which packets will be mirrored
2883  * @count: length of the list
2884  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2885  * @cmd_details: pointer to command details structure or NULL
2886  * @rule_id: Rule ID returned from FW
2887  * @rules_used: Number of rules used in internal switch
2888  * @rules_free: Number of rules free in internal switch
2889  *
2890  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2891  **/
2892 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2893                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2894                         struct i40e_asq_cmd_details *cmd_details,
2895                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2896 {
2897         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2898             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2899                 if (count == 0 || !mr_list)
2900                         return I40E_ERR_PARAM;
2901         }
2902
2903         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2904                                   rule_type, dest_vsi, count, mr_list,
2905                                   cmd_details, rule_id, rules_used, rules_free);
2906 }
2907
2908 /**
2909  * i40e_aq_delete_mirrorrule - delete a mirror rule
2910  * @hw: pointer to the hw struct
2911  * @sw_seid: Switch SEID (to which rule refers)
2912  * @rule_type: Rule Type (ingress/egress/VLAN)
2913  * @count: length of the list
2914  * @rule_id: Rule ID that is returned in the receive desc as part of
2915  *              add_mirrorrule.
2916  * @mr_list: list of mirrored VLAN IDs to be removed
2917  * @cmd_details: pointer to command details structure or NULL
2918  * @rules_used: Number of rules used in internal switch
2919  * @rules_free: Number of rules free in internal switch
2920  *
2921  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2922  **/
2923 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2924                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2925                         struct i40e_asq_cmd_details *cmd_details,
2926                         u16 *rules_used, u16 *rules_free)
2927 {
2928         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2929         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2930                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2931                  * mirroring. For other rule_type, count and rule_type should
2932                  * not matter.
2933                  */
2934                 if (count == 0 || !mr_list)
2935                         return I40E_ERR_PARAM;
2936         }
2937
2938         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2939                                   rule_type, rule_id, count, mr_list,
2940                                   cmd_details, NULL, rules_used, rules_free);
2941 }
2942
2943 /**
2944  * i40e_aq_send_msg_to_vf
2945  * @hw: pointer to the hardware structure
2946  * @vfid: VF id to send msg
2947  * @v_opcode: opcodes for VF-PF communication
2948  * @v_retval: return error code
2949  * @msg: pointer to the msg buffer
2950  * @msglen: msg length
2951  * @cmd_details: pointer to command details
2952  *
2953  * send msg to vf
2954  **/
2955 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2956                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2957                                 struct i40e_asq_cmd_details *cmd_details)
2958 {
2959         struct i40e_aq_desc desc;
2960         struct i40e_aqc_pf_vf_message *cmd =
2961                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2962         i40e_status status;
2963
2964         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2965         cmd->id = cpu_to_le32(vfid);
2966         desc.cookie_high = cpu_to_le32(v_opcode);
2967         desc.cookie_low = cpu_to_le32(v_retval);
2968         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2969         if (msglen) {
2970                 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2971                                                 I40E_AQ_FLAG_RD));
2972                 if (msglen > I40E_AQ_LARGE_BUF)
2973                         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2974                 desc.datalen = cpu_to_le16(msglen);
2975         }
2976         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2977
2978         return status;
2979 }
2980
2981 /**
2982  * i40e_aq_debug_read_register
2983  * @hw: pointer to the hw struct
2984  * @reg_addr: register address
2985  * @reg_val: register value
2986  * @cmd_details: pointer to command details structure or NULL
2987  *
2988  * Read the register using the admin queue commands
2989  **/
2990 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2991                                 u32 reg_addr, u64 *reg_val,
2992                                 struct i40e_asq_cmd_details *cmd_details)
2993 {
2994         struct i40e_aq_desc desc;
2995         struct i40e_aqc_debug_reg_read_write *cmd_resp =
2996                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2997         i40e_status status;
2998
2999         if (reg_val == NULL)
3000                 return I40E_ERR_PARAM;
3001
3002         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3003
3004         cmd_resp->address = cpu_to_le32(reg_addr);
3005
3006         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3007
3008         if (!status) {
3009                 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
3010                            (u64)le32_to_cpu(cmd_resp->value_low);
3011         }
3012
3013         return status;
3014 }
3015
3016 /**
3017  * i40e_aq_debug_write_register
3018  * @hw: pointer to the hw struct
3019  * @reg_addr: register address
3020  * @reg_val: register value
3021  * @cmd_details: pointer to command details structure or NULL
3022  *
3023  * Write to a register using the admin queue commands
3024  **/
3025 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
3026                                         u32 reg_addr, u64 reg_val,
3027                                         struct i40e_asq_cmd_details *cmd_details)
3028 {
3029         struct i40e_aq_desc desc;
3030         struct i40e_aqc_debug_reg_read_write *cmd =
3031                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3032         i40e_status status;
3033
3034         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3035
3036         cmd->address = cpu_to_le32(reg_addr);
3037         cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
3038         cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
3039
3040         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3041
3042         return status;
3043 }
3044
3045 /**
3046  * i40e_aq_request_resource
3047  * @hw: pointer to the hw struct
3048  * @resource: resource id
3049  * @access: access type
3050  * @sdp_number: resource number
3051  * @timeout: the maximum time in ms that the driver may hold the resource
3052  * @cmd_details: pointer to command details structure or NULL
3053  *
3054  * requests common resource using the admin queue commands
3055  **/
3056 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
3057                                 enum i40e_aq_resources_ids resource,
3058                                 enum i40e_aq_resource_access_type access,
3059                                 u8 sdp_number, u64 *timeout,
3060                                 struct i40e_asq_cmd_details *cmd_details)
3061 {
3062         struct i40e_aq_desc desc;
3063         struct i40e_aqc_request_resource *cmd_resp =
3064                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3065         i40e_status status;
3066
3067         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3068
3069         cmd_resp->resource_id = cpu_to_le16(resource);
3070         cmd_resp->access_type = cpu_to_le16(access);
3071         cmd_resp->resource_number = cpu_to_le32(sdp_number);
3072
3073         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3074         /* The completion specifies the maximum time in ms that the driver
3075          * may hold the resource in the Timeout field.
3076          * If the resource is held by someone else, the command completes with
3077          * busy return value and the timeout field indicates the maximum time
3078          * the current owner of the resource has to free it.
3079          */
3080         if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3081                 *timeout = le32_to_cpu(cmd_resp->timeout);
3082
3083         return status;
3084 }
3085
3086 /**
3087  * i40e_aq_release_resource
3088  * @hw: pointer to the hw struct
3089  * @resource: resource id
3090  * @sdp_number: resource number
3091  * @cmd_details: pointer to command details structure or NULL
3092  *
3093  * release common resource using the admin queue commands
3094  **/
3095 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
3096                                 enum i40e_aq_resources_ids resource,
3097                                 u8 sdp_number,
3098                                 struct i40e_asq_cmd_details *cmd_details)
3099 {
3100         struct i40e_aq_desc desc;
3101         struct i40e_aqc_request_resource *cmd =
3102                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3103         i40e_status status;
3104
3105         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3106
3107         cmd->resource_id = cpu_to_le16(resource);
3108         cmd->resource_number = cpu_to_le32(sdp_number);
3109
3110         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3111
3112         return status;
3113 }
3114
3115 /**
3116  * i40e_aq_read_nvm
3117  * @hw: pointer to the hw struct
3118  * @module_pointer: module pointer location in words from the NVM beginning
3119  * @offset: byte offset from the module beginning
3120  * @length: length of the section to be read (in bytes from the offset)
3121  * @data: command buffer (size [bytes] = length)
3122  * @last_command: tells if this is the last command in a series
3123  * @cmd_details: pointer to command details structure or NULL
3124  *
3125  * Read the NVM using the admin queue commands
3126  **/
3127 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3128                                 u32 offset, u16 length, void *data,
3129                                 bool last_command,
3130                                 struct i40e_asq_cmd_details *cmd_details)
3131 {
3132         struct i40e_aq_desc desc;
3133         struct i40e_aqc_nvm_update *cmd =
3134                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3135         i40e_status status;
3136
3137         /* In offset the highest byte must be zeroed. */
3138         if (offset & 0xFF000000) {
3139                 status = I40E_ERR_PARAM;
3140                 goto i40e_aq_read_nvm_exit;
3141         }
3142
3143         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3144
3145         /* If this is the last command in a series, set the proper flag. */
3146         if (last_command)
3147                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3148         cmd->module_pointer = module_pointer;
3149         cmd->offset = cpu_to_le32(offset);
3150         cmd->length = cpu_to_le16(length);
3151
3152         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3153         if (length > I40E_AQ_LARGE_BUF)
3154                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3155
3156         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3157
3158 i40e_aq_read_nvm_exit:
3159         return status;
3160 }
3161
3162 /**
3163  * i40e_aq_erase_nvm
3164  * @hw: pointer to the hw struct
3165  * @module_pointer: module pointer location in words from the NVM beginning
3166  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3167  * @length: length of the section to be erased (expressed in 4 KB)
3168  * @last_command: tells if this is the last command in a series
3169  * @cmd_details: pointer to command details structure or NULL
3170  *
3171  * Erase the NVM sector using the admin queue commands
3172  **/
3173 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3174                               u32 offset, u16 length, bool last_command,
3175                               struct i40e_asq_cmd_details *cmd_details)
3176 {
3177         struct i40e_aq_desc desc;
3178         struct i40e_aqc_nvm_update *cmd =
3179                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3180         i40e_status status;
3181
3182         /* In offset the highest byte must be zeroed. */
3183         if (offset & 0xFF000000) {
3184                 status = I40E_ERR_PARAM;
3185                 goto i40e_aq_erase_nvm_exit;
3186         }
3187
3188         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3189
3190         /* If this is the last command in a series, set the proper flag. */
3191         if (last_command)
3192                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3193         cmd->module_pointer = module_pointer;
3194         cmd->offset = cpu_to_le32(offset);
3195         cmd->length = cpu_to_le16(length);
3196
3197         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3198
3199 i40e_aq_erase_nvm_exit:
3200         return status;
3201 }
3202
3203 /**
3204  * i40e_parse_discover_capabilities
3205  * @hw: pointer to the hw struct
3206  * @buff: pointer to a buffer containing device/function capability records
3207  * @cap_count: number of capability records in the list
3208  * @list_type_opc: type of capabilities list to parse
3209  *
3210  * Parse the device/function capabilities list.
3211  **/
3212 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3213                                      u32 cap_count,
3214                                      enum i40e_admin_queue_opc list_type_opc)
3215 {
3216         struct i40e_aqc_list_capabilities_element_resp *cap;
3217         u32 valid_functions, num_functions;
3218         u32 number, logical_id, phys_id;
3219         struct i40e_hw_capabilities *p;
3220         u16 id, ocp_cfg_word0;
3221         i40e_status status;
3222         u8 major_rev;
3223         u32 i = 0;
3224
3225         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3226
3227         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3228                 p = &hw->dev_caps;
3229         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3230                 p = &hw->func_caps;
3231         else
3232                 return;
3233
3234         for (i = 0; i < cap_count; i++, cap++) {
3235                 id = le16_to_cpu(cap->id);
3236                 number = le32_to_cpu(cap->number);
3237                 logical_id = le32_to_cpu(cap->logical_id);
3238                 phys_id = le32_to_cpu(cap->phys_id);
3239                 major_rev = cap->major_rev;
3240
3241                 switch (id) {
3242                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3243                         p->switch_mode = number;
3244                         break;
3245                 case I40E_AQ_CAP_ID_MNG_MODE:
3246                         p->management_mode = number;
3247                         if (major_rev > 1) {
3248                                 p->mng_protocols_over_mctp = logical_id;
3249                                 i40e_debug(hw, I40E_DEBUG_INIT,
3250                                            "HW Capability: Protocols over MCTP = %d\n",
3251                                            p->mng_protocols_over_mctp);
3252                         } else {
3253                                 p->mng_protocols_over_mctp = 0;
3254                         }
3255                         break;
3256                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3257                         p->npar_enable = number;
3258                         break;
3259                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3260                         p->os2bmc = number;
3261                         break;
3262                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3263                         p->valid_functions = number;
3264                         break;
3265                 case I40E_AQ_CAP_ID_SRIOV:
3266                         if (number == 1)
3267                                 p->sr_iov_1_1 = true;
3268                         break;
3269                 case I40E_AQ_CAP_ID_VF:
3270                         p->num_vfs = number;
3271                         p->vf_base_id = logical_id;
3272                         break;
3273                 case I40E_AQ_CAP_ID_VMDQ:
3274                         if (number == 1)
3275                                 p->vmdq = true;
3276                         break;
3277                 case I40E_AQ_CAP_ID_8021QBG:
3278                         if (number == 1)
3279                                 p->evb_802_1_qbg = true;
3280                         break;
3281                 case I40E_AQ_CAP_ID_8021QBR:
3282                         if (number == 1)
3283                                 p->evb_802_1_qbh = true;
3284                         break;
3285                 case I40E_AQ_CAP_ID_VSI:
3286                         p->num_vsis = number;
3287                         break;
3288                 case I40E_AQ_CAP_ID_DCB:
3289                         if (number == 1) {
3290                                 p->dcb = true;
3291                                 p->enabled_tcmap = logical_id;
3292                                 p->maxtc = phys_id;
3293                         }
3294                         break;
3295                 case I40E_AQ_CAP_ID_FCOE:
3296                         if (number == 1)
3297                                 p->fcoe = true;
3298                         break;
3299                 case I40E_AQ_CAP_ID_ISCSI:
3300                         if (number == 1)
3301                                 p->iscsi = true;
3302                         break;
3303                 case I40E_AQ_CAP_ID_RSS:
3304                         p->rss = true;
3305                         p->rss_table_size = number;
3306                         p->rss_table_entry_width = logical_id;
3307                         break;
3308                 case I40E_AQ_CAP_ID_RXQ:
3309                         p->num_rx_qp = number;
3310                         p->base_queue = phys_id;
3311                         break;
3312                 case I40E_AQ_CAP_ID_TXQ:
3313                         p->num_tx_qp = number;
3314                         p->base_queue = phys_id;
3315                         break;
3316                 case I40E_AQ_CAP_ID_MSIX:
3317                         p->num_msix_vectors = number;
3318                         i40e_debug(hw, I40E_DEBUG_INIT,
3319                                    "HW Capability: MSIX vector count = %d\n",
3320                                    p->num_msix_vectors);
3321                         break;
3322                 case I40E_AQ_CAP_ID_VF_MSIX:
3323                         p->num_msix_vectors_vf = number;
3324                         break;
3325                 case I40E_AQ_CAP_ID_FLEX10:
3326                         if (major_rev == 1) {
3327                                 if (number == 1) {
3328                                         p->flex10_enable = true;
3329                                         p->flex10_capable = true;
3330                                 }
3331                         } else {
3332                                 /* Capability revision >= 2 */
3333                                 if (number & 1)
3334                                         p->flex10_enable = true;
3335                                 if (number & 2)
3336                                         p->flex10_capable = true;
3337                         }
3338                         p->flex10_mode = logical_id;
3339                         p->flex10_status = phys_id;
3340                         break;
3341                 case I40E_AQ_CAP_ID_CEM:
3342                         if (number == 1)
3343                                 p->mgmt_cem = true;
3344                         break;
3345                 case I40E_AQ_CAP_ID_IWARP:
3346                         if (number == 1)
3347                                 p->iwarp = true;
3348                         break;
3349                 case I40E_AQ_CAP_ID_LED:
3350                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3351                                 p->led[phys_id] = true;
3352                         break;
3353                 case I40E_AQ_CAP_ID_SDP:
3354                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3355                                 p->sdp[phys_id] = true;
3356                         break;
3357                 case I40E_AQ_CAP_ID_MDIO:
3358                         if (number == 1) {
3359                                 p->mdio_port_num = phys_id;
3360                                 p->mdio_port_mode = logical_id;
3361                         }
3362                         break;
3363                 case I40E_AQ_CAP_ID_1588:
3364                         if (number == 1)
3365                                 p->ieee_1588 = true;
3366                         break;
3367                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3368                         p->fd = true;
3369                         p->fd_filters_guaranteed = number;
3370                         p->fd_filters_best_effort = logical_id;
3371                         break;
3372                 case I40E_AQ_CAP_ID_WSR_PROT:
3373                         p->wr_csr_prot = (u64)number;
3374                         p->wr_csr_prot |= (u64)logical_id << 32;
3375                         break;
3376                 case I40E_AQ_CAP_ID_NVM_MGMT:
3377                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3378                                 p->sec_rev_disabled = true;
3379                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3380                                 p->update_disabled = true;
3381                         break;
3382                 default:
3383                         break;
3384                 }
3385         }
3386
3387         if (p->fcoe)
3388                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3389
3390         /* Software override ensuring FCoE is disabled if npar or mfp
3391          * mode because it is not supported in these modes.
3392          */
3393         if (p->npar_enable || p->flex10_enable)
3394                 p->fcoe = false;
3395
3396         /* count the enabled ports (aka the "not disabled" ports) */
3397         hw->num_ports = 0;
3398         for (i = 0; i < 4; i++) {
3399                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3400                 u64 port_cfg = 0;
3401
3402                 /* use AQ read to get the physical register offset instead
3403                  * of the port relative offset
3404                  */
3405                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3406                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3407                         hw->num_ports++;
3408         }
3409
3410         /* OCP cards case: if a mezz is removed the Ethernet port is at
3411          * disabled state in PRTGEN_CNF register. Additional NVM read is
3412          * needed in order to check if we are dealing with OCP card.
3413          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
3414          * physical ports results in wrong partition id calculation and thus
3415          * not supporting WoL.
3416          */
3417         if (hw->mac.type == I40E_MAC_X722) {
3418                 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) {
3419                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
3420                                                   2 * I40E_SR_OCP_CFG_WORD0,
3421                                                   sizeof(ocp_cfg_word0),
3422                                                   &ocp_cfg_word0, true, NULL);
3423                         if (!status &&
3424                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
3425                                 hw->num_ports = 4;
3426                         i40e_release_nvm(hw);
3427                 }
3428         }
3429
3430         valid_functions = p->valid_functions;
3431         num_functions = 0;
3432         while (valid_functions) {
3433                 if (valid_functions & 1)
3434                         num_functions++;
3435                 valid_functions >>= 1;
3436         }
3437
3438         /* partition id is 1-based, and functions are evenly spread
3439          * across the ports as partitions
3440          */
3441         if (hw->num_ports != 0) {
3442                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3443                 hw->num_partitions = num_functions / hw->num_ports;
3444         }
3445
3446         /* additional HW specific goodies that might
3447          * someday be HW version specific
3448          */
3449         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3450 }
3451
3452 /**
3453  * i40e_aq_discover_capabilities
3454  * @hw: pointer to the hw struct
3455  * @buff: a virtual buffer to hold the capabilities
3456  * @buff_size: Size of the virtual buffer
3457  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3458  * @list_type_opc: capabilities type to discover - pass in the command opcode
3459  * @cmd_details: pointer to command details structure or NULL
3460  *
3461  * Get the device capabilities descriptions from the firmware
3462  **/
3463 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3464                                 void *buff, u16 buff_size, u16 *data_size,
3465                                 enum i40e_admin_queue_opc list_type_opc,
3466                                 struct i40e_asq_cmd_details *cmd_details)
3467 {
3468         struct i40e_aqc_list_capabilites *cmd;
3469         struct i40e_aq_desc desc;
3470         i40e_status status = 0;
3471
3472         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3473
3474         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3475                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3476                 status = I40E_ERR_PARAM;
3477                 goto exit;
3478         }
3479
3480         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3481
3482         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3483         if (buff_size > I40E_AQ_LARGE_BUF)
3484                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3485
3486         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3487         *data_size = le16_to_cpu(desc.datalen);
3488
3489         if (status)
3490                 goto exit;
3491
3492         i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3493                                          list_type_opc);
3494
3495 exit:
3496         return status;
3497 }
3498
3499 /**
3500  * i40e_aq_update_nvm
3501  * @hw: pointer to the hw struct
3502  * @module_pointer: module pointer location in words from the NVM beginning
3503  * @offset: byte offset from the module beginning
3504  * @length: length of the section to be written (in bytes from the offset)
3505  * @data: command buffer (size [bytes] = length)
3506  * @last_command: tells if this is the last command in a series
3507  * @preservation_flags: Preservation mode flags
3508  * @cmd_details: pointer to command details structure or NULL
3509  *
3510  * Update the NVM using the admin queue commands
3511  **/
3512 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3513                                u32 offset, u16 length, void *data,
3514                                 bool last_command, u8 preservation_flags,
3515                                struct i40e_asq_cmd_details *cmd_details)
3516 {
3517         struct i40e_aq_desc desc;
3518         struct i40e_aqc_nvm_update *cmd =
3519                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3520         i40e_status status;
3521
3522         /* In offset the highest byte must be zeroed. */
3523         if (offset & 0xFF000000) {
3524                 status = I40E_ERR_PARAM;
3525                 goto i40e_aq_update_nvm_exit;
3526         }
3527
3528         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3529
3530         /* If this is the last command in a series, set the proper flag. */
3531         if (last_command)
3532                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3533         if (hw->mac.type == I40E_MAC_X722) {
3534                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
3535                         cmd->command_flags |=
3536                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
3537                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3538                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
3539                         cmd->command_flags |=
3540                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
3541                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3542         }
3543         cmd->module_pointer = module_pointer;
3544         cmd->offset = cpu_to_le32(offset);
3545         cmd->length = cpu_to_le16(length);
3546
3547         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3548         if (length > I40E_AQ_LARGE_BUF)
3549                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3550
3551         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3552
3553 i40e_aq_update_nvm_exit:
3554         return status;
3555 }
3556
3557 /**
3558  * i40e_aq_rearrange_nvm
3559  * @hw: pointer to the hw struct
3560  * @rearrange_nvm: defines direction of rearrangement
3561  * @cmd_details: pointer to command details structure or NULL
3562  *
3563  * Rearrange NVM structure, available only for transition FW
3564  **/
3565 i40e_status i40e_aq_rearrange_nvm(struct i40e_hw *hw,
3566                                   u8 rearrange_nvm,
3567                                   struct i40e_asq_cmd_details *cmd_details)
3568 {
3569         struct i40e_aqc_nvm_update *cmd;
3570         i40e_status status;
3571         struct i40e_aq_desc desc;
3572
3573         cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
3574
3575         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3576
3577         rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
3578                          I40E_AQ_NVM_REARRANGE_TO_STRUCT);
3579
3580         if (!rearrange_nvm) {
3581                 status = I40E_ERR_PARAM;
3582                 goto i40e_aq_rearrange_nvm_exit;
3583         }
3584
3585         cmd->command_flags |= rearrange_nvm;
3586         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3587
3588 i40e_aq_rearrange_nvm_exit:
3589         return status;
3590 }
3591
3592 /**
3593  * i40e_aq_get_lldp_mib
3594  * @hw: pointer to the hw struct
3595  * @bridge_type: type of bridge requested
3596  * @mib_type: Local, Remote or both Local and Remote MIBs
3597  * @buff: pointer to a user supplied buffer to store the MIB block
3598  * @buff_size: size of the buffer (in bytes)
3599  * @local_len : length of the returned Local LLDP MIB
3600  * @remote_len: length of the returned Remote LLDP MIB
3601  * @cmd_details: pointer to command details structure or NULL
3602  *
3603  * Requests the complete LLDP MIB (entire packet).
3604  **/
3605 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3606                                 u8 mib_type, void *buff, u16 buff_size,
3607                                 u16 *local_len, u16 *remote_len,
3608                                 struct i40e_asq_cmd_details *cmd_details)
3609 {
3610         struct i40e_aq_desc desc;
3611         struct i40e_aqc_lldp_get_mib *cmd =
3612                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3613         struct i40e_aqc_lldp_get_mib *resp =
3614                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3615         i40e_status status;
3616
3617         if (buff_size == 0 || !buff)
3618                 return I40E_ERR_PARAM;
3619
3620         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3621         /* Indirect Command */
3622         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3623
3624         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3625         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3626                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3627
3628         desc.datalen = cpu_to_le16(buff_size);
3629
3630         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3631         if (buff_size > I40E_AQ_LARGE_BUF)
3632                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3633
3634         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3635         if (!status) {
3636                 if (local_len != NULL)
3637                         *local_len = le16_to_cpu(resp->local_len);
3638                 if (remote_len != NULL)
3639                         *remote_len = le16_to_cpu(resp->remote_len);
3640         }
3641
3642         return status;
3643 }
3644
3645 /**
3646  * i40e_aq_cfg_lldp_mib_change_event
3647  * @hw: pointer to the hw struct
3648  * @enable_update: Enable or Disable event posting
3649  * @cmd_details: pointer to command details structure or NULL
3650  *
3651  * Enable or Disable posting of an event on ARQ when LLDP MIB
3652  * associated with the interface changes
3653  **/
3654 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3655                                 bool enable_update,
3656                                 struct i40e_asq_cmd_details *cmd_details)
3657 {
3658         struct i40e_aq_desc desc;
3659         struct i40e_aqc_lldp_update_mib *cmd =
3660                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3661         i40e_status status;
3662
3663         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3664
3665         if (!enable_update)
3666                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3667
3668         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3669
3670         return status;
3671 }
3672
3673 /**
3674  * i40e_aq_restore_lldp
3675  * @hw: pointer to the hw struct
3676  * @setting: pointer to factory setting variable or NULL
3677  * @restore: True if factory settings should be restored
3678  * @cmd_details: pointer to command details structure or NULL
3679  *
3680  * Restore LLDP Agent factory settings if @restore set to True. In other case
3681  * only returns factory setting in AQ response.
3682  **/
3683 enum i40e_status_code
3684 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
3685                      struct i40e_asq_cmd_details *cmd_details)
3686 {
3687         struct i40e_aq_desc desc;
3688         struct i40e_aqc_lldp_restore *cmd =
3689                 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
3690         i40e_status status;
3691
3692         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
3693                 i40e_debug(hw, I40E_DEBUG_ALL,
3694                            "Restore LLDP not supported by current FW version.\n");
3695                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
3696         }
3697
3698         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
3699
3700         if (restore)
3701                 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
3702
3703         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3704
3705         if (setting)
3706                 *setting = cmd->command & 1;
3707
3708         return status;
3709 }
3710
3711 /**
3712  * i40e_aq_stop_lldp
3713  * @hw: pointer to the hw struct
3714  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3715  * @persist: True if stop of LLDP should be persistent across power cycles
3716  * @cmd_details: pointer to command details structure or NULL
3717  *
3718  * Stop or Shutdown the embedded LLDP Agent
3719  **/
3720 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3721                                 bool persist,
3722                                 struct i40e_asq_cmd_details *cmd_details)
3723 {
3724         struct i40e_aq_desc desc;
3725         struct i40e_aqc_lldp_stop *cmd =
3726                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3727         i40e_status status;
3728
3729         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3730
3731         if (shutdown_agent)
3732                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3733
3734         if (persist) {
3735                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
3736                         cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
3737                 else
3738                         i40e_debug(hw, I40E_DEBUG_ALL,
3739                                    "Persistent Stop LLDP not supported by current FW version.\n");
3740         }
3741
3742         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3743
3744         return status;
3745 }
3746
3747 /**
3748  * i40e_aq_start_lldp
3749  * @hw: pointer to the hw struct
3750  * @buff: buffer for result
3751  * @persist: True if start of LLDP should be persistent across power cycles
3752  * @buff_size: buffer size
3753  * @cmd_details: pointer to command details structure or NULL
3754  *
3755  * Start the embedded LLDP Agent on all ports.
3756  **/
3757 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, bool persist,
3758                                struct i40e_asq_cmd_details *cmd_details)
3759 {
3760         struct i40e_aq_desc desc;
3761         struct i40e_aqc_lldp_start *cmd =
3762                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3763         i40e_status status;
3764
3765         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3766
3767         cmd->command = I40E_AQ_LLDP_AGENT_START;
3768
3769         if (persist) {
3770                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
3771                         cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
3772                 else
3773                         i40e_debug(hw, I40E_DEBUG_ALL,
3774                                    "Persistent Start LLDP not supported by current FW version.\n");
3775         }
3776
3777         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3778
3779         return status;
3780 }
3781
3782 /**
3783  * i40e_aq_set_dcb_parameters
3784  * @hw: pointer to the hw struct
3785  * @cmd_details: pointer to command details structure or NULL
3786  * @dcb_enable: True if DCB configuration needs to be applied
3787  *
3788  **/
3789 enum i40e_status_code
3790 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
3791                            struct i40e_asq_cmd_details *cmd_details)
3792 {
3793         struct i40e_aq_desc desc;
3794         struct i40e_aqc_set_dcb_parameters *cmd =
3795                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
3796         i40e_status status;
3797
3798         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
3799                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
3800
3801         i40e_fill_default_direct_cmd_desc(&desc,
3802                                           i40e_aqc_opc_set_dcb_parameters);
3803
3804         if (dcb_enable) {
3805                 cmd->valid_flags = I40E_DCB_VALID;
3806                 cmd->command = I40E_AQ_DCB_SET_AGENT;
3807         }
3808         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3809
3810         return status;
3811 }
3812
3813 /**
3814  * i40e_aq_get_cee_dcb_config
3815  * @hw: pointer to the hw struct
3816  * @buff: response buffer that stores CEE operational configuration
3817  * @buff_size: size of the buffer passed
3818  * @cmd_details: pointer to command details structure or NULL
3819  *
3820  * Get CEE DCBX mode operational configuration from firmware
3821  **/
3822 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3823                                        void *buff, u16 buff_size,
3824                                        struct i40e_asq_cmd_details *cmd_details)
3825 {
3826         struct i40e_aq_desc desc;
3827         i40e_status status;
3828
3829         if (buff_size == 0 || !buff)
3830                 return I40E_ERR_PARAM;
3831
3832         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3833
3834         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3835         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3836                                        cmd_details);
3837
3838         return status;
3839 }
3840
3841 /**
3842  * i40e_aq_add_udp_tunnel
3843  * @hw: pointer to the hw struct
3844  * @udp_port: the UDP port to add in Host byte order
3845  * @protocol_index: protocol index type
3846  * @filter_index: pointer to filter index
3847  * @cmd_details: pointer to command details structure or NULL
3848  *
3849  * Note: Firmware expects the udp_port value to be in Little Endian format,
3850  * and this function will call cpu_to_le16 to convert from Host byte order to
3851  * Little Endian order.
3852  **/
3853 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3854                                 u16 udp_port, u8 protocol_index,
3855                                 u8 *filter_index,
3856                                 struct i40e_asq_cmd_details *cmd_details)
3857 {
3858         struct i40e_aq_desc desc;
3859         struct i40e_aqc_add_udp_tunnel *cmd =
3860                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3861         struct i40e_aqc_del_udp_tunnel_completion *resp =
3862                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3863         i40e_status status;
3864
3865         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3866
3867         cmd->udp_port = cpu_to_le16(udp_port);
3868         cmd->protocol_type = protocol_index;
3869
3870         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3871
3872         if (!status && filter_index)
3873                 *filter_index = resp->index;
3874
3875         return status;
3876 }
3877
3878 /**
3879  * i40e_aq_del_udp_tunnel
3880  * @hw: pointer to the hw struct
3881  * @index: filter index
3882  * @cmd_details: pointer to command details structure or NULL
3883  **/
3884 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3885                                 struct i40e_asq_cmd_details *cmd_details)
3886 {
3887         struct i40e_aq_desc desc;
3888         struct i40e_aqc_remove_udp_tunnel *cmd =
3889                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3890         i40e_status status;
3891
3892         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3893
3894         cmd->index = index;
3895
3896         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3897
3898         return status;
3899 }
3900
3901 /**
3902  * i40e_aq_delete_element - Delete switch element
3903  * @hw: pointer to the hw struct
3904  * @seid: the SEID to delete from the switch
3905  * @cmd_details: pointer to command details structure or NULL
3906  *
3907  * This deletes a switch element from the switch.
3908  **/
3909 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3910                                 struct i40e_asq_cmd_details *cmd_details)
3911 {
3912         struct i40e_aq_desc desc;
3913         struct i40e_aqc_switch_seid *cmd =
3914                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3915         i40e_status status;
3916
3917         if (seid == 0)
3918                 return I40E_ERR_PARAM;
3919
3920         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3921
3922         cmd->seid = cpu_to_le16(seid);
3923
3924         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3925
3926         return status;
3927 }
3928
3929 /**
3930  * i40e_aq_dcb_updated - DCB Updated Command
3931  * @hw: pointer to the hw struct
3932  * @cmd_details: pointer to command details structure or NULL
3933  *
3934  * EMP will return when the shared RPB settings have been
3935  * recomputed and modified. The retval field in the descriptor
3936  * will be set to 0 when RPB is modified.
3937  **/
3938 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3939                                 struct i40e_asq_cmd_details *cmd_details)
3940 {
3941         struct i40e_aq_desc desc;
3942         i40e_status status;
3943
3944         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3945
3946         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3947
3948         return status;
3949 }
3950
3951 /**
3952  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3953  * @hw: pointer to the hw struct
3954  * @seid: seid for the physical port/switching component/vsi
3955  * @buff: Indirect buffer to hold data parameters and response
3956  * @buff_size: Indirect buffer size
3957  * @opcode: Tx scheduler AQ command opcode
3958  * @cmd_details: pointer to command details structure or NULL
3959  *
3960  * Generic command handler for Tx scheduler AQ commands
3961  **/
3962 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3963                                 void *buff, u16 buff_size,
3964                                  enum i40e_admin_queue_opc opcode,
3965                                 struct i40e_asq_cmd_details *cmd_details)
3966 {
3967         struct i40e_aq_desc desc;
3968         struct i40e_aqc_tx_sched_ind *cmd =
3969                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3970         i40e_status status;
3971         bool cmd_param_flag = false;
3972
3973         switch (opcode) {
3974         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3975         case i40e_aqc_opc_configure_vsi_tc_bw:
3976         case i40e_aqc_opc_enable_switching_comp_ets:
3977         case i40e_aqc_opc_modify_switching_comp_ets:
3978         case i40e_aqc_opc_disable_switching_comp_ets:
3979         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3980         case i40e_aqc_opc_configure_switching_comp_bw_config:
3981                 cmd_param_flag = true;
3982                 break;
3983         case i40e_aqc_opc_query_vsi_bw_config:
3984         case i40e_aqc_opc_query_vsi_ets_sla_config:
3985         case i40e_aqc_opc_query_switching_comp_ets_config:
3986         case i40e_aqc_opc_query_port_ets_config:
3987         case i40e_aqc_opc_query_switching_comp_bw_config:
3988                 cmd_param_flag = false;
3989                 break;
3990         default:
3991                 return I40E_ERR_PARAM;
3992         }
3993
3994         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3995
3996         /* Indirect command */
3997         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3998         if (cmd_param_flag)
3999                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4000         if (buff_size > I40E_AQ_LARGE_BUF)
4001                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4002
4003         desc.datalen = cpu_to_le16(buff_size);
4004
4005         cmd->vsi_seid = cpu_to_le16(seid);
4006
4007         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4008
4009         return status;
4010 }
4011
4012 /**
4013  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4014  * @hw: pointer to the hw struct
4015  * @seid: VSI seid
4016  * @credit: BW limit credits (0 = disabled)
4017  * @max_credit: Max BW limit credits
4018  * @cmd_details: pointer to command details structure or NULL
4019  **/
4020 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4021                                 u16 seid, u16 credit, u8 max_credit,
4022                                 struct i40e_asq_cmd_details *cmd_details)
4023 {
4024         struct i40e_aq_desc desc;
4025         struct i40e_aqc_configure_vsi_bw_limit *cmd =
4026                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4027         i40e_status status;
4028
4029         i40e_fill_default_direct_cmd_desc(&desc,
4030                                           i40e_aqc_opc_configure_vsi_bw_limit);
4031
4032         cmd->vsi_seid = cpu_to_le16(seid);
4033         cmd->credit = cpu_to_le16(credit);
4034         cmd->max_credit = max_credit;
4035
4036         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4037
4038         return status;
4039 }
4040
4041 /**
4042  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4043  * @hw: pointer to the hw struct
4044  * @seid: VSI seid
4045  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4046  * @cmd_details: pointer to command details structure or NULL
4047  **/
4048 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4049                         u16 seid,
4050                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4051                         struct i40e_asq_cmd_details *cmd_details)
4052 {
4053         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4054                                     i40e_aqc_opc_configure_vsi_tc_bw,
4055                                     cmd_details);
4056 }
4057
4058 /**
4059  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4060  * @hw: pointer to the hw struct
4061  * @seid: seid of the switching component connected to Physical Port
4062  * @ets_data: Buffer holding ETS parameters
4063  * @opcode: Tx scheduler AQ command opcode
4064  * @cmd_details: pointer to command details structure or NULL
4065  **/
4066 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4067                 u16 seid,
4068                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4069                 enum i40e_admin_queue_opc opcode,
4070                 struct i40e_asq_cmd_details *cmd_details)
4071 {
4072         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4073                                     sizeof(*ets_data), opcode, cmd_details);
4074 }
4075
4076 /**
4077  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4078  * @hw: pointer to the hw struct
4079  * @seid: seid of the switching component
4080  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4081  * @cmd_details: pointer to command details structure or NULL
4082  **/
4083 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4084         u16 seid,
4085         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4086         struct i40e_asq_cmd_details *cmd_details)
4087 {
4088         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4089                             i40e_aqc_opc_configure_switching_comp_bw_config,
4090                             cmd_details);
4091 }
4092
4093 /**
4094  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4095  * @hw: pointer to the hw struct
4096  * @seid: seid of the VSI
4097  * @bw_data: Buffer to hold VSI BW configuration
4098  * @cmd_details: pointer to command details structure or NULL
4099  **/
4100 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4101                         u16 seid,
4102                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4103                         struct i40e_asq_cmd_details *cmd_details)
4104 {
4105         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4106                                     i40e_aqc_opc_query_vsi_bw_config,
4107                                     cmd_details);
4108 }
4109
4110 /**
4111  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4112  * @hw: pointer to the hw struct
4113  * @seid: seid of the VSI
4114  * @bw_data: Buffer to hold VSI BW configuration per TC
4115  * @cmd_details: pointer to command details structure or NULL
4116  **/
4117 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4118                         u16 seid,
4119                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4120                         struct i40e_asq_cmd_details *cmd_details)
4121 {
4122         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4123                                     i40e_aqc_opc_query_vsi_ets_sla_config,
4124                                     cmd_details);
4125 }
4126
4127 /**
4128  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4129  * @hw: pointer to the hw struct
4130  * @seid: seid of the switching component
4131  * @bw_data: Buffer to hold switching component's per TC BW config
4132  * @cmd_details: pointer to command details structure or NULL
4133  **/
4134 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4135                 u16 seid,
4136                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4137                 struct i40e_asq_cmd_details *cmd_details)
4138 {
4139         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4140                                    i40e_aqc_opc_query_switching_comp_ets_config,
4141                                    cmd_details);
4142 }
4143
4144 /**
4145  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4146  * @hw: pointer to the hw struct
4147  * @seid: seid of the VSI or switching component connected to Physical Port
4148  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4149  * @cmd_details: pointer to command details structure or NULL
4150  **/
4151 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4152                         u16 seid,
4153                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
4154                         struct i40e_asq_cmd_details *cmd_details)
4155 {
4156         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4157                                     i40e_aqc_opc_query_port_ets_config,
4158                                     cmd_details);
4159 }
4160
4161 /**
4162  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4163  * @hw: pointer to the hw struct
4164  * @seid: seid of the switching component
4165  * @bw_data: Buffer to hold switching component's BW configuration
4166  * @cmd_details: pointer to command details structure or NULL
4167  **/
4168 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4169                 u16 seid,
4170                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4171                 struct i40e_asq_cmd_details *cmd_details)
4172 {
4173         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4174                                     i40e_aqc_opc_query_switching_comp_bw_config,
4175                                     cmd_details);
4176 }
4177
4178 /**
4179  * i40e_validate_filter_settings
4180  * @hw: pointer to the hardware structure
4181  * @settings: Filter control settings
4182  *
4183  * Check and validate the filter control settings passed.
4184  * The function checks for the valid filter/context sizes being
4185  * passed for FCoE and PE.
4186  *
4187  * Returns 0 if the values passed are valid and within
4188  * range else returns an error.
4189  **/
4190 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
4191                                 struct i40e_filter_control_settings *settings)
4192 {
4193         u32 fcoe_cntx_size, fcoe_filt_size;
4194         u32 pe_cntx_size, pe_filt_size;
4195         u32 fcoe_fmax;
4196         u32 val;
4197
4198         /* Validate FCoE settings passed */
4199         switch (settings->fcoe_filt_num) {
4200         case I40E_HASH_FILTER_SIZE_1K:
4201         case I40E_HASH_FILTER_SIZE_2K:
4202         case I40E_HASH_FILTER_SIZE_4K:
4203         case I40E_HASH_FILTER_SIZE_8K:
4204         case I40E_HASH_FILTER_SIZE_16K:
4205         case I40E_HASH_FILTER_SIZE_32K:
4206                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4207                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4208                 break;
4209         default:
4210                 return I40E_ERR_PARAM;
4211         }
4212
4213         switch (settings->fcoe_cntx_num) {
4214         case I40E_DMA_CNTX_SIZE_512:
4215         case I40E_DMA_CNTX_SIZE_1K:
4216         case I40E_DMA_CNTX_SIZE_2K:
4217         case I40E_DMA_CNTX_SIZE_4K:
4218                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4219                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4220                 break;
4221         default:
4222                 return I40E_ERR_PARAM;
4223         }
4224
4225         /* Validate PE settings passed */
4226         switch (settings->pe_filt_num) {
4227         case I40E_HASH_FILTER_SIZE_1K:
4228         case I40E_HASH_FILTER_SIZE_2K:
4229         case I40E_HASH_FILTER_SIZE_4K:
4230         case I40E_HASH_FILTER_SIZE_8K:
4231         case I40E_HASH_FILTER_SIZE_16K:
4232         case I40E_HASH_FILTER_SIZE_32K:
4233         case I40E_HASH_FILTER_SIZE_64K:
4234         case I40E_HASH_FILTER_SIZE_128K:
4235         case I40E_HASH_FILTER_SIZE_256K:
4236         case I40E_HASH_FILTER_SIZE_512K:
4237         case I40E_HASH_FILTER_SIZE_1M:
4238                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4239                 pe_filt_size <<= (u32)settings->pe_filt_num;
4240                 break;
4241         default:
4242                 return I40E_ERR_PARAM;
4243         }
4244
4245         switch (settings->pe_cntx_num) {
4246         case I40E_DMA_CNTX_SIZE_512:
4247         case I40E_DMA_CNTX_SIZE_1K:
4248         case I40E_DMA_CNTX_SIZE_2K:
4249         case I40E_DMA_CNTX_SIZE_4K:
4250         case I40E_DMA_CNTX_SIZE_8K:
4251         case I40E_DMA_CNTX_SIZE_16K:
4252         case I40E_DMA_CNTX_SIZE_32K:
4253         case I40E_DMA_CNTX_SIZE_64K:
4254         case I40E_DMA_CNTX_SIZE_128K:
4255         case I40E_DMA_CNTX_SIZE_256K:
4256                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4257                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4258                 break;
4259         default:
4260                 return I40E_ERR_PARAM;
4261         }
4262
4263         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4264         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4265         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4266                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4267         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
4268                 return I40E_ERR_INVALID_SIZE;
4269
4270         return 0;
4271 }
4272
4273 /**
4274  * i40e_set_filter_control
4275  * @hw: pointer to the hardware structure
4276  * @settings: Filter control settings
4277  *
4278  * Set the Queue Filters for PE/FCoE and enable filters required
4279  * for a single PF. It is expected that these settings are programmed
4280  * at the driver initialization time.
4281  **/
4282 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
4283                                 struct i40e_filter_control_settings *settings)
4284 {
4285         i40e_status ret = 0;
4286         u32 hash_lut_size = 0;
4287         u32 val;
4288
4289         if (!settings)
4290                 return I40E_ERR_PARAM;
4291
4292         /* Validate the input settings */
4293         ret = i40e_validate_filter_settings(hw, settings);
4294         if (ret)
4295                 return ret;
4296
4297         /* Read the PF Queue Filter control register */
4298         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
4299
4300         /* Program required PE hash buckets for the PF */
4301         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4302         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4303                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4304         /* Program required PE contexts for the PF */
4305         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4306         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4307                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4308
4309         /* Program required FCoE hash buckets for the PF */
4310         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4311         val |= ((u32)settings->fcoe_filt_num <<
4312                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4313                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4314         /* Program required FCoE DDP contexts for the PF */
4315         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4316         val |= ((u32)settings->fcoe_cntx_num <<
4317                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4318                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4319
4320         /* Program Hash LUT size for the PF */
4321         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4322         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4323                 hash_lut_size = 1;
4324         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4325                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4326
4327         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4328         if (settings->enable_fdir)
4329                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4330         if (settings->enable_ethtype)
4331                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4332         if (settings->enable_macvlan)
4333                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4334
4335         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
4336
4337         return 0;
4338 }
4339
4340 /**
4341  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4342  * @hw: pointer to the hw struct
4343  * @mac_addr: MAC address to use in the filter
4344  * @ethtype: Ethertype to use in the filter
4345  * @flags: Flags that needs to be applied to the filter
4346  * @vsi_seid: seid of the control VSI
4347  * @queue: VSI queue number to send the packet to
4348  * @is_add: Add control packet filter if True else remove
4349  * @stats: Structure to hold information on control filter counts
4350  * @cmd_details: pointer to command details structure or NULL
4351  *
4352  * This command will Add or Remove control packet filter for a control VSI.
4353  * In return it will update the total number of perfect filter count in
4354  * the stats member.
4355  **/
4356 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4357                                 u8 *mac_addr, u16 ethtype, u16 flags,
4358                                 u16 vsi_seid, u16 queue, bool is_add,
4359                                 struct i40e_control_filter_stats *stats,
4360                                 struct i40e_asq_cmd_details *cmd_details)
4361 {
4362         struct i40e_aq_desc desc;
4363         struct i40e_aqc_add_remove_control_packet_filter *cmd =
4364                 (struct i40e_aqc_add_remove_control_packet_filter *)
4365                 &desc.params.raw;
4366         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4367                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4368                 &desc.params.raw;
4369         i40e_status status;
4370
4371         if (vsi_seid == 0)
4372                 return I40E_ERR_PARAM;
4373
4374         if (is_add) {
4375                 i40e_fill_default_direct_cmd_desc(&desc,
4376                                 i40e_aqc_opc_add_control_packet_filter);
4377                 cmd->queue = cpu_to_le16(queue);
4378         } else {
4379                 i40e_fill_default_direct_cmd_desc(&desc,
4380                                 i40e_aqc_opc_remove_control_packet_filter);
4381         }
4382
4383         if (mac_addr)
4384                 ether_addr_copy(cmd->mac, mac_addr);
4385
4386         cmd->etype = cpu_to_le16(ethtype);
4387         cmd->flags = cpu_to_le16(flags);
4388         cmd->seid = cpu_to_le16(vsi_seid);
4389
4390         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4391
4392         if (!status && stats) {
4393                 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4394                 stats->etype_used = le16_to_cpu(resp->etype_used);
4395                 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4396                 stats->etype_free = le16_to_cpu(resp->etype_free);
4397         }
4398
4399         return status;
4400 }
4401
4402 /**
4403  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4404  * @hw: pointer to the hw struct
4405  * @seid: VSI seid to add ethertype filter from
4406  **/
4407 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4408                                                     u16 seid)
4409 {
4410 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4411         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4412                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4413                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4414         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4415         i40e_status status;
4416
4417         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4418                                                        seid, 0, true, NULL,
4419                                                        NULL);
4420         if (status)
4421                 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4422 }
4423
4424 /**
4425  * i40e_aq_alternate_read
4426  * @hw: pointer to the hardware structure
4427  * @reg_addr0: address of first dword to be read
4428  * @reg_val0: pointer for data read from 'reg_addr0'
4429  * @reg_addr1: address of second dword to be read
4430  * @reg_val1: pointer for data read from 'reg_addr1'
4431  *
4432  * Read one or two dwords from alternate structure. Fields are indicated
4433  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4434  * is not passed then only register at 'reg_addr0' is read.
4435  *
4436  **/
4437 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4438                                           u32 reg_addr0, u32 *reg_val0,
4439                                           u32 reg_addr1, u32 *reg_val1)
4440 {
4441         struct i40e_aq_desc desc;
4442         struct i40e_aqc_alternate_write *cmd_resp =
4443                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4444         i40e_status status;
4445
4446         if (!reg_val0)
4447                 return I40E_ERR_PARAM;
4448
4449         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4450         cmd_resp->address0 = cpu_to_le32(reg_addr0);
4451         cmd_resp->address1 = cpu_to_le32(reg_addr1);
4452
4453         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4454
4455         if (!status) {
4456                 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4457
4458                 if (reg_val1)
4459                         *reg_val1 = le32_to_cpu(cmd_resp->data1);
4460         }
4461
4462         return status;
4463 }
4464
4465 /**
4466  * i40e_aq_resume_port_tx
4467  * @hw: pointer to the hardware structure
4468  * @cmd_details: pointer to command details structure or NULL
4469  *
4470  * Resume port's Tx traffic
4471  **/
4472 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4473                                    struct i40e_asq_cmd_details *cmd_details)
4474 {
4475         struct i40e_aq_desc desc;
4476         i40e_status status;
4477
4478         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4479
4480         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4481
4482         return status;
4483 }
4484
4485 /**
4486  * i40e_set_pci_config_data - store PCI bus info
4487  * @hw: pointer to hardware structure
4488  * @link_status: the link status word from PCI config space
4489  *
4490  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4491  **/
4492 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4493 {
4494         hw->bus.type = i40e_bus_type_pci_express;
4495
4496         switch (link_status & PCI_EXP_LNKSTA_NLW) {
4497         case PCI_EXP_LNKSTA_NLW_X1:
4498                 hw->bus.width = i40e_bus_width_pcie_x1;
4499                 break;
4500         case PCI_EXP_LNKSTA_NLW_X2:
4501                 hw->bus.width = i40e_bus_width_pcie_x2;
4502                 break;
4503         case PCI_EXP_LNKSTA_NLW_X4:
4504                 hw->bus.width = i40e_bus_width_pcie_x4;
4505                 break;
4506         case PCI_EXP_LNKSTA_NLW_X8:
4507                 hw->bus.width = i40e_bus_width_pcie_x8;
4508                 break;
4509         default:
4510                 hw->bus.width = i40e_bus_width_unknown;
4511                 break;
4512         }
4513
4514         switch (link_status & PCI_EXP_LNKSTA_CLS) {
4515         case PCI_EXP_LNKSTA_CLS_2_5GB:
4516                 hw->bus.speed = i40e_bus_speed_2500;
4517                 break;
4518         case PCI_EXP_LNKSTA_CLS_5_0GB:
4519                 hw->bus.speed = i40e_bus_speed_5000;
4520                 break;
4521         case PCI_EXP_LNKSTA_CLS_8_0GB:
4522                 hw->bus.speed = i40e_bus_speed_8000;
4523                 break;
4524         default:
4525                 hw->bus.speed = i40e_bus_speed_unknown;
4526                 break;
4527         }
4528 }
4529
4530 /**
4531  * i40e_aq_debug_dump
4532  * @hw: pointer to the hardware structure
4533  * @cluster_id: specific cluster to dump
4534  * @table_id: table id within cluster
4535  * @start_index: index of line in the block to read
4536  * @buff_size: dump buffer size
4537  * @buff: dump buffer
4538  * @ret_buff_size: actual buffer size returned
4539  * @ret_next_table: next block to read
4540  * @ret_next_index: next index to read
4541  * @cmd_details: pointer to command details structure or NULL
4542  *
4543  * Dump internal FW/HW data for debug purposes.
4544  *
4545  **/
4546 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4547                                u8 table_id, u32 start_index, u16 buff_size,
4548                                void *buff, u16 *ret_buff_size,
4549                                u8 *ret_next_table, u32 *ret_next_index,
4550                                struct i40e_asq_cmd_details *cmd_details)
4551 {
4552         struct i40e_aq_desc desc;
4553         struct i40e_aqc_debug_dump_internals *cmd =
4554                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4555         struct i40e_aqc_debug_dump_internals *resp =
4556                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4557         i40e_status status;
4558
4559         if (buff_size == 0 || !buff)
4560                 return I40E_ERR_PARAM;
4561
4562         i40e_fill_default_direct_cmd_desc(&desc,
4563                                           i40e_aqc_opc_debug_dump_internals);
4564         /* Indirect Command */
4565         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4566         if (buff_size > I40E_AQ_LARGE_BUF)
4567                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4568
4569         cmd->cluster_id = cluster_id;
4570         cmd->table_id = table_id;
4571         cmd->idx = cpu_to_le32(start_index);
4572
4573         desc.datalen = cpu_to_le16(buff_size);
4574
4575         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4576         if (!status) {
4577                 if (ret_buff_size)
4578                         *ret_buff_size = le16_to_cpu(desc.datalen);
4579                 if (ret_next_table)
4580                         *ret_next_table = resp->table_id;
4581                 if (ret_next_index)
4582                         *ret_next_index = le32_to_cpu(resp->idx);
4583         }
4584
4585         return status;
4586 }
4587
4588 /**
4589  * i40e_read_bw_from_alt_ram
4590  * @hw: pointer to the hardware structure
4591  * @max_bw: pointer for max_bw read
4592  * @min_bw: pointer for min_bw read
4593  * @min_valid: pointer for bool that is true if min_bw is a valid value
4594  * @max_valid: pointer for bool that is true if max_bw is a valid value
4595  *
4596  * Read bw from the alternate ram for the given pf
4597  **/
4598 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4599                                       u32 *max_bw, u32 *min_bw,
4600                                       bool *min_valid, bool *max_valid)
4601 {
4602         i40e_status status;
4603         u32 max_bw_addr, min_bw_addr;
4604
4605         /* Calculate the address of the min/max bw registers */
4606         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4607                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
4608                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4609         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4610                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
4611                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4612
4613         /* Read the bandwidths from alt ram */
4614         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4615                                         min_bw_addr, min_bw);
4616
4617         if (*min_bw & I40E_ALT_BW_VALID_MASK)
4618                 *min_valid = true;
4619         else
4620                 *min_valid = false;
4621
4622         if (*max_bw & I40E_ALT_BW_VALID_MASK)
4623                 *max_valid = true;
4624         else
4625                 *max_valid = false;
4626
4627         return status;
4628 }
4629
4630 /**
4631  * i40e_aq_configure_partition_bw
4632  * @hw: pointer to the hardware structure
4633  * @bw_data: Buffer holding valid pfs and bw limits
4634  * @cmd_details: pointer to command details
4635  *
4636  * Configure partitions guaranteed/max bw
4637  **/
4638 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4639                         struct i40e_aqc_configure_partition_bw_data *bw_data,
4640                         struct i40e_asq_cmd_details *cmd_details)
4641 {
4642         i40e_status status;
4643         struct i40e_aq_desc desc;
4644         u16 bwd_size = sizeof(*bw_data);
4645
4646         i40e_fill_default_direct_cmd_desc(&desc,
4647                                           i40e_aqc_opc_configure_partition_bw);
4648
4649         /* Indirect command */
4650         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4651         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4652
4653         if (bwd_size > I40E_AQ_LARGE_BUF)
4654                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4655
4656         desc.datalen = cpu_to_le16(bwd_size);
4657
4658         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4659                                        cmd_details);
4660
4661         return status;
4662 }
4663
4664 /**
4665  * i40e_read_phy_register_clause22
4666  * @hw: pointer to the HW structure
4667  * @reg: register address in the page
4668  * @phy_addr: PHY address on MDIO interface
4669  * @value: PHY register value
4670  *
4671  * Reads specified PHY register value
4672  **/
4673 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,
4674                                             u16 reg, u8 phy_addr, u16 *value)
4675 {
4676         i40e_status status = I40E_ERR_TIMEOUT;
4677         u8 port_num = (u8)hw->func_caps.mdio_port_num;
4678         u32 command = 0;
4679         u16 retry = 1000;
4680
4681         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4682                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4683                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4684                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4685                   (I40E_GLGEN_MSCA_MDICMD_MASK);
4686         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4687         do {
4688                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4689                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4690                         status = 0;
4691                         break;
4692                 }
4693                 udelay(10);
4694                 retry--;
4695         } while (retry);
4696
4697         if (status) {
4698                 i40e_debug(hw, I40E_DEBUG_PHY,
4699                            "PHY: Can't write command to external PHY.\n");
4700         } else {
4701                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4702                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4703                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4704         }
4705
4706         return status;
4707 }
4708
4709 /**
4710  * i40e_write_phy_register_clause22
4711  * @hw: pointer to the HW structure
4712  * @reg: register address in the page
4713  * @phy_addr: PHY address on MDIO interface
4714  * @value: PHY register value
4715  *
4716  * Writes specified PHY register value
4717  **/
4718 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,
4719                                              u16 reg, u8 phy_addr, u16 value)
4720 {
4721         i40e_status status = I40E_ERR_TIMEOUT;
4722         u8 port_num = (u8)hw->func_caps.mdio_port_num;
4723         u32 command  = 0;
4724         u16 retry = 1000;
4725
4726         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4727         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4728
4729         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4730                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4731                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4732                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4733                   (I40E_GLGEN_MSCA_MDICMD_MASK);
4734
4735         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4736         do {
4737                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4738                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4739                         status = 0;
4740                         break;
4741                 }
4742                 udelay(10);
4743                 retry--;
4744         } while (retry);
4745
4746         return status;
4747 }
4748
4749 /**
4750  * i40e_read_phy_register_clause45
4751  * @hw: pointer to the HW structure
4752  * @page: registers page number
4753  * @reg: register address in the page
4754  * @phy_addr: PHY address on MDIO interface
4755  * @value: PHY register value
4756  *
4757  * Reads specified PHY register value
4758  **/
4759 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
4760                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
4761 {
4762         i40e_status status = I40E_ERR_TIMEOUT;
4763         u32 command = 0;
4764         u16 retry = 1000;
4765         u8 port_num = hw->func_caps.mdio_port_num;
4766
4767         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4768                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4769                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4770                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4771                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4772                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4773                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4774         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4775         do {
4776                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4777                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4778                         status = 0;
4779                         break;
4780                 }
4781                 usleep_range(10, 20);
4782                 retry--;
4783         } while (retry);
4784
4785         if (status) {
4786                 i40e_debug(hw, I40E_DEBUG_PHY,
4787                            "PHY: Can't write command to external PHY.\n");
4788                 goto phy_read_end;
4789         }
4790
4791         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4792                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4793                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4794                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4795                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4796                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4797         status = I40E_ERR_TIMEOUT;
4798         retry = 1000;
4799         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4800         do {
4801                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4802                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4803                         status = 0;
4804                         break;
4805                 }
4806                 usleep_range(10, 20);
4807                 retry--;
4808         } while (retry);
4809
4810         if (!status) {
4811                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4812                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4813                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4814         } else {
4815                 i40e_debug(hw, I40E_DEBUG_PHY,
4816                            "PHY: Can't read register value from external PHY.\n");
4817         }
4818
4819 phy_read_end:
4820         return status;
4821 }
4822
4823 /**
4824  * i40e_write_phy_register_clause45
4825  * @hw: pointer to the HW structure
4826  * @page: registers page number
4827  * @reg: register address in the page
4828  * @phy_addr: PHY address on MDIO interface
4829  * @value: PHY register value
4830  *
4831  * Writes value to specified PHY register
4832  **/
4833 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
4834                                 u8 page, u16 reg, u8 phy_addr, u16 value)
4835 {
4836         i40e_status status = I40E_ERR_TIMEOUT;
4837         u32 command = 0;
4838         u16 retry = 1000;
4839         u8 port_num = hw->func_caps.mdio_port_num;
4840
4841         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4842                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4843                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4844                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4845                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4846                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4847                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4848         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4849         do {
4850                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4851                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4852                         status = 0;
4853                         break;
4854                 }
4855                 usleep_range(10, 20);
4856                 retry--;
4857         } while (retry);
4858         if (status) {
4859                 i40e_debug(hw, I40E_DEBUG_PHY,
4860                            "PHY: Can't write command to external PHY.\n");
4861                 goto phy_write_end;
4862         }
4863
4864         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4865         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4866
4867         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4868                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4869                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4870                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4871                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4872                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4873         status = I40E_ERR_TIMEOUT;
4874         retry = 1000;
4875         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4876         do {
4877                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4878                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4879                         status = 0;
4880                         break;
4881                 }
4882                 usleep_range(10, 20);
4883                 retry--;
4884         } while (retry);
4885
4886 phy_write_end:
4887         return status;
4888 }
4889
4890 /**
4891  * i40e_write_phy_register
4892  * @hw: pointer to the HW structure
4893  * @page: registers page number
4894  * @reg: register address in the page
4895  * @phy_addr: PHY address on MDIO interface
4896  * @value: PHY register value
4897  *
4898  * Writes value to specified PHY register
4899  **/
4900 i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4901                                     u8 page, u16 reg, u8 phy_addr, u16 value)
4902 {
4903         i40e_status status;
4904
4905         switch (hw->device_id) {
4906         case I40E_DEV_ID_1G_BASE_T_X722:
4907                 status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
4908                                                           value);
4909                 break;
4910         case I40E_DEV_ID_5G_BASE_T_BC:
4911         case I40E_DEV_ID_10G_BASE_T:
4912         case I40E_DEV_ID_10G_BASE_T4:
4913         case I40E_DEV_ID_10G_BASE_T_BC:
4914         case I40E_DEV_ID_10G_BASE_T_X722:
4915         case I40E_DEV_ID_25G_B:
4916         case I40E_DEV_ID_25G_SFP28:
4917                 status = i40e_write_phy_register_clause45(hw, page, reg,
4918                                                           phy_addr, value);
4919                 break;
4920         default:
4921                 status = I40E_ERR_UNKNOWN_PHY;
4922                 break;
4923         }
4924
4925         return status;
4926 }
4927
4928 /**
4929  * i40e_read_phy_register
4930  * @hw: pointer to the HW structure
4931  * @page: registers page number
4932  * @reg: register address in the page
4933  * @phy_addr: PHY address on MDIO interface
4934  * @value: PHY register value
4935  *
4936  * Reads specified PHY register value
4937  **/
4938 i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4939                                    u8 page, u16 reg, u8 phy_addr, u16 *value)
4940 {
4941         i40e_status status;
4942
4943         switch (hw->device_id) {
4944         case I40E_DEV_ID_1G_BASE_T_X722:
4945                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
4946                                                          value);
4947                 break;
4948         case I40E_DEV_ID_5G_BASE_T_BC:
4949         case I40E_DEV_ID_10G_BASE_T:
4950         case I40E_DEV_ID_10G_BASE_T4:
4951         case I40E_DEV_ID_10G_BASE_T_BC:
4952         case I40E_DEV_ID_10G_BASE_T_X722:
4953         case I40E_DEV_ID_25G_B:
4954         case I40E_DEV_ID_25G_SFP28:
4955                 status = i40e_read_phy_register_clause45(hw, page, reg,
4956                                                          phy_addr, value);
4957                 break;
4958         default:
4959                 status = I40E_ERR_UNKNOWN_PHY;
4960                 break;
4961         }
4962
4963         return status;
4964 }
4965
4966 /**
4967  * i40e_get_phy_address
4968  * @hw: pointer to the HW structure
4969  * @dev_num: PHY port num that address we want
4970  *
4971  * Gets PHY address for current port
4972  **/
4973 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4974 {
4975         u8 port_num = hw->func_caps.mdio_port_num;
4976         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4977
4978         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4979 }
4980
4981 /**
4982  * i40e_blink_phy_led
4983  * @hw: pointer to the HW structure
4984  * @time: time how long led will blinks in secs
4985  * @interval: gap between LED on and off in msecs
4986  *
4987  * Blinks PHY link LED
4988  **/
4989 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4990                                     u32 time, u32 interval)
4991 {
4992         i40e_status status = 0;
4993         u32 i;
4994         u16 led_ctl;
4995         u16 gpio_led_port;
4996         u16 led_reg;
4997         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4998         u8 phy_addr = 0;
4999         u8 port_num;
5000
5001         i = rd32(hw, I40E_PFGEN_PORTNUM);
5002         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5003         phy_addr = i40e_get_phy_address(hw, port_num);
5004
5005         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
5006              led_addr++) {
5007                 status = i40e_read_phy_register_clause45(hw,
5008                                                          I40E_PHY_COM_REG_PAGE,
5009                                                          led_addr, phy_addr,
5010                                                          &led_reg);
5011                 if (status)
5012                         goto phy_blinking_end;
5013                 led_ctl = led_reg;
5014                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
5015                         led_reg = 0;
5016                         status = i40e_write_phy_register_clause45(hw,
5017                                                          I40E_PHY_COM_REG_PAGE,
5018                                                          led_addr, phy_addr,
5019                                                          led_reg);
5020                         if (status)
5021                                 goto phy_blinking_end;
5022                         break;
5023                 }
5024         }
5025
5026         if (time > 0 && interval > 0) {
5027                 for (i = 0; i < time * 1000; i += interval) {
5028                         status = i40e_read_phy_register_clause45(hw,
5029                                                 I40E_PHY_COM_REG_PAGE,
5030                                                 led_addr, phy_addr, &led_reg);
5031                         if (status)
5032                                 goto restore_config;
5033                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
5034                                 led_reg = 0;
5035                         else
5036                                 led_reg = I40E_PHY_LED_MANUAL_ON;
5037                         status = i40e_write_phy_register_clause45(hw,
5038                                                 I40E_PHY_COM_REG_PAGE,
5039                                                 led_addr, phy_addr, led_reg);
5040                         if (status)
5041                                 goto restore_config;
5042                         msleep(interval);
5043                 }
5044         }
5045
5046 restore_config:
5047         status = i40e_write_phy_register_clause45(hw,
5048                                                   I40E_PHY_COM_REG_PAGE,
5049                                                   led_addr, phy_addr, led_ctl);
5050
5051 phy_blinking_end:
5052         return status;
5053 }
5054
5055 /**
5056  * i40e_led_get_reg - read LED register
5057  * @hw: pointer to the HW structure
5058  * @led_addr: LED register address
5059  * @reg_val: read register value
5060  **/
5061 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
5062                                               u32 *reg_val)
5063 {
5064         enum i40e_status_code status;
5065         u8 phy_addr = 0;
5066         u8 port_num;
5067         u32 i;
5068
5069         *reg_val = 0;
5070         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5071                 status =
5072                        i40e_aq_get_phy_register(hw,
5073                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5074                                                 I40E_PHY_COM_REG_PAGE, true,
5075                                                 I40E_PHY_LED_PROV_REG_1,
5076                                                 reg_val, NULL);
5077         } else {
5078                 i = rd32(hw, I40E_PFGEN_PORTNUM);
5079                 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5080                 phy_addr = i40e_get_phy_address(hw, port_num);
5081                 status = i40e_read_phy_register_clause45(hw,
5082                                                          I40E_PHY_COM_REG_PAGE,
5083                                                          led_addr, phy_addr,
5084                                                          (u16 *)reg_val);
5085         }
5086         return status;
5087 }
5088
5089 /**
5090  * i40e_led_set_reg - write LED register
5091  * @hw: pointer to the HW structure
5092  * @led_addr: LED register address
5093  * @reg_val: register value to write
5094  **/
5095 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
5096                                               u32 reg_val)
5097 {
5098         enum i40e_status_code status;
5099         u8 phy_addr = 0;
5100         u8 port_num;
5101         u32 i;
5102
5103         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5104                 status =
5105                        i40e_aq_set_phy_register(hw,
5106                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5107                                                 I40E_PHY_COM_REG_PAGE, true,
5108                                                 I40E_PHY_LED_PROV_REG_1,
5109                                                 reg_val, NULL);
5110         } else {
5111                 i = rd32(hw, I40E_PFGEN_PORTNUM);
5112                 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5113                 phy_addr = i40e_get_phy_address(hw, port_num);
5114                 status = i40e_write_phy_register_clause45(hw,
5115                                                           I40E_PHY_COM_REG_PAGE,
5116                                                           led_addr, phy_addr,
5117                                                           (u16)reg_val);
5118         }
5119
5120         return status;
5121 }
5122
5123 /**
5124  * i40e_led_get_phy - return current on/off mode
5125  * @hw: pointer to the hw struct
5126  * @led_addr: address of led register to use
5127  * @val: original value of register to use
5128  *
5129  **/
5130 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
5131                              u16 *val)
5132 {
5133         i40e_status status = 0;
5134         u16 gpio_led_port;
5135         u8 phy_addr = 0;
5136         u16 reg_val;
5137         u16 temp_addr;
5138         u8 port_num;
5139         u32 i;
5140         u32 reg_val_aq;
5141
5142         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5143                 status =
5144                       i40e_aq_get_phy_register(hw,
5145                                                I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5146                                                I40E_PHY_COM_REG_PAGE, true,
5147                                                I40E_PHY_LED_PROV_REG_1,
5148                                                &reg_val_aq, NULL);
5149                 if (status == I40E_SUCCESS)
5150                         *val = (u16)reg_val_aq;
5151                 return status;
5152         }
5153         temp_addr = I40E_PHY_LED_PROV_REG_1;
5154         i = rd32(hw, I40E_PFGEN_PORTNUM);
5155         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5156         phy_addr = i40e_get_phy_address(hw, port_num);
5157
5158         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
5159              temp_addr++) {
5160                 status = i40e_read_phy_register_clause45(hw,
5161                                                          I40E_PHY_COM_REG_PAGE,
5162                                                          temp_addr, phy_addr,
5163                                                          &reg_val);
5164                 if (status)
5165                         return status;
5166                 *val = reg_val;
5167                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
5168                         *led_addr = temp_addr;
5169                         break;
5170                 }
5171         }
5172         return status;
5173 }
5174
5175 /**
5176  * i40e_led_set_phy
5177  * @hw: pointer to the HW structure
5178  * @on: true or false
5179  * @led_addr: address of led register to use
5180  * @mode: original val plus bit for set or ignore
5181  *
5182  * Set led's on or off when controlled by the PHY
5183  *
5184  **/
5185 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
5186                              u16 led_addr, u32 mode)
5187 {
5188         i40e_status status = 0;
5189         u32 led_ctl = 0;
5190         u32 led_reg = 0;
5191
5192         status = i40e_led_get_reg(hw, led_addr, &led_reg);
5193         if (status)
5194                 return status;
5195         led_ctl = led_reg;
5196         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
5197                 led_reg = 0;
5198                 status = i40e_led_set_reg(hw, led_addr, led_reg);
5199                 if (status)
5200                         return status;
5201         }
5202         status = i40e_led_get_reg(hw, led_addr, &led_reg);
5203         if (status)
5204                 goto restore_config;
5205         if (on)
5206                 led_reg = I40E_PHY_LED_MANUAL_ON;
5207         else
5208                 led_reg = 0;
5209
5210         status = i40e_led_set_reg(hw, led_addr, led_reg);
5211         if (status)
5212                 goto restore_config;
5213         if (mode & I40E_PHY_LED_MODE_ORIG) {
5214                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
5215                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
5216         }
5217         return status;
5218
5219 restore_config:
5220         status = i40e_led_set_reg(hw, led_addr, led_ctl);
5221         return status;
5222 }
5223
5224 /**
5225  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
5226  * @hw: pointer to the hw struct
5227  * @reg_addr: register address
5228  * @reg_val: ptr to register value
5229  * @cmd_details: pointer to command details structure or NULL
5230  *
5231  * Use the firmware to read the Rx control register,
5232  * especially useful if the Rx unit is under heavy pressure
5233  **/
5234 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
5235                                 u32 reg_addr, u32 *reg_val,
5236                                 struct i40e_asq_cmd_details *cmd_details)
5237 {
5238         struct i40e_aq_desc desc;
5239         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
5240                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5241         i40e_status status;
5242
5243         if (!reg_val)
5244                 return I40E_ERR_PARAM;
5245
5246         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
5247
5248         cmd_resp->address = cpu_to_le32(reg_addr);
5249
5250         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5251
5252         if (status == 0)
5253                 *reg_val = le32_to_cpu(cmd_resp->value);
5254
5255         return status;
5256 }
5257
5258 /**
5259  * i40e_read_rx_ctl - read from an Rx control register
5260  * @hw: pointer to the hw struct
5261  * @reg_addr: register address
5262  **/
5263 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
5264 {
5265         i40e_status status = 0;
5266         bool use_register;
5267         int retry = 5;
5268         u32 val = 0;
5269
5270         use_register = (((hw->aq.api_maj_ver == 1) &&
5271                         (hw->aq.api_min_ver < 5)) ||
5272                         (hw->mac.type == I40E_MAC_X722));
5273         if (!use_register) {
5274 do_retry:
5275                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
5276                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5277                         usleep_range(1000, 2000);
5278                         retry--;
5279                         goto do_retry;
5280                 }
5281         }
5282
5283         /* if the AQ access failed, try the old-fashioned way */
5284         if (status || use_register)
5285                 val = rd32(hw, reg_addr);
5286
5287         return val;
5288 }
5289
5290 /**
5291  * i40e_aq_rx_ctl_write_register
5292  * @hw: pointer to the hw struct
5293  * @reg_addr: register address
5294  * @reg_val: register value
5295  * @cmd_details: pointer to command details structure or NULL
5296  *
5297  * Use the firmware to write to an Rx control register,
5298  * especially useful if the Rx unit is under heavy pressure
5299  **/
5300 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
5301                                 u32 reg_addr, u32 reg_val,
5302                                 struct i40e_asq_cmd_details *cmd_details)
5303 {
5304         struct i40e_aq_desc desc;
5305         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
5306                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5307         i40e_status status;
5308
5309         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
5310
5311         cmd->address = cpu_to_le32(reg_addr);
5312         cmd->value = cpu_to_le32(reg_val);
5313
5314         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5315
5316         return status;
5317 }
5318
5319 /**
5320  * i40e_write_rx_ctl - write to an Rx control register
5321  * @hw: pointer to the hw struct
5322  * @reg_addr: register address
5323  * @reg_val: register value
5324  **/
5325 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
5326 {
5327         i40e_status status = 0;
5328         bool use_register;
5329         int retry = 5;
5330
5331         use_register = (((hw->aq.api_maj_ver == 1) &&
5332                         (hw->aq.api_min_ver < 5)) ||
5333                         (hw->mac.type == I40E_MAC_X722));
5334         if (!use_register) {
5335 do_retry:
5336                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
5337                                                        reg_val, NULL);
5338                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5339                         usleep_range(1000, 2000);
5340                         retry--;
5341                         goto do_retry;
5342                 }
5343         }
5344
5345         /* if the AQ access failed, try the old-fashioned way */
5346         if (status || use_register)
5347                 wr32(hw, reg_addr, reg_val);
5348 }
5349
5350 /**
5351  * i40e_mdio_if_number_selection - MDIO I/F number selection
5352  * @hw: pointer to the hw struct
5353  * @set_mdio: use MDIO I/F number specified by mdio_num
5354  * @mdio_num: MDIO I/F number
5355  * @cmd: pointer to PHY Register command structure
5356  **/
5357 static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio,
5358                                           u8 mdio_num,
5359                                           struct i40e_aqc_phy_register_access *cmd)
5360 {
5361         if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
5362                 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
5363                         cmd->cmd_flags |=
5364                                 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
5365                                 ((mdio_num <<
5366                                 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
5367                                 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
5368                 else
5369                         i40e_debug(hw, I40E_DEBUG_PHY,
5370                                    "MDIO I/F number selection not supported by current FW version.\n");
5371         }
5372 }
5373
5374 /**
5375  * i40e_aq_set_phy_register_ext
5376  * @hw: pointer to the hw struct
5377  * @phy_select: select which phy should be accessed
5378  * @dev_addr: PHY device address
5379  * @set_mdio: use MDIO I/F number specified by mdio_num
5380  * @mdio_num: MDIO I/F number
5381  * @reg_addr: PHY register address
5382  * @reg_val: new register value
5383  * @cmd_details: pointer to command details structure or NULL
5384  *
5385  * Write the external PHY register.
5386  * NOTE: In common cases MDIO I/F number should not be changed, thats why you
5387  * may use simple wrapper i40e_aq_set_phy_register.
5388  **/
5389 enum i40e_status_code i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
5390                              u8 phy_select, u8 dev_addr, bool page_change,
5391                              bool set_mdio, u8 mdio_num,
5392                              u32 reg_addr, u32 reg_val,
5393                              struct i40e_asq_cmd_details *cmd_details)
5394 {
5395         struct i40e_aq_desc desc;
5396         struct i40e_aqc_phy_register_access *cmd =
5397                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5398         i40e_status status;
5399
5400         i40e_fill_default_direct_cmd_desc(&desc,
5401                                           i40e_aqc_opc_set_phy_register);
5402
5403         cmd->phy_interface = phy_select;
5404         cmd->dev_address = dev_addr;
5405         cmd->reg_address = cpu_to_le32(reg_addr);
5406         cmd->reg_value = cpu_to_le32(reg_val);
5407
5408         i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5409
5410         if (!page_change)
5411                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5412
5413         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5414
5415         return status;
5416 }
5417
5418 /**
5419  * i40e_aq_get_phy_register_ext
5420  * @hw: pointer to the hw struct
5421  * @phy_select: select which phy should be accessed
5422  * @dev_addr: PHY device address
5423  * @set_mdio: use MDIO I/F number specified by mdio_num
5424  * @mdio_num: MDIO I/F number
5425  * @reg_addr: PHY register address
5426  * @reg_val: read register value
5427  * @cmd_details: pointer to command details structure or NULL
5428  *
5429  * Read the external PHY register.
5430  * NOTE: In common cases MDIO I/F number should not be changed, thats why you
5431  * may use simple wrapper i40e_aq_get_phy_register.
5432  **/
5433 enum i40e_status_code i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
5434                              u8 phy_select, u8 dev_addr, bool page_change,
5435                              bool set_mdio, u8 mdio_num,
5436                              u32 reg_addr, u32 *reg_val,
5437                              struct i40e_asq_cmd_details *cmd_details)
5438 {
5439         struct i40e_aq_desc desc;
5440         struct i40e_aqc_phy_register_access *cmd =
5441                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5442         i40e_status status;
5443
5444         i40e_fill_default_direct_cmd_desc(&desc,
5445                                           i40e_aqc_opc_get_phy_register);
5446
5447         cmd->phy_interface = phy_select;
5448         cmd->dev_address = dev_addr;
5449         cmd->reg_address = cpu_to_le32(reg_addr);
5450
5451         i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5452
5453         if (!page_change)
5454                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5455
5456         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5457         if (!status)
5458                 *reg_val = le32_to_cpu(cmd->reg_value);
5459
5460         return status;
5461 }
5462
5463 /**
5464  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
5465  * @hw: pointer to the hw struct
5466  * @buff: command buffer (size in bytes = buff_size)
5467  * @buff_size: buffer size in bytes
5468  * @track_id: package tracking id
5469  * @error_offset: returns error offset
5470  * @error_info: returns error information
5471  * @cmd_details: pointer to command details structure or NULL
5472  **/
5473 enum
5474 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
5475                                    u16 buff_size, u32 track_id,
5476                                    u32 *error_offset, u32 *error_info,
5477                                    struct i40e_asq_cmd_details *cmd_details)
5478 {
5479         struct i40e_aq_desc desc;
5480         struct i40e_aqc_write_personalization_profile *cmd =
5481                 (struct i40e_aqc_write_personalization_profile *)
5482                 &desc.params.raw;
5483         struct i40e_aqc_write_ddp_resp *resp;
5484         i40e_status status;
5485
5486         i40e_fill_default_direct_cmd_desc(&desc,
5487                                           i40e_aqc_opc_write_personalization_profile);
5488
5489         desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
5490         if (buff_size > I40E_AQ_LARGE_BUF)
5491                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5492
5493         desc.datalen = cpu_to_le16(buff_size);
5494
5495         cmd->profile_track_id = cpu_to_le32(track_id);
5496
5497         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5498         if (!status) {
5499                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
5500                 if (error_offset)
5501                         *error_offset = le32_to_cpu(resp->error_offset);
5502                 if (error_info)
5503                         *error_info = le32_to_cpu(resp->error_info);
5504         }
5505
5506         return status;
5507 }
5508
5509 /**
5510  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
5511  * @hw: pointer to the hw struct
5512  * @buff: command buffer (size in bytes = buff_size)
5513  * @buff_size: buffer size in bytes
5514  * @flags: AdminQ command flags
5515  * @cmd_details: pointer to command details structure or NULL
5516  **/
5517 enum
5518 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
5519                                       u16 buff_size, u8 flags,
5520                                       struct i40e_asq_cmd_details *cmd_details)
5521 {
5522         struct i40e_aq_desc desc;
5523         struct i40e_aqc_get_applied_profiles *cmd =
5524                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
5525         i40e_status status;
5526
5527         i40e_fill_default_direct_cmd_desc(&desc,
5528                                           i40e_aqc_opc_get_personalization_profile_list);
5529
5530         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
5531         if (buff_size > I40E_AQ_LARGE_BUF)
5532                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5533         desc.datalen = cpu_to_le16(buff_size);
5534
5535         cmd->flags = flags;
5536
5537         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5538
5539         return status;
5540 }
5541
5542 /**
5543  * i40e_find_segment_in_package
5544  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
5545  * @pkg_hdr: pointer to the package header to be searched
5546  *
5547  * This function searches a package file for a particular segment type. On
5548  * success it returns a pointer to the segment header, otherwise it will
5549  * return NULL.
5550  **/
5551 struct i40e_generic_seg_header *
5552 i40e_find_segment_in_package(u32 segment_type,
5553                              struct i40e_package_header *pkg_hdr)
5554 {
5555         struct i40e_generic_seg_header *segment;
5556         u32 i;
5557
5558         /* Search all package segments for the requested segment type */
5559         for (i = 0; i < pkg_hdr->segment_count; i++) {
5560                 segment =
5561                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
5562                          pkg_hdr->segment_offset[i]);
5563
5564                 if (segment->type == segment_type)
5565                         return segment;
5566         }
5567
5568         return NULL;
5569 }
5570
5571 /* Get section table in profile */
5572 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
5573         do {                                                            \
5574                 struct i40e_profile_segment *p = (profile);             \
5575                 u32 count;                                              \
5576                 u32 *nvm;                                               \
5577                 count = p->device_table_count;                          \
5578                 nvm = (u32 *)&p->device_table[count];                   \
5579                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
5580         } while (0)
5581
5582 /* Get section header in profile */
5583 #define I40E_SECTION_HEADER(profile, offset)                            \
5584         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
5585
5586 /**
5587  * i40e_find_section_in_profile
5588  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
5589  * @profile: pointer to the i40e segment header to be searched
5590  *
5591  * This function searches i40e segment for a particular section type. On
5592  * success it returns a pointer to the section header, otherwise it will
5593  * return NULL.
5594  **/
5595 struct i40e_profile_section_header *
5596 i40e_find_section_in_profile(u32 section_type,
5597                              struct i40e_profile_segment *profile)
5598 {
5599         struct i40e_profile_section_header *sec;
5600         struct i40e_section_table *sec_tbl;
5601         u32 sec_off;
5602         u32 i;
5603
5604         if (profile->header.type != SEGMENT_TYPE_I40E)
5605                 return NULL;
5606
5607         I40E_SECTION_TABLE(profile, sec_tbl);
5608
5609         for (i = 0; i < sec_tbl->section_count; i++) {
5610                 sec_off = sec_tbl->section_offset[i];
5611                 sec = I40E_SECTION_HEADER(profile, sec_off);
5612                 if (sec->section.type == section_type)
5613                         return sec;
5614         }
5615
5616         return NULL;
5617 }
5618
5619 /**
5620  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
5621  * @hw: pointer to the hw struct
5622  * @aq: command buffer containing all data to execute AQ
5623  **/
5624 static enum
5625 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
5626                                           struct i40e_profile_aq_section *aq)
5627 {
5628         i40e_status status;
5629         struct i40e_aq_desc desc;
5630         u8 *msg = NULL;
5631         u16 msglen;
5632
5633         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
5634         desc.flags |= cpu_to_le16(aq->flags);
5635         memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw));
5636
5637         msglen = aq->datalen;
5638         if (msglen) {
5639                 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
5640                                                 I40E_AQ_FLAG_RD));
5641                 if (msglen > I40E_AQ_LARGE_BUF)
5642                         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5643                 desc.datalen = cpu_to_le16(msglen);
5644                 msg = &aq->data[0];
5645         }
5646
5647         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
5648
5649         if (status) {
5650                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5651                            "unable to exec DDP AQ opcode %u, error %d\n",
5652                            aq->opcode, status);
5653                 return status;
5654         }
5655
5656         /* copy returned desc to aq_buf */
5657         memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw));
5658
5659         return 0;
5660 }
5661
5662 /**
5663  * i40e_validate_profile
5664  * @hw: pointer to the hardware structure
5665  * @profile: pointer to the profile segment of the package to be validated
5666  * @track_id: package tracking id
5667  * @rollback: flag if the profile is for rollback.
5668  *
5669  * Validates supported devices and profile's sections.
5670  */
5671 static enum i40e_status_code
5672 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5673                       u32 track_id, bool rollback)
5674 {
5675         struct i40e_profile_section_header *sec = NULL;
5676         i40e_status status = 0;
5677         struct i40e_section_table *sec_tbl;
5678         u32 vendor_dev_id;
5679         u32 dev_cnt;
5680         u32 sec_off;
5681         u32 i;
5682
5683         if (track_id == I40E_DDP_TRACKID_INVALID) {
5684                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
5685                 return I40E_NOT_SUPPORTED;
5686         }
5687
5688         dev_cnt = profile->device_table_count;
5689         for (i = 0; i < dev_cnt; i++) {
5690                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
5691                 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL &&
5692                     hw->device_id == (vendor_dev_id & 0xFFFF))
5693                         break;
5694         }
5695         if (dev_cnt && i == dev_cnt) {
5696                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5697                            "Device doesn't support DDP\n");
5698                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5699         }
5700
5701         I40E_SECTION_TABLE(profile, sec_tbl);
5702
5703         /* Validate sections types */
5704         for (i = 0; i < sec_tbl->section_count; i++) {
5705                 sec_off = sec_tbl->section_offset[i];
5706                 sec = I40E_SECTION_HEADER(profile, sec_off);
5707                 if (rollback) {
5708                         if (sec->section.type == SECTION_TYPE_MMIO ||
5709                             sec->section.type == SECTION_TYPE_AQ ||
5710                             sec->section.type == SECTION_TYPE_RB_AQ) {
5711                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5712                                            "Not a roll-back package\n");
5713                                 return I40E_NOT_SUPPORTED;
5714                         }
5715                 } else {
5716                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
5717                             sec->section.type == SECTION_TYPE_RB_MMIO) {
5718                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5719                                            "Not an original package\n");
5720                                 return I40E_NOT_SUPPORTED;
5721                         }
5722                 }
5723         }
5724
5725         return status;
5726 }
5727
5728 /**
5729  * i40e_write_profile
5730  * @hw: pointer to the hardware structure
5731  * @profile: pointer to the profile segment of the package to be downloaded
5732  * @track_id: package tracking id
5733  *
5734  * Handles the download of a complete package.
5735  */
5736 enum i40e_status_code
5737 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5738                    u32 track_id)
5739 {
5740         i40e_status status = 0;
5741         struct i40e_section_table *sec_tbl;
5742         struct i40e_profile_section_header *sec = NULL;
5743         struct i40e_profile_aq_section *ddp_aq;
5744         u32 section_size = 0;
5745         u32 offset = 0, info = 0;
5746         u32 sec_off;
5747         u32 i;
5748
5749         status = i40e_validate_profile(hw, profile, track_id, false);
5750         if (status)
5751                 return status;
5752
5753         I40E_SECTION_TABLE(profile, sec_tbl);
5754
5755         for (i = 0; i < sec_tbl->section_count; i++) {
5756                 sec_off = sec_tbl->section_offset[i];
5757                 sec = I40E_SECTION_HEADER(profile, sec_off);
5758                 /* Process generic admin command */
5759                 if (sec->section.type == SECTION_TYPE_AQ) {
5760                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
5761                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
5762                         if (status) {
5763                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5764                                            "Failed to execute aq: section %d, opcode %u\n",
5765                                            i, ddp_aq->opcode);
5766                                 break;
5767                         }
5768                         sec->section.type = SECTION_TYPE_RB_AQ;
5769                 }
5770
5771                 /* Skip any non-mmio sections */
5772                 if (sec->section.type != SECTION_TYPE_MMIO)
5773                         continue;
5774
5775                 section_size = sec->section.size +
5776                         sizeof(struct i40e_profile_section_header);
5777
5778                 /* Write MMIO section */
5779                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5780                                            track_id, &offset, &info, NULL);
5781                 if (status) {
5782                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
5783                                    "Failed to write profile: section %d, offset %d, info %d\n",
5784                                    i, offset, info);
5785                         break;
5786                 }
5787         }
5788         return status;
5789 }
5790
5791 /**
5792  * i40e_rollback_profile
5793  * @hw: pointer to the hardware structure
5794  * @profile: pointer to the profile segment of the package to be removed
5795  * @track_id: package tracking id
5796  *
5797  * Rolls back previously loaded package.
5798  */
5799 enum i40e_status_code
5800 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5801                       u32 track_id)
5802 {
5803         struct i40e_profile_section_header *sec = NULL;
5804         i40e_status status = 0;
5805         struct i40e_section_table *sec_tbl;
5806         u32 offset = 0, info = 0;
5807         u32 section_size = 0;
5808         u32 sec_off;
5809         int i;
5810
5811         status = i40e_validate_profile(hw, profile, track_id, true);
5812         if (status)
5813                 return status;
5814
5815         I40E_SECTION_TABLE(profile, sec_tbl);
5816
5817         /* For rollback write sections in reverse */
5818         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
5819                 sec_off = sec_tbl->section_offset[i];
5820                 sec = I40E_SECTION_HEADER(profile, sec_off);
5821
5822                 /* Skip any non-rollback sections */
5823                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
5824                         continue;
5825
5826                 section_size = sec->section.size +
5827                         sizeof(struct i40e_profile_section_header);
5828
5829                 /* Write roll-back MMIO section */
5830                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5831                                            track_id, &offset, &info, NULL);
5832                 if (status) {
5833                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
5834                                    "Failed to write profile: section %d, offset %d, info %d\n",
5835                                    i, offset, info);
5836                         break;
5837                 }
5838         }
5839         return status;
5840 }
5841
5842 /**
5843  * i40e_add_pinfo_to_list
5844  * @hw: pointer to the hardware structure
5845  * @profile: pointer to the profile segment of the package
5846  * @profile_info_sec: buffer for information section
5847  * @track_id: package tracking id
5848  *
5849  * Register a profile to the list of loaded profiles.
5850  */
5851 enum i40e_status_code
5852 i40e_add_pinfo_to_list(struct i40e_hw *hw,
5853                        struct i40e_profile_segment *profile,
5854                        u8 *profile_info_sec, u32 track_id)
5855 {
5856         i40e_status status = 0;
5857         struct i40e_profile_section_header *sec = NULL;
5858         struct i40e_profile_info *pinfo;
5859         u32 offset = 0, info = 0;
5860
5861         sec = (struct i40e_profile_section_header *)profile_info_sec;
5862         sec->tbl_size = 1;
5863         sec->data_end = sizeof(struct i40e_profile_section_header) +
5864                         sizeof(struct i40e_profile_info);
5865         sec->section.type = SECTION_TYPE_INFO;
5866         sec->section.offset = sizeof(struct i40e_profile_section_header);
5867         sec->section.size = sizeof(struct i40e_profile_info);
5868         pinfo = (struct i40e_profile_info *)(profile_info_sec +
5869                                              sec->section.offset);
5870         pinfo->track_id = track_id;
5871         pinfo->version = profile->version;
5872         pinfo->op = I40E_DDP_ADD_TRACKID;
5873         memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
5874
5875         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
5876                                    track_id, &offset, &info, NULL);
5877
5878         return status;
5879 }
5880
5881 /**
5882  * i40e_aq_add_cloud_filters
5883  * @hw: pointer to the hardware structure
5884  * @seid: VSI seid to add cloud filters from
5885  * @filters: Buffer which contains the filters to be added
5886  * @filter_count: number of filters contained in the buffer
5887  *
5888  * Set the cloud filters for a given VSI.  The contents of the
5889  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5890  * of the function.
5891  *
5892  **/
5893 enum i40e_status_code
5894 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid,
5895                           struct i40e_aqc_cloud_filters_element_data *filters,
5896                           u8 filter_count)
5897 {
5898         struct i40e_aq_desc desc;
5899         struct i40e_aqc_add_remove_cloud_filters *cmd =
5900         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5901         enum i40e_status_code status;
5902         u16 buff_len;
5903
5904         i40e_fill_default_direct_cmd_desc(&desc,
5905                                           i40e_aqc_opc_add_cloud_filters);
5906
5907         buff_len = filter_count * sizeof(*filters);
5908         desc.datalen = cpu_to_le16(buff_len);
5909         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5910         cmd->num_filters = filter_count;
5911         cmd->seid = cpu_to_le16(seid);
5912
5913         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5914
5915         return status;
5916 }
5917
5918 /**
5919  * i40e_aq_add_cloud_filters_bb
5920  * @hw: pointer to the hardware structure
5921  * @seid: VSI seid to add cloud filters from
5922  * @filters: Buffer which contains the filters in big buffer to be added
5923  * @filter_count: number of filters contained in the buffer
5924  *
5925  * Set the big buffer cloud filters for a given VSI.  The contents of the
5926  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5927  * function.
5928  *
5929  **/
5930 enum i40e_status_code
5931 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5932                              struct i40e_aqc_cloud_filters_element_bb *filters,
5933                              u8 filter_count)
5934 {
5935         struct i40e_aq_desc desc;
5936         struct i40e_aqc_add_remove_cloud_filters *cmd =
5937         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5938         i40e_status status;
5939         u16 buff_len;
5940         int i;
5941
5942         i40e_fill_default_direct_cmd_desc(&desc,
5943                                           i40e_aqc_opc_add_cloud_filters);
5944
5945         buff_len = filter_count * sizeof(*filters);
5946         desc.datalen = cpu_to_le16(buff_len);
5947         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5948         cmd->num_filters = filter_count;
5949         cmd->seid = cpu_to_le16(seid);
5950         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5951
5952         for (i = 0; i < filter_count; i++) {
5953                 u16 tnl_type;
5954                 u32 ti;
5955
5956                 tnl_type = (le16_to_cpu(filters[i].element.flags) &
5957                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5958                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5959
5960                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5961                  * one more byte further than normally used for Tenant ID in
5962                  * other tunnel types.
5963                  */
5964                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5965                         ti = le32_to_cpu(filters[i].element.tenant_id);
5966                         filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5967                 }
5968         }
5969
5970         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5971
5972         return status;
5973 }
5974
5975 /**
5976  * i40e_aq_rem_cloud_filters
5977  * @hw: pointer to the hardware structure
5978  * @seid: VSI seid to remove cloud filters from
5979  * @filters: Buffer which contains the filters to be removed
5980  * @filter_count: number of filters contained in the buffer
5981  *
5982  * Remove the cloud filters for a given VSI.  The contents of the
5983  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5984  * of the function.
5985  *
5986  **/
5987 enum i40e_status_code
5988 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5989                           struct i40e_aqc_cloud_filters_element_data *filters,
5990                           u8 filter_count)
5991 {
5992         struct i40e_aq_desc desc;
5993         struct i40e_aqc_add_remove_cloud_filters *cmd =
5994         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5995         enum i40e_status_code status;
5996         u16 buff_len;
5997
5998         i40e_fill_default_direct_cmd_desc(&desc,
5999                                           i40e_aqc_opc_remove_cloud_filters);
6000
6001         buff_len = filter_count * sizeof(*filters);
6002         desc.datalen = cpu_to_le16(buff_len);
6003         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6004         cmd->num_filters = filter_count;
6005         cmd->seid = cpu_to_le16(seid);
6006
6007         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
6008
6009         return status;
6010 }
6011
6012 /**
6013  * i40e_aq_rem_cloud_filters_bb
6014  * @hw: pointer to the hardware structure
6015  * @seid: VSI seid to remove cloud filters from
6016  * @filters: Buffer which contains the filters in big buffer to be removed
6017  * @filter_count: number of filters contained in the buffer
6018  *
6019  * Remove the big buffer cloud filters for a given VSI.  The contents of the
6020  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
6021  * function.
6022  *
6023  **/
6024 enum i40e_status_code
6025 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
6026                              struct i40e_aqc_cloud_filters_element_bb *filters,
6027                              u8 filter_count)
6028 {
6029         struct i40e_aq_desc desc;
6030         struct i40e_aqc_add_remove_cloud_filters *cmd =
6031         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
6032         i40e_status status;
6033         u16 buff_len;
6034         int i;
6035
6036         i40e_fill_default_direct_cmd_desc(&desc,
6037                                           i40e_aqc_opc_remove_cloud_filters);
6038
6039         buff_len = filter_count * sizeof(*filters);
6040         desc.datalen = cpu_to_le16(buff_len);
6041         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6042         cmd->num_filters = filter_count;
6043         cmd->seid = cpu_to_le16(seid);
6044         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
6045
6046         for (i = 0; i < filter_count; i++) {
6047                 u16 tnl_type;
6048                 u32 ti;
6049
6050                 tnl_type = (le16_to_cpu(filters[i].element.flags) &
6051                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
6052                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
6053
6054                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
6055                  * one more byte further than normally used for Tenant ID in
6056                  * other tunnel types.
6057                  */
6058                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
6059                         ti = le32_to_cpu(filters[i].element.tenant_id);
6060                         filters[i].element.tenant_id = cpu_to_le32(ti << 8);
6061                 }
6062         }
6063
6064         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
6065
6066         return status;
6067 }