drivers/mmc/host/sdhci-pci-o2micro.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 BayHub Technology Ltd.
   4  *
   5  * Authors: Peter Guo <[email protected]>
   6  *          Adam Lee <[email protected]>
   7  *          Ernest Zhang <[email protected]>
   8  */
   9
  10 #include <linux/pci.h>
  11 #include <linux/mmc/host.h>
  12 #include <linux/mmc/mmc.h>
  13 #include <linux/delay.h>
  14 #include <linux/iopoll.h>
  15
  16 #include "sdhci.h"
  17 #include "sdhci-pci.h"
  18
  19 /*
  20  * O2Micro device registers
  21  */
  22
  23 #define O2_SD_MISC_REG5         0x64
  24 #define O2_SD_LD0_CTRL          0x68
  25 #define O2_SD_DEV_CTRL          0x88
  26 #define O2_SD_LOCK_WP           0xD3
  27 #define O2_SD_TEST_REG          0xD4
  28 #define O2_SD_FUNC_REG0         0xDC
  29 #define O2_SD_MULTI_VCC3V       0xEE
  30 #define O2_SD_CLKREQ            0xEC
  31 #define O2_SD_CAPS              0xE0
  32 #define O2_SD_ADMA1             0xE2
  33 #define O2_SD_ADMA2             0xE7
  34 #define O2_SD_INF_MOD           0xF1
  35 #define O2_SD_MISC_CTRL4        0xFC
  36 #define O2_SD_TUNING_CTRL       0x300
  37 #define O2_SD_PLL_SETTING       0x304
  38 #define O2_SD_MISC_SETTING      0x308
  39 #define O2_SD_CLK_SETTING       0x328
  40 #define O2_SD_CAP_REG2          0x330
  41 #define O2_SD_CAP_REG0          0x334
  42 #define O2_SD_UHS1_CAP_SETTING  0x33C
  43 #define O2_SD_DELAY_CTRL        0x350
  44 #define O2_SD_UHS2_L1_CTRL      0x35C
  45 #define O2_SD_FUNC_REG3         0x3E0
  46 #define O2_SD_FUNC_REG4         0x3E4
  47 #define O2_SD_LED_ENABLE        BIT(6)
  48 #define O2_SD_FREG0_LEDOFF      BIT(13)
  49 #define O2_SD_FREG4_ENABLE_CLK_SET      BIT(22)
  50
  51 #define O2_SD_VENDOR_SETTING    0x110
  52 #define O2_SD_VENDOR_SETTING2   0x1C8
  53 #define O2_SD_HW_TUNING_DISABLE BIT(4)
  54
  55 #define O2_PLL_DLL_WDT_CONTROL1 0x1CC
  56 #define  O2_PLL_FORCE_ACTIVE    BIT(18)
  57 #define  O2_PLL_LOCK_STATUS     BIT(14)
  58 #define  O2_PLL_SOFT_RESET      BIT(12)
  59 #define  O2_DLL_LOCK_STATUS     BIT(11)
  60
  61 #define O2_SD_DETECT_SETTING 0x324
  62
  63 static const u32 dmdn_table[] = {0x2B1C0000,
  64         0x2C1A0000, 0x371B0000, 0x35100000};
  65 #define DMDN_SZ ARRAY_SIZE(dmdn_table)
  66
  67 struct o2_host {
  68         u8 dll_adjust_count;
  69 };
  70
  71 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
  72 {
  73         ktime_t timeout;
  74         u32 scratch32;
  75
  76         /* Wait max 50 ms */
  77         timeout = ktime_add_ms(ktime_get(), 50);
  78         while (1) {
  79                 bool timedout = ktime_after(ktime_get(), timeout);
  80
  81                 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
  82                 if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
  83                     == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
  84                         break;
  85
  86                 if (timedout) {
  87                         pr_err("%s: Card Detect debounce never finished.\n",
  88                                mmc_hostname(host->mmc));
  89                         sdhci_dumpregs(host);
  90                         return;
  91                 }
  92                 udelay(10);
  93         }
  94 }
  95
  96 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
  97 {
  98         ktime_t timeout;
  99         u16 scratch;
 100         u32 scratch32;
 101
 102         /* PLL software reset */
 103         scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
 104         scratch32 |= O2_PLL_SOFT_RESET;
 105         sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
 106         udelay(1);
 107         scratch32 &= ~(O2_PLL_SOFT_RESET);
 108         sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
 109
 110         /* PLL force active */
 111         scratch32 |= O2_PLL_FORCE_ACTIVE;
 112         sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
 113
 114         /* Wait max 20 ms */
 115         timeout = ktime_add_ms(ktime_get(), 20);
 116         while (1) {
 117                 bool timedout = ktime_after(ktime_get(), timeout);
 118
 119                 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
 120                 if (scratch & O2_PLL_LOCK_STATUS)
 121                         break;
 122                 if (timedout) {
 123                         pr_err("%s: Internal clock never stabilised.\n",
 124                                mmc_hostname(host->mmc));
 125                         sdhci_dumpregs(host);
 126                         goto out;
 127                 }
 128                 udelay(10);
 129         }
 130
 131         /* Wait for card detect finish */
 132         udelay(1);
 133         sdhci_o2_wait_card_detect_stable(host);
 134
 135 out:
 136         /* Cancel PLL force active */
 137         scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
 138         scratch32 &= ~O2_PLL_FORCE_ACTIVE;
 139         sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
 140 }
 141
 142 static int sdhci_o2_get_cd(struct mmc_host *mmc)
 143 {
 144         struct sdhci_host *host = mmc_priv(mmc);
 145
 146         if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
 147                 sdhci_o2_enable_internal_clock(host);
 148
 149         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
 150 }
 151
 152 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
 153 {
 154         u32 scratch_32;
 155
 156         pci_read_config_dword(chip->pdev,
 157                               O2_SD_PLL_SETTING, &scratch_32);
 158
 159         scratch_32 &= 0x0000FFFF;
 160         scratch_32 |= value;
 161
 162         pci_write_config_dword(chip->pdev,
 163                                O2_SD_PLL_SETTING, scratch_32);
 164 }
 165
 166 static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
 167 {
 168         return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
 169 }
 170
 171 /*
 172  * This function is used to detect dll lock status.
 173  * Since the dll lock status bit will toggle randomly
 174  * with very short interval which needs to be polled
 175  * as fast as possible. Set sleep_us as 1 microsecond.
 176  */
 177 static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
 178 {
 179         u32     scratch32 = 0;
 180
 181         return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
 182                 scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000);
 183 }
 184
 185 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
 186 {
 187         u16 reg;
 188
 189         /* enable hardware tuning */
 190         reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
 191         reg &= ~O2_SD_HW_TUNING_DISABLE;
 192         sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
 193 }
 194
 195 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
 196 {
 197         int i;
 198
 199         sdhci_send_tuning(host, opcode);
 200
 201         for (i = 0; i < 150; i++) {
 202                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 203
 204                 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
 205                         if (ctrl & SDHCI_CTRL_TUNED_CLK) {
 206                                 host->tuning_done = true;
 207                                 return;
 208                         }
 209                         pr_warn("%s: HW tuning failed !\n",
 210                                 mmc_hostname(host->mmc));
 211                         break;
 212                 }
 213
 214                 mdelay(1);
 215         }
 216
 217         pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
 218                 mmc_hostname(host->mmc));
 219         sdhci_reset_tuning(host);
 220 }
 221
 222 /*
 223  * This function is used to fix o2 dll shift issue.
 224  * It isn't necessary to detect card present before recovery.
 225  * Firstly, it is used by bht emmc card, which is embedded.
 226  * Second, before call recovery card present will be detected
 227  * outside of the execute tuning function.
 228  */
 229 static int sdhci_o2_dll_recovery(struct sdhci_host *host)
 230 {
 231         int ret = 0;
 232         u8 scratch_8 = 0;
 233         u32 scratch_32 = 0;
 234         struct sdhci_pci_slot *slot = sdhci_priv(host);
 235         struct sdhci_pci_chip *chip = slot->chip;
 236         struct o2_host *o2_host = sdhci_pci_priv(slot);
 237
 238         /* UnLock WP */
 239         pci_read_config_byte(chip->pdev,
 240                         O2_SD_LOCK_WP, &scratch_8);
 241         scratch_8 &= 0x7f;
 242         pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
 243         while (o2_host->dll_adjust_count < DMDN_SZ && !ret) {
 244                 /* Disable clock */
 245                 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
 246
 247                 /* PLL software reset */
 248                 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
 249                 scratch_32 |= O2_PLL_SOFT_RESET;
 250                 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
 251
 252                 pci_read_config_dword(chip->pdev,
 253                                             O2_SD_FUNC_REG4,
 254                                             &scratch_32);
 255                 /* Enable Base Clk setting change */
 256                 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
 257                 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
 258                 o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]);
 259
 260                 /* Enable internal clock */
 261                 scratch_8 = SDHCI_CLOCK_INT_EN;
 262                 sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
 263
 264                 if (sdhci_o2_get_cd(host->mmc)) {
 265                         /*
 266                          * need wait at least 5ms for dll status stable,
 267                          * after enable internal clock
 268                          */
 269                         usleep_range(5000, 6000);
 270                         if (sdhci_o2_wait_dll_detect_lock(host)) {
 271                                 scratch_8 |= SDHCI_CLOCK_CARD_EN;
 272                                 sdhci_writeb(host, scratch_8,
 273                                         SDHCI_CLOCK_CONTROL);
 274                                 ret = 1;
 275                         } else {
 276                                 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n",
 277                                         mmc_hostname(host->mmc),
 278                                         o2_host->dll_adjust_count);
 279                         }
 280                 } else {
 281                         pr_err("%s: card present detect failed.\n",
 282                                 mmc_hostname(host->mmc));
 283                         break;
 284                 }
 285
 286                 o2_host->dll_adjust_count++;
 287         }
 288         if (!ret && o2_host->dll_adjust_count == DMDN_SZ)
 289                 pr_err("%s: DLL adjust over max times\n",
 290                 mmc_hostname(host->mmc));
 291         /* Lock WP */
 292         pci_read_config_byte(chip->pdev,
 293                                    O2_SD_LOCK_WP, &scratch_8);
 294         scratch_8 |= 0x80;
 295         pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
 296         return ret;
 297 }
 298
 299 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
 300 {
 301         struct sdhci_host *host = mmc_priv(mmc);
 302         int current_bus_width = 0;
 303
 304         /*
 305          * This handler only implements the eMMC tuning that is specific to
 306          * this controller.  Fall back to the standard method for other TIMING.
 307          */
 308         if ((host->timing != MMC_TIMING_MMC_HS200) &&
 309                 (host->timing != MMC_TIMING_UHS_SDR104))
 310                 return sdhci_execute_tuning(mmc, opcode);
 311
 312         if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) &&
 313                         (opcode != MMC_SEND_TUNING_BLOCK)))
 314                 return -EINVAL;
 315         /*
 316          * Judge the tuning reason, whether caused by dll shift
 317          * If cause by dll shift, should call sdhci_o2_dll_recovery
 318          */
 319         if (!sdhci_o2_wait_dll_detect_lock(host))
 320                 if (!sdhci_o2_dll_recovery(host)) {
 321                         pr_err("%s: o2 dll recovery failed\n",
 322                                 mmc_hostname(host->mmc));
 323                         return -EINVAL;
 324                 }
 325         /*
 326          * o2 sdhci host didn't support 8bit emmc tuning
 327          */
 328         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
 329                 current_bus_width = mmc->ios.bus_width;
 330                 mmc->ios.bus_width = MMC_BUS_WIDTH_4;
 331                 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
 332         }
 333
 334         sdhci_o2_set_tuning_mode(host);
 335
 336         sdhci_start_tuning(host);
 337
 338         __sdhci_o2_execute_tuning(host, opcode);
 339
 340         sdhci_end_tuning(host);
 341
 342         if (current_bus_width == MMC_BUS_WIDTH_8) {
 343                 mmc->ios.bus_width = MMC_BUS_WIDTH_8;
 344                 sdhci_set_bus_width(host, current_bus_width);
 345         }
 346
 347         sdhci_reset(host, SDHCI_RESET_CMD);
 348         sdhci_reset(host, SDHCI_RESET_DATA);
 349
 350         host->flags &= ~SDHCI_HS400_TUNING;
 351         return 0;
 352 }
 353
 354 static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
 355 {
 356         int ret;
 357         u32 scratch_32;
 358
 359         /* Set led of SD host function enable */
 360         ret = pci_read_config_dword(chip->pdev,
 361                                     O2_SD_FUNC_REG0, &scratch_32);
 362         if (ret)
 363                 return;
 364
 365         scratch_32 &= ~O2_SD_FREG0_LEDOFF;
 366         pci_write_config_dword(chip->pdev,
 367                                O2_SD_FUNC_REG0, scratch_32);
 368
 369         ret = pci_read_config_dword(chip->pdev,
 370                                     O2_SD_TEST_REG, &scratch_32);
 371         if (ret)
 372                 return;
 373
 374         scratch_32 |= O2_SD_LED_ENABLE;
 375         pci_write_config_dword(chip->pdev,
 376                                O2_SD_TEST_REG, scratch_32);
 377 }
 378
 379 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
 380 {
 381         u32 scratch_32;
 382         int ret;
 383         /* Improve write performance for SD3.0 */
 384         ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
 385         if (ret)
 386                 return;
 387         scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
 388         pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
 389
 390         /* Enable Link abnormal reset generating Reset */
 391         ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
 392         if (ret)
 393                 return;
 394         scratch_32 &= ~((1 << 19) | (1 << 11));
 395         scratch_32 |= (1 << 10);
 396         pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
 397
 398         /* set card power over current protection */
 399         ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
 400         if (ret)
 401                 return;
 402         scratch_32 |= (1 << 4);
 403         pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
 404
 405         /* adjust the output delay for SD mode */
 406         pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
 407
 408         /* Set the output voltage setting of Aux 1.2v LDO */
 409         ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
 410         if (ret)
 411                 return;
 412         scratch_32 &= ~(3 << 12);
 413         pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
 414
 415         /* Set Max power supply capability of SD host */
 416         ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
 417         if (ret)
 418                 return;
 419         scratch_32 &= ~(0x01FE);
 420         scratch_32 |= 0x00CC;
 421         pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
 422         /* Set DLL Tuning Window */
 423         ret = pci_read_config_dword(chip->pdev,
 424                                     O2_SD_TUNING_CTRL, &scratch_32);
 425         if (ret)
 426                 return;
 427         scratch_32 &= ~(0x000000FF);
 428         scratch_32 |= 0x00000066;
 429         pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
 430
 431         /* Set UHS2 T_EIDLE */
 432         ret = pci_read_config_dword(chip->pdev,
 433                                     O2_SD_UHS2_L1_CTRL, &scratch_32);
 434         if (ret)
 435                 return;
 436         scratch_32 &= ~(0x000000FC);
 437         scratch_32 |= 0x00000084;
 438         pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
 439
 440         /* Set UHS2 Termination */
 441         ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
 442         if (ret)
 443                 return;
 444         scratch_32 &= ~((1 << 21) | (1 << 30));
 445
 446         pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
 447
 448         /* Set L1 Entrance Timer */
 449         ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
 450         if (ret)
 451                 return;
 452         scratch_32 &= ~(0xf0000000);
 453         scratch_32 |= 0x30000000;
 454         pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
 455
 456         ret = pci_read_config_dword(chip->pdev,
 457                                     O2_SD_MISC_CTRL4, &scratch_32);
 458         if (ret)
 459                 return;
 460         scratch_32 &= ~(0x000f0000);
 461         scratch_32 |= 0x00080000;
 462         pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
 463 }
 464
 465 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
 466                                     struct sdhci_host *host)
 467 {
 468         int ret;
 469
 470         ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
 471         if (!ret) {
 472                 pr_info("%s: unsupport msi, use INTx irq\n",
 473                         mmc_hostname(host->mmc));
 474                 return;
 475         }
 476
 477         ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
 478                                     PCI_IRQ_MSI | PCI_IRQ_MSIX);
 479         if (ret < 0) {
 480                 pr_err("%s: enable PCI MSI failed, err=%d\n",
 481                        mmc_hostname(host->mmc), ret);
 482                 return;
 483         }
 484
 485         host->irq = pci_irq_vector(chip->pdev, 0);
 486 }
 487
 488 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
 489 {
 490         /* Enable internal clock */
 491         clk |= SDHCI_CLOCK_INT_EN;
 492         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 493
 494         sdhci_o2_enable_internal_clock(host);
 495         if (sdhci_o2_get_cd(host->mmc)) {
 496                 clk |= SDHCI_CLOCK_CARD_EN;
 497                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 498         }
 499 }
 500
 501 static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
 502 {
 503         u16 clk;
 504         u8 scratch;
 505         u32 scratch_32;
 506         struct sdhci_pci_slot *slot = sdhci_priv(host);
 507         struct sdhci_pci_chip *chip = slot->chip;
 508
 509         host->mmc->actual_clock = 0;
 510
 511         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 512
 513         if (clock == 0)
 514                 return;
 515
 516         if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) {
 517                 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
 518
 519                 scratch &= 0x7f;
 520                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 521
 522                 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
 523
 524                 if ((scratch_32 & 0xFFFF0000) != 0x2c280000)
 525                         o2_pci_set_baseclk(chip, 0x2c280000);
 526
 527                 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
 528
 529                 scratch |= 0x80;
 530                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 531         }
 532
 533         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
 534         sdhci_o2_enable_clk(host, clk);
 535 }
 536
 537 static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
 538 {
 539         struct sdhci_pci_chip *chip;
 540         struct sdhci_host *host;
 541         struct o2_host *o2_host = sdhci_pci_priv(slot);
 542         u32 reg, caps;
 543         int ret;
 544
 545         chip = slot->chip;
 546         host = slot->host;
 547
 548         o2_host->dll_adjust_count = 0;
 549         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 550
 551         /*
 552          * mmc_select_bus_width() will test the bus to determine the actual bus
 553          * width.
 554          */
 555         if (caps & SDHCI_CAN_DO_8BIT)
 556                 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 557
 558         switch (chip->pdev->device) {
 559         case PCI_DEVICE_ID_O2_SDS0:
 560         case PCI_DEVICE_ID_O2_SEABIRD0:
 561         case PCI_DEVICE_ID_O2_SEABIRD1:
 562         case PCI_DEVICE_ID_O2_SDS1:
 563         case PCI_DEVICE_ID_O2_FUJIN2:
 564                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
 565                 if (reg & 0x1)
 566                         host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
 567
 568                 sdhci_pci_o2_enable_msi(chip, host);
 569
 570                 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
 571                         ret = pci_read_config_dword(chip->pdev,
 572                                                     O2_SD_MISC_SETTING, &reg);
 573                         if (ret)
 574                                 return -EIO;
 575                         if (reg & (1 << 4)) {
 576                                 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
 577                                         mmc_hostname(host->mmc));
 578                                 host->flags &= ~SDHCI_SIGNALING_330;
 579                                 host->flags |= SDHCI_SIGNALING_180;
 580                                 host->mmc->caps2 |= MMC_CAP2_NO_SD;
 581                                 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
 582                                 pci_write_config_dword(chip->pdev,
 583                                                        O2_SD_DETECT_SETTING, 3);
 584                         }
 585
 586                         slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
 587                 }
 588
 589                 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) {
 590                         slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
 591                         host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
 592                         host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
 593                 }
 594
 595                 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
 596
 597                 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
 598                         break;
 599                 /* set dll watch dog timer */
 600                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
 601                 reg |= (1 << 12);
 602                 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
 603
 604                 break;
 605         default:
 606                 break;
 607         }
 608
 609         return 0;
 610 }
 611
 612 static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
 613 {
 614         int ret;
 615         u8 scratch;
 616         u32 scratch_32;
 617
 618         switch (chip->pdev->device) {
 619         case PCI_DEVICE_ID_O2_8220:
 620         case PCI_DEVICE_ID_O2_8221:
 621         case PCI_DEVICE_ID_O2_8320:
 622         case PCI_DEVICE_ID_O2_8321:
 623                 /* This extra setup is required due to broken ADMA. */
 624                 ret = pci_read_config_byte(chip->pdev,
 625                                 O2_SD_LOCK_WP, &scratch);
 626                 if (ret)
 627                         return ret;
 628                 scratch &= 0x7f;
 629                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 630
 631                 /* Set Multi 3 to VCC3V# */
 632                 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
 633
 634                 /* Disable CLK_REQ# support after media DET */
 635                 ret = pci_read_config_byte(chip->pdev,
 636                                 O2_SD_CLKREQ, &scratch);
 637                 if (ret)
 638                         return ret;
 639                 scratch |= 0x20;
 640                 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
 641
 642                 /* Choose capabilities, enable SDMA.  We have to write 0x01
 643                  * to the capabilities register first to unlock it.
 644                  */
 645                 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
 646                 if (ret)
 647                         return ret;
 648                 scratch |= 0x01;
 649                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
 650                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
 651
 652                 /* Disable ADMA1/2 */
 653                 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
 654                 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
 655
 656                 /* Disable the infinite transfer mode */
 657                 ret = pci_read_config_byte(chip->pdev,
 658                                 O2_SD_INF_MOD, &scratch);
 659                 if (ret)
 660                         return ret;
 661                 scratch |= 0x08;
 662                 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
 663
 664                 /* Lock WP */
 665                 ret = pci_read_config_byte(chip->pdev,
 666                                 O2_SD_LOCK_WP, &scratch);
 667                 if (ret)
 668                         return ret;
 669                 scratch |= 0x80;
 670                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 671                 break;
 672         case PCI_DEVICE_ID_O2_SDS0:
 673         case PCI_DEVICE_ID_O2_SDS1:
 674         case PCI_DEVICE_ID_O2_FUJIN2:
 675                 /* UnLock WP */
 676                 ret = pci_read_config_byte(chip->pdev,
 677                                 O2_SD_LOCK_WP, &scratch);
 678                 if (ret)
 679                         return ret;
 680
 681                 scratch &= 0x7f;
 682                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 683
 684                 /* DevId=8520 subId= 0x11 or 0x12  Type Chip support */
 685                 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
 686                         ret = pci_read_config_dword(chip->pdev,
 687                                                     O2_SD_FUNC_REG0,
 688                                                     &scratch_32);
 689                         scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
 690
 691                         /* Check Whether subId is 0x11 or 0x12 */
 692                         if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
 693                                 scratch_32 = 0x25100000;
 694
 695                                 o2_pci_set_baseclk(chip, scratch_32);
 696                                 ret = pci_read_config_dword(chip->pdev,
 697                                                             O2_SD_FUNC_REG4,
 698                                                             &scratch_32);
 699
 700                                 /* Enable Base Clk setting change */
 701                                 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
 702                                 pci_write_config_dword(chip->pdev,
 703                                                        O2_SD_FUNC_REG4,
 704                                                        scratch_32);
 705
 706                                 /* Set Tuning Window to 4 */
 707                                 pci_write_config_byte(chip->pdev,
 708                                                       O2_SD_TUNING_CTRL, 0x44);
 709
 710                                 break;
 711                         }
 712                 }
 713
 714                 /* Enable 8520 led function */
 715                 o2_pci_led_enable(chip);
 716
 717                 /* Set timeout CLK */
 718                 ret = pci_read_config_dword(chip->pdev,
 719                                             O2_SD_CLK_SETTING, &scratch_32);
 720                 if (ret)
 721                         return ret;
 722
 723                 scratch_32 &= ~(0xFF00);
 724                 scratch_32 |= 0x07E0C800;
 725                 pci_write_config_dword(chip->pdev,
 726                                        O2_SD_CLK_SETTING, scratch_32);
 727
 728                 ret = pci_read_config_dword(chip->pdev,
 729                                             O2_SD_CLKREQ, &scratch_32);
 730                 if (ret)
 731                         return ret;
 732                 scratch_32 |= 0x3;
 733                 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
 734
 735                 ret = pci_read_config_dword(chip->pdev,
 736                                             O2_SD_PLL_SETTING, &scratch_32);
 737                 if (ret)
 738                         return ret;
 739
 740                 scratch_32 &= ~(0x1F3F070E);
 741                 scratch_32 |= 0x18270106;
 742                 pci_write_config_dword(chip->pdev,
 743                                        O2_SD_PLL_SETTING, scratch_32);
 744
 745                 /* Disable UHS1 funciton */
 746                 ret = pci_read_config_dword(chip->pdev,
 747                                             O2_SD_CAP_REG2, &scratch_32);
 748                 if (ret)
 749                         return ret;
 750                 scratch_32 &= ~(0xE0);
 751                 pci_write_config_dword(chip->pdev,
 752                                        O2_SD_CAP_REG2, scratch_32);
 753
 754                 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
 755                         sdhci_pci_o2_fujin2_pci_init(chip);
 756
 757                 /* Lock WP */
 758                 ret = pci_read_config_byte(chip->pdev,
 759                                            O2_SD_LOCK_WP, &scratch);
 760                 if (ret)
 761                         return ret;
 762                 scratch |= 0x80;
 763                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 764                 break;
 765         case PCI_DEVICE_ID_O2_SEABIRD0:
 766         case PCI_DEVICE_ID_O2_SEABIRD1:
 767                 /* UnLock WP */
 768                 ret = pci_read_config_byte(chip->pdev,
 769                                 O2_SD_LOCK_WP, &scratch);
 770                 if (ret)
 771                         return ret;
 772
 773                 scratch &= 0x7f;
 774                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 775
 776                 ret = pci_read_config_dword(chip->pdev,
 777                                             O2_SD_PLL_SETTING, &scratch_32);
 778
 779                 if ((scratch_32 & 0xff000000) == 0x01000000) {
 780                         scratch_32 &= 0x0000FFFF;
 781                         scratch_32 |= 0x1F340000;
 782
 783                         pci_write_config_dword(chip->pdev,
 784                                                O2_SD_PLL_SETTING, scratch_32);
 785                 } else {
 786                         scratch_32 &= 0x0000FFFF;
 787                         scratch_32 |= 0x25100000;
 788
 789                         pci_write_config_dword(chip->pdev,
 790                                                O2_SD_PLL_SETTING, scratch_32);
 791
 792                         ret = pci_read_config_dword(chip->pdev,
 793                                                     O2_SD_FUNC_REG4,
 794                                                     &scratch_32);
 795                         scratch_32 |= (1 << 22);
 796                         pci_write_config_dword(chip->pdev,
 797                                                O2_SD_FUNC_REG4, scratch_32);
 798                 }
 799
 800                 /* Set Tuning Windows to 5 */
 801                 pci_write_config_byte(chip->pdev,
 802                                 O2_SD_TUNING_CTRL, 0x55);
 803                 /* Lock WP */
 804                 ret = pci_read_config_byte(chip->pdev,
 805                                            O2_SD_LOCK_WP, &scratch);
 806                 if (ret)
 807                         return ret;
 808                 scratch |= 0x80;
 809                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 810                 break;
 811         }
 812
 813         return 0;
 814 }
 815
 816 #ifdef CONFIG_PM_SLEEP
 817 static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
 818 {
 819         sdhci_pci_o2_probe(chip);
 820         return sdhci_pci_resume_host(chip);
 821 }
 822 #endif
 823
 824 static const struct sdhci_ops sdhci_pci_o2_ops = {
 825         .set_clock = sdhci_pci_o2_set_clock,
 826         .enable_dma = sdhci_pci_enable_dma,
 827         .set_bus_width = sdhci_set_bus_width,
 828         .reset = sdhci_reset,
 829         .set_uhs_signaling = sdhci_set_uhs_signaling,
 830 };
 831
 832 const struct sdhci_pci_fixes sdhci_o2 = {
 833         .probe = sdhci_pci_o2_probe,
 834         .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 835         .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
 836         .probe_slot = sdhci_pci_o2_probe_slot,
 837 #ifdef CONFIG_PM_SLEEP
 838         .resume = sdhci_pci_o2_resume,
 839 #endif
 840         .ops = &sdhci_pci_o2_ops,
 841         .priv_size = sizeof(struct o2_host),
 842 };