drivers/irqchip/qcom-pdc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/err.h>
   7 #include <linux/init.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/irq.h>
  10 #include <linux/irqchip.h>
  11 #include <linux/irqdomain.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/soc/qcom/irq.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/slab.h>
  22 #include <linux/types.h>
  23
  24 #define PDC_MAX_IRQS            168
  25 #define PDC_MAX_GPIO_IRQS       256
  26
  27 #define CLEAR_INTR(reg, intr)   (reg & ~(1 << intr))
  28 #define ENABLE_INTR(reg, intr)  (reg | (1 << intr))
  29
  30 #define IRQ_ENABLE_BANK         0x10
  31 #define IRQ_i_CFG               0x110
  32
  33 #define PDC_NO_PARENT_IRQ       ~0UL
  34
  35 struct pdc_pin_region {
  36         u32 pin_base;
  37         u32 parent_base;
  38         u32 cnt;
  39 };
  40
  41 static DEFINE_RAW_SPINLOCK(pdc_lock);
  42 static void __iomem *pdc_base;
  43 static struct pdc_pin_region *pdc_region;
  44 static int pdc_region_cnt;
  45
  46 static void pdc_reg_write(int reg, u32 i, u32 val)
  47 {
  48         writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
  49 }
  50
  51 static u32 pdc_reg_read(int reg, u32 i)
  52 {
  53         return readl_relaxed(pdc_base + reg + i * sizeof(u32));
  54 }
  55
  56 static int qcom_pdc_gic_get_irqchip_state(struct irq_data *d,
  57                                           enum irqchip_irq_state which,
  58                                           bool *state)
  59 {
  60         if (d->hwirq == GPIO_NO_WAKE_IRQ)
  61                 return 0;
  62
  63         return irq_chip_get_parent_state(d, which, state);
  64 }
  65
  66 static int qcom_pdc_gic_set_irqchip_state(struct irq_data *d,
  67                                           enum irqchip_irq_state which,
  68                                           bool value)
  69 {
  70         if (d->hwirq == GPIO_NO_WAKE_IRQ)
  71                 return 0;
  72
  73         return irq_chip_set_parent_state(d, which, value);
  74 }
  75
  76 static void pdc_enable_intr(struct irq_data *d, bool on)
  77 {
  78         int pin_out = d->hwirq;
  79         u32 index, mask;
  80         u32 enable;
  81
  82         index = pin_out / 32;
  83         mask = pin_out % 32;
  84
  85         raw_spin_lock(&pdc_lock);
  86         enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
  87         enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
  88         pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
  89         raw_spin_unlock(&pdc_lock);
  90 }
  91
  92 static void qcom_pdc_gic_disable(struct irq_data *d)
  93 {
  94         if (d->hwirq == GPIO_NO_WAKE_IRQ)
  95                 return;
  96
  97         pdc_enable_intr(d, false);
  98         irq_chip_disable_parent(d);
  99 }
 100
 101 static void qcom_pdc_gic_enable(struct irq_data *d)
 102 {
 103         if (d->hwirq == GPIO_NO_WAKE_IRQ)
 104                 return;
 105
 106         pdc_enable_intr(d, true);
 107         irq_chip_enable_parent(d);
 108 }
 109
 110 static void qcom_pdc_gic_mask(struct irq_data *d)
 111 {
 112         if (d->hwirq == GPIO_NO_WAKE_IRQ)
 113                 return;
 114
 115         irq_chip_mask_parent(d);
 116 }
 117
 118 static void qcom_pdc_gic_unmask(struct irq_data *d)
 119 {
 120         if (d->hwirq == GPIO_NO_WAKE_IRQ)
 121                 return;
 122
 123         irq_chip_unmask_parent(d);
 124 }
 125
 126 /*
 127  * GIC does not handle falling edge or active low. To allow falling edge and
 128  * active low interrupts to be handled at GIC, PDC has an inverter that inverts
 129  * falling edge into a rising edge and active low into an active high.
 130  * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
 131  * set as per the table below.
 132  * Level sensitive active low    LOW
 133  * Rising edge sensitive         NOT USED
 134  * Falling edge sensitive        LOW
 135  * Dual Edge sensitive           NOT USED
 136  * Level sensitive active High   HIGH
 137  * Falling Edge sensitive        NOT USED
 138  * Rising edge sensitive         HIGH
 139  * Dual Edge sensitive           HIGH
 140  */
 141 enum pdc_irq_config_bits {
 142         PDC_LEVEL_LOW           = 0b000,
 143         PDC_EDGE_FALLING        = 0b010,
 144         PDC_LEVEL_HIGH          = 0b100,
 145         PDC_EDGE_RISING         = 0b110,
 146         PDC_EDGE_DUAL           = 0b111,
 147 };
 148
 149 /**
 150  * qcom_pdc_gic_set_type: Configure PDC for the interrupt
 151  *
 152  * @d: the interrupt data
 153  * @type: the interrupt type
 154  *
 155  * If @type is edge triggered, forward that as Rising edge as PDC
 156  * takes care of converting falling edge to rising edge signal
 157  * If @type is level, then forward that as level high as PDC
 158  * takes care of converting falling edge to rising edge signal
 159  */
 160 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
 161 {
 162         int pin_out = d->hwirq;
 163         enum pdc_irq_config_bits pdc_type;
 164
 165         if (pin_out == GPIO_NO_WAKE_IRQ)
 166                 return 0;
 167
 168         switch (type) {
 169         case IRQ_TYPE_EDGE_RISING:
 170                 pdc_type = PDC_EDGE_RISING;
 171                 break;
 172         case IRQ_TYPE_EDGE_FALLING:
 173                 pdc_type = PDC_EDGE_FALLING;
 174                 type = IRQ_TYPE_EDGE_RISING;
 175                 break;
 176         case IRQ_TYPE_EDGE_BOTH:
 177                 pdc_type = PDC_EDGE_DUAL;
 178                 type = IRQ_TYPE_EDGE_RISING;
 179                 break;
 180         case IRQ_TYPE_LEVEL_HIGH:
 181                 pdc_type = PDC_LEVEL_HIGH;
 182                 break;
 183         case IRQ_TYPE_LEVEL_LOW:
 184                 pdc_type = PDC_LEVEL_LOW;
 185                 type = IRQ_TYPE_LEVEL_HIGH;
 186                 break;
 187         default:
 188                 WARN_ON(1);
 189                 return -EINVAL;
 190         }
 191
 192         pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type);
 193
 194         return irq_chip_set_type_parent(d, type);
 195 }
 196
 197 static struct irq_chip qcom_pdc_gic_chip = {
 198         .name                   = "PDC",
 199         .irq_eoi                = irq_chip_eoi_parent,
 200         .irq_mask               = qcom_pdc_gic_mask,
 201         .irq_unmask             = qcom_pdc_gic_unmask,
 202         .irq_disable            = qcom_pdc_gic_disable,
 203         .irq_enable             = qcom_pdc_gic_enable,
 204         .irq_get_irqchip_state  = qcom_pdc_gic_get_irqchip_state,
 205         .irq_set_irqchip_state  = qcom_pdc_gic_set_irqchip_state,
 206         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 207         .irq_set_type           = qcom_pdc_gic_set_type,
 208         .flags                  = IRQCHIP_MASK_ON_SUSPEND |
 209                                   IRQCHIP_SET_TYPE_MASKED |
 210                                   IRQCHIP_SKIP_SET_WAKE,
 211         .irq_set_vcpu_affinity  = irq_chip_set_vcpu_affinity_parent,
 212         .irq_set_affinity       = irq_chip_set_affinity_parent,
 213 };
 214
 215 static irq_hw_number_t get_parent_hwirq(int pin)
 216 {
 217         int i;
 218         struct pdc_pin_region *region;
 219
 220         for (i = 0; i < pdc_region_cnt; i++) {
 221                 region = &pdc_region[i];
 222                 if (pin >= region->pin_base &&
 223                     pin < region->pin_base + region->cnt)
 224                         return (region->parent_base + pin - region->pin_base);
 225         }
 226
 227         return PDC_NO_PARENT_IRQ;
 228 }
 229
 230 static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
 231                               unsigned long *hwirq, unsigned int *type)
 232 {
 233         if (is_of_node(fwspec->fwnode)) {
 234                 if (fwspec->param_count != 2)
 235                         return -EINVAL;
 236
 237                 *hwirq = fwspec->param[0];
 238                 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
 239                 return 0;
 240         }
 241
 242         return -EINVAL;
 243 }
 244
 245 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
 246                           unsigned int nr_irqs, void *data)
 247 {
 248         struct irq_fwspec *fwspec = data;
 249         struct irq_fwspec parent_fwspec;
 250         irq_hw_number_t hwirq, parent_hwirq;
 251         unsigned int type;
 252         int ret;
 253
 254         ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
 255         if (ret)
 256                 return ret;
 257
 258         ret  = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
 259                                              &qcom_pdc_gic_chip, NULL);
 260         if (ret)
 261                 return ret;
 262
 263         parent_hwirq = get_parent_hwirq(hwirq);
 264         if (parent_hwirq == PDC_NO_PARENT_IRQ)
 265                 return 0;
 266
 267         if (type & IRQ_TYPE_EDGE_BOTH)
 268                 type = IRQ_TYPE_EDGE_RISING;
 269
 270         if (type & IRQ_TYPE_LEVEL_MASK)
 271                 type = IRQ_TYPE_LEVEL_HIGH;
 272
 273         parent_fwspec.fwnode      = domain->parent->fwnode;
 274         parent_fwspec.param_count = 3;
 275         parent_fwspec.param[0]    = 0;
 276         parent_fwspec.param[1]    = parent_hwirq;
 277         parent_fwspec.param[2]    = type;
 278
 279         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 280                                             &parent_fwspec);
 281 }
 282
 283 static const struct irq_domain_ops qcom_pdc_ops = {
 284         .translate      = qcom_pdc_translate,
 285         .alloc          = qcom_pdc_alloc,
 286         .free           = irq_domain_free_irqs_common,
 287 };
 288
 289 static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
 290                                unsigned int nr_irqs, void *data)
 291 {
 292         struct irq_fwspec *fwspec = data;
 293         struct irq_fwspec parent_fwspec;
 294         irq_hw_number_t hwirq, parent_hwirq;
 295         unsigned int type;
 296         int ret;
 297
 298         ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
 299         if (ret)
 300                 return ret;
 301
 302         ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
 303                                             &qcom_pdc_gic_chip, NULL);
 304         if (ret)
 305                 return ret;
 306
 307         if (hwirq == GPIO_NO_WAKE_IRQ)
 308                 return 0;
 309
 310         parent_hwirq = get_parent_hwirq(hwirq);
 311         if (parent_hwirq == PDC_NO_PARENT_IRQ)
 312                 return 0;
 313
 314         if (type & IRQ_TYPE_EDGE_BOTH)
 315                 type = IRQ_TYPE_EDGE_RISING;
 316
 317         if (type & IRQ_TYPE_LEVEL_MASK)
 318                 type = IRQ_TYPE_LEVEL_HIGH;
 319
 320         parent_fwspec.fwnode      = domain->parent->fwnode;
 321         parent_fwspec.param_count = 3;
 322         parent_fwspec.param[0]    = 0;
 323         parent_fwspec.param[1]    = parent_hwirq;
 324         parent_fwspec.param[2]    = type;
 325
 326         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 327                                             &parent_fwspec);
 328 }
 329
 330 static int qcom_pdc_gpio_domain_select(struct irq_domain *d,
 331                                        struct irq_fwspec *fwspec,
 332                                        enum irq_domain_bus_token bus_token)
 333 {
 334         return bus_token == DOMAIN_BUS_WAKEUP;
 335 }
 336
 337 static const struct irq_domain_ops qcom_pdc_gpio_ops = {
 338         .select         = qcom_pdc_gpio_domain_select,
 339         .alloc          = qcom_pdc_gpio_alloc,
 340         .free           = irq_domain_free_irqs_common,
 341 };
 342
 343 static int pdc_setup_pin_mapping(struct device_node *np)
 344 {
 345         int ret, n;
 346
 347         n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
 348         if (n <= 0 || n % 3)
 349                 return -EINVAL;
 350
 351         pdc_region_cnt = n / 3;
 352         pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
 353         if (!pdc_region) {
 354                 pdc_region_cnt = 0;
 355                 return -ENOMEM;
 356         }
 357
 358         for (n = 0; n < pdc_region_cnt; n++) {
 359                 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
 360                                                  n * 3 + 0,
 361                                                  &pdc_region[n].pin_base);
 362                 if (ret)
 363                         return ret;
 364                 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
 365                                                  n * 3 + 1,
 366                                                  &pdc_region[n].parent_base);
 367                 if (ret)
 368                         return ret;
 369                 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
 370                                                  n * 3 + 2,
 371                                                  &pdc_region[n].cnt);
 372                 if (ret)
 373                         return ret;
 374         }
 375
 376         return 0;
 377 }
 378
 379 static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
 380 {
 381         struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;
 382         int ret;
 383
 384         pdc_base = of_iomap(node, 0);
 385         if (!pdc_base) {
 386                 pr_err("%pOF: unable to map PDC registers\n", node);
 387                 return -ENXIO;
 388         }
 389
 390         parent_domain = irq_find_host(parent);
 391         if (!parent_domain) {
 392                 pr_err("%pOF: unable to find PDC's parent domain\n", node);
 393                 ret = -ENXIO;
 394                 goto fail;
 395         }
 396
 397         ret = pdc_setup_pin_mapping(node);
 398         if (ret) {
 399                 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
 400                 goto fail;
 401         }
 402
 403         pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS,
 404                                                  of_fwnode_handle(node),
 405                                                  &qcom_pdc_ops, NULL);
 406         if (!pdc_domain) {
 407                 pr_err("%pOF: GIC domain add failed\n", node);
 408                 ret = -ENOMEM;
 409                 goto fail;
 410         }
 411
 412         pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain,
 413                                         IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
 414                                         PDC_MAX_GPIO_IRQS,
 415                                         of_fwnode_handle(node),
 416                                         &qcom_pdc_gpio_ops, NULL);
 417         if (!pdc_gpio_domain) {
 418                 pr_err("%pOF: PDC domain add failed for GPIO domain\n", node);
 419                 ret = -ENOMEM;
 420                 goto remove;
 421         }
 422
 423         irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP);
 424
 425         return 0;
 426
 427 remove:
 428         irq_domain_remove(pdc_domain);
 429 fail:
 430         kfree(pdc_region);
 431         iounmap(pdc_base);
 432         return ret;
 433 }
 434
 435 IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc)
 436 IRQCHIP_MATCH("qcom,pdc", qcom_pdc_init)
 437 IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc)
 438 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller");
 439 MODULE_LICENSE("GPL v2");