arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, [email protected] and Carsten Langgaard, [email protected]
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/war.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #else
  38 #define _ULCAST_ (unsigned long)
  39 #endif
  40
  41 /*
  42  * Coprocessor 0 register names
  43  */
  44 #define CP0_INDEX $0
  45 #define CP0_RANDOM $1
  46 #define CP0_ENTRYLO0 $2
  47 #define CP0_ENTRYLO1 $3
  48 #define CP0_CONF $3
  49 #define CP0_CONTEXT $4
  50 #define CP0_PAGEMASK $5
  51 #define CP0_WIRED $6
  52 #define CP0_INFO $7
  53 #define CP0_HWRENA $7, 0
  54 #define CP0_BADVADDR $8
  55 #define CP0_BADINSTR $8, 1
  56 #define CP0_COUNT $9
  57 #define CP0_ENTRYHI $10
  58 #define CP0_COMPARE $11
  59 #define CP0_STATUS $12
  60 #define CP0_CAUSE $13
  61 #define CP0_EPC $14
  62 #define CP0_PRID $15
  63 #define CP0_EBASE $15, 1
  64 #define CP0_CMGCRBASE $15, 3
  65 #define CP0_CONFIG $16
  66 #define CP0_CONFIG3 $16, 3
  67 #define CP0_CONFIG5 $16, 5
  68 #define CP0_LLADDR $17
  69 #define CP0_WATCHLO $18
  70 #define CP0_WATCHHI $19
  71 #define CP0_XCONTEXT $20
  72 #define CP0_FRAMEMASK $21
  73 #define CP0_DIAGNOSTIC $22
  74 #define CP0_DEBUG $23
  75 #define CP0_DEPC $24
  76 #define CP0_PERFORMANCE $25
  77 #define CP0_ECC $26
  78 #define CP0_CACHEERR $27
  79 #define CP0_TAGLO $28
  80 #define CP0_TAGHI $29
  81 #define CP0_ERROREPC $30
  82 #define CP0_DESAVE $31
  83
  84 /*
  85  * R4640/R4650 cp0 register names.  These registers are listed
  86  * here only for completeness; without MMU these CPUs are not useable
  87  * by Linux.  A future ELKS port might take make Linux run on them
  88  * though ...
  89  */
  90 #define CP0_IBASE $0
  91 #define CP0_IBOUND $1
  92 #define CP0_DBASE $2
  93 #define CP0_DBOUND $3
  94 #define CP0_CALG $17
  95 #define CP0_IWATCH $18
  96 #define CP0_DWATCH $19
  97
  98 /*
  99  * Coprocessor 0 Set 1 register names
 100  */
 101 #define CP0_S1_DERRADDR0  $26
 102 #define CP0_S1_DERRADDR1  $27
 103 #define CP0_S1_INTCONTROL $20
 104
 105 /*
 106  * Coprocessor 0 Set 2 register names
 107  */
 108 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 109
 110 /*
 111  * Coprocessor 0 Set 3 register names
 112  */
 113 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 114
 115 /*
 116  *  TX39 Series
 117  */
 118 #define CP0_TX39_CACHE  $7
 119
 120
 121 /* Generic EntryLo bit definitions */
 122 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 123 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 124 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 125 #define ENTRYLO_C_SHIFT         3
 126 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 127
 128 /* R3000 EntryLo bit definitions */
 129 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 130 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 131 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 132 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 133
 134 /* MIPS32/64 EntryLo bit definitions */
 135 #define MIPS_ENTRYLO_PFN_SHIFT  6
 136 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 137 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 138
 139 /*
 140  * Values for PageMask register
 141  */
 142 #ifdef CONFIG_CPU_VR41XX
 143
 144 /* Why doesn't stupidity hurt ... */
 145
 146 #define PM_1K           0x00000000
 147 #define PM_4K           0x00001800
 148 #define PM_16K          0x00007800
 149 #define PM_64K          0x0001f800
 150 #define PM_256K         0x0007f800
 151
 152 #else
 153
 154 #define PM_4K           0x00000000
 155 #define PM_8K           0x00002000
 156 #define PM_16K          0x00006000
 157 #define PM_32K          0x0000e000
 158 #define PM_64K          0x0001e000
 159 #define PM_128K         0x0003e000
 160 #define PM_256K         0x0007e000
 161 #define PM_512K         0x000fe000
 162 #define PM_1M           0x001fe000
 163 #define PM_2M           0x003fe000
 164 #define PM_4M           0x007fe000
 165 #define PM_8M           0x00ffe000
 166 #define PM_16M          0x01ffe000
 167 #define PM_32M          0x03ffe000
 168 #define PM_64M          0x07ffe000
 169 #define PM_256M         0x1fffe000
 170 #define PM_1G           0x7fffe000
 171
 172 #endif
 173
 174 /*
 175  * Default page size for a given kernel configuration
 176  */
 177 #ifdef CONFIG_PAGE_SIZE_4KB
 178 #define PM_DEFAULT_MASK PM_4K
 179 #elif defined(CONFIG_PAGE_SIZE_8KB)
 180 #define PM_DEFAULT_MASK PM_8K
 181 #elif defined(CONFIG_PAGE_SIZE_16KB)
 182 #define PM_DEFAULT_MASK PM_16K
 183 #elif defined(CONFIG_PAGE_SIZE_32KB)
 184 #define PM_DEFAULT_MASK PM_32K
 185 #elif defined(CONFIG_PAGE_SIZE_64KB)
 186 #define PM_DEFAULT_MASK PM_64K
 187 #else
 188 #error Bad page size configuration!
 189 #endif
 190
 191 /*
 192  * Default huge tlb size for a given kernel configuration
 193  */
 194 #ifdef CONFIG_PAGE_SIZE_4KB
 195 #define PM_HUGE_MASK    PM_1M
 196 #elif defined(CONFIG_PAGE_SIZE_8KB)
 197 #define PM_HUGE_MASK    PM_4M
 198 #elif defined(CONFIG_PAGE_SIZE_16KB)
 199 #define PM_HUGE_MASK    PM_16M
 200 #elif defined(CONFIG_PAGE_SIZE_32KB)
 201 #define PM_HUGE_MASK    PM_64M
 202 #elif defined(CONFIG_PAGE_SIZE_64KB)
 203 #define PM_HUGE_MASK    PM_256M
 204 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 205 #error Bad page size configuration for hugetlbfs!
 206 #endif
 207
 208 /*
 209  * Values used for computation of new tlb entries
 210  */
 211 #define PL_4K           12
 212 #define PL_16K          14
 213 #define PL_64K          16
 214 #define PL_256K         18
 215 #define PL_1M           20
 216 #define PL_4M           22
 217 #define PL_16M          24
 218 #define PL_64M          26
 219 #define PL_256M         28
 220
 221 /*
 222  * PageGrain bits
 223  */
 224 #define PG_RIE          (_ULCAST_(1) <<  31)
 225 #define PG_XIE          (_ULCAST_(1) <<  30)
 226 #define PG_ELPA         (_ULCAST_(1) <<  29)
 227 #define PG_ESP          (_ULCAST_(1) <<  28)
 228 #define PG_IEC          (_ULCAST_(1) <<  27)
 229
 230 /* MIPS32/64 EntryHI bit definitions */
 231 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 232
 233 /*
 234  * R4x00 interrupt enable / cause bits
 235  */
 236 #define IE_SW0          (_ULCAST_(1) <<  8)
 237 #define IE_SW1          (_ULCAST_(1) <<  9)
 238 #define IE_IRQ0         (_ULCAST_(1) << 10)
 239 #define IE_IRQ1         (_ULCAST_(1) << 11)
 240 #define IE_IRQ2         (_ULCAST_(1) << 12)
 241 #define IE_IRQ3         (_ULCAST_(1) << 13)
 242 #define IE_IRQ4         (_ULCAST_(1) << 14)
 243 #define IE_IRQ5         (_ULCAST_(1) << 15)
 244
 245 /*
 246  * R4x00 interrupt cause bits
 247  */
 248 #define C_SW0           (_ULCAST_(1) <<  8)
 249 #define C_SW1           (_ULCAST_(1) <<  9)
 250 #define C_IRQ0          (_ULCAST_(1) << 10)
 251 #define C_IRQ1          (_ULCAST_(1) << 11)
 252 #define C_IRQ2          (_ULCAST_(1) << 12)
 253 #define C_IRQ3          (_ULCAST_(1) << 13)
 254 #define C_IRQ4          (_ULCAST_(1) << 14)
 255 #define C_IRQ5          (_ULCAST_(1) << 15)
 256
 257 /*
 258  * Bitfields in the R4xx0 cp0 status register
 259  */
 260 #define ST0_IE                  0x00000001
 261 #define ST0_EXL                 0x00000002
 262 #define ST0_ERL                 0x00000004
 263 #define ST0_KSU                 0x00000018
 264 #  define KSU_USER              0x00000010
 265 #  define KSU_SUPERVISOR        0x00000008
 266 #  define KSU_KERNEL            0x00000000
 267 #define ST0_UX                  0x00000020
 268 #define ST0_SX                  0x00000040
 269 #define ST0_KX                  0x00000080
 270 #define ST0_DE                  0x00010000
 271 #define ST0_CE                  0x00020000
 272
 273 /*
 274  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 275  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 276  * processors.
 277  */
 278 #define ST0_CO                  0x08000000
 279
 280 /*
 281  * Bitfields in the R[23]000 cp0 status register.
 282  */
 283 #define ST0_IEC                 0x00000001
 284 #define ST0_KUC                 0x00000002
 285 #define ST0_IEP                 0x00000004
 286 #define ST0_KUP                 0x00000008
 287 #define ST0_IEO                 0x00000010
 288 #define ST0_KUO                 0x00000020
 289 /* bits 6 & 7 are reserved on R[23]000 */
 290 #define ST0_ISC                 0x00010000
 291 #define ST0_SWC                 0x00020000
 292 #define ST0_CM                  0x00080000
 293
 294 /*
 295  * Bits specific to the R4640/R4650
 296  */
 297 #define ST0_UM                  (_ULCAST_(1) <<  4)
 298 #define ST0_IL                  (_ULCAST_(1) << 23)
 299 #define ST0_DL                  (_ULCAST_(1) << 24)
 300
 301 /*
 302  * Enable the MIPS MDMX and DSP ASEs
 303  */
 304 #define ST0_MX                  0x01000000
 305
 306 /*
 307  * Status register bits available in all MIPS CPUs.
 308  */
 309 #define ST0_IM                  0x0000ff00
 310 #define  STATUSB_IP0            8
 311 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 312 #define  STATUSB_IP1            9
 313 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 314 #define  STATUSB_IP2            10
 315 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 316 #define  STATUSB_IP3            11
 317 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 318 #define  STATUSB_IP4            12
 319 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 320 #define  STATUSB_IP5            13
 321 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 322 #define  STATUSB_IP6            14
 323 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 324 #define  STATUSB_IP7            15
 325 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 326 #define  STATUSB_IP8            0
 327 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 328 #define  STATUSB_IP9            1
 329 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 330 #define  STATUSB_IP10           2
 331 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 332 #define  STATUSB_IP11           3
 333 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 334 #define  STATUSB_IP12           4
 335 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 336 #define  STATUSB_IP13           5
 337 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 338 #define  STATUSB_IP14           6
 339 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 340 #define  STATUSB_IP15           7
 341 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 342 #define ST0_CH                  0x00040000
 343 #define ST0_NMI                 0x00080000
 344 #define ST0_SR                  0x00100000
 345 #define ST0_TS                  0x00200000
 346 #define ST0_BEV                 0x00400000
 347 #define ST0_RE                  0x02000000
 348 #define ST0_FR                  0x04000000
 349 #define ST0_CU                  0xf0000000
 350 #define ST0_CU0                 0x10000000
 351 #define ST0_CU1                 0x20000000
 352 #define ST0_CU2                 0x40000000
 353 #define ST0_CU3                 0x80000000
 354 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 355
 356 /*
 357  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 358  */
 359 #define INTCTLB_IPFDC           23
 360 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 361 #define INTCTLB_IPPCI           26
 362 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 363 #define INTCTLB_IPTI            29
 364 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 365
 366 /*
 367  * Bitfields and bit numbers in the coprocessor 0 cause register.
 368  *
 369  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 370  */
 371 #define CAUSEB_EXCCODE          2
 372 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 373 #define CAUSEB_IP               8
 374 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 375 #define  CAUSEB_IP0             8
 376 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 377 #define  CAUSEB_IP1             9
 378 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 379 #define  CAUSEB_IP2             10
 380 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 381 #define  CAUSEB_IP3             11
 382 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 383 #define  CAUSEB_IP4             12
 384 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 385 #define  CAUSEB_IP5             13
 386 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 387 #define  CAUSEB_IP6             14
 388 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 389 #define  CAUSEB_IP7             15
 390 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 391 #define CAUSEB_FDCI             21
 392 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 393 #define CAUSEB_IV               23
 394 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 395 #define CAUSEB_PCI              26
 396 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 397 #define CAUSEB_DC               27
 398 #define CAUSEF_DC               (_ULCAST_(1)   << 27)
 399 #define CAUSEB_CE               28
 400 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 401 #define CAUSEB_TI               30
 402 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 403 #define CAUSEB_BD               31
 404 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 405
 406 /*
 407  * Cause.ExcCode trap codes.
 408  */
 409 #define EXCCODE_INT             0       /* Interrupt pending */
 410 #define EXCCODE_MOD             1       /* TLB modified fault */
 411 #define EXCCODE_TLBL            2       /* TLB miss on load or ifetch */
 412 #define EXCCODE_TLBS            3       /* TLB miss on a store */
 413 #define EXCCODE_ADEL            4       /* Address error on a load or ifetch */
 414 #define EXCCODE_ADES            5       /* Address error on a store */
 415 #define EXCCODE_IBE             6       /* Bus error on an ifetch */
 416 #define EXCCODE_DBE             7       /* Bus error on a load or store */
 417 #define EXCCODE_SYS             8       /* System call */
 418 #define EXCCODE_BP              9       /* Breakpoint */
 419 #define EXCCODE_RI              10      /* Reserved instruction exception */
 420 #define EXCCODE_CPU             11      /* Coprocessor unusable */
 421 #define EXCCODE_OV              12      /* Arithmetic overflow */
 422 #define EXCCODE_TR              13      /* Trap instruction */
 423 #define EXCCODE_MSAFPE          14      /* MSA floating point exception */
 424 #define EXCCODE_FPE             15      /* Floating point exception */
 425 #define EXCCODE_TLBRI           19      /* TLB Read-Inhibit exception */
 426 #define EXCCODE_TLBXI           20      /* TLB Execution-Inhibit exception */
 427 #define EXCCODE_MSADIS          21      /* MSA disabled exception */
 428 #define EXCCODE_MDMX            22      /* MDMX unusable exception */
 429 #define EXCCODE_WATCH           23      /* Watch address reference */
 430 #define EXCCODE_MCHECK          24      /* Machine check */
 431 #define EXCCODE_THREAD          25      /* Thread exceptions (MT) */
 432 #define EXCCODE_DSPDIS          26      /* DSP disabled exception */
 433 #define EXCCODE_GE              27      /* Virtualized guest exception (VZ) */
 434
 435 /* Implementation specific trap codes used by MIPS cores */
 436 #define MIPS_EXCCODE_TLBPAR     16      /* TLB parity error exception */
 437
 438 /*
 439  * Bits in the coprocessor 0 config register.
 440  */
 441 /* Generic bits.  */
 442 #define CONF_CM_CACHABLE_NO_WA          0
 443 #define CONF_CM_CACHABLE_WA             1
 444 #define CONF_CM_UNCACHED                2
 445 #define CONF_CM_CACHABLE_NONCOHERENT    3
 446 #define CONF_CM_CACHABLE_CE             4
 447 #define CONF_CM_CACHABLE_COW            5
 448 #define CONF_CM_CACHABLE_CUW            6
 449 #define CONF_CM_CACHABLE_ACCELERATED    7
 450 #define CONF_CM_CMASK                   7
 451 #define CONF_BE                 (_ULCAST_(1) << 15)
 452
 453 /* Bits common to various processors.  */
 454 #define CONF_CU                 (_ULCAST_(1) <<  3)
 455 #define CONF_DB                 (_ULCAST_(1) <<  4)
 456 #define CONF_IB                 (_ULCAST_(1) <<  5)
 457 #define CONF_DC                 (_ULCAST_(7) <<  6)
 458 #define CONF_IC                 (_ULCAST_(7) <<  9)
 459 #define CONF_EB                 (_ULCAST_(1) << 13)
 460 #define CONF_EM                 (_ULCAST_(1) << 14)
 461 #define CONF_SM                 (_ULCAST_(1) << 16)
 462 #define CONF_SC                 (_ULCAST_(1) << 17)
 463 #define CONF_EW                 (_ULCAST_(3) << 18)
 464 #define CONF_EP                 (_ULCAST_(15)<< 24)
 465 #define CONF_EC                 (_ULCAST_(7) << 28)
 466 #define CONF_CM                 (_ULCAST_(1) << 31)
 467
 468 /* Bits specific to the R4xx0.  */
 469 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 470 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 471 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 472
 473 /* Bits specific to the R5000.  */
 474 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 475 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 476
 477 /* Bits specific to the RM7000.  */
 478 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 479 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 480 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 481 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 482 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 483 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 484
 485 /* Bits specific to the R10000.  */
 486 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 487 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 488 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 489 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 490 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 491 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 492 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 493 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 494 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 495 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 496 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 497
 498 /* Bits specific to the VR41xx.  */
 499 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 500 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 501 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 502 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 503 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 504
 505 /* Bits specific to the R30xx.  */
 506 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 507 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 508 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 509 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 510 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 511 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 512 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 513 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 514 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 515
 516 /* Bits specific to the TX49.  */
 517 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 518 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 519 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 520 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 521
 522 /* Bits specific to the MIPS32/64 PRA.  */
 523 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 524 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 525 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 526 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 527 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 528 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 529
 530 /*
 531  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 532  */
 533 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 534 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 535 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 536 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 537 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 538 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 539 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 540 #define MIPS_CONF1_DA_SHF       7
 541 #define MIPS_CONF1_DA_SZ        3
 542 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 543 #define MIPS_CONF1_DL_SHF       10
 544 #define MIPS_CONF1_DL_SZ        3
 545 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 546 #define MIPS_CONF1_DS_SHF       13
 547 #define MIPS_CONF1_DS_SZ        3
 548 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 549 #define MIPS_CONF1_IA_SHF       16
 550 #define MIPS_CONF1_IA_SZ        3
 551 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 552 #define MIPS_CONF1_IL_SHF       19
 553 #define MIPS_CONF1_IL_SZ        3
 554 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 555 #define MIPS_CONF1_IS_SHF       22
 556 #define MIPS_CONF1_IS_SZ        3
 557 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 558 #define MIPS_CONF1_TLBS_SHIFT   (25)
 559 #define MIPS_CONF1_TLBS_SIZE    (6)
 560 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 561
 562 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 563 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 564 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 565 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 566 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 567 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 568 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 569 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 570
 571 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 572 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 573 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 574 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 575 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 576 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 577 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 578 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 579 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 580 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 581 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 582 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 583 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 584 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 585 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 586 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 587 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 588 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 589 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 590 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 591 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 592 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 593 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 594 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 595 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 596 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 597 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 598
 599 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 600 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 601 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 602 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 603 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 604 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 605 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 606 /* bits 10:8 in FTLB-only configurations */
 607 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 608 /* bits 12:8 in VTLB-FTLB only configurations */
 609 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 610 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 611 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 612 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 613 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 614 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << 16)
 615 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 616 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 617 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 618 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 619 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 620
 621 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 622 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 623 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 624 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 625 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 626 #define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
 627 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 628 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 629 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 630 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 631 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 632 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 633
 634 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 635 /* proAptiv FTLB on/off bit */
 636 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 637 /* FTLB probability bits */
 638 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 639
 640 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 641
 642 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 643
 644 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 645 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 646 /* FTLB probability bits for R6 */
 647 #define MIPS_CONF7_FTLBP_SHIFT  (18)
 648
 649 /* MAAR bit definitions */
 650 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 651 #define MIPS_MAAR_ADDR_SHIFT    12
 652 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 653 #define MIPS_MAAR_V             (_ULCAST_(1) << 0)
 654
 655 /* CMGCRBase bit definitions */
 656 #define MIPS_CMGCRB_BASE        11
 657 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 658
 659 /*
 660  * Bits in the MIPS32 Memory Segmentation registers.
 661  */
 662 #define MIPS_SEGCFG_PA_SHIFT    9
 663 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 664 #define MIPS_SEGCFG_AM_SHIFT    4
 665 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 666 #define MIPS_SEGCFG_EU_SHIFT    3
 667 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 668 #define MIPS_SEGCFG_C_SHIFT     0
 669 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 670
 671 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 672 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 673 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 674 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 675 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 676 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 677 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 678
 679 #define MIPS_PWFIELD_GDI_SHIFT  24
 680 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 681 #define MIPS_PWFIELD_UDI_SHIFT  18
 682 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 683 #define MIPS_PWFIELD_MDI_SHIFT  12
 684 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 685 #define MIPS_PWFIELD_PTI_SHIFT  6
 686 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 687 #define MIPS_PWFIELD_PTEI_SHIFT 0
 688 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 689
 690 #define MIPS_PWSIZE_GDW_SHIFT   24
 691 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 692 #define MIPS_PWSIZE_UDW_SHIFT   18
 693 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 694 #define MIPS_PWSIZE_MDW_SHIFT   12
 695 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 696 #define MIPS_PWSIZE_PTW_SHIFT   6
 697 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 698 #define MIPS_PWSIZE_PTEW_SHIFT  0
 699 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 700
 701 #define MIPS_PWCTL_PWEN_SHIFT   31
 702 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 703 #define MIPS_PWCTL_DPH_SHIFT    7
 704 #define MIPS_PWCTL_DPH_MASK     0x00000080
 705 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 706 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 707 #define MIPS_PWCTL_PSN_SHIFT    0
 708 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 709
 710 /* CDMMBase register bit definitions */
 711 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 712 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 713 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 714 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 715 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 716 #define MIPS_CDMMBASE_ADDR_START 15
 717
 718 /*
 719  * Bitfields in the TX39 family CP0 Configuration Register 3
 720  */
 721 #define TX39_CONF_ICS_SHIFT     19
 722 #define TX39_CONF_ICS_MASK      0x00380000
 723 #define TX39_CONF_ICS_1KB       0x00000000
 724 #define TX39_CONF_ICS_2KB       0x00080000
 725 #define TX39_CONF_ICS_4KB       0x00100000
 726 #define TX39_CONF_ICS_8KB       0x00180000
 727 #define TX39_CONF_ICS_16KB      0x00200000
 728
 729 #define TX39_CONF_DCS_SHIFT     16
 730 #define TX39_CONF_DCS_MASK      0x00070000
 731 #define TX39_CONF_DCS_1KB       0x00000000
 732 #define TX39_CONF_DCS_2KB       0x00010000
 733 #define TX39_CONF_DCS_4KB       0x00020000
 734 #define TX39_CONF_DCS_8KB       0x00030000
 735 #define TX39_CONF_DCS_16KB      0x00040000
 736
 737 #define TX39_CONF_CWFON         0x00004000
 738 #define TX39_CONF_WBON          0x00002000
 739 #define TX39_CONF_RF_SHIFT      10
 740 #define TX39_CONF_RF_MASK       0x00000c00
 741 #define TX39_CONF_DOZE          0x00000200
 742 #define TX39_CONF_HALT          0x00000100
 743 #define TX39_CONF_LOCK          0x00000080
 744 #define TX39_CONF_ICE           0x00000020
 745 #define TX39_CONF_DCE           0x00000010
 746 #define TX39_CONF_IRSIZE_SHIFT  2
 747 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 748 #define TX39_CONF_DRSIZE_SHIFT  0
 749 #define TX39_CONF_DRSIZE_MASK   0x00000003
 750
 751 /*
 752  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 753  */
 754 /* Disable Branch Target Address Cache */
 755 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
 756 /* Enable Branch Prediction Global History */
 757 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
 758 /* Disable Branch Return Cache */
 759 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
 760
 761 /*
 762  * Coprocessor 1 (FPU) register names
 763  */
 764 #define CP1_REVISION    $0
 765 #define CP1_UFR         $1
 766 #define CP1_UNFR        $4
 767 #define CP1_FCCR        $25
 768 #define CP1_FEXR        $26
 769 #define CP1_FENR        $28
 770 #define CP1_STATUS      $31
 771
 772
 773 /*
 774  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 775  */
 776 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 777 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 778 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 779 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 780 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 781 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 782 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 783 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
 784 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
 785 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
 786
 787 /*
 788  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
 789  */
 790 #define MIPS_FCCR_CONDX_S       0
 791 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
 792 #define MIPS_FCCR_COND0_S       0
 793 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
 794 #define MIPS_FCCR_COND1_S       1
 795 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
 796 #define MIPS_FCCR_COND2_S       2
 797 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
 798 #define MIPS_FCCR_COND3_S       3
 799 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
 800 #define MIPS_FCCR_COND4_S       4
 801 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
 802 #define MIPS_FCCR_COND5_S       5
 803 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
 804 #define MIPS_FCCR_COND6_S       6
 805 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
 806 #define MIPS_FCCR_COND7_S       7
 807 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
 808
 809 /*
 810  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
 811  */
 812 #define MIPS_FENR_FS_S          2
 813 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
 814
 815 /*
 816  * FPU Status Register Values
 817  */
 818 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
 819 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
 820
 821 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
 822 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
 823
 824 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
 825 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
 826 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
 827 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
 828 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
 829 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
 830 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
 831 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
 832 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
 833 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
 834 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
 835 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
 836 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
 837 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
 838 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
 839 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
 840
 841 /*
 842  * Bits 22:20 of the FPU Status Register will be read as 0,
 843  * and should be written as zero.
 844  */
 845 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
 846
 847 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
 848 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
 849
 850 /*
 851  * X the exception cause indicator
 852  * E the exception enable
 853  * S the sticky/flag bit
 854 */
 855 #define FPU_CSR_ALL_X   0x0003f000
 856 #define FPU_CSR_UNI_X   0x00020000
 857 #define FPU_CSR_INV_X   0x00010000
 858 #define FPU_CSR_DIV_X   0x00008000
 859 #define FPU_CSR_OVF_X   0x00004000
 860 #define FPU_CSR_UDF_X   0x00002000
 861 #define FPU_CSR_INE_X   0x00001000
 862
 863 #define FPU_CSR_ALL_E   0x00000f80
 864 #define FPU_CSR_INV_E   0x00000800
 865 #define FPU_CSR_DIV_E   0x00000400
 866 #define FPU_CSR_OVF_E   0x00000200
 867 #define FPU_CSR_UDF_E   0x00000100
 868 #define FPU_CSR_INE_E   0x00000080
 869
 870 #define FPU_CSR_ALL_S   0x0000007c
 871 #define FPU_CSR_INV_S   0x00000040
 872 #define FPU_CSR_DIV_S   0x00000020
 873 #define FPU_CSR_OVF_S   0x00000010
 874 #define FPU_CSR_UDF_S   0x00000008
 875 #define FPU_CSR_INE_S   0x00000004
 876
 877 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
 878 #define FPU_CSR_RM      0x00000003
 879 #define FPU_CSR_RN      0x0     /* nearest */
 880 #define FPU_CSR_RZ      0x1     /* towards zero */
 881 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 882 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 883
 884
 885 #ifndef __ASSEMBLY__
 886
 887 /*
 888  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
 889  */
 890 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
 891     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
 892 #define get_isa16_mode(x)               ((x) & 0x1)
 893 #define msk_isa16_mode(x)               ((x) & ~0x1)
 894 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
 895 #else
 896 #define get_isa16_mode(x)               0
 897 #define msk_isa16_mode(x)               (x)
 898 #define set_isa16_mode(x)               do { } while(0)
 899 #endif
 900
 901 /*
 902  * microMIPS instructions can be 16-bit or 32-bit in length. This
 903  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
 904  */
 905 static inline int mm_insn_16bit(u16 insn)
 906 {
 907         u16 opcode = (insn >> 10) & 0x7;
 908
 909         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
 910 }
 911
 912 /*
 913  * TLB Invalidate Flush
 914  */
 915 static inline void tlbinvf(void)
 916 {
 917         __asm__ __volatile__(
 918                 ".set push\n\t"
 919                 ".set noreorder\n\t"
 920                 ".word 0x42000004\n\t" /* tlbinvf */
 921                 ".set pop");
 922 }
 923
 924
 925 /*
 926  * Functions to access the R10000 performance counters.  These are basically
 927  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
 928  * performance counter number encoded into bits 1 ... 5 of the instruction.
 929  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
 930  * disassembler these will look like an access to sel 0 or 1.
 931  */
 932 #define read_r10k_perf_cntr(counter)                            \
 933 ({                                                              \
 934         unsigned int __res;                                     \
 935         __asm__ __volatile__(                                   \
 936         "mfpc\t%0, %1"                                          \
 937         : "=r" (__res)                                          \
 938         : "i" (counter));                                       \
 939                                                                 \
 940         __res;                                                  \
 941 })
 942
 943 #define write_r10k_perf_cntr(counter,val)                       \
 944 do {                                                            \
 945         __asm__ __volatile__(                                   \
 946         "mtpc\t%0, %1"                                          \
 947         :                                                       \
 948         : "r" (val), "i" (counter));                            \
 949 } while (0)
 950
 951 #define read_r10k_perf_event(counter)                           \
 952 ({                                                              \
 953         unsigned int __res;                                     \
 954         __asm__ __volatile__(                                   \
 955         "mfps\t%0, %1"                                          \
 956         : "=r" (__res)                                          \
 957         : "i" (counter));                                       \
 958                                                                 \
 959         __res;                                                  \
 960 })
 961
 962 #define write_r10k_perf_cntl(counter,val)                       \
 963 do {                                                            \
 964         __asm__ __volatile__(                                   \
 965         "mtps\t%0, %1"                                          \
 966         :                                                       \
 967         : "r" (val), "i" (counter));                            \
 968 } while (0)
 969
 970
 971 /*
 972  * Macros to access the system control coprocessor
 973  */
 974
 975 #define __read_32bit_c0_register(source, sel)                           \
 976 ({ unsigned int __res;                                                  \
 977         if (sel == 0)                                                   \
 978                 __asm__ __volatile__(                                   \
 979                         "mfc0\t%0, " #source "\n\t"                     \
 980                         : "=r" (__res));                                \
 981         else                                                            \
 982                 __asm__ __volatile__(                                   \
 983                         ".set\tmips32\n\t"                              \
 984                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
 985                         ".set\tmips0\n\t"                               \
 986                         : "=r" (__res));                                \
 987         __res;                                                          \
 988 })
 989
 990 #define __read_64bit_c0_register(source, sel)                           \
 991 ({ unsigned long long __res;                                            \
 992         if (sizeof(unsigned long) == 4)                                 \
 993                 __res = __read_64bit_c0_split(source, sel);             \
 994         else if (sel == 0)                                              \
 995                 __asm__ __volatile__(                                   \
 996                         ".set\tmips3\n\t"                               \
 997                         "dmfc0\t%0, " #source "\n\t"                    \
 998                         ".set\tmips0"                                   \
 999                         : "=r" (__res));                                \
1000         else                                                            \
1001                 __asm__ __volatile__(                                   \
1002                         ".set\tmips64\n\t"                              \
1003                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
1004                         ".set\tmips0"                                   \
1005                         : "=r" (__res));                                \
1006         __res;                                                          \
1007 })
1008
1009 #define __write_32bit_c0_register(register, sel, value)                 \
1010 do {                                                                    \
1011         if (sel == 0)                                                   \
1012                 __asm__ __volatile__(                                   \
1013                         "mtc0\t%z0, " #register "\n\t"                  \
1014                         : : "Jr" ((unsigned int)(value)));              \
1015         else                                                            \
1016                 __asm__ __volatile__(                                   \
1017                         ".set\tmips32\n\t"                              \
1018                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
1019                         ".set\tmips0"                                   \
1020                         : : "Jr" ((unsigned int)(value)));              \
1021 } while (0)
1022
1023 #define __write_64bit_c0_register(register, sel, value)                 \
1024 do {                                                                    \
1025         if (sizeof(unsigned long) == 4)                                 \
1026                 __write_64bit_c0_split(register, sel, value);           \
1027         else if (sel == 0)                                              \
1028                 __asm__ __volatile__(                                   \
1029                         ".set\tmips3\n\t"                               \
1030                         "dmtc0\t%z0, " #register "\n\t"                 \
1031                         ".set\tmips0"                                   \
1032                         : : "Jr" (value));                              \
1033         else                                                            \
1034                 __asm__ __volatile__(                                   \
1035                         ".set\tmips64\n\t"                              \
1036                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
1037                         ".set\tmips0"                                   \
1038                         : : "Jr" (value));                              \
1039 } while (0)
1040
1041 #define __read_ulong_c0_register(reg, sel)                              \
1042         ((sizeof(unsigned long) == 4) ?                                 \
1043         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1044         (unsigned long) __read_64bit_c0_register(reg, sel))
1045
1046 #define __write_ulong_c0_register(reg, sel, val)                        \
1047 do {                                                                    \
1048         if (sizeof(unsigned long) == 4)                                 \
1049                 __write_32bit_c0_register(reg, sel, val);               \
1050         else                                                            \
1051                 __write_64bit_c0_register(reg, sel, val);               \
1052 } while (0)
1053
1054 /*
1055  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1056  */
1057 #define __read_32bit_c0_ctrl_register(source)                           \
1058 ({ unsigned int __res;                                                  \
1059         __asm__ __volatile__(                                           \
1060                 "cfc0\t%0, " #source "\n\t"                             \
1061                 : "=r" (__res));                                        \
1062         __res;                                                          \
1063 })
1064
1065 #define __write_32bit_c0_ctrl_register(register, value)                 \
1066 do {                                                                    \
1067         __asm__ __volatile__(                                           \
1068                 "ctc0\t%z0, " #register "\n\t"                          \
1069                 : : "Jr" ((unsigned int)(value)));                      \
1070 } while (0)
1071
1072 /*
1073  * These versions are only needed for systems with more than 38 bits of
1074  * physical address space running the 32-bit kernel.  That's none atm :-)
1075  */
1076 #define __read_64bit_c0_split(source, sel)                              \
1077 ({                                                                      \
1078         unsigned long long __val;                                       \
1079         unsigned long __flags;                                          \
1080                                                                         \
1081         local_irq_save(__flags);                                        \
1082         if (sel == 0)                                                   \
1083                 __asm__ __volatile__(                                   \
1084                         ".set\tmips64\n\t"                              \
1085                         "dmfc0\t%M0, " #source "\n\t"                   \
1086                         "dsll\t%L0, %M0, 32\n\t"                        \
1087                         "dsra\t%M0, %M0, 32\n\t"                        \
1088                         "dsra\t%L0, %L0, 32\n\t"                        \
1089                         ".set\tmips0"                                   \
1090                         : "=r" (__val));                                \
1091         else                                                            \
1092                 __asm__ __volatile__(                                   \
1093                         ".set\tmips64\n\t"                              \
1094                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
1095                         "dsll\t%L0, %M0, 32\n\t"                        \
1096                         "dsra\t%M0, %M0, 32\n\t"                        \
1097                         "dsra\t%L0, %L0, 32\n\t"                        \
1098                         ".set\tmips0"                                   \
1099                         : "=r" (__val));                                \
1100         local_irq_restore(__flags);                                     \
1101                                                                         \
1102         __val;                                                          \
1103 })
1104
1105 #define __write_64bit_c0_split(source, sel, val)                        \
1106 do {                                                                    \
1107         unsigned long __flags;                                          \
1108                                                                         \
1109         local_irq_save(__flags);                                        \
1110         if (sel == 0)                                                   \
1111                 __asm__ __volatile__(                                   \
1112                         ".set\tmips64\n\t"                              \
1113                         "dsll\t%L0, %L0, 32\n\t"                        \
1114                         "dsrl\t%L0, %L0, 32\n\t"                        \
1115                         "dsll\t%M0, %M0, 32\n\t"                        \
1116                         "or\t%L0, %L0, %M0\n\t"                         \
1117                         "dmtc0\t%L0, " #source "\n\t"                   \
1118                         ".set\tmips0"                                   \
1119                         : : "r" (val));                                 \
1120         else                                                            \
1121                 __asm__ __volatile__(                                   \
1122                         ".set\tmips64\n\t"                              \
1123                         "dsll\t%L0, %L0, 32\n\t"                        \
1124                         "dsrl\t%L0, %L0, 32\n\t"                        \
1125                         "dsll\t%M0, %M0, 32\n\t"                        \
1126                         "or\t%L0, %L0, %M0\n\t"                         \
1127                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1128                         ".set\tmips0"                                   \
1129                         : : "r" (val));                                 \
1130         local_irq_restore(__flags);                                     \
1131 } while (0)
1132
1133 #define __readx_32bit_c0_register(source)                               \
1134 ({                                                                      \
1135         unsigned int __res;                                             \
1136                                                                         \
1137         __asm__ __volatile__(                                           \
1138         "       .set    push                                    \n"     \
1139         "       .set    noat                                    \n"     \
1140         "       .set    mips32r2                                \n"     \
1141         "       .insn                                           \n"     \
1142         "       # mfhc0 $1, %1                                  \n"     \
1143         "       .word   (0x40410000 | ((%1 & 0x1f) << 11))      \n"     \
1144         "       move    %0, $1                                  \n"     \
1145         "       .set    pop                                     \n"     \
1146         : "=r" (__res)                                                  \
1147         : "i" (source));                                                \
1148         __res;                                                          \
1149 })
1150
1151 #define __writex_32bit_c0_register(register, value)                     \
1152 do {                                                                    \
1153         __asm__ __volatile__(                                           \
1154         "       .set    push                                    \n"     \
1155         "       .set    noat                                    \n"     \
1156         "       .set    mips32r2                                \n"     \
1157         "       move    $1, %0                                  \n"     \
1158         "       # mthc0 $1, %1                                  \n"     \
1159         "       .insn                                           \n"     \
1160         "       .word   (0x40c10000 | ((%1 & 0x1f) << 11))      \n"     \
1161         "       .set    pop                                     \n"     \
1162         :                                                               \
1163         : "r" (value), "i" (register));                                 \
1164 } while (0)
1165
1166 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1167 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1168
1169 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1170 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1171
1172 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1173 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1174
1175 #define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
1176 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1177
1178 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1179 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1180
1181 #define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
1182 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1183
1184 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1185 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1186
1187 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1188 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1189
1190 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1191 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1192
1193 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1194 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1195
1196 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1197 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1198
1199 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1200 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1201
1202 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1203
1204 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1205 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1206
1207 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1208 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1209
1210 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1211 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1212
1213 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1214 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1215
1216 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1217 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1218
1219 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1220 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1221
1222 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1223 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1224
1225 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1226 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1227
1228 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1229 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1230
1231 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1232
1233 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1234
1235 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1236 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1237
1238 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1239 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1240
1241 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1242
1243 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1244
1245 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1246 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1247 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1248 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1249 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1250 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1251 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1252 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1253 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1254 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1255 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1256 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1257 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1258 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1259 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1260 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1261
1262 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1263 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1264 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1265 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1266 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1267 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1268
1269 /*
1270  * The WatchLo register.  There may be up to 8 of them.
1271  */
1272 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1273 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1274 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1275 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1276 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1277 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1278 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1279 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1280 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1281 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1282 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1283 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1284 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1285 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1286 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1287 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1288
1289 /*
1290  * The WatchHi register.  There may be up to 8 of them.
1291  */
1292 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1293 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1294 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1295 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1296 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1297 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1298 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1299 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1300
1301 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1302 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1303 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1304 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1305 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1306 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1307 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1308 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1309
1310 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1311 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1312
1313 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1314 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1315
1316 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1317 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1318
1319 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1320 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1321
1322 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1323 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1324 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1325
1326 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1327 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1328
1329 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1330 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1331
1332 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1333 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1334
1335 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1336 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1337
1338 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1339 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1340
1341 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1342 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1343
1344 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1345 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1346
1347 /*
1348  * MIPS32 / MIPS64 performance counters
1349  */
1350 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1351 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1352 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1353 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1354 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1355 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1356 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1357 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1358 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1359 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1360 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1361 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1362 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1363 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1364 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1365 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1366 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1367 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1368 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1369 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1370 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1371 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1372 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1373 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1374
1375 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1376 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1377
1378 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1379 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1380
1381 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1382
1383 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1384 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1385
1386 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1387 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1388
1389 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1390 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1391
1392 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1393 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1394
1395 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1396 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1397
1398 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1399 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1400
1401 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1402 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1403
1404 /* MIPSR2 */
1405 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1406 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1407
1408 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1409 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1410
1411 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1412 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1413
1414 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1415 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1416
1417 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1418 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1419
1420 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1421 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1422
1423 /* MIPSR3 */
1424 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1425 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1426
1427 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1428 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1429
1430 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1431 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1432
1433 /* Hardware Page Table Walker */
1434 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1435 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1436
1437 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1438 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1439
1440 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1441 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1442
1443 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1444 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1445
1446 /* Cavium OCTEON (cnMIPS) */
1447 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1448 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1449
1450 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1451 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1452
1453 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1454 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1455 /*
1456  * The cacheerr registers are not standardized.  On OCTEON, they are
1457  * 64 bits wide.
1458  */
1459 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1460 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1461
1462 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1463 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1464
1465 /* BMIPS3300 */
1466 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1467 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1468
1469 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1470 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1471
1472 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1473 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1474
1475 /* BMIPS43xx */
1476 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1477 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1478
1479 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1480 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1481
1482 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1483 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1484
1485 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1486 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1487
1488 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1489 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1490
1491 /* BMIPS5000 */
1492 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1493 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1494
1495 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1496 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1497
1498 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1499 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1500
1501 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1502 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1503
1504 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1505 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1506
1507 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1508 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1509
1510 /*
1511  * Macros to access the floating point coprocessor control registers
1512  */
1513 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
1514 ({                                                                      \
1515         unsigned int __res;                                             \
1516                                                                         \
1517         __asm__ __volatile__(                                           \
1518         "       .set    push                                    \n"     \
1519         "       .set    reorder                                 \n"     \
1520         "       # gas fails to assemble cfc1 for some archs,    \n"     \
1521         "       # like Octeon.                                  \n"     \
1522         "       .set    mips1                                   \n"     \
1523         "       "STR(gas_hardfloat)"                            \n"     \
1524         "       cfc1    %0,"STR(source)"                        \n"     \
1525         "       .set    pop                                     \n"     \
1526         : "=r" (__res));                                                \
1527         __res;                                                          \
1528 })
1529
1530 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
1531 do {                                                                    \
1532         __asm__ __volatile__(                                           \
1533         "       .set    push                                    \n"     \
1534         "       .set    reorder                                 \n"     \
1535         "       "STR(gas_hardfloat)"                            \n"     \
1536         "       ctc1    %0,"STR(dest)"                          \n"     \
1537         "       .set    pop                                     \n"     \
1538         : : "r" (val));                                                 \
1539 } while (0)
1540
1541 #ifdef GAS_HAS_SET_HARDFLOAT
1542 #define read_32bit_cp1_register(source)                                 \
1543         _read_32bit_cp1_register(source, .set hardfloat)
1544 #define write_32bit_cp1_register(dest, val)                             \
1545         _write_32bit_cp1_register(dest, val, .set hardfloat)
1546 #else
1547 #define read_32bit_cp1_register(source)                                 \
1548         _read_32bit_cp1_register(source, )
1549 #define write_32bit_cp1_register(dest, val)                             \
1550         _write_32bit_cp1_register(dest, val, )
1551 #endif
1552
1553 #ifdef HAVE_AS_DSP
1554 #define rddsp(mask)                                                     \
1555 ({                                                                      \
1556         unsigned int __dspctl;                                          \
1557                                                                         \
1558         __asm__ __volatile__(                                           \
1559         "       .set push                                       \n"     \
1560         "       .set dsp                                        \n"     \
1561         "       rddsp   %0, %x1                                 \n"     \
1562         "       .set pop                                        \n"     \
1563         : "=r" (__dspctl)                                               \
1564         : "i" (mask));                                                  \
1565         __dspctl;                                                       \
1566 })
1567
1568 #define wrdsp(val, mask)                                                \
1569 do {                                                                    \
1570         __asm__ __volatile__(                                           \
1571         "       .set push                                       \n"     \
1572         "       .set dsp                                        \n"     \
1573         "       wrdsp   %0, %x1                                 \n"     \
1574         "       .set pop                                        \n"     \
1575         :                                                               \
1576         : "r" (val), "i" (mask));                                       \
1577 } while (0)
1578
1579 #define mflo0()                                                         \
1580 ({                                                                      \
1581         long mflo0;                                                     \
1582         __asm__(                                                        \
1583         "       .set push                                       \n"     \
1584         "       .set dsp                                        \n"     \
1585         "       mflo %0, $ac0                                   \n"     \
1586         "       .set pop                                        \n"     \
1587         : "=r" (mflo0));                                                \
1588         mflo0;                                                          \
1589 })
1590
1591 #define mflo1()                                                         \
1592 ({                                                                      \
1593         long mflo1;                                                     \
1594         __asm__(                                                        \
1595         "       .set push                                       \n"     \
1596         "       .set dsp                                        \n"     \
1597         "       mflo %0, $ac1                                   \n"     \
1598         "       .set pop                                        \n"     \
1599         : "=r" (mflo1));                                                \
1600         mflo1;                                                          \
1601 })
1602
1603 #define mflo2()                                                         \
1604 ({                                                                      \
1605         long mflo2;                                                     \
1606         __asm__(                                                        \
1607         "       .set push                                       \n"     \
1608         "       .set dsp                                        \n"     \
1609         "       mflo %0, $ac2                                   \n"     \
1610         "       .set pop                                        \n"     \
1611         : "=r" (mflo2));                                                \
1612         mflo2;                                                          \
1613 })
1614
1615 #define mflo3()                                                         \
1616 ({                                                                      \
1617         long mflo3;                                                     \
1618         __asm__(                                                        \
1619         "       .set push                                       \n"     \
1620         "       .set dsp                                        \n"     \
1621         "       mflo %0, $ac3                                   \n"     \
1622         "       .set pop                                        \n"     \
1623         : "=r" (mflo3));                                                \
1624         mflo3;                                                          \
1625 })
1626
1627 #define mfhi0()                                                         \
1628 ({                                                                      \
1629         long mfhi0;                                                     \
1630         __asm__(                                                        \
1631         "       .set push                                       \n"     \
1632         "       .set dsp                                        \n"     \
1633         "       mfhi %0, $ac0                                   \n"     \
1634         "       .set pop                                        \n"     \
1635         : "=r" (mfhi0));                                                \
1636         mfhi0;                                                          \
1637 })
1638
1639 #define mfhi1()                                                         \
1640 ({                                                                      \
1641         long mfhi1;                                                     \
1642         __asm__(                                                        \
1643         "       .set push                                       \n"     \
1644         "       .set dsp                                        \n"     \
1645         "       mfhi %0, $ac1                                   \n"     \
1646         "       .set pop                                        \n"     \
1647         : "=r" (mfhi1));                                                \
1648         mfhi1;                                                          \
1649 })
1650
1651 #define mfhi2()                                                         \
1652 ({                                                                      \
1653         long mfhi2;                                                     \
1654         __asm__(                                                        \
1655         "       .set push                                       \n"     \
1656         "       .set dsp                                        \n"     \
1657         "       mfhi %0, $ac2                                   \n"     \
1658         "       .set pop                                        \n"     \
1659         : "=r" (mfhi2));                                                \
1660         mfhi2;                                                          \
1661 })
1662
1663 #define mfhi3()                                                         \
1664 ({                                                                      \
1665         long mfhi3;                                                     \
1666         __asm__(                                                        \
1667         "       .set push                                       \n"     \
1668         "       .set dsp                                        \n"     \
1669         "       mfhi %0, $ac3                                   \n"     \
1670         "       .set pop                                        \n"     \
1671         : "=r" (mfhi3));                                                \
1672         mfhi3;                                                          \
1673 })
1674
1675
1676 #define mtlo0(x)                                                        \
1677 ({                                                                      \
1678         __asm__(                                                        \
1679         "       .set push                                       \n"     \
1680         "       .set dsp                                        \n"     \
1681         "       mtlo %0, $ac0                                   \n"     \
1682         "       .set pop                                        \n"     \
1683         :                                                               \
1684         : "r" (x));                                                     \
1685 })
1686
1687 #define mtlo1(x)                                                        \
1688 ({                                                                      \
1689         __asm__(                                                        \
1690         "       .set push                                       \n"     \
1691         "       .set dsp                                        \n"     \
1692         "       mtlo %0, $ac1                                   \n"     \
1693         "       .set pop                                        \n"     \
1694         :                                                               \
1695         : "r" (x));                                                     \
1696 })
1697
1698 #define mtlo2(x)                                                        \
1699 ({                                                                      \
1700         __asm__(                                                        \
1701         "       .set push                                       \n"     \
1702         "       .set dsp                                        \n"     \
1703         "       mtlo %0, $ac2                                   \n"     \
1704         "       .set pop                                        \n"     \
1705         :                                                               \
1706         : "r" (x));                                                     \
1707 })
1708
1709 #define mtlo3(x)                                                        \
1710 ({                                                                      \
1711         __asm__(                                                        \
1712         "       .set push                                       \n"     \
1713         "       .set dsp                                        \n"     \
1714         "       mtlo %0, $ac3                                   \n"     \
1715         "       .set pop                                        \n"     \
1716         :                                                               \
1717         : "r" (x));                                                     \
1718 })
1719
1720 #define mthi0(x)                                                        \
1721 ({                                                                      \
1722         __asm__(                                                        \
1723         "       .set push                                       \n"     \
1724         "       .set dsp                                        \n"     \
1725         "       mthi %0, $ac0                                   \n"     \
1726         "       .set pop                                        \n"     \
1727         :                                                               \
1728         : "r" (x));                                                     \
1729 })
1730
1731 #define mthi1(x)                                                        \
1732 ({                                                                      \
1733         __asm__(                                                        \
1734         "       .set push                                       \n"     \
1735         "       .set dsp                                        \n"     \
1736         "       mthi %0, $ac1                                   \n"     \
1737         "       .set pop                                        \n"     \
1738         :                                                               \
1739         : "r" (x));                                                     \
1740 })
1741
1742 #define mthi2(x)                                                        \
1743 ({                                                                      \
1744         __asm__(                                                        \
1745         "       .set push                                       \n"     \
1746         "       .set dsp                                        \n"     \
1747         "       mthi %0, $ac2                                   \n"     \
1748         "       .set pop                                        \n"     \
1749         :                                                               \
1750         : "r" (x));                                                     \
1751 })
1752
1753 #define mthi3(x)                                                        \
1754 ({                                                                      \
1755         __asm__(                                                        \
1756         "       .set push                                       \n"     \
1757         "       .set dsp                                        \n"     \
1758         "       mthi %0, $ac3                                   \n"     \
1759         "       .set pop                                        \n"     \
1760         :                                                               \
1761         : "r" (x));                                                     \
1762 })
1763
1764 #else
1765
1766 #ifdef CONFIG_CPU_MICROMIPS
1767 #define rddsp(mask)                                                     \
1768 ({                                                                      \
1769         unsigned int __res;                                             \
1770                                                                         \
1771         __asm__ __volatile__(                                           \
1772         "       .set    push                                    \n"     \
1773         "       .set    noat                                    \n"     \
1774         "       # rddsp $1, %x1                                 \n"     \
1775         "       .hword  ((0x0020067c | (%x1 << 14)) >> 16)      \n"     \
1776         "       .hword  ((0x0020067c | (%x1 << 14)) & 0xffff)   \n"     \
1777         "       move    %0, $1                                  \n"     \
1778         "       .set    pop                                     \n"     \
1779         : "=r" (__res)                                                  \
1780         : "i" (mask));                                                  \
1781         __res;                                                          \
1782 })
1783
1784 #define wrdsp(val, mask)                                                \
1785 do {                                                                    \
1786         __asm__ __volatile__(                                           \
1787         "       .set    push                                    \n"     \
1788         "       .set    noat                                    \n"     \
1789         "       move    $1, %0                                  \n"     \
1790         "       # wrdsp $1, %x1                                 \n"     \
1791         "       .hword  ((0x0020167c | (%x1 << 14)) >> 16)      \n"     \
1792         "       .hword  ((0x0020167c | (%x1 << 14)) & 0xffff)   \n"     \
1793         "       .set    pop                                     \n"     \
1794         :                                                               \
1795         : "r" (val), "i" (mask));                                       \
1796 } while (0)
1797
1798 #define _umips_dsp_mfxxx(ins)                                           \
1799 ({                                                                      \
1800         unsigned long __treg;                                           \
1801                                                                         \
1802         __asm__ __volatile__(                                           \
1803         "       .set    push                                    \n"     \
1804         "       .set    noat                                    \n"     \
1805         "       .hword  0x0001                                  \n"     \
1806         "       .hword  %x1                                     \n"     \
1807         "       move    %0, $1                                  \n"     \
1808         "       .set    pop                                     \n"     \
1809         : "=r" (__treg)                                                 \
1810         : "i" (ins));                                                   \
1811         __treg;                                                         \
1812 })
1813
1814 #define _umips_dsp_mtxxx(val, ins)                                      \
1815 do {                                                                    \
1816         __asm__ __volatile__(                                           \
1817         "       .set    push                                    \n"     \
1818         "       .set    noat                                    \n"     \
1819         "       move    $1, %0                                  \n"     \
1820         "       .hword  0x0001                                  \n"     \
1821         "       .hword  %x1                                     \n"     \
1822         "       .set    pop                                     \n"     \
1823         :                                                               \
1824         : "r" (val), "i" (ins));                                        \
1825 } while (0)
1826
1827 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1828 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1829
1830 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1831 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1832
1833 #define mflo0() _umips_dsp_mflo(0)
1834 #define mflo1() _umips_dsp_mflo(1)
1835 #define mflo2() _umips_dsp_mflo(2)
1836 #define mflo3() _umips_dsp_mflo(3)
1837
1838 #define mfhi0() _umips_dsp_mfhi(0)
1839 #define mfhi1() _umips_dsp_mfhi(1)
1840 #define mfhi2() _umips_dsp_mfhi(2)
1841 #define mfhi3() _umips_dsp_mfhi(3)
1842
1843 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1844 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1845 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1846 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1847
1848 #define mthi0(x) _umips_dsp_mthi(x, 0)
1849 #define mthi1(x) _umips_dsp_mthi(x, 1)
1850 #define mthi2(x) _umips_dsp_mthi(x, 2)
1851 #define mthi3(x) _umips_dsp_mthi(x, 3)
1852
1853 #else  /* !CONFIG_CPU_MICROMIPS */
1854 #define rddsp(mask)                                                     \
1855 ({                                                                      \
1856         unsigned int __res;                                             \
1857                                                                         \
1858         __asm__ __volatile__(                                           \
1859         "       .set    push                            \n"             \
1860         "       .set    noat                            \n"             \
1861         "       # rddsp $1, %x1                         \n"             \
1862         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1863         "       move    %0, $1                          \n"             \
1864         "       .set    pop                             \n"             \
1865         : "=r" (__res)                                                  \
1866         : "i" (mask));                                                  \
1867         __res;                                                          \
1868 })
1869
1870 #define wrdsp(val, mask)                                                \
1871 do {                                                                    \
1872         __asm__ __volatile__(                                           \
1873         "       .set    push                                    \n"     \
1874         "       .set    noat                                    \n"     \
1875         "       move    $1, %0                                  \n"     \
1876         "       # wrdsp $1, %x1                                 \n"     \
1877         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1878         "       .set    pop                                     \n"     \
1879         :                                                               \
1880         : "r" (val), "i" (mask));                                       \
1881 } while (0)
1882
1883 #define _dsp_mfxxx(ins)                                                 \
1884 ({                                                                      \
1885         unsigned long __treg;                                           \
1886                                                                         \
1887         __asm__ __volatile__(                                           \
1888         "       .set    push                                    \n"     \
1889         "       .set    noat                                    \n"     \
1890         "       .word   (0x00000810 | %1)                       \n"     \
1891         "       move    %0, $1                                  \n"     \
1892         "       .set    pop                                     \n"     \
1893         : "=r" (__treg)                                                 \
1894         : "i" (ins));                                                   \
1895         __treg;                                                         \
1896 })
1897
1898 #define _dsp_mtxxx(val, ins)                                            \
1899 do {                                                                    \
1900         __asm__ __volatile__(                                           \
1901         "       .set    push                                    \n"     \
1902         "       .set    noat                                    \n"     \
1903         "       move    $1, %0                                  \n"     \
1904         "       .word   (0x00200011 | %1)                       \n"     \
1905         "       .set    pop                                     \n"     \
1906         :                                                               \
1907         : "r" (val), "i" (ins));                                        \
1908 } while (0)
1909
1910 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1911 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1912
1913 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1914 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1915
1916 #define mflo0() _dsp_mflo(0)
1917 #define mflo1() _dsp_mflo(1)
1918 #define mflo2() _dsp_mflo(2)
1919 #define mflo3() _dsp_mflo(3)
1920
1921 #define mfhi0() _dsp_mfhi(0)
1922 #define mfhi1() _dsp_mfhi(1)
1923 #define mfhi2() _dsp_mfhi(2)
1924 #define mfhi3() _dsp_mfhi(3)
1925
1926 #define mtlo0(x) _dsp_mtlo(x, 0)
1927 #define mtlo1(x) _dsp_mtlo(x, 1)
1928 #define mtlo2(x) _dsp_mtlo(x, 2)
1929 #define mtlo3(x) _dsp_mtlo(x, 3)
1930
1931 #define mthi0(x) _dsp_mthi(x, 0)
1932 #define mthi1(x) _dsp_mthi(x, 1)
1933 #define mthi2(x) _dsp_mthi(x, 2)
1934 #define mthi3(x) _dsp_mthi(x, 3)
1935
1936 #endif /* CONFIG_CPU_MICROMIPS */
1937 #endif
1938
1939 /*
1940  * TLB operations.
1941  *
1942  * It is responsibility of the caller to take care of any TLB hazards.
1943  */
1944 static inline void tlb_probe(void)
1945 {
1946         __asm__ __volatile__(
1947                 ".set noreorder\n\t"
1948                 "tlbp\n\t"
1949                 ".set reorder");
1950 }
1951
1952 static inline void tlb_read(void)
1953 {
1954 #if MIPS34K_MISSED_ITLB_WAR
1955         int res = 0;
1956
1957         __asm__ __volatile__(
1958         "       .set    push                                    \n"
1959         "       .set    noreorder                               \n"
1960         "       .set    noat                                    \n"
1961         "       .set    mips32r2                                \n"
1962         "       .word   0x41610001              # dvpe $1       \n"
1963         "       move    %0, $1                                  \n"
1964         "       ehb                                             \n"
1965         "       .set    pop                                     \n"
1966         : "=r" (res));
1967
1968         instruction_hazard();
1969 #endif
1970
1971         __asm__ __volatile__(
1972                 ".set noreorder\n\t"
1973                 "tlbr\n\t"
1974                 ".set reorder");
1975
1976 #if MIPS34K_MISSED_ITLB_WAR
1977         if ((res & _ULCAST_(1)))
1978                 __asm__ __volatile__(
1979                 "       .set    push                            \n"
1980                 "       .set    noreorder                       \n"
1981                 "       .set    noat                            \n"
1982                 "       .set    mips32r2                        \n"
1983                 "       .word   0x41600021      # evpe          \n"
1984                 "       ehb                                     \n"
1985                 "       .set    pop                             \n");
1986 #endif
1987 }
1988
1989 static inline void tlb_write_indexed(void)
1990 {
1991         __asm__ __volatile__(
1992                 ".set noreorder\n\t"
1993                 "tlbwi\n\t"
1994                 ".set reorder");
1995 }
1996
1997 static inline void tlb_write_random(void)
1998 {
1999         __asm__ __volatile__(
2000                 ".set noreorder\n\t"
2001                 "tlbwr\n\t"
2002                 ".set reorder");
2003 }
2004
2005 /*
2006  * Manipulate bits in a c0 register.
2007  */
2008 #define __BUILD_SET_C0(name)                                    \
2009 static inline unsigned int                                      \
2010 set_c0_##name(unsigned int set)                                 \
2011 {                                                               \
2012         unsigned int res, new;                                  \
2013                                                                 \
2014         res = read_c0_##name();                                 \
2015         new = res | set;                                        \
2016         write_c0_##name(new);                                   \
2017                                                                 \
2018         return res;                                             \
2019 }                                                               \
2020                                                                 \
2021 static inline unsigned int                                      \
2022 clear_c0_##name(unsigned int clear)                             \
2023 {                                                               \
2024         unsigned int res, new;                                  \
2025                                                                 \
2026         res = read_c0_##name();                                 \
2027         new = res & ~clear;                                     \
2028         write_c0_##name(new);                                   \
2029                                                                 \
2030         return res;                                             \
2031 }                                                               \
2032                                                                 \
2033 static inline unsigned int                                      \
2034 change_c0_##name(unsigned int change, unsigned int val)         \
2035 {                                                               \
2036         unsigned int res, new;                                  \
2037                                                                 \
2038         res = read_c0_##name();                                 \
2039         new = res & ~change;                                    \
2040         new |= (val & change);                                  \
2041         write_c0_##name(new);                                   \
2042                                                                 \
2043         return res;                                             \
2044 }
2045
2046 __BUILD_SET_C0(status)
2047 __BUILD_SET_C0(cause)
2048 __BUILD_SET_C0(config)
2049 __BUILD_SET_C0(config5)
2050 __BUILD_SET_C0(intcontrol)
2051 __BUILD_SET_C0(intctl)
2052 __BUILD_SET_C0(srsmap)
2053 __BUILD_SET_C0(pagegrain)
2054 __BUILD_SET_C0(brcm_config_0)
2055 __BUILD_SET_C0(brcm_bus_pll)
2056 __BUILD_SET_C0(brcm_reset)
2057 __BUILD_SET_C0(brcm_cmt_intr)
2058 __BUILD_SET_C0(brcm_cmt_ctrl)
2059 __BUILD_SET_C0(brcm_config)
2060 __BUILD_SET_C0(brcm_mode)
2061
2062 /*
2063  * Return low 10 bits of ebase.
2064  * Note that under KVM (MIPSVZ) this returns vcpu id.
2065  */
2066 static inline unsigned int get_ebase_cpunum(void)
2067 {
2068         return read_c0_ebase() & 0x3ff;
2069 }
2070
2071 #endif /* !__ASSEMBLY__ */
2072
2073 #endif /* _ASM_MIPSREGS_H */