drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "gmc_v8_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "gmc/gmc_8_1_d.h"
  30 #include "gmc/gmc_8_1_sh_mask.h"
  31
  32 #include "bif/bif_5_0_d.h"
  33 #include "bif/bif_5_0_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "dce/dce_10_0_d.h"
  39 #include "dce/dce_10_0_sh_mask.h"
  40
  41 #include "vid.h"
  42 #include "vi.h"
  43
  44 #include "amdgpu_atombios.h"
  45
  46
  47 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
  48 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  49 static int gmc_v8_0_wait_for_idle(void *handle);
  50
  51 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
  52 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
  53 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
  54 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
  55
  56 static const u32 golden_settings_tonga_a11[] =
  57 {
  58         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  59         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  60         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  61         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  62         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  63         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  64         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  65 };
  66
  67 static const u32 tonga_mgcg_cgcg_init[] =
  68 {
  69         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  70 };
  71
  72 static const u32 golden_settings_fiji_a10[] =
  73 {
  74         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  75         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  76         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  77         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  78 };
  79
  80 static const u32 fiji_mgcg_cgcg_init[] =
  81 {
  82         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  83 };
  84
  85 static const u32 golden_settings_polaris11_a11[] =
  86 {
  87         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  88         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  89         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  90         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  91 };
  92
  93 static const u32 golden_settings_polaris10_a11[] =
  94 {
  95         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  96         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  97         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  98         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  99         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
 100 };
 101
 102 static const u32 cz_mgcg_cgcg_init[] =
 103 {
 104         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 105 };
 106
 107 static const u32 stoney_mgcg_cgcg_init[] =
 108 {
 109         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 110         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 111 };
 112
 113 static const u32 golden_settings_stoney_common[] =
 114 {
 115         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 116         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 117 };
 118
 119 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 120 {
 121         switch (adev->asic_type) {
 122         case CHIP_FIJI:
 123                 amdgpu_program_register_sequence(adev,
 124                                                  fiji_mgcg_cgcg_init,
 125                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 126                 amdgpu_program_register_sequence(adev,
 127                                                  golden_settings_fiji_a10,
 128                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 129                 break;
 130         case CHIP_TONGA:
 131                 amdgpu_program_register_sequence(adev,
 132                                                  tonga_mgcg_cgcg_init,
 133                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 134                 amdgpu_program_register_sequence(adev,
 135                                                  golden_settings_tonga_a11,
 136                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 137                 break;
 138         case CHIP_POLARIS11:
 139         case CHIP_POLARIS12:
 140                 amdgpu_program_register_sequence(adev,
 141                                                  golden_settings_polaris11_a11,
 142                                                  (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 143                 break;
 144         case CHIP_POLARIS10:
 145                 amdgpu_program_register_sequence(adev,
 146                                                  golden_settings_polaris10_a11,
 147                                                  (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 148                 break;
 149         case CHIP_CARRIZO:
 150                 amdgpu_program_register_sequence(adev,
 151                                                  cz_mgcg_cgcg_init,
 152                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 153                 break;
 154         case CHIP_STONEY:
 155                 amdgpu_program_register_sequence(adev,
 156                                                  stoney_mgcg_cgcg_init,
 157                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 158                 amdgpu_program_register_sequence(adev,
 159                                                  golden_settings_stoney_common,
 160                                                  (const u32)ARRAY_SIZE(golden_settings_stoney_common));
 161                 break;
 162         default:
 163                 break;
 164         }
 165 }
 166
 167 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
 168 {
 169         u32 blackout;
 170
 171         gmc_v8_0_wait_for_idle(adev);
 172
 173         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 174         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 175                 /* Block CPU access */
 176                 WREG32(mmBIF_FB_EN, 0);
 177                 /* blackout the MC */
 178                 blackout = REG_SET_FIELD(blackout,
 179                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 180                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 181         }
 182         /* wait for the MC to settle */
 183         udelay(100);
 184 }
 185
 186 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
 187 {
 188         u32 tmp;
 189
 190         /* unblackout the MC */
 191         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 192         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 193         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 194         /* allow CPU access */
 195         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 196         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 197         WREG32(mmBIF_FB_EN, tmp);
 198 }
 199
 200 /**
 201  * gmc_v8_0_init_microcode - load ucode images from disk
 202  *
 203  * @adev: amdgpu_device pointer
 204  *
 205  * Use the firmware interface to load the ucode images into
 206  * the driver (not loaded into hw).
 207  * Returns 0 on success, error on failure.
 208  */
 209 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 210 {
 211         const char *chip_name;
 212         char fw_name[30];
 213         int err;
 214
 215         DRM_DEBUG("\n");
 216
 217         switch (adev->asic_type) {
 218         case CHIP_TONGA:
 219                 chip_name = "tonga";
 220                 break;
 221         case CHIP_POLARIS11:
 222                 chip_name = "polaris11";
 223                 break;
 224         case CHIP_POLARIS10:
 225                 chip_name = "polaris10";
 226                 break;
 227         case CHIP_POLARIS12:
 228                 chip_name = "polaris12";
 229                 break;
 230         case CHIP_FIJI:
 231         case CHIP_CARRIZO:
 232         case CHIP_STONEY:
 233                 return 0;
 234         default: BUG();
 235         }
 236
 237         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 238         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 239         if (err)
 240                 goto out;
 241         err = amdgpu_ucode_validate(adev->mc.fw);
 242
 243 out:
 244         if (err) {
 245                 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
 246                 release_firmware(adev->mc.fw);
 247                 adev->mc.fw = NULL;
 248         }
 249         return err;
 250 }
 251
 252 /**
 253  * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
 254  *
 255  * @adev: amdgpu_device pointer
 256  *
 257  * Load the GDDR MC ucode into the hw (CIK).
 258  * Returns 0 on success, error on failure.
 259  */
 260 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
 261 {
 262         const struct mc_firmware_header_v1_0 *hdr;
 263         const __le32 *fw_data = NULL;
 264         const __le32 *io_mc_regs = NULL;
 265         u32 running;
 266         int i, ucode_size, regs_size;
 267
 268         /* Skip MC ucode loading on SR-IOV capable boards.
 269          * vbios does this for us in asic_init in that case.
 270          * Skip MC ucode loading on VF, because hypervisor will do that
 271          * for this adaptor.
 272          */
 273         if (amdgpu_sriov_bios(adev))
 274                 return 0;
 275
 276         if (!adev->mc.fw)
 277                 return -EINVAL;
 278
 279         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 280         amdgpu_ucode_print_mc_hdr(&hdr->header);
 281
 282         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 283         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 284         io_mc_regs = (const __le32 *)
 285                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 286         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 287         fw_data = (const __le32 *)
 288                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 289
 290         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 291
 292         if (running == 0) {
 293                 /* reset the engine and set to writable */
 294                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 295                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 296
 297                 /* load mc io regs */
 298                 for (i = 0; i < regs_size; i++) {
 299                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 300                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 301                 }
 302                 /* load the MC ucode */
 303                 for (i = 0; i < ucode_size; i++)
 304                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 305
 306                 /* put the engine back into the active state */
 307                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 308                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 309                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 310
 311                 /* wait for training to complete */
 312                 for (i = 0; i < adev->usec_timeout; i++) {
 313                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 314                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 315                                 break;
 316                         udelay(1);
 317                 }
 318                 for (i = 0; i < adev->usec_timeout; i++) {
 319                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 320                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 321                                 break;
 322                         udelay(1);
 323                 }
 324         }
 325
 326         return 0;
 327 }
 328
 329 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
 330 {
 331         const struct mc_firmware_header_v1_0 *hdr;
 332         const __le32 *fw_data = NULL;
 333         const __le32 *io_mc_regs = NULL;
 334         u32 data, vbios_version;
 335         int i, ucode_size, regs_size;
 336
 337         /* Skip MC ucode loading on SR-IOV capable boards.
 338          * vbios does this for us in asic_init in that case.
 339          * Skip MC ucode loading on VF, because hypervisor will do that
 340          * for this adaptor.
 341          */
 342         if (amdgpu_sriov_bios(adev))
 343                 return 0;
 344
 345         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 346         data = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
 347         vbios_version = data & 0xf;
 348
 349         if (vbios_version == 0)
 350                 return 0;
 351
 352         if (!adev->mc.fw)
 353                 return -EINVAL;
 354
 355         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 356         amdgpu_ucode_print_mc_hdr(&hdr->header);
 357
 358         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 359         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 360         io_mc_regs = (const __le32 *)
 361                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 362         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 363         fw_data = (const __le32 *)
 364                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 365
 366         data = RREG32(mmMC_SEQ_MISC0);
 367         data &= ~(0x40);
 368         WREG32(mmMC_SEQ_MISC0, data);
 369
 370         /* load mc io regs */
 371         for (i = 0; i < regs_size; i++) {
 372                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 373                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 374         }
 375
 376         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 377         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 378
 379         /* load the MC ucode */
 380         for (i = 0; i < ucode_size; i++)
 381                 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 382
 383         /* put the engine back into the active state */
 384         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 385         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 386         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 387
 388         /* wait for training to complete */
 389         for (i = 0; i < adev->usec_timeout; i++) {
 390                 data = RREG32(mmMC_SEQ_MISC0);
 391                 if (data & 0x80)
 392                         break;
 393                 udelay(1);
 394         }
 395
 396         return 0;
 397 }
 398
 399 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 400                                        struct amdgpu_mc *mc)
 401 {
 402         u64 base = 0;
 403
 404         if (!amdgpu_sriov_vf(adev))
 405                 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 406         base <<= 24;
 407
 408         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 409                 /* leave room for at least 1024M GTT */
 410                 dev_warn(adev->dev, "limiting VRAM\n");
 411                 mc->real_vram_size = 0xFFC0000000ULL;
 412                 mc->mc_vram_size = 0xFFC0000000ULL;
 413         }
 414         amdgpu_vram_location(adev, &adev->mc, base);
 415         amdgpu_gart_location(adev, mc);
 416 }
 417
 418 /**
 419  * gmc_v8_0_mc_program - program the GPU memory controller
 420  *
 421  * @adev: amdgpu_device pointer
 422  *
 423  * Set the location of vram, gart, and AGP in the GPU's
 424  * physical address space (CIK).
 425  */
 426 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 427 {
 428         u32 tmp;
 429         int i, j;
 430
 431         /* Initialize HDP */
 432         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 433                 WREG32((0xb05 + j), 0x00000000);
 434                 WREG32((0xb06 + j), 0x00000000);
 435                 WREG32((0xb07 + j), 0x00000000);
 436                 WREG32((0xb08 + j), 0x00000000);
 437                 WREG32((0xb09 + j), 0x00000000);
 438         }
 439         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 440
 441         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 442                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 443         }
 444         if (adev->mode_info.num_crtc) {
 445                 /* Lockout access through VGA aperture*/
 446                 tmp = RREG32(mmVGA_HDP_CONTROL);
 447                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 448                 WREG32(mmVGA_HDP_CONTROL, tmp);
 449
 450                 /* disable VGA render */
 451                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 452                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 453                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 454         }
 455         /* Update configuration */
 456         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 457                adev->mc.vram_start >> 12);
 458         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 459                adev->mc.vram_end >> 12);
 460         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 461                adev->vram_scratch.gpu_addr >> 12);
 462
 463         if (amdgpu_sriov_vf(adev)) {
 464                 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 465                 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 466                 WREG32(mmMC_VM_FB_LOCATION, tmp);
 467                 /* XXX double check these! */
 468                 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 469                 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 470                 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 471         }
 472
 473         WREG32(mmMC_VM_AGP_BASE, 0);
 474         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 475         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 476         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 477                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 478         }
 479
 480         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 481
 482         tmp = RREG32(mmHDP_MISC_CNTL);
 483         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 484         WREG32(mmHDP_MISC_CNTL, tmp);
 485
 486         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 487         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 488 }
 489
 490 /**
 491  * gmc_v8_0_mc_init - initialize the memory controller driver params
 492  *
 493  * @adev: amdgpu_device pointer
 494  *
 495  * Look up the amount of vram, vram width, and decide how to place
 496  * vram and gart within the GPU's physical address space (CIK).
 497  * Returns 0 for success.
 498  */
 499 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 500 {
 501         adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
 502         if (!adev->mc.vram_width) {
 503                 u32 tmp;
 504                 int chansize, numchan;
 505
 506                 /* Get VRAM informations */
 507                 tmp = RREG32(mmMC_ARB_RAMCFG);
 508                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 509                         chansize = 64;
 510                 } else {
 511                         chansize = 32;
 512                 }
 513                 tmp = RREG32(mmMC_SHARED_CHMAP);
 514                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 515                 case 0:
 516                 default:
 517                         numchan = 1;
 518                         break;
 519                 case 1:
 520                         numchan = 2;
 521                         break;
 522                 case 2:
 523                         numchan = 4;
 524                         break;
 525                 case 3:
 526                         numchan = 8;
 527                         break;
 528                 case 4:
 529                         numchan = 3;
 530                         break;
 531                 case 5:
 532                         numchan = 6;
 533                         break;
 534                 case 6:
 535                         numchan = 10;
 536                         break;
 537                 case 7:
 538                         numchan = 12;
 539                         break;
 540                 case 8:
 541                         numchan = 16;
 542                         break;
 543                 }
 544                 adev->mc.vram_width = numchan * chansize;
 545         }
 546         /* Could aper size report 0 ? */
 547         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 548         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 549         /* size in MB on si */
 550         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 551         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 552
 553 #ifdef CONFIG_X86_64
 554         if (adev->flags & AMD_IS_APU) {
 555                 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 556                 adev->mc.aper_size = adev->mc.real_vram_size;
 557         }
 558 #endif
 559
 560         /* In case the PCI BAR is larger than the actual amount of vram */
 561         adev->mc.visible_vram_size = adev->mc.aper_size;
 562         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 563                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 564
 565         amdgpu_gart_set_defaults(adev);
 566         gmc_v8_0_vram_gtt_location(adev, &adev->mc);
 567
 568         return 0;
 569 }
 570
 571 /*
 572  * GART
 573  * VMID 0 is the physical GPU addresses as used by the kernel.
 574  * VMIDs 1-15 are used for userspace clients and are handled
 575  * by the amdgpu vm/hsa code.
 576  */
 577
 578 /**
 579  * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
 580  *
 581  * @adev: amdgpu_device pointer
 582  * @vmid: vm instance to flush
 583  *
 584  * Flush the TLB for the requested page table (CIK).
 585  */
 586 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 587                                         uint32_t vmid)
 588 {
 589         /* flush hdp cache */
 590         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 591
 592         /* bits 0-15 are the VM contexts0-15 */
 593         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 594 }
 595
 596 /**
 597  * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
 598  *
 599  * @adev: amdgpu_device pointer
 600  * @cpu_pt_addr: cpu address of the page table
 601  * @gpu_page_idx: entry in the page table to update
 602  * @addr: dst addr to write into pte/pde
 603  * @flags: access flags
 604  *
 605  * Update the page tables using the CPU.
 606  */
 607 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
 608                                      void *cpu_pt_addr,
 609                                      uint32_t gpu_page_idx,
 610                                      uint64_t addr,
 611                                      uint64_t flags)
 612 {
 613         void __iomem *ptr = (void *)cpu_pt_addr;
 614         uint64_t value;
 615
 616         /*
 617          * PTE format on VI:
 618          * 63:40 reserved
 619          * 39:12 4k physical page base address
 620          * 11:7 fragment
 621          * 6 write
 622          * 5 read
 623          * 4 exe
 624          * 3 reserved
 625          * 2 snooped
 626          * 1 system
 627          * 0 valid
 628          *
 629          * PDE format on VI:
 630          * 63:59 block fragment size
 631          * 58:40 reserved
 632          * 39:1 physical base address of PTE
 633          * bits 5:1 must be 0.
 634          * 0 valid
 635          */
 636         value = addr & 0x000000FFFFFFF000ULL;
 637         value |= flags;
 638         writeq(value, ptr + (gpu_page_idx * 8));
 639
 640         return 0;
 641 }
 642
 643 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
 644                                           uint32_t flags)
 645 {
 646         uint64_t pte_flag = 0;
 647
 648         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 649                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 650         if (flags & AMDGPU_VM_PAGE_READABLE)
 651                 pte_flag |= AMDGPU_PTE_READABLE;
 652         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 653                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 654         if (flags & AMDGPU_VM_PAGE_PRT)
 655                 pte_flag |= AMDGPU_PTE_PRT;
 656
 657         return pte_flag;
 658 }
 659
 660 static uint64_t gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
 661 {
 662         BUG_ON(addr & 0xFFFFFF0000000FFFULL);
 663         return addr;
 664 }
 665
 666 /**
 667  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 668  *
 669  * @adev: amdgpu_device pointer
 670  * @value: true redirects VM faults to the default page
 671  */
 672 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 673                                               bool value)
 674 {
 675         u32 tmp;
 676
 677         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 678         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 679                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 680         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 681                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 682         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 683                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 684         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 685                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 686         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 687                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 688         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 689                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 690         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 691                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 692         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 693 }
 694
 695 /**
 696  * gmc_v8_0_set_prt - set PRT VM fault
 697  *
 698  * @adev: amdgpu_device pointer
 699  * @enable: enable/disable VM fault handling for PRT
 700 */
 701 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
 702 {
 703         u32 tmp;
 704
 705         if (enable && !adev->mc.prt_warning) {
 706                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 707                 adev->mc.prt_warning = true;
 708         }
 709
 710         tmp = RREG32(mmVM_PRT_CNTL);
 711         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 712                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 713         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 714                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 715         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 716                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 717         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 718                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 719         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 720                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 721         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 722                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 723         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 724                             MASK_PDE0_FAULT, enable);
 725         WREG32(mmVM_PRT_CNTL, tmp);
 726
 727         if (enable) {
 728                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 729                 uint32_t high = adev->vm_manager.max_pfn;
 730
 731                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 732                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 733                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 734                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 735                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 736                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 737                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 738                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 739         } else {
 740                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 741                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 742                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 743                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 744                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 745                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 746                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 747                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 748         }
 749 }
 750
 751 /**
 752  * gmc_v8_0_gart_enable - gart enable
 753  *
 754  * @adev: amdgpu_device pointer
 755  *
 756  * This sets up the TLBs, programs the page tables for VMID0,
 757  * sets up the hw for VMIDs 1-15 which are allocated on
 758  * demand, and sets up the global locations for the LDS, GDS,
 759  * and GPUVM for FSA64 clients (CIK).
 760  * Returns 0 for success, errors for failure.
 761  */
 762 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 763 {
 764         int r, i;
 765         u32 tmp, field;
 766
 767         if (adev->gart.robj == NULL) {
 768                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 769                 return -EINVAL;
 770         }
 771         r = amdgpu_gart_table_vram_pin(adev);
 772         if (r)
 773                 return r;
 774         /* Setup TLB control */
 775         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 776         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 777         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 778         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 779         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 780         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 781         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 782         /* Setup L2 cache */
 783         tmp = RREG32(mmVM_L2_CNTL);
 784         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 785         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 786         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 787         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 788         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 789         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 790         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 791         WREG32(mmVM_L2_CNTL, tmp);
 792         tmp = RREG32(mmVM_L2_CNTL2);
 793         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 794         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 795         WREG32(mmVM_L2_CNTL2, tmp);
 796
 797         field = adev->vm_manager.fragment_size;
 798         tmp = RREG32(mmVM_L2_CNTL3);
 799         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 800         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 801         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 802         WREG32(mmVM_L2_CNTL3, tmp);
 803         /* XXX: set to enable PTE/PDE in system memory */
 804         tmp = RREG32(mmVM_L2_CNTL4);
 805         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 806         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 807         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 808         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 809         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 810         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 811         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 812         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 813         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 814         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 815         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 816         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 817         WREG32(mmVM_L2_CNTL4, tmp);
 818         /* setup context0 */
 819         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12);
 820         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12);
 821         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 822         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 823                         (u32)(adev->dummy_page.addr >> 12));
 824         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 825         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 826         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 827         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 828         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 829         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 830
 831         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 832         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 833         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 834
 835         /* empty context1-15 */
 836         /* FIXME start with 4G, once using 2 level pt switch to full
 837          * vm size space
 838          */
 839         /* set vm size, must be a multiple of 4 */
 840         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 841         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 842         for (i = 1; i < 16; i++) {
 843                 if (i < 8)
 844                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 845                                adev->gart.table_addr >> 12);
 846                 else
 847                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 848                                adev->gart.table_addr >> 12);
 849         }
 850
 851         /* enable context1-15 */
 852         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 853                (u32)(adev->dummy_page.addr >> 12));
 854         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 855         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 856         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 857         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 858         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 859         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 860         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 861         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 862         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 863         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 864         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 865         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 866                             adev->vm_manager.block_size - 9);
 867         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 868         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 869                 gmc_v8_0_set_fault_enable_default(adev, false);
 870         else
 871                 gmc_v8_0_set_fault_enable_default(adev, true);
 872
 873         gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
 874         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 875                  (unsigned)(adev->mc.gart_size >> 20),
 876                  (unsigned long long)adev->gart.table_addr);
 877         adev->gart.ready = true;
 878         return 0;
 879 }
 880
 881 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 882 {
 883         int r;
 884
 885         if (adev->gart.robj) {
 886                 WARN(1, "R600 PCIE GART already initialized\n");
 887                 return 0;
 888         }
 889         /* Initialize common gart structure */
 890         r = amdgpu_gart_init(adev);
 891         if (r)
 892                 return r;
 893         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 894         adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
 895         return amdgpu_gart_table_vram_alloc(adev);
 896 }
 897
 898 /**
 899  * gmc_v8_0_gart_disable - gart disable
 900  *
 901  * @adev: amdgpu_device pointer
 902  *
 903  * This disables all VM page table (CIK).
 904  */
 905 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 906 {
 907         u32 tmp;
 908
 909         /* Disable all tables */
 910         WREG32(mmVM_CONTEXT0_CNTL, 0);
 911         WREG32(mmVM_CONTEXT1_CNTL, 0);
 912         /* Setup TLB control */
 913         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 914         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 915         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 916         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 917         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 918         /* Setup L2 cache */
 919         tmp = RREG32(mmVM_L2_CNTL);
 920         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 921         WREG32(mmVM_L2_CNTL, tmp);
 922         WREG32(mmVM_L2_CNTL2, 0);
 923         amdgpu_gart_table_vram_unpin(adev);
 924 }
 925
 926 /**
 927  * gmc_v8_0_gart_fini - vm fini callback
 928  *
 929  * @adev: amdgpu_device pointer
 930  *
 931  * Tears down the driver GART/VM setup (CIK).
 932  */
 933 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
 934 {
 935         amdgpu_gart_table_vram_free(adev);
 936         amdgpu_gart_fini(adev);
 937 }
 938
 939 /**
 940  * gmc_v8_0_vm_decode_fault - print human readable fault info
 941  *
 942  * @adev: amdgpu_device pointer
 943  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 944  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 945  *
 946  * Print human readable fault information (CIK).
 947  */
 948 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
 949                                      u32 status, u32 addr, u32 mc_client)
 950 {
 951         u32 mc_id;
 952         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 953         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 954                                         PROTECTIONS);
 955         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 956                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 957
 958         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 959                               MEMORY_CLIENT_ID);
 960
 961         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 962                protections, vmid, addr,
 963                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 964                              MEMORY_CLIENT_RW) ?
 965                "write" : "read", block, mc_client, mc_id);
 966 }
 967
 968 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
 969 {
 970         switch (mc_seq_vram_type) {
 971         case MC_SEQ_MISC0__MT__GDDR1:
 972                 return AMDGPU_VRAM_TYPE_GDDR1;
 973         case MC_SEQ_MISC0__MT__DDR2:
 974                 return AMDGPU_VRAM_TYPE_DDR2;
 975         case MC_SEQ_MISC0__MT__GDDR3:
 976                 return AMDGPU_VRAM_TYPE_GDDR3;
 977         case MC_SEQ_MISC0__MT__GDDR4:
 978                 return AMDGPU_VRAM_TYPE_GDDR4;
 979         case MC_SEQ_MISC0__MT__GDDR5:
 980                 return AMDGPU_VRAM_TYPE_GDDR5;
 981         case MC_SEQ_MISC0__MT__HBM:
 982                 return AMDGPU_VRAM_TYPE_HBM;
 983         case MC_SEQ_MISC0__MT__DDR3:
 984                 return AMDGPU_VRAM_TYPE_DDR3;
 985         default:
 986                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 987         }
 988 }
 989
 990 static int gmc_v8_0_early_init(void *handle)
 991 {
 992         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 993
 994         gmc_v8_0_set_gart_funcs(adev);
 995         gmc_v8_0_set_irq_funcs(adev);
 996
 997         adev->mc.shared_aperture_start = 0x2000000000000000ULL;
 998         adev->mc.shared_aperture_end =
 999                 adev->mc.shared_aperture_start + (4ULL << 30) - 1;
1000         adev->mc.private_aperture_start =
1001                 adev->mc.shared_aperture_end + 1;
1002         adev->mc.private_aperture_end =
1003                 adev->mc.private_aperture_start + (4ULL << 30) - 1;
1004
1005         return 0;
1006 }
1007
1008 static int gmc_v8_0_late_init(void *handle)
1009 {
1010         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1011
1012         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1013                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
1014         else
1015                 return 0;
1016 }
1017
1018 #define mmMC_SEQ_MISC0_FIJI 0xA71
1019
1020 static int gmc_v8_0_sw_init(void *handle)
1021 {
1022         int r;
1023         int dma_bits;
1024         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1025
1026         if (adev->flags & AMD_IS_APU) {
1027                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1028         } else {
1029                 u32 tmp;
1030
1031                 if (adev->asic_type == CHIP_FIJI)
1032                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1033                 else
1034                         tmp = RREG32(mmMC_SEQ_MISC0);
1035                 tmp &= MC_SEQ_MISC0__MT__MASK;
1036                 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1037         }
1038
1039         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
1040         if (r)
1041                 return r;
1042
1043         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
1044         if (r)
1045                 return r;
1046
1047         /* Adjust VM size here.
1048          * Currently set to 4GB ((1 << 20) 4k pages).
1049          * Max GPUVM size for cayman and SI is 40 bits.
1050          */
1051         amdgpu_vm_adjust_size(adev, 64, 4);
1052         adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
1053
1054         /* Set the internal MC address mask
1055          * This is the max address of the GPU's
1056          * internal address space.
1057          */
1058         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1059
1060         adev->mc.stolen_size = 256 * 1024;
1061
1062         /* set DMA mask + need_dma32 flags.
1063          * PCIE - can handle 40-bits.
1064          * IGP - can handle 40-bits
1065          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1066          */
1067         adev->need_dma32 = false;
1068         dma_bits = adev->need_dma32 ? 32 : 40;
1069         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1070         if (r) {
1071                 adev->need_dma32 = true;
1072                 dma_bits = 32;
1073                 pr_warn("amdgpu: No suitable DMA available\n");
1074         }
1075         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1076         if (r) {
1077                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1078                 pr_warn("amdgpu: No coherent DMA available\n");
1079         }
1080
1081         r = gmc_v8_0_init_microcode(adev);
1082         if (r) {
1083                 DRM_ERROR("Failed to load mc firmware!\n");
1084                 return r;
1085         }
1086
1087         r = gmc_v8_0_mc_init(adev);
1088         if (r)
1089                 return r;
1090
1091         /* Memory manager */
1092         r = amdgpu_bo_init(adev);
1093         if (r)
1094                 return r;
1095
1096         r = gmc_v8_0_gart_init(adev);
1097         if (r)
1098                 return r;
1099
1100         /*
1101          * number of VMs
1102          * VMID 0 is reserved for System
1103          * amdgpu graphics/compute will use VMIDs 1-7
1104          * amdkfd will use VMIDs 8-15
1105          */
1106         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1107         adev->vm_manager.num_level = 1;
1108         amdgpu_vm_manager_init(adev);
1109
1110         /* base offset of vram pages */
1111         if (adev->flags & AMD_IS_APU) {
1112                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1113
1114                 tmp <<= 22;
1115                 adev->vm_manager.vram_base_offset = tmp;
1116         } else {
1117                 adev->vm_manager.vram_base_offset = 0;
1118         }
1119
1120         return 0;
1121 }
1122
1123 static int gmc_v8_0_sw_fini(void *handle)
1124 {
1125         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1126
1127         amdgpu_vm_manager_fini(adev);
1128         gmc_v8_0_gart_fini(adev);
1129         amdgpu_gem_force_release(adev);
1130         amdgpu_bo_fini(adev);
1131
1132         return 0;
1133 }
1134
1135 static int gmc_v8_0_hw_init(void *handle)
1136 {
1137         int r;
1138         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1139
1140         gmc_v8_0_init_golden_registers(adev);
1141
1142         gmc_v8_0_mc_program(adev);
1143
1144         if (adev->asic_type == CHIP_TONGA) {
1145                 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1146                 if (r) {
1147                         DRM_ERROR("Failed to load MC firmware!\n");
1148                         return r;
1149                 }
1150         } else if (adev->asic_type == CHIP_POLARIS11 ||
1151                         adev->asic_type == CHIP_POLARIS10 ||
1152                         adev->asic_type == CHIP_POLARIS12) {
1153                 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1154                 if (r) {
1155                         DRM_ERROR("Failed to load MC firmware!\n");
1156                         return r;
1157                 }
1158         }
1159
1160         r = gmc_v8_0_gart_enable(adev);
1161         if (r)
1162                 return r;
1163
1164         return r;
1165 }
1166
1167 static int gmc_v8_0_hw_fini(void *handle)
1168 {
1169         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1170
1171         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1172         gmc_v8_0_gart_disable(adev);
1173
1174         return 0;
1175 }
1176
1177 static int gmc_v8_0_suspend(void *handle)
1178 {
1179         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1180
1181         gmc_v8_0_hw_fini(adev);
1182
1183         return 0;
1184 }
1185
1186 static int gmc_v8_0_resume(void *handle)
1187 {
1188         int r;
1189         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1190
1191         r = gmc_v8_0_hw_init(adev);
1192         if (r)
1193                 return r;
1194
1195         amdgpu_vm_reset_all_ids(adev);
1196
1197         return 0;
1198 }
1199
1200 static bool gmc_v8_0_is_idle(void *handle)
1201 {
1202         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1203         u32 tmp = RREG32(mmSRBM_STATUS);
1204
1205         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1206                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1207                 return false;
1208
1209         return true;
1210 }
1211
1212 static int gmc_v8_0_wait_for_idle(void *handle)
1213 {
1214         unsigned i;
1215         u32 tmp;
1216         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1217
1218         for (i = 0; i < adev->usec_timeout; i++) {
1219                 /* read MC_STATUS */
1220                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1221                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1222                                                SRBM_STATUS__MCC_BUSY_MASK |
1223                                                SRBM_STATUS__MCD_BUSY_MASK |
1224                                                SRBM_STATUS__VMC_BUSY_MASK |
1225                                                SRBM_STATUS__VMC1_BUSY_MASK);
1226                 if (!tmp)
1227                         return 0;
1228                 udelay(1);
1229         }
1230         return -ETIMEDOUT;
1231
1232 }
1233
1234 static bool gmc_v8_0_check_soft_reset(void *handle)
1235 {
1236         u32 srbm_soft_reset = 0;
1237         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1238         u32 tmp = RREG32(mmSRBM_STATUS);
1239
1240         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1241                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1242                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1243
1244         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1245                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1246                 if (!(adev->flags & AMD_IS_APU))
1247                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1248                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1249         }
1250         if (srbm_soft_reset) {
1251                 adev->mc.srbm_soft_reset = srbm_soft_reset;
1252                 return true;
1253         } else {
1254                 adev->mc.srbm_soft_reset = 0;
1255                 return false;
1256         }
1257 }
1258
1259 static int gmc_v8_0_pre_soft_reset(void *handle)
1260 {
1261         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1262
1263         if (!adev->mc.srbm_soft_reset)
1264                 return 0;
1265
1266         gmc_v8_0_mc_stop(adev);
1267         if (gmc_v8_0_wait_for_idle(adev)) {
1268                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1269         }
1270
1271         return 0;
1272 }
1273
1274 static int gmc_v8_0_soft_reset(void *handle)
1275 {
1276         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1277         u32 srbm_soft_reset;
1278
1279         if (!adev->mc.srbm_soft_reset)
1280                 return 0;
1281         srbm_soft_reset = adev->mc.srbm_soft_reset;
1282
1283         if (srbm_soft_reset) {
1284                 u32 tmp;
1285
1286                 tmp = RREG32(mmSRBM_SOFT_RESET);
1287                 tmp |= srbm_soft_reset;
1288                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1289                 WREG32(mmSRBM_SOFT_RESET, tmp);
1290                 tmp = RREG32(mmSRBM_SOFT_RESET);
1291
1292                 udelay(50);
1293
1294                 tmp &= ~srbm_soft_reset;
1295                 WREG32(mmSRBM_SOFT_RESET, tmp);
1296                 tmp = RREG32(mmSRBM_SOFT_RESET);
1297
1298                 /* Wait a little for things to settle down */
1299                 udelay(50);
1300         }
1301
1302         return 0;
1303 }
1304
1305 static int gmc_v8_0_post_soft_reset(void *handle)
1306 {
1307         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1308
1309         if (!adev->mc.srbm_soft_reset)
1310                 return 0;
1311
1312         gmc_v8_0_mc_resume(adev);
1313         return 0;
1314 }
1315
1316 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1317                                              struct amdgpu_irq_src *src,
1318                                              unsigned type,
1319                                              enum amdgpu_interrupt_state state)
1320 {
1321         u32 tmp;
1322         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1323                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1324                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1325                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1326                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1327                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1328                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1329
1330         switch (state) {
1331         case AMDGPU_IRQ_STATE_DISABLE:
1332                 /* system context */
1333                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1334                 tmp &= ~bits;
1335                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1336                 /* VMs */
1337                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1338                 tmp &= ~bits;
1339                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1340                 break;
1341         case AMDGPU_IRQ_STATE_ENABLE:
1342                 /* system context */
1343                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1344                 tmp |= bits;
1345                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1346                 /* VMs */
1347                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1348                 tmp |= bits;
1349                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1350                 break;
1351         default:
1352                 break;
1353         }
1354
1355         return 0;
1356 }
1357
1358 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1359                                       struct amdgpu_irq_src *source,
1360                                       struct amdgpu_iv_entry *entry)
1361 {
1362         u32 addr, status, mc_client;
1363
1364         if (amdgpu_sriov_vf(adev)) {
1365                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1366                         entry->src_id, entry->src_data[0]);
1367                 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1368                 return 0;
1369         }
1370
1371         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1372         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1373         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1374         /* reset addr and status */
1375         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1376
1377         if (!addr && !status)
1378                 return 0;
1379
1380         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1381                 gmc_v8_0_set_fault_enable_default(adev, false);
1382
1383         if (printk_ratelimit()) {
1384                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1385                         entry->src_id, entry->src_data[0]);
1386                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1387                         addr);
1388                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1389                         status);
1390                 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1391         }
1392
1393         return 0;
1394 }
1395
1396 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1397                                                      bool enable)
1398 {
1399         uint32_t data;
1400
1401         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1402                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1403                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1404                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1405
1406                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1407                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1408                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1409
1410                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1411                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1412                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1413
1414                 data = RREG32(mmMC_XPB_CLK_GAT);
1415                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1416                 WREG32(mmMC_XPB_CLK_GAT, data);
1417
1418                 data = RREG32(mmATC_MISC_CG);
1419                 data |= ATC_MISC_CG__ENABLE_MASK;
1420                 WREG32(mmATC_MISC_CG, data);
1421
1422                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1423                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1424                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1425
1426                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1427                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1428                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1429
1430                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1431                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1432                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1433
1434                 data = RREG32(mmVM_L2_CG);
1435                 data |= VM_L2_CG__ENABLE_MASK;
1436                 WREG32(mmVM_L2_CG, data);
1437         } else {
1438                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1439                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1440                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1441
1442                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1443                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1444                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1445
1446                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1447                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1448                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1449
1450                 data = RREG32(mmMC_XPB_CLK_GAT);
1451                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1452                 WREG32(mmMC_XPB_CLK_GAT, data);
1453
1454                 data = RREG32(mmATC_MISC_CG);
1455                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1456                 WREG32(mmATC_MISC_CG, data);
1457
1458                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1459                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1460                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1461
1462                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1463                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1464                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1465
1466                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1467                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1468                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1469
1470                 data = RREG32(mmVM_L2_CG);
1471                 data &= ~VM_L2_CG__ENABLE_MASK;
1472                 WREG32(mmVM_L2_CG, data);
1473         }
1474 }
1475
1476 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1477                                        bool enable)
1478 {
1479         uint32_t data;
1480
1481         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1482                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1483                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1484                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1485
1486                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1487                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1488                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1489
1490                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1491                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1492                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1493
1494                 data = RREG32(mmMC_XPB_CLK_GAT);
1495                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1496                 WREG32(mmMC_XPB_CLK_GAT, data);
1497
1498                 data = RREG32(mmATC_MISC_CG);
1499                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1500                 WREG32(mmATC_MISC_CG, data);
1501
1502                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1503                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1504                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1505
1506                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1507                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1508                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1509
1510                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1511                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1512                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1513
1514                 data = RREG32(mmVM_L2_CG);
1515                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1516                 WREG32(mmVM_L2_CG, data);
1517         } else {
1518                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1519                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1520                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1521
1522                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1523                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1524                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1525
1526                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1527                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1528                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1529
1530                 data = RREG32(mmMC_XPB_CLK_GAT);
1531                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1532                 WREG32(mmMC_XPB_CLK_GAT, data);
1533
1534                 data = RREG32(mmATC_MISC_CG);
1535                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1536                 WREG32(mmATC_MISC_CG, data);
1537
1538                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1539                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1540                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1541
1542                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1543                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1544                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1545
1546                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1547                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1548                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1549
1550                 data = RREG32(mmVM_L2_CG);
1551                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1552                 WREG32(mmVM_L2_CG, data);
1553         }
1554 }
1555
1556 static int gmc_v8_0_set_clockgating_state(void *handle,
1557                                           enum amd_clockgating_state state)
1558 {
1559         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1560
1561         if (amdgpu_sriov_vf(adev))
1562                 return 0;
1563
1564         switch (adev->asic_type) {
1565         case CHIP_FIJI:
1566                 fiji_update_mc_medium_grain_clock_gating(adev,
1567                                 state == AMD_CG_STATE_GATE);
1568                 fiji_update_mc_light_sleep(adev,
1569                                 state == AMD_CG_STATE_GATE);
1570                 break;
1571         default:
1572                 break;
1573         }
1574         return 0;
1575 }
1576
1577 static int gmc_v8_0_set_powergating_state(void *handle,
1578                                           enum amd_powergating_state state)
1579 {
1580         return 0;
1581 }
1582
1583 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1584 {
1585         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1586         int data;
1587
1588         if (amdgpu_sriov_vf(adev))
1589                 *flags = 0;
1590
1591         /* AMD_CG_SUPPORT_MC_MGCG */
1592         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1593         if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1594                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1595
1596         /* AMD_CG_SUPPORT_MC_LS */
1597         if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1598                 *flags |= AMD_CG_SUPPORT_MC_LS;
1599 }
1600
1601 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1602         .name = "gmc_v8_0",
1603         .early_init = gmc_v8_0_early_init,
1604         .late_init = gmc_v8_0_late_init,
1605         .sw_init = gmc_v8_0_sw_init,
1606         .sw_fini = gmc_v8_0_sw_fini,
1607         .hw_init = gmc_v8_0_hw_init,
1608         .hw_fini = gmc_v8_0_hw_fini,
1609         .suspend = gmc_v8_0_suspend,
1610         .resume = gmc_v8_0_resume,
1611         .is_idle = gmc_v8_0_is_idle,
1612         .wait_for_idle = gmc_v8_0_wait_for_idle,
1613         .check_soft_reset = gmc_v8_0_check_soft_reset,
1614         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1615         .soft_reset = gmc_v8_0_soft_reset,
1616         .post_soft_reset = gmc_v8_0_post_soft_reset,
1617         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1618         .set_powergating_state = gmc_v8_0_set_powergating_state,
1619         .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1620 };
1621
1622 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1623         .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1624         .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1625         .set_prt = gmc_v8_0_set_prt,
1626         .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
1627         .get_vm_pde = gmc_v8_0_get_vm_pde
1628 };
1629
1630 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1631         .set = gmc_v8_0_vm_fault_interrupt_state,
1632         .process = gmc_v8_0_process_interrupt,
1633 };
1634
1635 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1636 {
1637         if (adev->gart.gart_funcs == NULL)
1638                 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1639 }
1640
1641 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1642 {
1643         adev->mc.vm_fault.num_types = 1;
1644         adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1645 }
1646
1647 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1648 {
1649         .type = AMD_IP_BLOCK_TYPE_GMC,
1650         .major = 8,
1651         .minor = 0,
1652         .rev = 0,
1653         .funcs = &gmc_v8_0_ip_funcs,
1654 };
1655
1656 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1657 {
1658         .type = AMD_IP_BLOCK_TYPE_GMC,
1659         .major = 8,
1660         .minor = 1,
1661         .rev = 0,
1662         .funcs = &gmc_v8_0_ip_funcs,
1663 };
1664
1665 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1666 {
1667         .type = AMD_IP_BLOCK_TYPE_GMC,
1668         .major = 8,
1669         .minor = 5,
1670         .rev = 0,
1671         .funcs = &gmc_v8_0_ip_funcs,
1672 };