2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/debugfs.h>
34 #include <drm/amdgpu_drm.h>
40 * Most engines on the GPU are fed via ring buffers. Ring
41 * buffers are areas of GPU accessible memory that the host
42 * writes commands into and the GPU reads commands out of.
43 * There is a rptr (read pointer) that determines where the
44 * GPU is currently reading, and a wptr (write pointer)
45 * which determines where the host has written. When the
46 * pointers are equal, the ring is idle. When the host
47 * writes commands to the ring buffer, it increments the
48 * wptr. The GPU then starts fetching commands and executes
49 * them until the pointers are equal again.
53 * amdgpu_ring_max_ibs - Return max IBs that fit in a single submission.
55 * @type: ring type for which to return the limit.
57 unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type)
60 case AMDGPU_RING_TYPE_GFX:
61 /* Need to keep at least 192 on GFX7+ for old radv. */
63 case AMDGPU_RING_TYPE_COMPUTE:
65 case AMDGPU_RING_TYPE_VCN_JPEG:
73 * amdgpu_ring_alloc - allocate space on the ring buffer
75 * @ring: amdgpu_ring structure holding ring information
76 * @ndw: number of dwords to allocate in the ring buffer
78 * Allocate @ndw dwords in the ring buffer (all asics).
79 * Returns 0 on success, error on failure.
81 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
83 /* Align requested size with padding so unlock_commit can
85 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
87 /* Make sure we aren't trying to allocate more space
88 * than the maximum for one submission
90 if (WARN_ON_ONCE(ndw > ring->max_dw))
94 ring->wptr_old = ring->wptr;
96 if (ring->funcs->begin_use)
97 ring->funcs->begin_use(ring);
102 /** amdgpu_ring_insert_nop - insert NOP packets
104 * @ring: amdgpu_ring structure holding ring information
105 * @count: the number of NOP packets to insert
107 * This is the generic insert_nop function for rings except SDMA
109 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
113 for (i = 0; i < count; i++)
114 amdgpu_ring_write(ring, ring->funcs->nop);
118 * amdgpu_ring_generic_pad_ib - pad IB with NOP packets
120 * @ring: amdgpu_ring structure holding ring information
121 * @ib: IB to add NOP packets to
123 * This is the generic pad_ib function for rings except SDMA
125 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
127 while (ib->length_dw & ring->funcs->align_mask)
128 ib->ptr[ib->length_dw++] = ring->funcs->nop;
132 * amdgpu_ring_commit - tell the GPU to execute the new
133 * commands on the ring buffer
135 * @ring: amdgpu_ring structure holding ring information
137 * Update the wptr (write pointer) to tell the GPU to
138 * execute new commands on the ring buffer (all asics).
140 void amdgpu_ring_commit(struct amdgpu_ring *ring)
144 /* We pad to match fetch size */
145 count = ring->funcs->align_mask + 1 -
146 (ring->wptr & ring->funcs->align_mask);
147 count %= ring->funcs->align_mask + 1;
148 ring->funcs->insert_nop(ring, count);
151 amdgpu_ring_set_wptr(ring);
153 if (ring->funcs->end_use)
154 ring->funcs->end_use(ring);
158 * amdgpu_ring_undo - reset the wptr
160 * @ring: amdgpu_ring structure holding ring information
162 * Reset the driver's copy of the wptr (all asics).
164 void amdgpu_ring_undo(struct amdgpu_ring *ring)
166 ring->wptr = ring->wptr_old;
168 if (ring->funcs->end_use)
169 ring->funcs->end_use(ring);
172 #define amdgpu_ring_get_gpu_addr(ring, offset) \
173 (ring->is_mes_queue ? \
174 (ring->mes_ctx->meta_data_gpu_addr + offset) : \
175 (ring->adev->wb.gpu_addr + offset * 4))
177 #define amdgpu_ring_get_cpu_addr(ring, offset) \
178 (ring->is_mes_queue ? \
179 (void *)((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : \
180 (&ring->adev->wb.wb[offset]))
183 * amdgpu_ring_init - init driver ring struct.
185 * @adev: amdgpu_device pointer
186 * @ring: amdgpu_ring structure holding ring information
187 * @max_dw: maximum number of dw for ring alloc
188 * @irq_src: interrupt source to use for this ring
189 * @irq_type: interrupt type to use for this ring
190 * @hw_prio: ring priority (NORMAL/HIGH)
191 * @sched_score: optional score atomic shared with other schedulers
193 * Initialize the driver information for the selected ring (all asics).
194 * Returns 0 on success, error on failure.
196 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
197 unsigned int max_dw, struct amdgpu_irq_src *irq_src,
198 unsigned int irq_type, unsigned int hw_prio,
199 atomic_t *sched_score)
202 int sched_hw_submission = amdgpu_sched_hw_submission;
205 unsigned int max_ibs_dw;
207 /* Set the hw submission limit higher for KIQ because
208 * it's used for a number of gfx/compute tasks by both
209 * KFD and KGD which may have outstanding fences and
210 * it doesn't really use the gpu scheduler anyway;
211 * KIQ tasks get submitted directly to the ring.
213 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
214 sched_hw_submission = max(sched_hw_submission, 256);
215 else if (ring == &adev->sdma.instance[0].page)
216 sched_hw_submission = 256;
218 if (ring->adev == NULL) {
219 if (adev->num_rings >= AMDGPU_MAX_RINGS)
223 ring->num_hw_submission = sched_hw_submission;
224 ring->sched_score = sched_score;
225 ring->vmid_wait = dma_fence_get_stub();
227 if (!ring->is_mes_queue) {
228 ring->idx = adev->num_rings++;
229 adev->rings[ring->idx] = ring;
232 r = amdgpu_fence_driver_init_ring(ring);
237 if (ring->is_mes_queue) {
238 ring->rptr_offs = amdgpu_mes_ctx_get_offs(ring,
239 AMDGPU_MES_CTX_RPTR_OFFS);
240 ring->wptr_offs = amdgpu_mes_ctx_get_offs(ring,
241 AMDGPU_MES_CTX_WPTR_OFFS);
242 ring->fence_offs = amdgpu_mes_ctx_get_offs(ring,
243 AMDGPU_MES_CTX_FENCE_OFFS);
244 ring->trail_fence_offs = amdgpu_mes_ctx_get_offs(ring,
245 AMDGPU_MES_CTX_TRAIL_FENCE_OFFS);
246 ring->cond_exe_offs = amdgpu_mes_ctx_get_offs(ring,
247 AMDGPU_MES_CTX_COND_EXE_OFFS);
249 r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
251 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
255 r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
257 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
261 r = amdgpu_device_wb_get(adev, &ring->fence_offs);
263 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
267 r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs);
269 dev_err(adev->dev, "(%d) ring trail_fence_offs wb alloc failed\n", r);
273 r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
275 dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
280 ring->fence_gpu_addr =
281 amdgpu_ring_get_gpu_addr(ring, ring->fence_offs);
282 ring->fence_cpu_addr =
283 amdgpu_ring_get_cpu_addr(ring, ring->fence_offs);
285 ring->rptr_gpu_addr =
286 amdgpu_ring_get_gpu_addr(ring, ring->rptr_offs);
287 ring->rptr_cpu_addr =
288 amdgpu_ring_get_cpu_addr(ring, ring->rptr_offs);
290 ring->wptr_gpu_addr =
291 amdgpu_ring_get_gpu_addr(ring, ring->wptr_offs);
292 ring->wptr_cpu_addr =
293 amdgpu_ring_get_cpu_addr(ring, ring->wptr_offs);
295 ring->trail_fence_gpu_addr =
296 amdgpu_ring_get_gpu_addr(ring, ring->trail_fence_offs);
297 ring->trail_fence_cpu_addr =
298 amdgpu_ring_get_cpu_addr(ring, ring->trail_fence_offs);
300 ring->cond_exe_gpu_addr =
301 amdgpu_ring_get_gpu_addr(ring, ring->cond_exe_offs);
302 ring->cond_exe_cpu_addr =
303 amdgpu_ring_get_cpu_addr(ring, ring->cond_exe_offs);
305 /* always set cond_exec_polling to CONTINUE */
306 *ring->cond_exe_cpu_addr = 1;
308 r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
310 dev_err(adev->dev, "failed initializing fences (%d).\n", r);
314 max_ibs_dw = ring->funcs->emit_frame_size +
315 amdgpu_ring_max_ibs(ring->funcs->type) * ring->funcs->emit_ib_size;
316 max_ibs_dw = (max_ibs_dw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
318 if (WARN_ON(max_ibs_dw > max_dw)) {
322 ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
324 ring->buf_mask = (ring->ring_size / 4) - 1;
325 ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
326 0xffffffffffffffff : ring->buf_mask;
328 /* Allocate ring buffer */
329 if (ring->is_mes_queue) {
332 BUG_ON(ring->ring_size > PAGE_SIZE*4);
334 offset = amdgpu_mes_ctx_get_offs(ring,
335 AMDGPU_MES_CTX_RING_OFFS);
336 ring->gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
337 ring->ring = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
338 amdgpu_ring_clear_ring(ring);
340 } else if (ring->ring_obj == NULL) {
341 r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE,
342 AMDGPU_GEM_DOMAIN_GTT,
345 (void **)&ring->ring);
347 dev_err(adev->dev, "(%d) ring create failed\n", r);
350 amdgpu_ring_clear_ring(ring);
353 ring->max_dw = max_dw;
354 ring->hw_prio = hw_prio;
356 if (!ring->no_scheduler) {
357 hw_ip = ring->funcs->type;
358 num_sched = &adev->gpu_sched[hw_ip][hw_prio].num_scheds;
359 adev->gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] =
367 * amdgpu_ring_fini - tear down the driver ring struct.
369 * @ring: amdgpu_ring structure holding ring information
371 * Tear down the driver information for the selected ring (all asics).
373 void amdgpu_ring_fini(struct amdgpu_ring *ring)
376 /* Not to finish a ring which is not initialized */
378 (!ring->is_mes_queue && !(ring->adev->rings[ring->idx])))
381 ring->sched.ready = false;
383 if (!ring->is_mes_queue) {
384 amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
385 amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
387 amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
388 amdgpu_device_wb_free(ring->adev, ring->fence_offs);
390 amdgpu_bo_free_kernel(&ring->ring_obj,
392 (void **)&ring->ring);
394 kfree(ring->fence_drv.fences);
397 dma_fence_put(ring->vmid_wait);
398 ring->vmid_wait = NULL;
401 if (!ring->is_mes_queue)
402 ring->adev->rings[ring->idx] = NULL;
406 * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
408 * @ring: ring to write to
409 * @reg0: register to write
410 * @reg1: register to wait on
411 * @ref: reference value to write/wait on
412 * @mask: mask to wait on
414 * Helper for rings that don't support write and wait in a
415 * single oneshot packet.
417 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
418 uint32_t reg0, uint32_t reg1,
419 uint32_t ref, uint32_t mask)
421 amdgpu_ring_emit_wreg(ring, reg0, ref);
422 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
426 * amdgpu_ring_soft_recovery - try to soft recover a ring lockup
428 * @ring: ring to try the recovery on
429 * @vmid: VMID we try to get going again
430 * @fence: timedout fence
432 * Tries to get a ring proceeding again when it is stuck.
434 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
435 struct dma_fence *fence)
437 ktime_t deadline = ktime_add_us(ktime_get(), 10000);
439 if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
442 atomic_inc(&ring->adev->gpu_reset_counter);
443 while (!dma_fence_is_signaled(fence) &&
444 ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
445 ring->funcs->soft_recovery(ring, vmid);
447 return dma_fence_is_signaled(fence);
453 #if defined(CONFIG_DEBUG_FS)
455 /* Layout of file is 12 bytes consisting of
458 * - driver's copy of wptr
460 * followed by n-words of ring data
462 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
463 size_t size, loff_t *pos)
465 struct amdgpu_ring *ring = file_inode(f)->i_private;
467 uint32_t value, result, early[3];
469 if (*pos & 3 || size & 3)
475 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
476 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
477 early[2] = ring->wptr & ring->buf_mask;
478 for (i = *pos / 4; i < 3 && size; i++) {
479 r = put_user(early[i], (uint32_t *)buf);
490 if (*pos >= (ring->ring_size + 12))
493 value = ring->ring[(*pos - 12)/4];
494 r = put_user(value, (uint32_t *)buf);
506 static const struct file_operations amdgpu_debugfs_ring_fops = {
507 .owner = THIS_MODULE,
508 .read = amdgpu_debugfs_ring_read,
509 .llseek = default_llseek
512 static ssize_t amdgpu_debugfs_mqd_read(struct file *f, char __user *buf,
513 size_t size, loff_t *pos)
515 struct amdgpu_ring *ring = file_inode(f)->i_private;
518 uint32_t value, result;
520 if (*pos & 3 || size & 3)
525 r = amdgpu_bo_reserve(ring->mqd_obj, false);
526 if (unlikely(r != 0))
529 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&mqd);
531 amdgpu_bo_unreserve(ring->mqd_obj);
536 if (*pos >= ring->mqd_size)
540 r = put_user(value, (uint32_t *)buf);
550 amdgpu_bo_kunmap(ring->mqd_obj);
552 amdgpu_bo_unreserve(ring->mqd_obj);
559 static const struct file_operations amdgpu_debugfs_mqd_fops = {
560 .owner = THIS_MODULE,
561 .read = amdgpu_debugfs_mqd_read,
562 .llseek = default_llseek
567 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
568 struct amdgpu_ring *ring)
570 #if defined(CONFIG_DEBUG_FS)
571 struct drm_minor *minor = adev_to_drm(adev)->primary;
572 struct dentry *root = minor->debugfs_root;
575 sprintf(name, "amdgpu_ring_%s", ring->name);
576 debugfs_create_file_size(name, S_IFREG | S_IRUGO, root, ring,
577 &amdgpu_debugfs_ring_fops,
578 ring->ring_size + 12);
581 sprintf(name, "amdgpu_mqd_%s", ring->name);
582 debugfs_create_file_size(name, S_IFREG | S_IRUGO, root, ring,
583 &amdgpu_debugfs_mqd_fops,
590 * amdgpu_ring_test_helper - tests ring and set sched readiness status
592 * @ring: ring to try the recovery on
594 * Tests ring and set sched readiness status
596 * Returns 0 on success, error on failure.
598 int amdgpu_ring_test_helper(struct amdgpu_ring *ring)
600 struct amdgpu_device *adev = ring->adev;
603 r = amdgpu_ring_test_ring(ring);
605 DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n",
608 DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n",
611 ring->sched.ready = !r;
615 static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring,
616 struct amdgpu_mqd_prop *prop)
618 struct amdgpu_device *adev = ring->adev;
620 memset(prop, 0, sizeof(*prop));
622 prop->mqd_gpu_addr = ring->mqd_gpu_addr;
623 prop->hqd_base_gpu_addr = ring->gpu_addr;
624 prop->rptr_gpu_addr = ring->rptr_gpu_addr;
625 prop->wptr_gpu_addr = ring->wptr_gpu_addr;
626 prop->queue_size = ring->ring_size;
627 prop->eop_gpu_addr = ring->eop_gpu_addr;
628 prop->use_doorbell = ring->use_doorbell;
629 prop->doorbell_index = ring->doorbell_index;
631 /* map_queues packet doesn't need activate the queue,
632 * so only kiq need set this field.
634 prop->hqd_active = ring->funcs->type == AMDGPU_RING_TYPE_KIQ;
636 if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE &&
637 amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) ||
638 (ring->funcs->type == AMDGPU_RING_TYPE_GFX &&
639 amdgpu_gfx_is_high_priority_graphics_queue(adev, ring))) {
640 prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
641 prop->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
645 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring)
647 struct amdgpu_device *adev = ring->adev;
648 struct amdgpu_mqd *mqd_mgr;
649 struct amdgpu_mqd_prop prop;
651 amdgpu_ring_to_mqd_prop(ring, &prop);
655 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
656 mqd_mgr = &adev->mqds[AMDGPU_HW_IP_COMPUTE];
658 mqd_mgr = &adev->mqds[ring->funcs->type];
660 return mqd_mgr->init_mqd(adev, ring->mqd_ptr, &prop);
663 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring)
665 if (ring->is_sw_ring)
666 amdgpu_sw_ring_ib_begin(ring);
669 void amdgpu_ring_ib_end(struct amdgpu_ring *ring)
671 if (ring->is_sw_ring)
672 amdgpu_sw_ring_ib_end(ring);