drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drm_drv.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_xgmi.h"
  33 #include "soc15_common.h"
  34 #include "psp_v3_1.h"
  35 #include "psp_v10_0.h"
  36 #include "psp_v11_0.h"
  37 #include "psp_v11_0_8.h"
  38 #include "psp_v12_0.h"
  39 #include "psp_v13_0.h"
  40 #include "psp_v13_0_4.h"
  41
  42 #include "amdgpu_ras.h"
  43 #include "amdgpu_securedisplay.h"
  44 #include "amdgpu_atomfirmware.h"
  45
  46 #define AMD_VBIOS_FILE_MAX_SIZE_B      (1024*1024*3)
  47
  48 static int psp_sysfs_init(struct amdgpu_device *adev);
  49 static void psp_sysfs_fini(struct amdgpu_device *adev);
  50
  51 static int psp_load_smu_fw(struct psp_context *psp);
  52 static int psp_rap_terminate(struct psp_context *psp);
  53 static int psp_securedisplay_terminate(struct psp_context *psp);
  54
  55 static int psp_ring_init(struct psp_context *psp,
  56                          enum psp_ring_type ring_type)
  57 {
  58         int ret = 0;
  59         struct psp_ring *ring;
  60         struct amdgpu_device *adev = psp->adev;
  61
  62         ring = &psp->km_ring;
  63
  64         ring->ring_type = ring_type;
  65
  66         /* allocate 4k Page of Local Frame Buffer memory for ring */
  67         ring->ring_size = 0x1000;
  68         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
  69                                       AMDGPU_GEM_DOMAIN_VRAM |
  70                                       AMDGPU_GEM_DOMAIN_GTT,
  71                                       &adev->firmware.rbuf,
  72                                       &ring->ring_mem_mc_addr,
  73                                       (void **)&ring->ring_mem);
  74         if (ret) {
  75                 ring->ring_size = 0;
  76                 return ret;
  77         }
  78
  79         return 0;
  80 }
  81
  82 /*
  83  * Due to DF Cstate management centralized to PMFW, the firmware
  84  * loading sequence will be updated as below:
  85  *   - Load KDB
  86  *   - Load SYS_DRV
  87  *   - Load tOS
  88  *   - Load PMFW
  89  *   - Setup TMR
  90  *   - Load other non-psp fw
  91  *   - Load ASD
  92  *   - Load XGMI/RAS/HDCP/DTM TA if any
  93  *
  94  * This new sequence is required for
  95  *   - Arcturus and onwards
  96  */
  97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  98 {
  99         struct amdgpu_device *adev = psp->adev;
 100
 101         if (amdgpu_sriov_vf(adev)) {
 102                 psp->pmfw_centralized_cstate_management = false;
 103                 return;
 104         }
 105
 106         switch (adev->ip_versions[MP0_HWIP][0]) {
 107         case IP_VERSION(11, 0, 0):
 108         case IP_VERSION(11, 0, 4):
 109         case IP_VERSION(11, 0, 5):
 110         case IP_VERSION(11, 0, 7):
 111         case IP_VERSION(11, 0, 9):
 112         case IP_VERSION(11, 0, 11):
 113         case IP_VERSION(11, 0, 12):
 114         case IP_VERSION(11, 0, 13):
 115         case IP_VERSION(13, 0, 0):
 116         case IP_VERSION(13, 0, 2):
 117         case IP_VERSION(13, 0, 7):
 118                 psp->pmfw_centralized_cstate_management = true;
 119                 break;
 120         default:
 121                 psp->pmfw_centralized_cstate_management = false;
 122                 break;
 123         }
 124 }
 125
 126 static int psp_init_sriov_microcode(struct psp_context *psp)
 127 {
 128         struct amdgpu_device *adev = psp->adev;
 129         char ucode_prefix[30];
 130         int ret = 0;
 131
 132         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 133
 134         switch (adev->ip_versions[MP0_HWIP][0]) {
 135         case IP_VERSION(9, 0, 0):
 136         case IP_VERSION(11, 0, 7):
 137         case IP_VERSION(11, 0, 9):
 138                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 139                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 140                 break;
 141         case IP_VERSION(13, 0, 2):
 142                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 143                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 144                 ret &= psp_init_ta_microcode(psp, ucode_prefix);
 145                 break;
 146         case IP_VERSION(13, 0, 0):
 147                 adev->virt.autoload_ucode_id = 0;
 148                 break;
 149         case IP_VERSION(13, 0, 10):
 150                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
 151                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 152                 break;
 153         default:
 154                 return -EINVAL;
 155         }
 156         return ret;
 157 }
 158
 159 static int psp_early_init(void *handle)
 160 {
 161         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 162         struct psp_context *psp = &adev->psp;
 163
 164         switch (adev->ip_versions[MP0_HWIP][0]) {
 165         case IP_VERSION(9, 0, 0):
 166                 psp_v3_1_set_psp_funcs(psp);
 167                 psp->autoload_supported = false;
 168                 break;
 169         case IP_VERSION(10, 0, 0):
 170         case IP_VERSION(10, 0, 1):
 171                 psp_v10_0_set_psp_funcs(psp);
 172                 psp->autoload_supported = false;
 173                 break;
 174         case IP_VERSION(11, 0, 2):
 175         case IP_VERSION(11, 0, 4):
 176                 psp_v11_0_set_psp_funcs(psp);
 177                 psp->autoload_supported = false;
 178                 break;
 179         case IP_VERSION(11, 0, 0):
 180         case IP_VERSION(11, 0, 5):
 181         case IP_VERSION(11, 0, 9):
 182         case IP_VERSION(11, 0, 7):
 183         case IP_VERSION(11, 0, 11):
 184         case IP_VERSION(11, 5, 0):
 185         case IP_VERSION(11, 0, 12):
 186         case IP_VERSION(11, 0, 13):
 187                 psp_v11_0_set_psp_funcs(psp);
 188                 psp->autoload_supported = true;
 189                 break;
 190         case IP_VERSION(11, 0, 3):
 191         case IP_VERSION(12, 0, 1):
 192                 psp_v12_0_set_psp_funcs(psp);
 193                 break;
 194         case IP_VERSION(13, 0, 2):
 195         case IP_VERSION(13, 0, 6):
 196                 psp_v13_0_set_psp_funcs(psp);
 197                 break;
 198         case IP_VERSION(13, 0, 1):
 199         case IP_VERSION(13, 0, 3):
 200         case IP_VERSION(13, 0, 5):
 201         case IP_VERSION(13, 0, 8):
 202         case IP_VERSION(13, 0, 10):
 203         case IP_VERSION(13, 0, 11):
 204                 psp_v13_0_set_psp_funcs(psp);
 205                 psp->autoload_supported = true;
 206                 break;
 207         case IP_VERSION(11, 0, 8):
 208                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
 209                         psp_v11_0_8_set_psp_funcs(psp);
 210                         psp->autoload_supported = false;
 211                 }
 212                 break;
 213         case IP_VERSION(13, 0, 0):
 214         case IP_VERSION(13, 0, 7):
 215                 psp_v13_0_set_psp_funcs(psp);
 216                 psp->autoload_supported = true;
 217                 break;
 218         case IP_VERSION(13, 0, 4):
 219                 psp_v13_0_4_set_psp_funcs(psp);
 220                 psp->autoload_supported = true;
 221                 break;
 222         default:
 223                 return -EINVAL;
 224         }
 225
 226         psp->adev = adev;
 227
 228         psp_check_pmfw_centralized_cstate_management(psp);
 229
 230         if (amdgpu_sriov_vf(adev))
 231                 return psp_init_sriov_microcode(psp);
 232         else
 233                 return psp_init_microcode(psp);
 234 }
 235
 236 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
 237 {
 238         amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
 239                               &mem_ctx->shared_buf);
 240         mem_ctx->shared_bo = NULL;
 241 }
 242
 243 static void psp_free_shared_bufs(struct psp_context *psp)
 244 {
 245         void *tmr_buf;
 246         void **pptr;
 247
 248         /* free TMR memory buffer */
 249         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 250         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 251         psp->tmr_bo = NULL;
 252
 253         /* free xgmi shared memory */
 254         psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
 255
 256         /* free ras shared memory */
 257         psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
 258
 259         /* free hdcp shared memory */
 260         psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
 261
 262         /* free dtm shared memory */
 263         psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
 264
 265         /* free rap shared memory */
 266         psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
 267
 268         /* free securedisplay shared memory */
 269         psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
 270
 271
 272 }
 273
 274 static void psp_memory_training_fini(struct psp_context *psp)
 275 {
 276         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 277
 278         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 279         kfree(ctx->sys_cache);
 280         ctx->sys_cache = NULL;
 281 }
 282
 283 static int psp_memory_training_init(struct psp_context *psp)
 284 {
 285         int ret;
 286         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 287
 288         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 289                 DRM_DEBUG("memory training is not supported!\n");
 290                 return 0;
 291         }
 292
 293         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 294         if (ctx->sys_cache == NULL) {
 295                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 296                 ret = -ENOMEM;
 297                 goto Err_out;
 298         }
 299
 300         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 301                   ctx->train_data_size,
 302                   ctx->p2c_train_data_offset,
 303                   ctx->c2p_train_data_offset);
 304         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 305         return 0;
 306
 307 Err_out:
 308         psp_memory_training_fini(psp);
 309         return ret;
 310 }
 311
 312 /*
 313  * Helper funciton to query psp runtime database entry
 314  *
 315  * @adev: amdgpu_device pointer
 316  * @entry_type: the type of psp runtime database entry
 317  * @db_entry: runtime database entry pointer
 318  *
 319  * Return false if runtime database doesn't exit or entry is invalid
 320  * or true if the specific database entry is found, and copy to @db_entry
 321  */
 322 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
 323                                      enum psp_runtime_entry_type entry_type,
 324                                      void *db_entry)
 325 {
 326         uint64_t db_header_pos, db_dir_pos;
 327         struct psp_runtime_data_header db_header = {0};
 328         struct psp_runtime_data_directory db_dir = {0};
 329         bool ret = false;
 330         int i;
 331
 332         db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
 333         db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
 334
 335         /* read runtime db header from vram */
 336         amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
 337                         sizeof(struct psp_runtime_data_header), false);
 338
 339         if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
 340                 /* runtime db doesn't exist, exit */
 341                 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n");
 342                 return false;
 343         }
 344
 345         /* read runtime database entry from vram */
 346         amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
 347                         sizeof(struct psp_runtime_data_directory), false);
 348
 349         if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
 350                 /* invalid db entry count, exit */
 351                 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
 352                 return false;
 353         }
 354
 355         /* look up for requested entry type */
 356         for (i = 0; i < db_dir.entry_count && !ret; i++) {
 357                 if (db_dir.entry_list[i].entry_type == entry_type) {
 358                         switch (entry_type) {
 359                         case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
 360                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
 361                                         /* invalid db entry size */
 362                                         dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
 363                                         return false;
 364                                 }
 365                                 /* read runtime database entry */
 366                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 367                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
 368                                 ret = true;
 369                                 break;
 370                         case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
 371                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
 372                                         /* invalid db entry size */
 373                                         dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
 374                                         return false;
 375                                 }
 376                                 /* read runtime database entry */
 377                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 378                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
 379                                 ret = true;
 380                                 break;
 381                         default:
 382                                 ret = false;
 383                                 break;
 384                         }
 385                 }
 386         }
 387
 388         return ret;
 389 }
 390
 391 static int psp_sw_init(void *handle)
 392 {
 393         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 394         struct psp_context *psp = &adev->psp;
 395         int ret;
 396         struct psp_runtime_boot_cfg_entry boot_cfg_entry;
 397         struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
 398         struct psp_runtime_scpm_entry scpm_entry;
 399
 400         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 401         if (!psp->cmd) {
 402                 DRM_ERROR("Failed to allocate memory to command buffer!\n");
 403                 ret = -ENOMEM;
 404         }
 405
 406         adev->psp.xgmi_context.supports_extended_data =
 407                 !adev->gmc.xgmi.connected_to_cpu &&
 408                         adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
 409
 410         memset(&scpm_entry, 0, sizeof(scpm_entry));
 411         if ((psp_get_runtime_db_entry(adev,
 412                                 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
 413                                 &scpm_entry)) &&
 414             (SCPM_DISABLE != scpm_entry.scpm_status)) {
 415                 adev->scpm_enabled = true;
 416                 adev->scpm_status = scpm_entry.scpm_status;
 417         } else {
 418                 adev->scpm_enabled = false;
 419                 adev->scpm_status = SCPM_DISABLE;
 420         }
 421
 422         /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
 423
 424         memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
 425         if (psp_get_runtime_db_entry(adev,
 426                                 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
 427                                 &boot_cfg_entry)) {
 428                 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
 429                 if ((psp->boot_cfg_bitmask) &
 430                     BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
 431                         /* If psp runtime database exists, then
 432                          * only enable two stage memory training
 433                          * when TWO_STAGE_DRAM_TRAINING bit is set
 434                          * in runtime database */
 435                         mem_training_ctx->enable_mem_training = true;
 436                 }
 437
 438         } else {
 439                 /* If psp runtime database doesn't exist or
 440                  * is invalid, force enable two stage memory
 441                  * training */
 442                 mem_training_ctx->enable_mem_training = true;
 443         }
 444
 445         if (mem_training_ctx->enable_mem_training) {
 446                 ret = psp_memory_training_init(psp);
 447                 if (ret) {
 448                         DRM_ERROR("Failed to initialize memory training!\n");
 449                         return ret;
 450                 }
 451
 452                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 453                 if (ret) {
 454                         DRM_ERROR("Failed to process memory training!\n");
 455                         return ret;
 456                 }
 457         }
 458
 459         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 460             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
 461                 ret= psp_sysfs_init(adev);
 462                 if (ret) {
 463                         return ret;
 464                 }
 465         }
 466
 467         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 468                                       amdgpu_sriov_vf(adev) ?
 469                                       AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 470                                       &psp->fw_pri_bo,
 471                                       &psp->fw_pri_mc_addr,
 472                                       &psp->fw_pri_buf);
 473         if (ret)
 474                 return ret;
 475
 476         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 477                                       AMDGPU_GEM_DOMAIN_VRAM,
 478                                       &psp->fence_buf_bo,
 479                                       &psp->fence_buf_mc_addr,
 480                                       &psp->fence_buf);
 481         if (ret)
 482                 goto failed1;
 483
 484         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 485                                       AMDGPU_GEM_DOMAIN_VRAM,
 486                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 487                                       (void **)&psp->cmd_buf_mem);
 488         if (ret)
 489                 goto failed2;
 490
 491         return 0;
 492
 493 failed2:
 494         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 495                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 496 failed1:
 497         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 498                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 499         return ret;
 500 }
 501
 502 static int psp_sw_fini(void *handle)
 503 {
 504         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 505         struct psp_context *psp = &adev->psp;
 506         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 507
 508         psp_memory_training_fini(psp);
 509
 510         amdgpu_ucode_release(&psp->sos_fw);
 511         amdgpu_ucode_release(&psp->asd_fw);
 512         amdgpu_ucode_release(&psp->ta_fw);
 513         amdgpu_ucode_release(&psp->cap_fw);
 514         amdgpu_ucode_release(&psp->toc_fw);
 515
 516         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 517             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
 518                 psp_sysfs_fini(adev);
 519
 520         kfree(cmd);
 521         cmd = NULL;
 522
 523         psp_free_shared_bufs(psp);
 524
 525         if (psp->km_ring.ring_mem)
 526                 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 527                                       &psp->km_ring.ring_mem_mc_addr,
 528                                       (void **)&psp->km_ring.ring_mem);
 529
 530         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 531                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 532         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 533                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 534         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 535                               (void **)&psp->cmd_buf_mem);
 536
 537         return 0;
 538 }
 539
 540 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 541                  uint32_t reg_val, uint32_t mask, bool check_changed)
 542 {
 543         uint32_t val;
 544         int i;
 545         struct amdgpu_device *adev = psp->adev;
 546
 547         if (psp->adev->no_hw_access)
 548                 return 0;
 549
 550         for (i = 0; i < adev->usec_timeout; i++) {
 551                 val = RREG32(reg_index);
 552                 if (check_changed) {
 553                         if (val != reg_val)
 554                                 return 0;
 555                 } else {
 556                         if ((val & mask) == reg_val)
 557                                 return 0;
 558                 }
 559                 udelay(1);
 560         }
 561
 562         return -ETIME;
 563 }
 564
 565 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
 566 {
 567         switch (cmd_id) {
 568         case GFX_CMD_ID_LOAD_TA:
 569                 return "LOAD_TA";
 570         case GFX_CMD_ID_UNLOAD_TA:
 571                 return "UNLOAD_TA";
 572         case GFX_CMD_ID_INVOKE_CMD:
 573                 return "INVOKE_CMD";
 574         case GFX_CMD_ID_LOAD_ASD:
 575                 return "LOAD_ASD";
 576         case GFX_CMD_ID_SETUP_TMR:
 577                 return "SETUP_TMR";
 578         case GFX_CMD_ID_LOAD_IP_FW:
 579                 return "LOAD_IP_FW";
 580         case GFX_CMD_ID_DESTROY_TMR:
 581                 return "DESTROY_TMR";
 582         case GFX_CMD_ID_SAVE_RESTORE:
 583                 return "SAVE_RESTORE_IP_FW";
 584         case GFX_CMD_ID_SETUP_VMR:
 585                 return "SETUP_VMR";
 586         case GFX_CMD_ID_DESTROY_VMR:
 587                 return "DESTROY_VMR";
 588         case GFX_CMD_ID_PROG_REG:
 589                 return "PROG_REG";
 590         case GFX_CMD_ID_GET_FW_ATTESTATION:
 591                 return "GET_FW_ATTESTATION";
 592         case GFX_CMD_ID_LOAD_TOC:
 593                 return "ID_LOAD_TOC";
 594         case GFX_CMD_ID_AUTOLOAD_RLC:
 595                 return "AUTOLOAD_RLC";
 596         case GFX_CMD_ID_BOOT_CFG:
 597                 return "BOOT_CFG";
 598         default:
 599                 return "UNKNOWN CMD";
 600         }
 601 }
 602
 603 static int
 604 psp_cmd_submit_buf(struct psp_context *psp,
 605                    struct amdgpu_firmware_info *ucode,
 606                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 607 {
 608         int ret;
 609         int index;
 610         int timeout = 20000;
 611         bool ras_intr = false;
 612         bool skip_unsupport = false;
 613
 614         if (psp->adev->no_hw_access)
 615                 return 0;
 616
 617         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 618
 619         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 620
 621         index = atomic_inc_return(&psp->fence_value);
 622         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 623         if (ret) {
 624                 atomic_dec(&psp->fence_value);
 625                 goto exit;
 626         }
 627
 628         amdgpu_device_invalidate_hdp(psp->adev, NULL);
 629         while (*((unsigned int *)psp->fence_buf) != index) {
 630                 if (--timeout == 0)
 631                         break;
 632                 /*
 633                  * Shouldn't wait for timeout when err_event_athub occurs,
 634                  * because gpu reset thread triggered and lock resource should
 635                  * be released for psp resume sequence.
 636                  */
 637                 ras_intr = amdgpu_ras_intr_triggered();
 638                 if (ras_intr)
 639                         break;
 640                 usleep_range(10, 100);
 641                 amdgpu_device_invalidate_hdp(psp->adev, NULL);
 642         }
 643
 644         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 645         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 646                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 647
 648         memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 649
 650         /* In some cases, psp response status is not 0 even there is no
 651          * problem while the command is submitted. Some version of PSP FW
 652          * doesn't write 0 to that field.
 653          * So here we would like to only print a warning instead of an error
 654          * during psp initialization to avoid breaking hw_init and it doesn't
 655          * return -EINVAL.
 656          */
 657         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 658                 if (ucode)
 659                         DRM_WARN("failed to load ucode %s(0x%X) ",
 660                                   amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
 661                 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
 662                          psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
 663                          psp->cmd_buf_mem->resp.status);
 664                 /* If any firmware (including CAP) load fails under SRIOV, it should
 665                  * return failure to stop the VF from initializing.
 666                  * Also return failure in case of timeout
 667                  */
 668                 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
 669                         ret = -EINVAL;
 670                         goto exit;
 671                 }
 672         }
 673
 674         if (ucode) {
 675                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 676                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 677         }
 678
 679 exit:
 680         return ret;
 681 }
 682
 683 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
 684 {
 685         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 686
 687         mutex_lock(&psp->mutex);
 688
 689         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 690
 691         return cmd;
 692 }
 693
 694 static void release_psp_cmd_buf(struct psp_context *psp)
 695 {
 696         mutex_unlock(&psp->mutex);
 697 }
 698
 699 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 700                                  struct psp_gfx_cmd_resp *cmd,
 701                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 702 {
 703         struct amdgpu_device *adev = psp->adev;
 704         uint32_t size = amdgpu_bo_size(tmr_bo);
 705         uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 706
 707         if (amdgpu_sriov_vf(psp->adev))
 708                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 709         else
 710                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 711         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 712         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 713         cmd->cmd.cmd_setup_tmr.buf_size = size;
 714         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 715         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 716         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 717 }
 718
 719 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 720                                       uint64_t pri_buf_mc, uint32_t size)
 721 {
 722         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 723         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 724         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 725         cmd->cmd.cmd_load_toc.toc_size = size;
 726 }
 727
 728 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 729 static int psp_load_toc(struct psp_context *psp,
 730                         uint32_t *tmr_size)
 731 {
 732         int ret;
 733         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 734
 735         /* Copy toc to psp firmware private buffer */
 736         psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
 737
 738         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
 739
 740         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 741                                  psp->fence_buf_mc_addr);
 742         if (!ret)
 743                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 744
 745         release_psp_cmd_buf(psp);
 746
 747         return ret;
 748 }
 749
 750 /* Set up Trusted Memory Region */
 751 static int psp_tmr_init(struct psp_context *psp)
 752 {
 753         int ret = 0;
 754         int tmr_size;
 755         void *tmr_buf;
 756         void **pptr;
 757
 758         /*
 759          * According to HW engineer, they prefer the TMR address be "naturally
 760          * aligned" , e.g. the start address be an integer divide of TMR size.
 761          *
 762          * Note: this memory need be reserved till the driver
 763          * uninitializes.
 764          */
 765         tmr_size = PSP_TMR_SIZE(psp->adev);
 766
 767         /* For ASICs support RLC autoload, psp will parse the toc
 768          * and calculate the total size of TMR needed */
 769         if (!amdgpu_sriov_vf(psp->adev) &&
 770             psp->toc.start_addr &&
 771             psp->toc.size_bytes &&
 772             psp->fw_pri_buf) {
 773                 ret = psp_load_toc(psp, &tmr_size);
 774                 if (ret) {
 775                         DRM_ERROR("Failed to load toc\n");
 776                         return ret;
 777                 }
 778         }
 779
 780         if (!psp->tmr_bo) {
 781                 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 782                 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
 783                                               PSP_TMR_ALIGNMENT,
 784                                               AMDGPU_HAS_VRAM(psp->adev) ?
 785                                               AMDGPU_GEM_DOMAIN_VRAM :
 786                                               AMDGPU_GEM_DOMAIN_GTT,
 787                                               &psp->tmr_bo, &psp->tmr_mc_addr,
 788                                               pptr);
 789         }
 790
 791         return ret;
 792 }
 793
 794 static bool psp_skip_tmr(struct psp_context *psp)
 795 {
 796         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 797         case IP_VERSION(11, 0, 9):
 798         case IP_VERSION(11, 0, 7):
 799         case IP_VERSION(13, 0, 2):
 800         case IP_VERSION(13, 0, 10):
 801                 return true;
 802         default:
 803                 return false;
 804         }
 805 }
 806
 807 static int psp_tmr_load(struct psp_context *psp)
 808 {
 809         int ret;
 810         struct psp_gfx_cmd_resp *cmd;
 811
 812         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 813          * Already set up by host driver.
 814          */
 815         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 816                 return 0;
 817
 818         cmd = acquire_psp_cmd_buf(psp);
 819
 820         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 821         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 822                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 823
 824         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 825                                  psp->fence_buf_mc_addr);
 826
 827         release_psp_cmd_buf(psp);
 828
 829         return ret;
 830 }
 831
 832 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 833                                         struct psp_gfx_cmd_resp *cmd)
 834 {
 835         if (amdgpu_sriov_vf(psp->adev))
 836                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 837         else
 838                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 839 }
 840
 841 static int psp_tmr_unload(struct psp_context *psp)
 842 {
 843         int ret;
 844         struct psp_gfx_cmd_resp *cmd;
 845
 846         /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV,
 847          * as TMR is not loaded at all
 848          */
 849         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 850                 return 0;
 851
 852         cmd = acquire_psp_cmd_buf(psp);
 853
 854         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 855         dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
 856
 857         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 858                                  psp->fence_buf_mc_addr);
 859
 860         release_psp_cmd_buf(psp);
 861
 862         return ret;
 863 }
 864
 865 static int psp_tmr_terminate(struct psp_context *psp)
 866 {
 867         return psp_tmr_unload(psp);
 868 }
 869
 870 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 871                                         uint64_t *output_ptr)
 872 {
 873         int ret;
 874         struct psp_gfx_cmd_resp *cmd;
 875
 876         if (!output_ptr)
 877                 return -EINVAL;
 878
 879         if (amdgpu_sriov_vf(psp->adev))
 880                 return 0;
 881
 882         cmd = acquire_psp_cmd_buf(psp);
 883
 884         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 885
 886         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 887                                  psp->fence_buf_mc_addr);
 888
 889         if (!ret) {
 890                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 891                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 892         }
 893
 894         release_psp_cmd_buf(psp);
 895
 896         return ret;
 897 }
 898
 899 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 900 {
 901         struct psp_context *psp = &adev->psp;
 902         struct psp_gfx_cmd_resp *cmd;
 903         int ret;
 904
 905         if (amdgpu_sriov_vf(adev))
 906                 return 0;
 907
 908         cmd = acquire_psp_cmd_buf(psp);
 909
 910         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 911         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
 912
 913         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 914         if (!ret) {
 915                 *boot_cfg =
 916                         (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
 917         }
 918
 919         release_psp_cmd_buf(psp);
 920
 921         return ret;
 922 }
 923
 924 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
 925 {
 926         int ret;
 927         struct psp_context *psp = &adev->psp;
 928         struct psp_gfx_cmd_resp *cmd;
 929
 930         if (amdgpu_sriov_vf(adev))
 931                 return 0;
 932
 933         cmd = acquire_psp_cmd_buf(psp);
 934
 935         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 936         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 937         cmd->cmd.boot_cfg.boot_config = boot_cfg;
 938         cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 939
 940         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 941
 942         release_psp_cmd_buf(psp);
 943
 944         return ret;
 945 }
 946
 947 static int psp_rl_load(struct amdgpu_device *adev)
 948 {
 949         int ret;
 950         struct psp_context *psp = &adev->psp;
 951         struct psp_gfx_cmd_resp *cmd;
 952
 953         if (!is_psp_fw_valid(psp->rl))
 954                 return 0;
 955
 956         cmd = acquire_psp_cmd_buf(psp);
 957
 958         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 959         memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
 960
 961         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 962         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 963         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 964         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
 965         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
 966
 967         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 968
 969         release_psp_cmd_buf(psp);
 970
 971         return ret;
 972 }
 973
 974 static int psp_asd_initialize(struct psp_context *psp)
 975 {
 976         int ret;
 977
 978         /* If PSP version doesn't match ASD version, asd loading will be failed.
 979          * add workaround to bypass it for sriov now.
 980          * TODO: add version check to make it common
 981          */
 982         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
 983                 return 0;
 984
 985         psp->asd_context.mem_context.shared_mc_addr  = 0;
 986         psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
 987         psp->asd_context.ta_load_type                = GFX_CMD_ID_LOAD_ASD;
 988
 989         ret = psp_ta_load(psp, &psp->asd_context);
 990         if (!ret)
 991                 psp->asd_context.initialized = true;
 992
 993         return ret;
 994 }
 995
 996 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 997                                        uint32_t session_id)
 998 {
 999         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
1000         cmd->cmd.cmd_unload_ta.session_id = session_id;
1001 }
1002
1003 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
1004 {
1005         int ret;
1006         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1007
1008         psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
1009
1010         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1011
1012         context->resp_status = cmd->resp.status;
1013
1014         release_psp_cmd_buf(psp);
1015
1016         return ret;
1017 }
1018
1019 static int psp_asd_terminate(struct psp_context *psp)
1020 {
1021         int ret;
1022
1023         if (amdgpu_sriov_vf(psp->adev))
1024                 return 0;
1025
1026         if (!psp->asd_context.initialized)
1027                 return 0;
1028
1029         ret = psp_ta_unload(psp, &psp->asd_context);
1030         if (!ret)
1031                 psp->asd_context.initialized = false;
1032
1033         return ret;
1034 }
1035
1036 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1037                 uint32_t id, uint32_t value)
1038 {
1039         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1040         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1041         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1042 }
1043
1044 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1045                 uint32_t value)
1046 {
1047         struct psp_gfx_cmd_resp *cmd;
1048         int ret = 0;
1049
1050         if (reg >= PSP_REG_LAST)
1051                 return -EINVAL;
1052
1053         cmd = acquire_psp_cmd_buf(psp);
1054
1055         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1056         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1057         if (ret)
1058                 DRM_ERROR("PSP failed to program reg id %d", reg);
1059
1060         release_psp_cmd_buf(psp);
1061
1062         return ret;
1063 }
1064
1065 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1066                                      uint64_t ta_bin_mc,
1067                                      struct ta_context *context)
1068 {
1069         cmd->cmd_id                             = context->ta_load_type;
1070         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
1071         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
1072         cmd->cmd.cmd_load_ta.app_len            = context->bin_desc.size_bytes;
1073
1074         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1075                 lower_32_bits(context->mem_context.shared_mc_addr);
1076         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1077                 upper_32_bits(context->mem_context.shared_mc_addr);
1078         cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1079 }
1080
1081 int psp_ta_init_shared_buf(struct psp_context *psp,
1082                                   struct ta_mem_context *mem_ctx)
1083 {
1084         /*
1085         * Allocate 16k memory aligned to 4k from Frame Buffer (local
1086         * physical) for ta to host memory
1087         */
1088         return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1089                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
1090                                       AMDGPU_GEM_DOMAIN_GTT,
1091                                       &mem_ctx->shared_bo,
1092                                       &mem_ctx->shared_mc_addr,
1093                                       &mem_ctx->shared_buf);
1094 }
1095
1096 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1097                                        uint32_t ta_cmd_id,
1098                                        uint32_t session_id)
1099 {
1100         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
1101         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
1102         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
1103 }
1104
1105 int psp_ta_invoke(struct psp_context *psp,
1106                   uint32_t ta_cmd_id,
1107                   struct ta_context *context)
1108 {
1109         int ret;
1110         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1111
1112         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1113
1114         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1115                                  psp->fence_buf_mc_addr);
1116
1117         context->resp_status = cmd->resp.status;
1118
1119         release_psp_cmd_buf(psp);
1120
1121         return ret;
1122 }
1123
1124 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1125 {
1126         int ret;
1127         struct psp_gfx_cmd_resp *cmd;
1128
1129         cmd = acquire_psp_cmd_buf(psp);
1130
1131         psp_copy_fw(psp, context->bin_desc.start_addr,
1132                     context->bin_desc.size_bytes);
1133
1134         psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1135
1136         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1137                                  psp->fence_buf_mc_addr);
1138
1139         context->resp_status = cmd->resp.status;
1140
1141         if (!ret) {
1142                 context->session_id = cmd->resp.session_id;
1143         }
1144
1145         release_psp_cmd_buf(psp);
1146
1147         return ret;
1148 }
1149
1150 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1151 {
1152         return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1153 }
1154
1155 int psp_xgmi_terminate(struct psp_context *psp)
1156 {
1157         int ret;
1158         struct amdgpu_device *adev = psp->adev;
1159
1160         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1161         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1162             (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1163              adev->gmc.xgmi.connected_to_cpu))
1164                 return 0;
1165
1166         if (!psp->xgmi_context.context.initialized)
1167                 return 0;
1168
1169         ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1170
1171         psp->xgmi_context.context.initialized = false;
1172
1173         return ret;
1174 }
1175
1176 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1177 {
1178         struct ta_xgmi_shared_memory *xgmi_cmd;
1179         int ret;
1180
1181         if (!psp->ta_fw ||
1182             !psp->xgmi_context.context.bin_desc.size_bytes ||
1183             !psp->xgmi_context.context.bin_desc.start_addr)
1184                 return -ENOENT;
1185
1186         if (!load_ta)
1187                 goto invoke;
1188
1189         psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1190         psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1191
1192         if (!psp->xgmi_context.context.mem_context.shared_buf) {
1193                 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1194                 if (ret)
1195                         return ret;
1196         }
1197
1198         /* Load XGMI TA */
1199         ret = psp_ta_load(psp, &psp->xgmi_context.context);
1200         if (!ret)
1201                 psp->xgmi_context.context.initialized = true;
1202         else
1203                 return ret;
1204
1205 invoke:
1206         /* Initialize XGMI session */
1207         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1208         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1209         xgmi_cmd->flag_extend_link_record = set_extended_data;
1210         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1211
1212         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1213
1214         return ret;
1215 }
1216
1217 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1218 {
1219         struct ta_xgmi_shared_memory *xgmi_cmd;
1220         int ret;
1221
1222         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1223         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1224
1225         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1226
1227         /* Invoke xgmi ta to get hive id */
1228         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1229         if (ret)
1230                 return ret;
1231
1232         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1233
1234         return 0;
1235 }
1236
1237 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1238 {
1239         struct ta_xgmi_shared_memory *xgmi_cmd;
1240         int ret;
1241
1242         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1243         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1244
1245         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1246
1247         /* Invoke xgmi ta to get the node id */
1248         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1249         if (ret)
1250                 return ret;
1251
1252         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1253
1254         return 0;
1255 }
1256
1257 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1258 {
1259         return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1260                 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b;
1261 }
1262
1263 /*
1264  * Chips that support extended topology information require the driver to
1265  * reflect topology information in the opposite direction.  This is
1266  * because the TA has already exceeded its link record limit and if the
1267  * TA holds bi-directional information, the driver would have to do
1268  * multiple fetches instead of just two.
1269  */
1270 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1271                                         struct psp_xgmi_node_info node_info)
1272 {
1273         struct amdgpu_device *mirror_adev;
1274         struct amdgpu_hive_info *hive;
1275         uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1276         uint64_t dst_node_id = node_info.node_id;
1277         uint8_t dst_num_hops = node_info.num_hops;
1278         uint8_t dst_num_links = node_info.num_links;
1279
1280         hive = amdgpu_get_xgmi_hive(psp->adev);
1281         list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1282                 struct psp_xgmi_topology_info *mirror_top_info;
1283                 int j;
1284
1285                 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1286                         continue;
1287
1288                 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1289                 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1290                         if (mirror_top_info->nodes[j].node_id != src_node_id)
1291                                 continue;
1292
1293                         mirror_top_info->nodes[j].num_hops = dst_num_hops;
1294                         /*
1295                          * prevent 0 num_links value re-reflection since reflection
1296                          * criteria is based on num_hops (direct or indirect).
1297                          *
1298                          */
1299                         if (dst_num_links)
1300                                 mirror_top_info->nodes[j].num_links = dst_num_links;
1301
1302                         break;
1303                 }
1304
1305                 break;
1306         }
1307
1308         amdgpu_put_xgmi_hive(hive);
1309 }
1310
1311 int psp_xgmi_get_topology_info(struct psp_context *psp,
1312                                int number_devices,
1313                                struct psp_xgmi_topology_info *topology,
1314                                bool get_extended_data)
1315 {
1316         struct ta_xgmi_shared_memory *xgmi_cmd;
1317         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1318         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1319         int i;
1320         int ret;
1321
1322         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1323                 return -EINVAL;
1324
1325         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1326         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1327         xgmi_cmd->flag_extend_link_record = get_extended_data;
1328
1329         /* Fill in the shared memory with topology information as input */
1330         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1331         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1332         topology_info_input->num_nodes = number_devices;
1333
1334         for (i = 0; i < topology_info_input->num_nodes; i++) {
1335                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1336                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1337                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1338                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1339         }
1340
1341         /* Invoke xgmi ta to get the topology information */
1342         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1343         if (ret)
1344                 return ret;
1345
1346         /* Read the output topology information from the shared memory */
1347         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1348         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1349         for (i = 0; i < topology->num_nodes; i++) {
1350                 /* extended data will either be 0 or equal to non-extended data */
1351                 if (topology_info_output->nodes[i].num_hops)
1352                         topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1353
1354                 /* non-extended data gets everything here so no need to update */
1355                 if (!get_extended_data) {
1356                         topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1357                         topology->nodes[i].is_sharing_enabled =
1358                                         topology_info_output->nodes[i].is_sharing_enabled;
1359                         topology->nodes[i].sdma_engine =
1360                                         topology_info_output->nodes[i].sdma_engine;
1361                 }
1362
1363         }
1364
1365         /* Invoke xgmi ta again to get the link information */
1366         if (psp_xgmi_peer_link_info_supported(psp)) {
1367                 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1368
1369                 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1370
1371                 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1372
1373                 if (ret)
1374                         return ret;
1375
1376                 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1377                 for (i = 0; i < topology->num_nodes; i++) {
1378                         /* accumulate num_links on extended data */
1379                         topology->nodes[i].num_links = get_extended_data ?
1380                                         topology->nodes[i].num_links +
1381                                                         link_info_output->nodes[i].num_links :
1382                                         link_info_output->nodes[i].num_links;
1383
1384                         /* reflect the topology information for bi-directionality */
1385                         if (psp->xgmi_context.supports_extended_data &&
1386                                         get_extended_data && topology->nodes[i].num_hops)
1387                                 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1388                 }
1389         }
1390
1391         return 0;
1392 }
1393
1394 int psp_xgmi_set_topology_info(struct psp_context *psp,
1395                                int number_devices,
1396                                struct psp_xgmi_topology_info *topology)
1397 {
1398         struct ta_xgmi_shared_memory *xgmi_cmd;
1399         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1400         int i;
1401
1402         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1403                 return -EINVAL;
1404
1405         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1406         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1407
1408         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1409         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1410         topology_info_input->num_nodes = number_devices;
1411
1412         for (i = 0; i < topology_info_input->num_nodes; i++) {
1413                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1414                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1415                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1416                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1417         }
1418
1419         /* Invoke xgmi ta to set topology information */
1420         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1421 }
1422
1423 // ras begin
1424 static void psp_ras_ta_check_status(struct psp_context *psp)
1425 {
1426         struct ta_ras_shared_memory *ras_cmd =
1427                 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1428
1429         switch (ras_cmd->ras_status) {
1430         case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1431                 dev_warn(psp->adev->dev,
1432                                 "RAS WARNING: cmd failed due to unsupported ip\n");
1433                 break;
1434         case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1435                 dev_warn(psp->adev->dev,
1436                                 "RAS WARNING: cmd failed due to unsupported error injection\n");
1437                 break;
1438         case TA_RAS_STATUS__SUCCESS:
1439                 break;
1440         case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1441                 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1442                         dev_warn(psp->adev->dev,
1443                                         "RAS WARNING: Inject error to critical region is not allowed\n");
1444                 break;
1445         default:
1446                 dev_warn(psp->adev->dev,
1447                                 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1448                 break;
1449         }
1450 }
1451
1452 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1453 {
1454         struct ta_ras_shared_memory *ras_cmd;
1455         int ret;
1456
1457         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1458
1459         /*
1460          * TODO: bypass the loading in sriov for now
1461          */
1462         if (amdgpu_sriov_vf(psp->adev))
1463                 return 0;
1464
1465         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1466
1467         if (amdgpu_ras_intr_triggered())
1468                 return ret;
1469
1470         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1471         {
1472                 DRM_WARN("RAS: Unsupported Interface");
1473                 return -EINVAL;
1474         }
1475
1476         if (!ret) {
1477                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1478                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1479
1480                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1481                 }
1482                 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1483                         dev_warn(psp->adev->dev,
1484                                  "RAS internal register access blocked\n");
1485
1486                 psp_ras_ta_check_status(psp);
1487         }
1488
1489         return ret;
1490 }
1491
1492 int psp_ras_enable_features(struct psp_context *psp,
1493                 union ta_ras_cmd_input *info, bool enable)
1494 {
1495         struct ta_ras_shared_memory *ras_cmd;
1496         int ret;
1497
1498         if (!psp->ras_context.context.initialized)
1499                 return -EINVAL;
1500
1501         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1502         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1503
1504         if (enable)
1505                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1506         else
1507                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1508
1509         ras_cmd->ras_in_message = *info;
1510
1511         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1512         if (ret)
1513                 return -EINVAL;
1514
1515         return 0;
1516 }
1517
1518 int psp_ras_terminate(struct psp_context *psp)
1519 {
1520         int ret;
1521
1522         /*
1523          * TODO: bypass the terminate in sriov for now
1524          */
1525         if (amdgpu_sriov_vf(psp->adev))
1526                 return 0;
1527
1528         if (!psp->ras_context.context.initialized)
1529                 return 0;
1530
1531         ret = psp_ta_unload(psp, &psp->ras_context.context);
1532
1533         psp->ras_context.context.initialized = false;
1534
1535         return ret;
1536 }
1537
1538 int psp_ras_initialize(struct psp_context *psp)
1539 {
1540         int ret;
1541         uint32_t boot_cfg = 0xFF;
1542         struct amdgpu_device *adev = psp->adev;
1543         struct ta_ras_shared_memory *ras_cmd;
1544
1545         /*
1546          * TODO: bypass the initialize in sriov for now
1547          */
1548         if (amdgpu_sriov_vf(adev))
1549                 return 0;
1550
1551         if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1552             !adev->psp.ras_context.context.bin_desc.start_addr) {
1553                 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1554                 return 0;
1555         }
1556
1557         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1558                 /* query GECC enablement status from boot config
1559                  * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1560                  */
1561                 ret = psp_boot_config_get(adev, &boot_cfg);
1562                 if (ret)
1563                         dev_warn(adev->dev, "PSP get boot config failed\n");
1564
1565                 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1566                         if (!boot_cfg) {
1567                                 dev_info(adev->dev, "GECC is disabled\n");
1568                         } else {
1569                                 /* disable GECC in next boot cycle if ras is
1570                                  * disabled by module parameter amdgpu_ras_enable
1571                                  * and/or amdgpu_ras_mask, or boot_config_get call
1572                                  * is failed
1573                                  */
1574                                 ret = psp_boot_config_set(adev, 0);
1575                                 if (ret)
1576                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1577                                 else
1578                                         dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1579                                                  "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1580                         }
1581                 } else {
1582                         if (1 == boot_cfg) {
1583                                 dev_info(adev->dev, "GECC is enabled\n");
1584                         } else {
1585                                 /* enable GECC in next boot cycle if it is disabled
1586                                  * in boot config, or force enable GECC if failed to
1587                                  * get boot configuration
1588                                  */
1589                                 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1590                                 if (ret)
1591                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1592                                 else
1593                                         dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1594                         }
1595                 }
1596         }
1597
1598         psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1599         psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1600
1601         if (!psp->ras_context.context.mem_context.shared_buf) {
1602                 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1603                 if (ret)
1604                         return ret;
1605         }
1606
1607         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1608         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1609
1610         if (amdgpu_ras_is_poison_mode_supported(adev))
1611                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1612         if (!adev->gmc.xgmi.connected_to_cpu)
1613                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1614
1615         ret = psp_ta_load(psp, &psp->ras_context.context);
1616
1617         if (!ret && !ras_cmd->ras_status)
1618                 psp->ras_context.context.initialized = true;
1619         else {
1620                 if (ras_cmd->ras_status)
1621                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1622
1623                 /* fail to load RAS TA */
1624                 psp->ras_context.context.initialized = false;
1625         }
1626
1627         return ret;
1628 }
1629
1630 int psp_ras_trigger_error(struct psp_context *psp,
1631                           struct ta_ras_trigger_error_input *info)
1632 {
1633         struct ta_ras_shared_memory *ras_cmd;
1634         int ret;
1635
1636         if (!psp->ras_context.context.initialized)
1637                 return -EINVAL;
1638
1639         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1640         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1641
1642         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1643         ras_cmd->ras_in_message.trigger_error = *info;
1644
1645         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1646         if (ret)
1647                 return -EINVAL;
1648
1649         /* If err_event_athub occurs error inject was successful, however
1650            return status from TA is no long reliable */
1651         if (amdgpu_ras_intr_triggered())
1652                 return 0;
1653
1654         if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1655                 return -EACCES;
1656         else if (ras_cmd->ras_status)
1657                 return -EINVAL;
1658
1659         return 0;
1660 }
1661 // ras end
1662
1663 // HDCP start
1664 static int psp_hdcp_initialize(struct psp_context *psp)
1665 {
1666         int ret;
1667
1668         /*
1669          * TODO: bypass the initialize in sriov for now
1670          */
1671         if (amdgpu_sriov_vf(psp->adev))
1672                 return 0;
1673
1674         if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1675             !psp->hdcp_context.context.bin_desc.start_addr) {
1676                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1677                 return 0;
1678         }
1679
1680         psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1681         psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1682
1683         if (!psp->hdcp_context.context.mem_context.shared_buf) {
1684                 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1685                 if (ret)
1686                         return ret;
1687         }
1688
1689         ret = psp_ta_load(psp, &psp->hdcp_context.context);
1690         if (!ret) {
1691                 psp->hdcp_context.context.initialized = true;
1692                 mutex_init(&psp->hdcp_context.mutex);
1693         }
1694
1695         return ret;
1696 }
1697
1698 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1699 {
1700         /*
1701          * TODO: bypass the loading in sriov for now
1702          */
1703         if (amdgpu_sriov_vf(psp->adev))
1704                 return 0;
1705
1706         return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1707 }
1708
1709 static int psp_hdcp_terminate(struct psp_context *psp)
1710 {
1711         int ret;
1712
1713         /*
1714          * TODO: bypass the terminate in sriov for now
1715          */
1716         if (amdgpu_sriov_vf(psp->adev))
1717                 return 0;
1718
1719         if (!psp->hdcp_context.context.initialized)
1720                 return 0;
1721
1722         ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1723
1724         psp->hdcp_context.context.initialized = false;
1725
1726         return ret;
1727 }
1728 // HDCP end
1729
1730 // DTM start
1731 static int psp_dtm_initialize(struct psp_context *psp)
1732 {
1733         int ret;
1734
1735         /*
1736          * TODO: bypass the initialize in sriov for now
1737          */
1738         if (amdgpu_sriov_vf(psp->adev))
1739                 return 0;
1740
1741         if (!psp->dtm_context.context.bin_desc.size_bytes ||
1742             !psp->dtm_context.context.bin_desc.start_addr) {
1743                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1744                 return 0;
1745         }
1746
1747         psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1748         psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1749
1750         if (!psp->dtm_context.context.mem_context.shared_buf) {
1751                 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1752                 if (ret)
1753                         return ret;
1754         }
1755
1756         ret = psp_ta_load(psp, &psp->dtm_context.context);
1757         if (!ret) {
1758                 psp->dtm_context.context.initialized = true;
1759                 mutex_init(&psp->dtm_context.mutex);
1760         }
1761
1762         return ret;
1763 }
1764
1765 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1766 {
1767         /*
1768          * TODO: bypass the loading in sriov for now
1769          */
1770         if (amdgpu_sriov_vf(psp->adev))
1771                 return 0;
1772
1773         return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1774 }
1775
1776 static int psp_dtm_terminate(struct psp_context *psp)
1777 {
1778         int ret;
1779
1780         /*
1781          * TODO: bypass the terminate in sriov for now
1782          */
1783         if (amdgpu_sriov_vf(psp->adev))
1784                 return 0;
1785
1786         if (!psp->dtm_context.context.initialized)
1787                 return 0;
1788
1789         ret = psp_ta_unload(psp, &psp->dtm_context.context);
1790
1791         psp->dtm_context.context.initialized = false;
1792
1793         return ret;
1794 }
1795 // DTM end
1796
1797 // RAP start
1798 static int psp_rap_initialize(struct psp_context *psp)
1799 {
1800         int ret;
1801         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1802
1803         /*
1804          * TODO: bypass the initialize in sriov for now
1805          */
1806         if (amdgpu_sriov_vf(psp->adev))
1807                 return 0;
1808
1809         if (!psp->rap_context.context.bin_desc.size_bytes ||
1810             !psp->rap_context.context.bin_desc.start_addr) {
1811                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1812                 return 0;
1813         }
1814
1815         psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1816         psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1817
1818         if (!psp->rap_context.context.mem_context.shared_buf) {
1819                 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1820                 if (ret)
1821                         return ret;
1822         }
1823
1824         ret = psp_ta_load(psp, &psp->rap_context.context);
1825         if (!ret) {
1826                 psp->rap_context.context.initialized = true;
1827                 mutex_init(&psp->rap_context.mutex);
1828         } else
1829                 return ret;
1830
1831         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1832         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1833                 psp_rap_terminate(psp);
1834                 /* free rap shared memory */
1835                 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1836
1837                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1838                          ret, status);
1839
1840                 return ret;
1841         }
1842
1843         return 0;
1844 }
1845
1846 static int psp_rap_terminate(struct psp_context *psp)
1847 {
1848         int ret;
1849
1850         if (!psp->rap_context.context.initialized)
1851                 return 0;
1852
1853         ret = psp_ta_unload(psp, &psp->rap_context.context);
1854
1855         psp->rap_context.context.initialized = false;
1856
1857         return ret;
1858 }
1859
1860 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1861 {
1862         struct ta_rap_shared_memory *rap_cmd;
1863         int ret = 0;
1864
1865         if (!psp->rap_context.context.initialized)
1866                 return 0;
1867
1868         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1869             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1870                 return -EINVAL;
1871
1872         mutex_lock(&psp->rap_context.mutex);
1873
1874         rap_cmd = (struct ta_rap_shared_memory *)
1875                   psp->rap_context.context.mem_context.shared_buf;
1876         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1877
1878         rap_cmd->cmd_id = ta_cmd_id;
1879         rap_cmd->validation_method_id = METHOD_A;
1880
1881         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1882         if (ret)
1883                 goto out_unlock;
1884
1885         if (status)
1886                 *status = rap_cmd->rap_status;
1887
1888 out_unlock:
1889         mutex_unlock(&psp->rap_context.mutex);
1890
1891         return ret;
1892 }
1893 // RAP end
1894
1895 /* securedisplay start */
1896 static int psp_securedisplay_initialize(struct psp_context *psp)
1897 {
1898         int ret;
1899         struct ta_securedisplay_cmd *securedisplay_cmd;
1900
1901         /*
1902          * TODO: bypass the initialize in sriov for now
1903          */
1904         if (amdgpu_sriov_vf(psp->adev))
1905                 return 0;
1906
1907         if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1908             !psp->securedisplay_context.context.bin_desc.start_addr) {
1909                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1910                 return 0;
1911         }
1912
1913         psp->securedisplay_context.context.mem_context.shared_mem_size =
1914                 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1915         psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1916
1917         if (!psp->securedisplay_context.context.initialized) {
1918                 ret = psp_ta_init_shared_buf(psp,
1919                                              &psp->securedisplay_context.context.mem_context);
1920                 if (ret)
1921                         return ret;
1922         }
1923
1924         ret = psp_ta_load(psp, &psp->securedisplay_context.context);
1925         if (!ret) {
1926                 psp->securedisplay_context.context.initialized = true;
1927                 mutex_init(&psp->securedisplay_context.mutex);
1928         } else
1929                 return ret;
1930
1931         mutex_lock(&psp->securedisplay_context.mutex);
1932
1933         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1934                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1935
1936         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1937
1938         mutex_unlock(&psp->securedisplay_context.mutex);
1939
1940         if (ret) {
1941                 psp_securedisplay_terminate(psp);
1942                 /* free securedisplay shared memory */
1943                 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
1944                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1945                 return -EINVAL;
1946         }
1947
1948         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1949                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1950                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1951                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1952         }
1953
1954         return 0;
1955 }
1956
1957 static int psp_securedisplay_terminate(struct psp_context *psp)
1958 {
1959         int ret;
1960
1961         /*
1962          * TODO:bypass the terminate in sriov for now
1963          */
1964         if (amdgpu_sriov_vf(psp->adev))
1965                 return 0;
1966
1967         if (!psp->securedisplay_context.context.initialized)
1968                 return 0;
1969
1970         ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
1971
1972         psp->securedisplay_context.context.initialized = false;
1973
1974         return ret;
1975 }
1976
1977 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1978 {
1979         int ret;
1980
1981         if (!psp->securedisplay_context.context.initialized)
1982                 return -EINVAL;
1983
1984         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
1985             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
1986                 return -EINVAL;
1987
1988         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
1989
1990         return ret;
1991 }
1992 /* SECUREDISPLAY end */
1993
1994 static int psp_hw_start(struct psp_context *psp)
1995 {
1996         struct amdgpu_device *adev = psp->adev;
1997         int ret;
1998
1999         if (!amdgpu_sriov_vf(adev)) {
2000                 if ((is_psp_fw_valid(psp->kdb)) &&
2001                     (psp->funcs->bootloader_load_kdb != NULL)) {
2002                         ret = psp_bootloader_load_kdb(psp);
2003                         if (ret) {
2004                                 DRM_ERROR("PSP load kdb failed!\n");
2005                                 return ret;
2006                         }
2007                 }
2008
2009                 if ((is_psp_fw_valid(psp->spl)) &&
2010                     (psp->funcs->bootloader_load_spl != NULL)) {
2011                         ret = psp_bootloader_load_spl(psp);
2012                         if (ret) {
2013                                 DRM_ERROR("PSP load spl failed!\n");
2014                                 return ret;
2015                         }
2016                 }
2017
2018                 if ((is_psp_fw_valid(psp->sys)) &&
2019                     (psp->funcs->bootloader_load_sysdrv != NULL)) {
2020                         ret = psp_bootloader_load_sysdrv(psp);
2021                         if (ret) {
2022                                 DRM_ERROR("PSP load sys drv failed!\n");
2023                                 return ret;
2024                         }
2025                 }
2026
2027                 if ((is_psp_fw_valid(psp->soc_drv)) &&
2028                     (psp->funcs->bootloader_load_soc_drv != NULL)) {
2029                         ret = psp_bootloader_load_soc_drv(psp);
2030                         if (ret) {
2031                                 DRM_ERROR("PSP load soc drv failed!\n");
2032                                 return ret;
2033                         }
2034                 }
2035
2036                 if ((is_psp_fw_valid(psp->intf_drv)) &&
2037                     (psp->funcs->bootloader_load_intf_drv != NULL)) {
2038                         ret = psp_bootloader_load_intf_drv(psp);
2039                         if (ret) {
2040                                 DRM_ERROR("PSP load intf drv failed!\n");
2041                                 return ret;
2042                         }
2043                 }
2044
2045                 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2046                     (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2047                         ret = psp_bootloader_load_dbg_drv(psp);
2048                         if (ret) {
2049                                 DRM_ERROR("PSP load dbg drv failed!\n");
2050                                 return ret;
2051                         }
2052                 }
2053
2054                 if ((is_psp_fw_valid(psp->ras_drv)) &&
2055                     (psp->funcs->bootloader_load_ras_drv != NULL)) {
2056                         ret = psp_bootloader_load_ras_drv(psp);
2057                         if (ret) {
2058                                 DRM_ERROR("PSP load ras_drv failed!\n");
2059                                 return ret;
2060                         }
2061                 }
2062
2063                 if ((is_psp_fw_valid(psp->sos)) &&
2064                     (psp->funcs->bootloader_load_sos != NULL)) {
2065                         ret = psp_bootloader_load_sos(psp);
2066                         if (ret) {
2067                                 DRM_ERROR("PSP load sos failed!\n");
2068                                 return ret;
2069                         }
2070                 }
2071         }
2072
2073         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2074         if (ret) {
2075                 DRM_ERROR("PSP create ring failed!\n");
2076                 return ret;
2077         }
2078
2079         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2080                 goto skip_pin_bo;
2081
2082         ret = psp_tmr_init(psp);
2083         if (ret) {
2084                 DRM_ERROR("PSP tmr init failed!\n");
2085                 return ret;
2086         }
2087
2088 skip_pin_bo:
2089         /*
2090          * For ASICs with DF Cstate management centralized
2091          * to PMFW, TMR setup should be performed after PMFW
2092          * loaded and before other non-psp firmware loaded.
2093          */
2094         if (psp->pmfw_centralized_cstate_management) {
2095                 ret = psp_load_smu_fw(psp);
2096                 if (ret)
2097                         return ret;
2098         }
2099
2100         ret = psp_tmr_load(psp);
2101         if (ret) {
2102                 DRM_ERROR("PSP load tmr failed!\n");
2103                 return ret;
2104         }
2105
2106         return 0;
2107 }
2108
2109 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2110                            enum psp_gfx_fw_type *type)
2111 {
2112         switch (ucode->ucode_id) {
2113         case AMDGPU_UCODE_ID_CAP:
2114                 *type = GFX_FW_TYPE_CAP;
2115                 break;
2116         case AMDGPU_UCODE_ID_SDMA0:
2117                 *type = GFX_FW_TYPE_SDMA0;
2118                 break;
2119         case AMDGPU_UCODE_ID_SDMA1:
2120                 *type = GFX_FW_TYPE_SDMA1;
2121                 break;
2122         case AMDGPU_UCODE_ID_SDMA2:
2123                 *type = GFX_FW_TYPE_SDMA2;
2124                 break;
2125         case AMDGPU_UCODE_ID_SDMA3:
2126                 *type = GFX_FW_TYPE_SDMA3;
2127                 break;
2128         case AMDGPU_UCODE_ID_SDMA4:
2129                 *type = GFX_FW_TYPE_SDMA4;
2130                 break;
2131         case AMDGPU_UCODE_ID_SDMA5:
2132                 *type = GFX_FW_TYPE_SDMA5;
2133                 break;
2134         case AMDGPU_UCODE_ID_SDMA6:
2135                 *type = GFX_FW_TYPE_SDMA6;
2136                 break;
2137         case AMDGPU_UCODE_ID_SDMA7:
2138                 *type = GFX_FW_TYPE_SDMA7;
2139                 break;
2140         case AMDGPU_UCODE_ID_CP_MES:
2141                 *type = GFX_FW_TYPE_CP_MES;
2142                 break;
2143         case AMDGPU_UCODE_ID_CP_MES_DATA:
2144                 *type = GFX_FW_TYPE_MES_STACK;
2145                 break;
2146         case AMDGPU_UCODE_ID_CP_MES1:
2147                 *type = GFX_FW_TYPE_CP_MES_KIQ;
2148                 break;
2149         case AMDGPU_UCODE_ID_CP_MES1_DATA:
2150                 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2151                 break;
2152         case AMDGPU_UCODE_ID_CP_CE:
2153                 *type = GFX_FW_TYPE_CP_CE;
2154                 break;
2155         case AMDGPU_UCODE_ID_CP_PFP:
2156                 *type = GFX_FW_TYPE_CP_PFP;
2157                 break;
2158         case AMDGPU_UCODE_ID_CP_ME:
2159                 *type = GFX_FW_TYPE_CP_ME;
2160                 break;
2161         case AMDGPU_UCODE_ID_CP_MEC1:
2162                 *type = GFX_FW_TYPE_CP_MEC;
2163                 break;
2164         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2165                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2166                 break;
2167         case AMDGPU_UCODE_ID_CP_MEC2:
2168                 *type = GFX_FW_TYPE_CP_MEC;
2169                 break;
2170         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2171                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2172                 break;
2173         case AMDGPU_UCODE_ID_RLC_P:
2174                 *type = GFX_FW_TYPE_RLC_P;
2175                 break;
2176         case AMDGPU_UCODE_ID_RLC_V:
2177                 *type = GFX_FW_TYPE_RLC_V;
2178                 break;
2179         case AMDGPU_UCODE_ID_RLC_G:
2180                 *type = GFX_FW_TYPE_RLC_G;
2181                 break;
2182         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2183                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2184                 break;
2185         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2186                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2187                 break;
2188         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2189                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2190                 break;
2191         case AMDGPU_UCODE_ID_RLC_IRAM:
2192                 *type = GFX_FW_TYPE_RLC_IRAM;
2193                 break;
2194         case AMDGPU_UCODE_ID_RLC_DRAM:
2195                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2196                 break;
2197         case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2198                 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2199                 break;
2200         case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2201                 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2202                 break;
2203         case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2204                 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2205                 break;
2206         case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2207                 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2208                 break;
2209         case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2210                 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2211                 break;
2212         case AMDGPU_UCODE_ID_SMC:
2213                 *type = GFX_FW_TYPE_SMU;
2214                 break;
2215         case AMDGPU_UCODE_ID_PPTABLE:
2216                 *type = GFX_FW_TYPE_PPTABLE;
2217                 break;
2218         case AMDGPU_UCODE_ID_UVD:
2219                 *type = GFX_FW_TYPE_UVD;
2220                 break;
2221         case AMDGPU_UCODE_ID_UVD1:
2222                 *type = GFX_FW_TYPE_UVD1;
2223                 break;
2224         case AMDGPU_UCODE_ID_VCE:
2225                 *type = GFX_FW_TYPE_VCE;
2226                 break;
2227         case AMDGPU_UCODE_ID_VCN:
2228                 *type = GFX_FW_TYPE_VCN;
2229                 break;
2230         case AMDGPU_UCODE_ID_VCN1:
2231                 *type = GFX_FW_TYPE_VCN1;
2232                 break;
2233         case AMDGPU_UCODE_ID_DMCU_ERAM:
2234                 *type = GFX_FW_TYPE_DMCU_ERAM;
2235                 break;
2236         case AMDGPU_UCODE_ID_DMCU_INTV:
2237                 *type = GFX_FW_TYPE_DMCU_ISR;
2238                 break;
2239         case AMDGPU_UCODE_ID_VCN0_RAM:
2240                 *type = GFX_FW_TYPE_VCN0_RAM;
2241                 break;
2242         case AMDGPU_UCODE_ID_VCN1_RAM:
2243                 *type = GFX_FW_TYPE_VCN1_RAM;
2244                 break;
2245         case AMDGPU_UCODE_ID_DMCUB:
2246                 *type = GFX_FW_TYPE_DMUB;
2247                 break;
2248         case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2249                 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2250                 break;
2251         case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2252                 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2253                 break;
2254         case AMDGPU_UCODE_ID_IMU_I:
2255                 *type = GFX_FW_TYPE_IMU_I;
2256                 break;
2257         case AMDGPU_UCODE_ID_IMU_D:
2258                 *type = GFX_FW_TYPE_IMU_D;
2259                 break;
2260         case AMDGPU_UCODE_ID_CP_RS64_PFP:
2261                 *type = GFX_FW_TYPE_RS64_PFP;
2262                 break;
2263         case AMDGPU_UCODE_ID_CP_RS64_ME:
2264                 *type = GFX_FW_TYPE_RS64_ME;
2265                 break;
2266         case AMDGPU_UCODE_ID_CP_RS64_MEC:
2267                 *type = GFX_FW_TYPE_RS64_MEC;
2268                 break;
2269         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2270                 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2271                 break;
2272         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2273                 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2274                 break;
2275         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2276                 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2277                 break;
2278         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2279                 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2280                 break;
2281         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2282                 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2283                 break;
2284         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2285                 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2286                 break;
2287         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2288                 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2289                 break;
2290         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2291                 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2292                 break;
2293         case AMDGPU_UCODE_ID_MAXIMUM:
2294         default:
2295                 return -EINVAL;
2296         }
2297
2298         return 0;
2299 }
2300
2301 static void psp_print_fw_hdr(struct psp_context *psp,
2302                              struct amdgpu_firmware_info *ucode)
2303 {
2304         struct amdgpu_device *adev = psp->adev;
2305         struct common_firmware_header *hdr;
2306
2307         switch (ucode->ucode_id) {
2308         case AMDGPU_UCODE_ID_SDMA0:
2309         case AMDGPU_UCODE_ID_SDMA1:
2310         case AMDGPU_UCODE_ID_SDMA2:
2311         case AMDGPU_UCODE_ID_SDMA3:
2312         case AMDGPU_UCODE_ID_SDMA4:
2313         case AMDGPU_UCODE_ID_SDMA5:
2314         case AMDGPU_UCODE_ID_SDMA6:
2315         case AMDGPU_UCODE_ID_SDMA7:
2316                 hdr = (struct common_firmware_header *)
2317                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2318                 amdgpu_ucode_print_sdma_hdr(hdr);
2319                 break;
2320         case AMDGPU_UCODE_ID_CP_CE:
2321                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2322                 amdgpu_ucode_print_gfx_hdr(hdr);
2323                 break;
2324         case AMDGPU_UCODE_ID_CP_PFP:
2325                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2326                 amdgpu_ucode_print_gfx_hdr(hdr);
2327                 break;
2328         case AMDGPU_UCODE_ID_CP_ME:
2329                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2330                 amdgpu_ucode_print_gfx_hdr(hdr);
2331                 break;
2332         case AMDGPU_UCODE_ID_CP_MEC1:
2333                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2334                 amdgpu_ucode_print_gfx_hdr(hdr);
2335                 break;
2336         case AMDGPU_UCODE_ID_RLC_G:
2337                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2338                 amdgpu_ucode_print_rlc_hdr(hdr);
2339                 break;
2340         case AMDGPU_UCODE_ID_SMC:
2341                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2342                 amdgpu_ucode_print_smc_hdr(hdr);
2343                 break;
2344         default:
2345                 break;
2346         }
2347 }
2348
2349 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2350                                        struct psp_gfx_cmd_resp *cmd)
2351 {
2352         int ret;
2353         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2354
2355         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2356         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2357         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2358         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2359
2360         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2361         if (ret)
2362                 DRM_ERROR("Unknown firmware type\n");
2363
2364         return ret;
2365 }
2366
2367 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2368                                   struct amdgpu_firmware_info *ucode)
2369 {
2370         int ret = 0;
2371         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2372
2373         ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2374         if (!ret) {
2375                 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2376                                          psp->fence_buf_mc_addr);
2377         }
2378
2379         release_psp_cmd_buf(psp);
2380
2381         return ret;
2382 }
2383
2384 static int psp_load_smu_fw(struct psp_context *psp)
2385 {
2386         int ret;
2387         struct amdgpu_device *adev = psp->adev;
2388         struct amdgpu_firmware_info *ucode =
2389                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2390         struct amdgpu_ras *ras = psp->ras_context.ras;
2391
2392         /*
2393          * Skip SMU FW reloading in case of using BACO for runpm only,
2394          * as SMU is always alive.
2395          */
2396         if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2397                 return 0;
2398
2399         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2400                 return 0;
2401
2402         if ((amdgpu_in_reset(adev) &&
2403              ras && adev->ras_enabled &&
2404              (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2405               adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2406                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2407                 if (ret) {
2408                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2409                 }
2410         }
2411
2412         ret = psp_execute_non_psp_fw_load(psp, ucode);
2413
2414         if (ret)
2415                 DRM_ERROR("PSP load smu failed!\n");
2416
2417         return ret;
2418 }
2419
2420 static bool fw_load_skip_check(struct psp_context *psp,
2421                                struct amdgpu_firmware_info *ucode)
2422 {
2423         if (!ucode->fw || !ucode->ucode_size)
2424                 return true;
2425
2426         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2427             (psp_smu_reload_quirk(psp) ||
2428              psp->autoload_supported ||
2429              psp->pmfw_centralized_cstate_management))
2430                 return true;
2431
2432         if (amdgpu_sriov_vf(psp->adev) &&
2433             amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2434                 return true;
2435
2436         if (psp->autoload_supported &&
2437             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2438              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2439                 /* skip mec JT when autoload is enabled */
2440                 return true;
2441
2442         return false;
2443 }
2444
2445 int psp_load_fw_list(struct psp_context *psp,
2446                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2447 {
2448         int ret = 0, i;
2449         struct amdgpu_firmware_info *ucode;
2450
2451         for (i = 0; i < ucode_count; ++i) {
2452                 ucode = ucode_list[i];
2453                 psp_print_fw_hdr(psp, ucode);
2454                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2455                 if (ret)
2456                         return ret;
2457         }
2458         return ret;
2459 }
2460
2461 static int psp_load_non_psp_fw(struct psp_context *psp)
2462 {
2463         int i, ret;
2464         struct amdgpu_firmware_info *ucode;
2465         struct amdgpu_device *adev = psp->adev;
2466
2467         if (psp->autoload_supported &&
2468             !psp->pmfw_centralized_cstate_management) {
2469                 ret = psp_load_smu_fw(psp);
2470                 if (ret)
2471                         return ret;
2472         }
2473
2474         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2475                 ucode = &adev->firmware.ucode[i];
2476
2477                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2478                     !fw_load_skip_check(psp, ucode)) {
2479                         ret = psp_load_smu_fw(psp);
2480                         if (ret)
2481                                 return ret;
2482                         continue;
2483                 }
2484
2485                 if (fw_load_skip_check(psp, ucode))
2486                         continue;
2487
2488                 if (psp->autoload_supported &&
2489                     (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2490                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2491                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2492                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2493                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2494                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2495                         /* PSP only receive one SDMA fw for sienna_cichlid,
2496                          * as all four sdma fw are same */
2497                         continue;
2498
2499                 psp_print_fw_hdr(psp, ucode);
2500
2501                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2502                 if (ret)
2503                         return ret;
2504
2505                 /* Start rlc autoload after psp recieved all the gfx firmware */
2506                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2507                     adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2508                         ret = psp_rlc_autoload_start(psp);
2509                         if (ret) {
2510                                 DRM_ERROR("Failed to start rlc autoload\n");
2511                                 return ret;
2512                         }
2513                 }
2514         }
2515
2516         return 0;
2517 }
2518
2519 static int psp_load_fw(struct amdgpu_device *adev)
2520 {
2521         int ret;
2522         struct psp_context *psp = &adev->psp;
2523
2524         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2525                 /* should not destroy ring, only stop */
2526                 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2527         } else {
2528                 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2529
2530                 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2531                 if (ret) {
2532                         DRM_ERROR("PSP ring init failed!\n");
2533                         goto failed;
2534                 }
2535         }
2536
2537         ret = psp_hw_start(psp);
2538         if (ret)
2539                 goto failed;
2540
2541         ret = psp_load_non_psp_fw(psp);
2542         if (ret)
2543                 goto failed1;
2544
2545         ret = psp_asd_initialize(psp);
2546         if (ret) {
2547                 DRM_ERROR("PSP load asd failed!\n");
2548                 goto failed1;
2549         }
2550
2551         ret = psp_rl_load(adev);
2552         if (ret) {
2553                 DRM_ERROR("PSP load RL failed!\n");
2554                 goto failed1;
2555         }
2556
2557         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2558                 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2559                         ret = psp_xgmi_initialize(psp, false, true);
2560                         /* Warning the XGMI seesion initialize failure
2561                         * Instead of stop driver initialization
2562                         */
2563                         if (ret)
2564                                 dev_err(psp->adev->dev,
2565                                         "XGMI: Failed to initialize XGMI session\n");
2566                 }
2567         }
2568
2569         if (psp->ta_fw) {
2570                 ret = psp_ras_initialize(psp);
2571                 if (ret)
2572                         dev_err(psp->adev->dev,
2573                                         "RAS: Failed to initialize RAS\n");
2574
2575                 ret = psp_hdcp_initialize(psp);
2576                 if (ret)
2577                         dev_err(psp->adev->dev,
2578                                 "HDCP: Failed to initialize HDCP\n");
2579
2580                 ret = psp_dtm_initialize(psp);
2581                 if (ret)
2582                         dev_err(psp->adev->dev,
2583                                 "DTM: Failed to initialize DTM\n");
2584
2585                 ret = psp_rap_initialize(psp);
2586                 if (ret)
2587                         dev_err(psp->adev->dev,
2588                                 "RAP: Failed to initialize RAP\n");
2589
2590                 ret = psp_securedisplay_initialize(psp);
2591                 if (ret)
2592                         dev_err(psp->adev->dev,
2593                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2594         }
2595
2596         return 0;
2597
2598 failed1:
2599         psp_free_shared_bufs(psp);
2600 failed:
2601         /*
2602          * all cleanup jobs (xgmi terminate, ras terminate,
2603          * ring destroy, cmd/fence/fw buffers destory,
2604          * psp->cmd destory) are delayed to psp_hw_fini
2605          */
2606         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2607         return ret;
2608 }
2609
2610 static int psp_hw_init(void *handle)
2611 {
2612         int ret;
2613         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2614
2615         mutex_lock(&adev->firmware.mutex);
2616         /*
2617          * This sequence is just used on hw_init only once, no need on
2618          * resume.
2619          */
2620         ret = amdgpu_ucode_init_bo(adev);
2621         if (ret)
2622                 goto failed;
2623
2624         ret = psp_load_fw(adev);
2625         if (ret) {
2626                 DRM_ERROR("PSP firmware loading failed\n");
2627                 goto failed;
2628         }
2629
2630         mutex_unlock(&adev->firmware.mutex);
2631         return 0;
2632
2633 failed:
2634         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2635         mutex_unlock(&adev->firmware.mutex);
2636         return -EINVAL;
2637 }
2638
2639 static int psp_hw_fini(void *handle)
2640 {
2641         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2642         struct psp_context *psp = &adev->psp;
2643
2644         if (psp->ta_fw) {
2645                 psp_ras_terminate(psp);
2646                 psp_securedisplay_terminate(psp);
2647                 psp_rap_terminate(psp);
2648                 psp_dtm_terminate(psp);
2649                 psp_hdcp_terminate(psp);
2650
2651                 if (adev->gmc.xgmi.num_physical_nodes > 1)
2652                         psp_xgmi_terminate(psp);
2653         }
2654
2655         psp_asd_terminate(psp);
2656         psp_tmr_terminate(psp);
2657
2658         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2659
2660         return 0;
2661 }
2662
2663 static int psp_suspend(void *handle)
2664 {
2665         int ret = 0;
2666         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2667         struct psp_context *psp = &adev->psp;
2668
2669         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2670             psp->xgmi_context.context.initialized) {
2671                 ret = psp_xgmi_terminate(psp);
2672                 if (ret) {
2673                         DRM_ERROR("Failed to terminate xgmi ta\n");
2674                         goto out;
2675                 }
2676         }
2677
2678         if (psp->ta_fw) {
2679                 ret = psp_ras_terminate(psp);
2680                 if (ret) {
2681                         DRM_ERROR("Failed to terminate ras ta\n");
2682                         goto out;
2683                 }
2684                 ret = psp_hdcp_terminate(psp);
2685                 if (ret) {
2686                         DRM_ERROR("Failed to terminate hdcp ta\n");
2687                         goto out;
2688                 }
2689                 ret = psp_dtm_terminate(psp);
2690                 if (ret) {
2691                         DRM_ERROR("Failed to terminate dtm ta\n");
2692                         goto out;
2693                 }
2694                 ret = psp_rap_terminate(psp);
2695                 if (ret) {
2696                         DRM_ERROR("Failed to terminate rap ta\n");
2697                         goto out;
2698                 }
2699                 ret = psp_securedisplay_terminate(psp);
2700                 if (ret) {
2701                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2702                         goto out;
2703                 }
2704         }
2705
2706         ret = psp_asd_terminate(psp);
2707         if (ret) {
2708                 DRM_ERROR("Failed to terminate asd\n");
2709                 goto out;
2710         }
2711
2712         ret = psp_tmr_terminate(psp);
2713         if (ret) {
2714                 DRM_ERROR("Failed to terminate tmr\n");
2715                 goto out;
2716         }
2717
2718         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2719         if (ret) {
2720                 DRM_ERROR("PSP ring stop failed\n");
2721         }
2722
2723 out:
2724         return ret;
2725 }
2726
2727 static int psp_resume(void *handle)
2728 {
2729         int ret;
2730         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2731         struct psp_context *psp = &adev->psp;
2732
2733         DRM_INFO("PSP is resuming...\n");
2734
2735         if (psp->mem_train_ctx.enable_mem_training) {
2736                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2737                 if (ret) {
2738                         DRM_ERROR("Failed to process memory training!\n");
2739                         return ret;
2740                 }
2741         }
2742
2743         mutex_lock(&adev->firmware.mutex);
2744
2745         ret = psp_hw_start(psp);
2746         if (ret)
2747                 goto failed;
2748
2749         ret = psp_load_non_psp_fw(psp);
2750         if (ret)
2751                 goto failed;
2752
2753         ret = psp_asd_initialize(psp);
2754         if (ret) {
2755                 DRM_ERROR("PSP load asd failed!\n");
2756                 goto failed;
2757         }
2758
2759         ret = psp_rl_load(adev);
2760         if (ret) {
2761                 dev_err(adev->dev, "PSP load RL failed!\n");
2762                 goto failed;
2763         }
2764
2765         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2766                 ret = psp_xgmi_initialize(psp, false, true);
2767                 /* Warning the XGMI seesion initialize failure
2768                  * Instead of stop driver initialization
2769                  */
2770                 if (ret)
2771                         dev_err(psp->adev->dev,
2772                                 "XGMI: Failed to initialize XGMI session\n");
2773         }
2774
2775         if (psp->ta_fw) {
2776                 ret = psp_ras_initialize(psp);
2777                 if (ret)
2778                         dev_err(psp->adev->dev,
2779                                         "RAS: Failed to initialize RAS\n");
2780
2781                 ret = psp_hdcp_initialize(psp);
2782                 if (ret)
2783                         dev_err(psp->adev->dev,
2784                                 "HDCP: Failed to initialize HDCP\n");
2785
2786                 ret = psp_dtm_initialize(psp);
2787                 if (ret)
2788                         dev_err(psp->adev->dev,
2789                                 "DTM: Failed to initialize DTM\n");
2790
2791                 ret = psp_rap_initialize(psp);
2792                 if (ret)
2793                         dev_err(psp->adev->dev,
2794                                 "RAP: Failed to initialize RAP\n");
2795
2796                 ret = psp_securedisplay_initialize(psp);
2797                 if (ret)
2798                         dev_err(psp->adev->dev,
2799                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2800         }
2801
2802         mutex_unlock(&adev->firmware.mutex);
2803
2804         return 0;
2805
2806 failed:
2807         DRM_ERROR("PSP resume failed\n");
2808         mutex_unlock(&adev->firmware.mutex);
2809         return ret;
2810 }
2811
2812 int psp_gpu_reset(struct amdgpu_device *adev)
2813 {
2814         int ret;
2815
2816         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2817                 return 0;
2818
2819         mutex_lock(&adev->psp.mutex);
2820         ret = psp_mode1_reset(&adev->psp);
2821         mutex_unlock(&adev->psp.mutex);
2822
2823         return ret;
2824 }
2825
2826 int psp_rlc_autoload_start(struct psp_context *psp)
2827 {
2828         int ret;
2829         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2830
2831         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2832
2833         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2834                                  psp->fence_buf_mc_addr);
2835
2836         release_psp_cmd_buf(psp);
2837
2838         return ret;
2839 }
2840
2841 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2842                         uint64_t cmd_gpu_addr, int cmd_size)
2843 {
2844         struct amdgpu_firmware_info ucode = {0};
2845
2846         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2847                 AMDGPU_UCODE_ID_VCN0_RAM;
2848         ucode.mc_addr = cmd_gpu_addr;
2849         ucode.ucode_size = cmd_size;
2850
2851         return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2852 }
2853
2854 int psp_ring_cmd_submit(struct psp_context *psp,
2855                         uint64_t cmd_buf_mc_addr,
2856                         uint64_t fence_mc_addr,
2857                         int index)
2858 {
2859         unsigned int psp_write_ptr_reg = 0;
2860         struct psp_gfx_rb_frame *write_frame;
2861         struct psp_ring *ring = &psp->km_ring;
2862         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2863         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2864                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2865         struct amdgpu_device *adev = psp->adev;
2866         uint32_t ring_size_dw = ring->ring_size / 4;
2867         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2868
2869         /* KM (GPCOM) prepare write pointer */
2870         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2871
2872         /* Update KM RB frame pointer to new frame */
2873         /* write_frame ptr increments by size of rb_frame in bytes */
2874         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2875         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2876                 write_frame = ring_buffer_start;
2877         else
2878                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2879         /* Check invalid write_frame ptr address */
2880         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2881                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2882                           ring_buffer_start, ring_buffer_end, write_frame);
2883                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2884                 return -EINVAL;
2885         }
2886
2887         /* Initialize KM RB frame */
2888         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2889
2890         /* Update KM RB frame */
2891         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2892         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2893         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2894         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2895         write_frame->fence_value = index;
2896         amdgpu_device_flush_hdp(adev, NULL);
2897
2898         /* Update the write Pointer in DWORDs */
2899         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2900         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2901         return 0;
2902 }
2903
2904 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
2905 {
2906         struct amdgpu_device *adev = psp->adev;
2907         char fw_name[PSP_FW_NAME_LEN];
2908         const struct psp_firmware_header_v1_0 *asd_hdr;
2909         int err = 0;
2910
2911         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2912         err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name);
2913         if (err)
2914                 goto out;
2915
2916         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2917         adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2918         adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2919         adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2920         adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
2921                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2922         return 0;
2923 out:
2924         amdgpu_ucode_release(&adev->psp.asd_fw);
2925         return err;
2926 }
2927
2928 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
2929 {
2930         struct amdgpu_device *adev = psp->adev;
2931         char fw_name[PSP_FW_NAME_LEN];
2932         const struct psp_firmware_header_v1_0 *toc_hdr;
2933         int err = 0;
2934
2935         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2936         err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
2937         if (err)
2938                 goto out;
2939
2940         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2941         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2942         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
2943         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2944         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
2945                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2946         return 0;
2947 out:
2948         amdgpu_ucode_release(&adev->psp.toc_fw);
2949         return err;
2950 }
2951
2952 static int parse_sos_bin_descriptor(struct psp_context *psp,
2953                                    const struct psp_fw_bin_desc *desc,
2954                                    const struct psp_firmware_header_v2_0 *sos_hdr)
2955 {
2956         uint8_t *ucode_start_addr  = NULL;
2957
2958         if (!psp || !desc || !sos_hdr)
2959                 return -EINVAL;
2960
2961         ucode_start_addr  = (uint8_t *)sos_hdr +
2962                             le32_to_cpu(desc->offset_bytes) +
2963                             le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2964
2965         switch (desc->fw_type) {
2966         case PSP_FW_TYPE_PSP_SOS:
2967                 psp->sos.fw_version        = le32_to_cpu(desc->fw_version);
2968                 psp->sos.feature_version   = le32_to_cpu(desc->fw_version);
2969                 psp->sos.size_bytes        = le32_to_cpu(desc->size_bytes);
2970                 psp->sos.start_addr        = ucode_start_addr;
2971                 break;
2972         case PSP_FW_TYPE_PSP_SYS_DRV:
2973                 psp->sys.fw_version        = le32_to_cpu(desc->fw_version);
2974                 psp->sys.feature_version   = le32_to_cpu(desc->fw_version);
2975                 psp->sys.size_bytes        = le32_to_cpu(desc->size_bytes);
2976                 psp->sys.start_addr        = ucode_start_addr;
2977                 break;
2978         case PSP_FW_TYPE_PSP_KDB:
2979                 psp->kdb.fw_version        = le32_to_cpu(desc->fw_version);
2980                 psp->kdb.feature_version   = le32_to_cpu(desc->fw_version);
2981                 psp->kdb.size_bytes        = le32_to_cpu(desc->size_bytes);
2982                 psp->kdb.start_addr        = ucode_start_addr;
2983                 break;
2984         case PSP_FW_TYPE_PSP_TOC:
2985                 psp->toc.fw_version        = le32_to_cpu(desc->fw_version);
2986                 psp->toc.feature_version   = le32_to_cpu(desc->fw_version);
2987                 psp->toc.size_bytes        = le32_to_cpu(desc->size_bytes);
2988                 psp->toc.start_addr        = ucode_start_addr;
2989                 break;
2990         case PSP_FW_TYPE_PSP_SPL:
2991                 psp->spl.fw_version        = le32_to_cpu(desc->fw_version);
2992                 psp->spl.feature_version   = le32_to_cpu(desc->fw_version);
2993                 psp->spl.size_bytes        = le32_to_cpu(desc->size_bytes);
2994                 psp->spl.start_addr        = ucode_start_addr;
2995                 break;
2996         case PSP_FW_TYPE_PSP_RL:
2997                 psp->rl.fw_version         = le32_to_cpu(desc->fw_version);
2998                 psp->rl.feature_version    = le32_to_cpu(desc->fw_version);
2999                 psp->rl.size_bytes         = le32_to_cpu(desc->size_bytes);
3000                 psp->rl.start_addr         = ucode_start_addr;
3001                 break;
3002         case PSP_FW_TYPE_PSP_SOC_DRV:
3003                 psp->soc_drv.fw_version         = le32_to_cpu(desc->fw_version);
3004                 psp->soc_drv.feature_version    = le32_to_cpu(desc->fw_version);
3005                 psp->soc_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3006                 psp->soc_drv.start_addr         = ucode_start_addr;
3007                 break;
3008         case PSP_FW_TYPE_PSP_INTF_DRV:
3009                 psp->intf_drv.fw_version        = le32_to_cpu(desc->fw_version);
3010                 psp->intf_drv.feature_version   = le32_to_cpu(desc->fw_version);
3011                 psp->intf_drv.size_bytes        = le32_to_cpu(desc->size_bytes);
3012                 psp->intf_drv.start_addr        = ucode_start_addr;
3013                 break;
3014         case PSP_FW_TYPE_PSP_DBG_DRV:
3015                 psp->dbg_drv.fw_version         = le32_to_cpu(desc->fw_version);
3016                 psp->dbg_drv.feature_version    = le32_to_cpu(desc->fw_version);
3017                 psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3018                 psp->dbg_drv.start_addr         = ucode_start_addr;
3019                 break;
3020         case PSP_FW_TYPE_PSP_RAS_DRV:
3021                 psp->ras_drv.fw_version         = le32_to_cpu(desc->fw_version);
3022                 psp->ras_drv.feature_version    = le32_to_cpu(desc->fw_version);
3023                 psp->ras_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3024                 psp->ras_drv.start_addr         = ucode_start_addr;
3025                 break;
3026         default:
3027                 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3028                 break;
3029         }
3030
3031         return 0;
3032 }
3033
3034 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3035 {
3036         const struct psp_firmware_header_v1_0 *sos_hdr;
3037         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3038         uint8_t *ucode_array_start_addr;
3039
3040         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3041         ucode_array_start_addr = (uint8_t *)sos_hdr +
3042                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3043
3044         if (adev->gmc.xgmi.connected_to_cpu ||
3045             (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3046                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3047                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3048
3049                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3050                 adev->psp.sys.start_addr = ucode_array_start_addr;
3051
3052                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3053                 adev->psp.sos.start_addr = ucode_array_start_addr +
3054                                 le32_to_cpu(sos_hdr->sos.offset_bytes);
3055         } else {
3056                 /* Load alternate PSP SOS FW */
3057                 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3058
3059                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3060                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3061
3062                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3063                 adev->psp.sys.start_addr = ucode_array_start_addr +
3064                         le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3065
3066                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3067                 adev->psp.sos.start_addr = ucode_array_start_addr +
3068                         le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3069         }
3070
3071         if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3072                 dev_warn(adev->dev, "PSP SOS FW not available");
3073                 return -EINVAL;
3074         }
3075
3076         return 0;
3077 }
3078
3079 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
3080 {
3081         struct amdgpu_device *adev = psp->adev;
3082         char fw_name[PSP_FW_NAME_LEN];
3083         const struct psp_firmware_header_v1_0 *sos_hdr;
3084         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3085         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3086         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3087         const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3088         int err = 0;
3089         uint8_t *ucode_array_start_addr;
3090         int fw_index = 0;
3091
3092         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3093         err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name);
3094         if (err)
3095                 goto out;
3096
3097         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3098         ucode_array_start_addr = (uint8_t *)sos_hdr +
3099                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3100         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3101
3102         switch (sos_hdr->header.header_version_major) {
3103         case 1:
3104                 err = psp_init_sos_base_fw(adev);
3105                 if (err)
3106                         goto out;
3107
3108                 if (sos_hdr->header.header_version_minor == 1) {
3109                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3110                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3111                         adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3112                                         le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3113                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3114                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3115                                         le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3116                 }
3117                 if (sos_hdr->header.header_version_minor == 2) {
3118                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3119                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3120                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3121                                                     le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3122                 }
3123                 if (sos_hdr->header.header_version_minor == 3) {
3124                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3125                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3126                         adev->psp.toc.start_addr = ucode_array_start_addr +
3127                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3128                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3129                         adev->psp.kdb.start_addr = ucode_array_start_addr +
3130                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3131                         adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3132                         adev->psp.spl.start_addr = ucode_array_start_addr +
3133                                 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3134                         adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3135                         adev->psp.rl.start_addr = ucode_array_start_addr +
3136                                 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3137                 }
3138                 break;
3139         case 2:
3140                 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3141
3142                 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3143                         dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3144                         err = -EINVAL;
3145                         goto out;
3146                 }
3147
3148                 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3149                         err = parse_sos_bin_descriptor(psp,
3150                                                        &sos_hdr_v2_0->psp_fw_bin[fw_index],
3151                                                        sos_hdr_v2_0);
3152                         if (err)
3153                                 goto out;
3154                 }
3155                 break;
3156         default:
3157                 dev_err(adev->dev,
3158                         "unsupported psp sos firmware\n");
3159                 err = -EINVAL;
3160                 goto out;
3161         }
3162
3163         return 0;
3164 out:
3165         amdgpu_ucode_release(&adev->psp.sos_fw);
3166
3167         return err;
3168 }
3169
3170 static int parse_ta_bin_descriptor(struct psp_context *psp,
3171                                    const struct psp_fw_bin_desc *desc,
3172                                    const struct ta_firmware_header_v2_0 *ta_hdr)
3173 {
3174         uint8_t *ucode_start_addr  = NULL;
3175
3176         if (!psp || !desc || !ta_hdr)
3177                 return -EINVAL;
3178
3179         ucode_start_addr  = (uint8_t *)ta_hdr +
3180                             le32_to_cpu(desc->offset_bytes) +
3181                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3182
3183         switch (desc->fw_type) {
3184         case TA_FW_TYPE_PSP_ASD:
3185                 psp->asd_context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3186                 psp->asd_context.bin_desc.feature_version   = le32_to_cpu(desc->fw_version);
3187                 psp->asd_context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3188                 psp->asd_context.bin_desc.start_addr        = ucode_start_addr;
3189                 break;
3190         case TA_FW_TYPE_PSP_XGMI:
3191                 psp->xgmi_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3192                 psp->xgmi_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3193                 psp->xgmi_context.context.bin_desc.start_addr       = ucode_start_addr;
3194                 break;
3195         case TA_FW_TYPE_PSP_RAS:
3196                 psp->ras_context.context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3197                 psp->ras_context.context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3198                 psp->ras_context.context.bin_desc.start_addr        = ucode_start_addr;
3199                 break;
3200         case TA_FW_TYPE_PSP_HDCP:
3201                 psp->hdcp_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3202                 psp->hdcp_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3203                 psp->hdcp_context.context.bin_desc.start_addr       = ucode_start_addr;
3204                 break;
3205         case TA_FW_TYPE_PSP_DTM:
3206                 psp->dtm_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3207                 psp->dtm_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3208                 psp->dtm_context.context.bin_desc.start_addr       = ucode_start_addr;
3209                 break;
3210         case TA_FW_TYPE_PSP_RAP:
3211                 psp->rap_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3212                 psp->rap_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3213                 psp->rap_context.context.bin_desc.start_addr       = ucode_start_addr;
3214                 break;
3215         case TA_FW_TYPE_PSP_SECUREDISPLAY:
3216                 psp->securedisplay_context.context.bin_desc.fw_version =
3217                         le32_to_cpu(desc->fw_version);
3218                 psp->securedisplay_context.context.bin_desc.size_bytes =
3219                         le32_to_cpu(desc->size_bytes);
3220                 psp->securedisplay_context.context.bin_desc.start_addr =
3221                         ucode_start_addr;
3222                 break;
3223         default:
3224                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3225                 break;
3226         }
3227
3228         return 0;
3229 }
3230
3231 static int parse_ta_v1_microcode(struct psp_context *psp)
3232 {
3233         const struct ta_firmware_header_v1_0 *ta_hdr;
3234         struct amdgpu_device *adev = psp->adev;
3235
3236         ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data;
3237
3238         if (le16_to_cpu(ta_hdr->header.header_version_major) != 1)
3239                 return -EINVAL;
3240
3241         adev->psp.xgmi_context.context.bin_desc.fw_version =
3242                 le32_to_cpu(ta_hdr->xgmi.fw_version);
3243         adev->psp.xgmi_context.context.bin_desc.size_bytes =
3244                 le32_to_cpu(ta_hdr->xgmi.size_bytes);
3245         adev->psp.xgmi_context.context.bin_desc.start_addr =
3246                 (uint8_t *)ta_hdr +
3247                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3248
3249         adev->psp.ras_context.context.bin_desc.fw_version =
3250                 le32_to_cpu(ta_hdr->ras.fw_version);
3251         adev->psp.ras_context.context.bin_desc.size_bytes =
3252                 le32_to_cpu(ta_hdr->ras.size_bytes);
3253         adev->psp.ras_context.context.bin_desc.start_addr =
3254                 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
3255                 le32_to_cpu(ta_hdr->ras.offset_bytes);
3256
3257         adev->psp.hdcp_context.context.bin_desc.fw_version =
3258                 le32_to_cpu(ta_hdr->hdcp.fw_version);
3259         adev->psp.hdcp_context.context.bin_desc.size_bytes =
3260                 le32_to_cpu(ta_hdr->hdcp.size_bytes);
3261         adev->psp.hdcp_context.context.bin_desc.start_addr =
3262                 (uint8_t *)ta_hdr +
3263                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3264
3265         adev->psp.dtm_context.context.bin_desc.fw_version =
3266                 le32_to_cpu(ta_hdr->dtm.fw_version);
3267         adev->psp.dtm_context.context.bin_desc.size_bytes =
3268                 le32_to_cpu(ta_hdr->dtm.size_bytes);
3269         adev->psp.dtm_context.context.bin_desc.start_addr =
3270                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3271                 le32_to_cpu(ta_hdr->dtm.offset_bytes);
3272
3273         adev->psp.securedisplay_context.context.bin_desc.fw_version =
3274                 le32_to_cpu(ta_hdr->securedisplay.fw_version);
3275         adev->psp.securedisplay_context.context.bin_desc.size_bytes =
3276                 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
3277         adev->psp.securedisplay_context.context.bin_desc.start_addr =
3278                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3279                 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
3280
3281         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
3282
3283         return 0;
3284 }
3285
3286 static int parse_ta_v2_microcode(struct psp_context *psp)
3287 {
3288         const struct ta_firmware_header_v2_0 *ta_hdr;
3289         struct amdgpu_device *adev = psp->adev;
3290         int err = 0;
3291         int ta_index = 0;
3292
3293         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3294
3295         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2)
3296                 return -EINVAL;
3297
3298         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3299                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3300                 return -EINVAL;
3301         }
3302
3303         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3304                 err = parse_ta_bin_descriptor(psp,
3305                                               &ta_hdr->ta_fw_bin[ta_index],
3306                                               ta_hdr);
3307                 if (err)
3308                         return err;
3309         }
3310
3311         return 0;
3312 }
3313
3314 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
3315 {
3316         const struct common_firmware_header *hdr;
3317         struct amdgpu_device *adev = psp->adev;
3318         char fw_name[PSP_FW_NAME_LEN];
3319         int err;
3320
3321         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3322         err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name);
3323         if (err)
3324                 return err;
3325
3326         hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data;
3327         switch (le16_to_cpu(hdr->header_version_major)) {
3328         case 1:
3329                 err = parse_ta_v1_microcode(psp);
3330                 break;
3331         case 2:
3332                 err = parse_ta_v2_microcode(psp);
3333                 break;
3334         default:
3335                 dev_err(adev->dev, "unsupported TA header version\n");
3336                 err = -EINVAL;
3337         }
3338
3339         if (err)
3340                 amdgpu_ucode_release(&adev->psp.ta_fw);
3341
3342         return err;
3343 }
3344
3345 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
3346 {
3347         struct amdgpu_device *adev = psp->adev;
3348         char fw_name[PSP_FW_NAME_LEN];
3349         const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3350         struct amdgpu_firmware_info *info = NULL;
3351         int err = 0;
3352
3353         if (!amdgpu_sriov_vf(adev)) {
3354                 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3355                 return -EINVAL;
3356         }
3357
3358         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3359         err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name);
3360         if (err) {
3361                 if (err == -ENODEV) {
3362                         dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3363                         err = 0;
3364                         goto out;
3365                 }
3366                 dev_err(adev->dev, "fail to initialize cap microcode\n");
3367         }
3368
3369         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3370         info->ucode_id = AMDGPU_UCODE_ID_CAP;
3371         info->fw = adev->psp.cap_fw;
3372         cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3373                 adev->psp.cap_fw->data;
3374         adev->firmware.fw_size += ALIGN(
3375                         le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3376         adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3377         adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3378         adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3379
3380         return 0;
3381
3382 out:
3383         amdgpu_ucode_release(&adev->psp.cap_fw);
3384         return err;
3385 }
3386
3387 static int psp_set_clockgating_state(void *handle,
3388                                      enum amd_clockgating_state state)
3389 {
3390         return 0;
3391 }
3392
3393 static int psp_set_powergating_state(void *handle,
3394                                      enum amd_powergating_state state)
3395 {
3396         return 0;
3397 }
3398
3399 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3400                                          struct device_attribute *attr,
3401                                          char *buf)
3402 {
3403         struct drm_device *ddev = dev_get_drvdata(dev);
3404         struct amdgpu_device *adev = drm_to_adev(ddev);
3405         uint32_t fw_ver;
3406         int ret;
3407
3408         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3409                 DRM_INFO("PSP block is not ready yet.");
3410                 return -EBUSY;
3411         }
3412
3413         mutex_lock(&adev->psp.mutex);
3414         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3415         mutex_unlock(&adev->psp.mutex);
3416
3417         if (ret) {
3418                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3419                 return ret;
3420         }
3421
3422         return sysfs_emit(buf, "%x\n", fw_ver);
3423 }
3424
3425 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3426                                                        struct device_attribute *attr,
3427                                                        const char *buf,
3428                                                        size_t count)
3429 {
3430         struct drm_device *ddev = dev_get_drvdata(dev);
3431         struct amdgpu_device *adev = drm_to_adev(ddev);
3432         int ret, idx;
3433         char fw_name[100];
3434         const struct firmware *usbc_pd_fw;
3435         struct amdgpu_bo *fw_buf_bo = NULL;
3436         uint64_t fw_pri_mc_addr;
3437         void *fw_pri_cpu_addr;
3438
3439         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3440                 DRM_INFO("PSP block is not ready yet.");
3441                 return -EBUSY;
3442         }
3443
3444         if (!drm_dev_enter(ddev, &idx))
3445                 return -ENODEV;
3446
3447         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3448         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3449         if (ret)
3450                 goto fail;
3451
3452         /* LFB address which is aligned to 1MB boundary per PSP request */
3453         ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3454                                       AMDGPU_GEM_DOMAIN_VRAM |
3455                                       AMDGPU_GEM_DOMAIN_GTT,
3456                                       &fw_buf_bo, &fw_pri_mc_addr,
3457                                       &fw_pri_cpu_addr);
3458         if (ret)
3459                 goto rel_buf;
3460
3461         memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3462
3463         mutex_lock(&adev->psp.mutex);
3464         ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3465         mutex_unlock(&adev->psp.mutex);
3466
3467         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3468
3469 rel_buf:
3470         release_firmware(usbc_pd_fw);
3471 fail:
3472         if (ret) {
3473                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3474                 count = ret;
3475         }
3476
3477         drm_dev_exit(idx);
3478         return count;
3479 }
3480
3481 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3482 {
3483         int idx;
3484
3485         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3486                 return;
3487
3488         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3489         memcpy(psp->fw_pri_buf, start_addr, bin_size);
3490
3491         drm_dev_exit(idx);
3492 }
3493
3494 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3495                    psp_usbc_pd_fw_sysfs_read,
3496                    psp_usbc_pd_fw_sysfs_write);
3497
3498 int is_psp_fw_valid(struct psp_bin_desc bin)
3499 {
3500         return bin.size_bytes;
3501 }
3502
3503 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3504                                         struct bin_attribute *bin_attr,
3505                                         char *buffer, loff_t pos, size_t count)
3506 {
3507         struct device *dev = kobj_to_dev(kobj);
3508         struct drm_device *ddev = dev_get_drvdata(dev);
3509         struct amdgpu_device *adev = drm_to_adev(ddev);
3510
3511         adev->psp.vbflash_done = false;
3512
3513         /* Safeguard against memory drain */
3514         if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3515                 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3516                 kvfree(adev->psp.vbflash_tmp_buf);
3517                 adev->psp.vbflash_tmp_buf = NULL;
3518                 adev->psp.vbflash_image_size = 0;
3519                 return -ENOMEM;
3520         }
3521
3522         /* TODO Just allocate max for now and optimize to realloc later if needed */
3523         if (!adev->psp.vbflash_tmp_buf) {
3524                 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3525                 if (!adev->psp.vbflash_tmp_buf)
3526                         return -ENOMEM;
3527         }
3528
3529         mutex_lock(&adev->psp.mutex);
3530         memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3531         adev->psp.vbflash_image_size += count;
3532         mutex_unlock(&adev->psp.mutex);
3533
3534         dev_info(adev->dev, "VBIOS flash write PSP done");
3535
3536         return count;
3537 }
3538
3539 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3540                                        struct bin_attribute *bin_attr, char *buffer,
3541                                        loff_t pos, size_t count)
3542 {
3543         struct device *dev = kobj_to_dev(kobj);
3544         struct drm_device *ddev = dev_get_drvdata(dev);
3545         struct amdgpu_device *adev = drm_to_adev(ddev);
3546         struct amdgpu_bo *fw_buf_bo = NULL;
3547         uint64_t fw_pri_mc_addr;
3548         void *fw_pri_cpu_addr;
3549         int ret;
3550
3551         dev_info(adev->dev, "VBIOS flash to PSP started");
3552
3553         ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3554                                         AMDGPU_GPU_PAGE_SIZE,
3555                                         AMDGPU_GEM_DOMAIN_VRAM,
3556                                         &fw_buf_bo,
3557                                         &fw_pri_mc_addr,
3558                                         &fw_pri_cpu_addr);
3559         if (ret)
3560                 goto rel_buf;
3561
3562         memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3563
3564         mutex_lock(&adev->psp.mutex);
3565         ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3566         mutex_unlock(&adev->psp.mutex);
3567
3568         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3569
3570 rel_buf:
3571         kvfree(adev->psp.vbflash_tmp_buf);
3572         adev->psp.vbflash_tmp_buf = NULL;
3573         adev->psp.vbflash_image_size = 0;
3574
3575         if (ret) {
3576                 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret);
3577                 return ret;
3578         }
3579
3580         dev_info(adev->dev, "VBIOS flash to PSP done");
3581         return 0;
3582 }
3583
3584 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3585                                          struct device_attribute *attr,
3586                                          char *buf)
3587 {
3588         struct drm_device *ddev = dev_get_drvdata(dev);
3589         struct amdgpu_device *adev = drm_to_adev(ddev);
3590         uint32_t vbflash_status;
3591
3592         vbflash_status = psp_vbflash_status(&adev->psp);
3593         if (!adev->psp.vbflash_done)
3594                 vbflash_status = 0;
3595         else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3596                 vbflash_status = 1;
3597
3598         return sysfs_emit(buf, "0x%x\n", vbflash_status);
3599 }
3600
3601 static const struct bin_attribute psp_vbflash_bin_attr = {
3602         .attr = {.name = "psp_vbflash", .mode = 0664},
3603         .size = 0,
3604         .write = amdgpu_psp_vbflash_write,
3605         .read = amdgpu_psp_vbflash_read,
3606 };
3607
3608 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL);
3609
3610 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
3611 {
3612         int ret = 0;
3613         struct psp_context *psp = &adev->psp;
3614
3615         if (amdgpu_sriov_vf(adev))
3616                 return -EINVAL;
3617
3618         switch (adev->ip_versions[MP0_HWIP][0]) {
3619         case IP_VERSION(13, 0, 0):
3620         case IP_VERSION(13, 0, 7):
3621         case IP_VERSION(13, 0, 10):
3622                 if (!psp->adev) {
3623                         psp->adev = adev;
3624                         psp_v13_0_set_psp_funcs(psp);
3625                 }
3626                 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3627                 if (ret)
3628                         dev_err(adev->dev, "Failed to create device file psp_vbflash");
3629                 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status);
3630                 if (ret)
3631                         dev_err(adev->dev, "Failed to create device file psp_vbflash_status");
3632                 return ret;
3633         default:
3634                 return 0;
3635         }
3636 }
3637
3638 const struct amd_ip_funcs psp_ip_funcs = {
3639         .name = "psp",
3640         .early_init = psp_early_init,
3641         .late_init = NULL,
3642         .sw_init = psp_sw_init,
3643         .sw_fini = psp_sw_fini,
3644         .hw_init = psp_hw_init,
3645         .hw_fini = psp_hw_fini,
3646         .suspend = psp_suspend,
3647         .resume = psp_resume,
3648         .is_idle = NULL,
3649         .check_soft_reset = NULL,
3650         .wait_for_idle = NULL,
3651         .soft_reset = NULL,
3652         .set_clockgating_state = psp_set_clockgating_state,
3653         .set_powergating_state = psp_set_powergating_state,
3654 };
3655
3656 static int psp_sysfs_init(struct amdgpu_device *adev)
3657 {
3658         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3659
3660         if (ret)
3661                 DRM_ERROR("Failed to create USBC PD FW control file!");
3662
3663         return ret;
3664 }
3665
3666 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev)
3667 {
3668         sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3669         device_remove_file(adev->dev, &dev_attr_psp_vbflash_status);
3670 }
3671
3672 static void psp_sysfs_fini(struct amdgpu_device *adev)
3673 {
3674         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3675 }
3676
3677 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3678 {
3679         .type = AMD_IP_BLOCK_TYPE_PSP,
3680         .major = 3,
3681         .minor = 1,
3682         .rev = 0,
3683         .funcs = &psp_ip_funcs,
3684 };
3685
3686 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3687 {
3688         .type = AMD_IP_BLOCK_TYPE_PSP,
3689         .major = 10,
3690         .minor = 0,
3691         .rev = 0,
3692         .funcs = &psp_ip_funcs,
3693 };
3694
3695 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3696 {
3697         .type = AMD_IP_BLOCK_TYPE_PSP,
3698         .major = 11,
3699         .minor = 0,
3700         .rev = 0,
3701         .funcs = &psp_ip_funcs,
3702 };
3703
3704 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3705         .type = AMD_IP_BLOCK_TYPE_PSP,
3706         .major = 11,
3707         .minor = 0,
3708         .rev = 8,
3709         .funcs = &psp_ip_funcs,
3710 };
3711
3712 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3713 {
3714         .type = AMD_IP_BLOCK_TYPE_PSP,
3715         .major = 12,
3716         .minor = 0,
3717         .rev = 0,
3718         .funcs = &psp_ip_funcs,
3719 };
3720
3721 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3722         .type = AMD_IP_BLOCK_TYPE_PSP,
3723         .major = 13,
3724         .minor = 0,
3725         .rev = 0,
3726         .funcs = &psp_ip_funcs,
3727 };
3728
3729 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3730         .type = AMD_IP_BLOCK_TYPE_PSP,
3731         .major = 13,
3732         .minor = 0,
3733         .rev = 4,
3734         .funcs = &psp_ip_funcs,
3735 };