drivers/platform/x86/intel/vsec.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Vendor Specific Extended Capabilities auxiliary bus driver
   4  *
   5  * Copyright (c) 2021, Intel Corporation.
   6  * All Rights Reserved.
   7  *
   8  * Author: David E. Box <[email protected]>
   9  *
  10  * This driver discovers and creates auxiliary devices for Intel defined PCIe
  11  * "Vendor Specific" and "Designated Vendor Specific" Extended Capabilities,
  12  * VSEC and DVSEC respectively. The driver supports features on specific PCIe
  13  * endpoints that exist primarily to expose them.
  14  */
  15
  16 #include <linux/auxiliary_bus.h>
  17 #include <linux/bits.h>
  18 #include <linux/cleanup.h>
  19 #include <linux/delay.h>
  20 #include <linux/kernel.h>
  21 #include <linux/idr.h>
  22 #include <linux/module.h>
  23 #include <linux/pci.h>
  24 #include <linux/types.h>
  25
  26 #include "vsec.h"
  27
  28 #define PMT_XA_START                    0
  29 #define PMT_XA_MAX                      INT_MAX
  30 #define PMT_XA_LIMIT                    XA_LIMIT(PMT_XA_START, PMT_XA_MAX)
  31
  32 static DEFINE_IDA(intel_vsec_ida);
  33 static DEFINE_IDA(intel_vsec_sdsi_ida);
  34 static DEFINE_XARRAY_ALLOC(auxdev_array);
  35
  36 static const char *intel_vsec_name(enum intel_vsec_id id)
  37 {
  38         switch (id) {
  39         case VSEC_ID_TELEMETRY:
  40                 return "telemetry";
  41
  42         case VSEC_ID_WATCHER:
  43                 return "watcher";
  44
  45         case VSEC_ID_CRASHLOG:
  46                 return "crashlog";
  47
  48         case VSEC_ID_SDSI:
  49                 return "sdsi";
  50
  51         case VSEC_ID_TPMI:
  52                 return "tpmi";
  53
  54         default:
  55                 return NULL;
  56         }
  57 }
  58
  59 static bool intel_vsec_supported(u16 id, unsigned long caps)
  60 {
  61         switch (id) {
  62         case VSEC_ID_TELEMETRY:
  63                 return !!(caps & VSEC_CAP_TELEMETRY);
  64         case VSEC_ID_WATCHER:
  65                 return !!(caps & VSEC_CAP_WATCHER);
  66         case VSEC_ID_CRASHLOG:
  67                 return !!(caps & VSEC_CAP_CRASHLOG);
  68         case VSEC_ID_SDSI:
  69                 return !!(caps & VSEC_CAP_SDSI);
  70         case VSEC_ID_TPMI:
  71                 return !!(caps & VSEC_CAP_TPMI);
  72         default:
  73                 return false;
  74         }
  75 }
  76
  77 static void intel_vsec_remove_aux(void *data)
  78 {
  79         auxiliary_device_delete(data);
  80         auxiliary_device_uninit(data);
  81 }
  82
  83 static DEFINE_MUTEX(vsec_ida_lock);
  84
  85 static void intel_vsec_dev_release(struct device *dev)
  86 {
  87         struct intel_vsec_device *intel_vsec_dev = dev_to_ivdev(dev);
  88
  89         xa_erase(&auxdev_array, intel_vsec_dev->id);
  90
  91         mutex_lock(&vsec_ida_lock);
  92         ida_free(intel_vsec_dev->ida, intel_vsec_dev->auxdev.id);
  93         mutex_unlock(&vsec_ida_lock);
  94
  95         kfree(intel_vsec_dev->resource);
  96         kfree(intel_vsec_dev);
  97 }
  98
  99 int intel_vsec_add_aux(struct pci_dev *pdev, struct device *parent,
 100                        struct intel_vsec_device *intel_vsec_dev,
 101                        const char *name)
 102 {
 103         struct auxiliary_device *auxdev = &intel_vsec_dev->auxdev;
 104         int ret, id;
 105
 106         if (!parent)
 107                 return -EINVAL;
 108
 109         ret = xa_alloc(&auxdev_array, &intel_vsec_dev->id, intel_vsec_dev,
 110                        PMT_XA_LIMIT, GFP_KERNEL);
 111         if (ret < 0) {
 112                 kfree(intel_vsec_dev->resource);
 113                 kfree(intel_vsec_dev);
 114                 return ret;
 115         }
 116
 117         mutex_lock(&vsec_ida_lock);
 118         id = ida_alloc(intel_vsec_dev->ida, GFP_KERNEL);
 119         mutex_unlock(&vsec_ida_lock);
 120         if (id < 0) {
 121                 xa_erase(&auxdev_array, intel_vsec_dev->id);
 122                 kfree(intel_vsec_dev->resource);
 123                 kfree(intel_vsec_dev);
 124                 return id;
 125         }
 126
 127         auxdev->id = id;
 128         auxdev->name = name;
 129         auxdev->dev.parent = parent;
 130         auxdev->dev.release = intel_vsec_dev_release;
 131
 132         ret = auxiliary_device_init(auxdev);
 133         if (ret < 0) {
 134                 intel_vsec_dev_release(&auxdev->dev);
 135                 return ret;
 136         }
 137
 138         ret = auxiliary_device_add(auxdev);
 139         if (ret < 0) {
 140                 auxiliary_device_uninit(auxdev);
 141                 return ret;
 142         }
 143
 144         return devm_add_action_or_reset(parent, intel_vsec_remove_aux,
 145                                        auxdev);
 146 }
 147 EXPORT_SYMBOL_NS_GPL(intel_vsec_add_aux, INTEL_VSEC);
 148
 149 static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *header,
 150                               struct intel_vsec_platform_info *info)
 151 {
 152         struct intel_vsec_device __free(kfree) *intel_vsec_dev = NULL;
 153         struct resource __free(kfree) *res = NULL;
 154         struct resource *tmp;
 155         struct device *parent;
 156         unsigned long quirks = info->quirks;
 157         u64 base_addr;
 158         int i;
 159
 160         if (info->parent)
 161                 parent = info->parent;
 162         else
 163                 parent = &pdev->dev;
 164
 165         if (!intel_vsec_supported(header->id, info->caps))
 166                 return -EINVAL;
 167
 168         if (!header->num_entries) {
 169                 dev_dbg(&pdev->dev, "Invalid 0 entry count for header id %d\n", header->id);
 170                 return -EINVAL;
 171         }
 172
 173         if (!header->entry_size) {
 174                 dev_dbg(&pdev->dev, "Invalid 0 entry size for header id %d\n", header->id);
 175                 return -EINVAL;
 176         }
 177
 178         intel_vsec_dev = kzalloc(sizeof(*intel_vsec_dev), GFP_KERNEL);
 179         if (!intel_vsec_dev)
 180                 return -ENOMEM;
 181
 182         res = kcalloc(header->num_entries, sizeof(*res), GFP_KERNEL);
 183         if (!res)
 184                 return -ENOMEM;
 185
 186         if (quirks & VSEC_QUIRK_TABLE_SHIFT)
 187                 header->offset >>= TABLE_OFFSET_SHIFT;
 188
 189         if (info->base_addr)
 190                 base_addr = info->base_addr;
 191         else
 192                 base_addr = pdev->resource[header->tbir].start;
 193
 194         /*
 195          * The DVSEC/VSEC contains the starting offset and count for a block of
 196          * discovery tables. Create a resource array of these tables to the
 197          * auxiliary device driver.
 198          */
 199         for (i = 0, tmp = res; i < header->num_entries; i++, tmp++) {
 200                 tmp->start = base_addr + header->offset + i * (header->entry_size * sizeof(u32));
 201                 tmp->end = tmp->start + (header->entry_size * sizeof(u32)) - 1;
 202                 tmp->flags = IORESOURCE_MEM;
 203
 204                 /* Check resource is not in use */
 205                 if (!request_mem_region(tmp->start, resource_size(tmp), ""))
 206                         return -EBUSY;
 207
 208                 release_mem_region(tmp->start, resource_size(tmp));
 209         }
 210
 211         intel_vsec_dev->pcidev = pdev;
 212         intel_vsec_dev->resource = no_free_ptr(res);
 213         intel_vsec_dev->num_resources = header->num_entries;
 214         intel_vsec_dev->quirks = info->quirks;
 215         intel_vsec_dev->base_addr = info->base_addr;
 216
 217         if (header->id == VSEC_ID_SDSI)
 218                 intel_vsec_dev->ida = &intel_vsec_sdsi_ida;
 219         else
 220                 intel_vsec_dev->ida = &intel_vsec_ida;
 221
 222         /*
 223          * Pass the ownership of intel_vsec_dev and resource within it to
 224          * intel_vsec_add_aux()
 225          */
 226         return intel_vsec_add_aux(pdev, parent, no_free_ptr(intel_vsec_dev),
 227                                   intel_vsec_name(header->id));
 228 }
 229
 230 static bool intel_vsec_walk_header(struct pci_dev *pdev,
 231                                    struct intel_vsec_platform_info *info)
 232 {
 233         struct intel_vsec_header **header = info->headers;
 234         bool have_devices = false;
 235         int ret;
 236
 237         for ( ; *header; header++) {
 238                 ret = intel_vsec_add_dev(pdev, *header, info);
 239                 if (!ret)
 240                         have_devices = true;
 241         }
 242
 243         return have_devices;
 244 }
 245
 246 static bool intel_vsec_walk_dvsec(struct pci_dev *pdev,
 247                                   struct intel_vsec_platform_info *info)
 248 {
 249         bool have_devices = false;
 250         int pos = 0;
 251
 252         do {
 253                 struct intel_vsec_header header;
 254                 u32 table, hdr;
 255                 u16 vid;
 256                 int ret;
 257
 258                 pos = pci_find_next_ext_capability(pdev, pos, PCI_EXT_CAP_ID_DVSEC);
 259                 if (!pos)
 260                         break;
 261
 262                 pci_read_config_dword(pdev, pos + PCI_DVSEC_HEADER1, &hdr);
 263                 vid = PCI_DVSEC_HEADER1_VID(hdr);
 264                 if (vid != PCI_VENDOR_ID_INTEL)
 265                         continue;
 266
 267                 /* Support only revision 1 */
 268                 header.rev = PCI_DVSEC_HEADER1_REV(hdr);
 269                 if (header.rev != 1) {
 270                         dev_info(&pdev->dev, "Unsupported DVSEC revision %d\n", header.rev);
 271                         continue;
 272                 }
 273
 274                 header.length = PCI_DVSEC_HEADER1_LEN(hdr);
 275
 276                 pci_read_config_byte(pdev, pos + INTEL_DVSEC_ENTRIES, &header.num_entries);
 277                 pci_read_config_byte(pdev, pos + INTEL_DVSEC_SIZE, &header.entry_size);
 278                 pci_read_config_dword(pdev, pos + INTEL_DVSEC_TABLE, &table);
 279
 280                 header.tbir = INTEL_DVSEC_TABLE_BAR(table);
 281                 header.offset = INTEL_DVSEC_TABLE_OFFSET(table);
 282
 283                 pci_read_config_dword(pdev, pos + PCI_DVSEC_HEADER2, &hdr);
 284                 header.id = PCI_DVSEC_HEADER2_ID(hdr);
 285
 286                 ret = intel_vsec_add_dev(pdev, &header, info);
 287                 if (ret)
 288                         continue;
 289
 290                 have_devices = true;
 291         } while (true);
 292
 293         return have_devices;
 294 }
 295
 296 static bool intel_vsec_walk_vsec(struct pci_dev *pdev,
 297                                  struct intel_vsec_platform_info *info)
 298 {
 299         bool have_devices = false;
 300         int pos = 0;
 301
 302         do {
 303                 struct intel_vsec_header header;
 304                 u32 table, hdr;
 305                 int ret;
 306
 307                 pos = pci_find_next_ext_capability(pdev, pos, PCI_EXT_CAP_ID_VNDR);
 308                 if (!pos)
 309                         break;
 310
 311                 pci_read_config_dword(pdev, pos + PCI_VNDR_HEADER, &hdr);
 312
 313                 /* Support only revision 1 */
 314                 header.rev = PCI_VNDR_HEADER_REV(hdr);
 315                 if (header.rev != 1) {
 316                         dev_info(&pdev->dev, "Unsupported VSEC revision %d\n", header.rev);
 317                         continue;
 318                 }
 319
 320                 header.id = PCI_VNDR_HEADER_ID(hdr);
 321                 header.length = PCI_VNDR_HEADER_LEN(hdr);
 322
 323                 /* entry, size, and table offset are the same as DVSEC */
 324                 pci_read_config_byte(pdev, pos + INTEL_DVSEC_ENTRIES, &header.num_entries);
 325                 pci_read_config_byte(pdev, pos + INTEL_DVSEC_SIZE, &header.entry_size);
 326                 pci_read_config_dword(pdev, pos + INTEL_DVSEC_TABLE, &table);
 327
 328                 header.tbir = INTEL_DVSEC_TABLE_BAR(table);
 329                 header.offset = INTEL_DVSEC_TABLE_OFFSET(table);
 330
 331                 ret = intel_vsec_add_dev(pdev, &header, info);
 332                 if (ret)
 333                         continue;
 334
 335                 have_devices = true;
 336         } while (true);
 337
 338         return have_devices;
 339 }
 340
 341 void intel_vsec_register(struct pci_dev *pdev,
 342                          struct intel_vsec_platform_info *info)
 343 {
 344         if (!pdev || !info)
 345                 return;
 346
 347         intel_vsec_walk_header(pdev, info);
 348 }
 349 EXPORT_SYMBOL_NS_GPL(intel_vsec_register, INTEL_VSEC);
 350
 351 static int intel_vsec_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 352 {
 353         struct intel_vsec_platform_info *info;
 354         bool have_devices = false;
 355         int ret;
 356
 357         ret = pcim_enable_device(pdev);
 358         if (ret)
 359                 return ret;
 360
 361         pci_save_state(pdev);
 362         info = (struct intel_vsec_platform_info *)id->driver_data;
 363         if (!info)
 364                 return -EINVAL;
 365
 366         if (intel_vsec_walk_dvsec(pdev, info))
 367                 have_devices = true;
 368
 369         if (intel_vsec_walk_vsec(pdev, info))
 370                 have_devices = true;
 371
 372         if (info && (info->quirks & VSEC_QUIRK_NO_DVSEC) &&
 373             intel_vsec_walk_header(pdev, info))
 374                 have_devices = true;
 375
 376         if (!have_devices)
 377                 return -ENODEV;
 378
 379         return 0;
 380 }
 381
 382 /* DG1 info */
 383 static struct intel_vsec_header dg1_header = {
 384         .length = 0x10,
 385         .id = 2,
 386         .num_entries = 1,
 387         .entry_size = 3,
 388         .tbir = 0,
 389         .offset = 0x466000,
 390 };
 391
 392 static struct intel_vsec_header *dg1_headers[] = {
 393         &dg1_header,
 394         NULL
 395 };
 396
 397 static const struct intel_vsec_platform_info dg1_info = {
 398         .caps = VSEC_CAP_TELEMETRY,
 399         .headers = dg1_headers,
 400         .quirks = VSEC_QUIRK_NO_DVSEC | VSEC_QUIRK_EARLY_HW,
 401 };
 402
 403 /* MTL info */
 404 static const struct intel_vsec_platform_info mtl_info = {
 405         .caps = VSEC_CAP_TELEMETRY,
 406 };
 407
 408 /* OOBMSM info */
 409 static const struct intel_vsec_platform_info oobmsm_info = {
 410         .caps = VSEC_CAP_TELEMETRY | VSEC_CAP_SDSI | VSEC_CAP_TPMI,
 411 };
 412
 413 /* TGL info */
 414 static const struct intel_vsec_platform_info tgl_info = {
 415         .caps = VSEC_CAP_TELEMETRY,
 416         .quirks = VSEC_QUIRK_TABLE_SHIFT | VSEC_QUIRK_EARLY_HW,
 417 };
 418
 419 /* LNL info */
 420 static const struct intel_vsec_platform_info lnl_info = {
 421         .caps = VSEC_CAP_TELEMETRY | VSEC_CAP_WATCHER,
 422 };
 423
 424 #define PCI_DEVICE_ID_INTEL_VSEC_ADL            0x467d
 425 #define PCI_DEVICE_ID_INTEL_VSEC_DG1            0x490e
 426 #define PCI_DEVICE_ID_INTEL_VSEC_MTL_M          0x7d0d
 427 #define PCI_DEVICE_ID_INTEL_VSEC_MTL_S          0xad0d
 428 #define PCI_DEVICE_ID_INTEL_VSEC_OOBMSM         0x09a7
 429 #define PCI_DEVICE_ID_INTEL_VSEC_RPL            0xa77d
 430 #define PCI_DEVICE_ID_INTEL_VSEC_TGL            0x9a0d
 431 #define PCI_DEVICE_ID_INTEL_VSEC_LNL_M          0x647d
 432 static const struct pci_device_id intel_vsec_pci_ids[] = {
 433         { PCI_DEVICE_DATA(INTEL, VSEC_ADL, &tgl_info) },
 434         { PCI_DEVICE_DATA(INTEL, VSEC_DG1, &dg1_info) },
 435         { PCI_DEVICE_DATA(INTEL, VSEC_MTL_M, &mtl_info) },
 436         { PCI_DEVICE_DATA(INTEL, VSEC_MTL_S, &mtl_info) },
 437         { PCI_DEVICE_DATA(INTEL, VSEC_OOBMSM, &oobmsm_info) },
 438         { PCI_DEVICE_DATA(INTEL, VSEC_RPL, &tgl_info) },
 439         { PCI_DEVICE_DATA(INTEL, VSEC_TGL, &tgl_info) },
 440         { PCI_DEVICE_DATA(INTEL, VSEC_LNL_M, &lnl_info) },
 441         { }
 442 };
 443 MODULE_DEVICE_TABLE(pci, intel_vsec_pci_ids);
 444
 445 static pci_ers_result_t intel_vsec_pci_error_detected(struct pci_dev *pdev,
 446                                                       pci_channel_state_t state)
 447 {
 448         pci_ers_result_t status = PCI_ERS_RESULT_NEED_RESET;
 449
 450         dev_info(&pdev->dev, "PCI error detected, state %d", state);
 451
 452         if (state == pci_channel_io_perm_failure)
 453                 status = PCI_ERS_RESULT_DISCONNECT;
 454         else
 455                 pci_disable_device(pdev);
 456
 457         return status;
 458 }
 459
 460 static pci_ers_result_t intel_vsec_pci_slot_reset(struct pci_dev *pdev)
 461 {
 462         struct intel_vsec_device *intel_vsec_dev;
 463         pci_ers_result_t status = PCI_ERS_RESULT_DISCONNECT;
 464         const struct pci_device_id *pci_dev_id;
 465         unsigned long index;
 466
 467         dev_info(&pdev->dev, "Resetting PCI slot\n");
 468
 469         msleep(2000);
 470         if (pci_enable_device(pdev)) {
 471                 dev_info(&pdev->dev,
 472                          "Failed to re-enable PCI device after reset.\n");
 473                 goto out;
 474         }
 475
 476         status = PCI_ERS_RESULT_RECOVERED;
 477
 478         xa_for_each(&auxdev_array, index, intel_vsec_dev) {
 479                 /* check if pdev doesn't match */
 480                 if (pdev != intel_vsec_dev->pcidev)
 481                         continue;
 482                 devm_release_action(&pdev->dev, intel_vsec_remove_aux,
 483                                     &intel_vsec_dev->auxdev);
 484         }
 485         pci_disable_device(pdev);
 486         pci_restore_state(pdev);
 487         pci_dev_id = pci_match_id(intel_vsec_pci_ids, pdev);
 488         intel_vsec_pci_probe(pdev, pci_dev_id);
 489
 490 out:
 491         return status;
 492 }
 493
 494 static void intel_vsec_pci_resume(struct pci_dev *pdev)
 495 {
 496         dev_info(&pdev->dev, "Done resuming PCI device\n");
 497 }
 498
 499 static const struct pci_error_handlers intel_vsec_pci_err_handlers = {
 500         .error_detected = intel_vsec_pci_error_detected,
 501         .slot_reset = intel_vsec_pci_slot_reset,
 502         .resume = intel_vsec_pci_resume,
 503 };
 504
 505 static struct pci_driver intel_vsec_pci_driver = {
 506         .name = "intel_vsec",
 507         .id_table = intel_vsec_pci_ids,
 508         .probe = intel_vsec_pci_probe,
 509         .err_handler = &intel_vsec_pci_err_handlers,
 510 };
 511 module_pci_driver(intel_vsec_pci_driver);
 512
 513 MODULE_AUTHOR("David E. Box <[email protected]>");
 514 MODULE_DESCRIPTION("Intel Extended Capabilities auxiliary bus driver");
 515 MODULE_LICENSE("GPL v2");