drivers/platform/x86/intel/pmc/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Core SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2016, Intel Corporation.
   6  * All Rights Reserved.
   7  *
   8  * Authors: Rajneesh Bhardwaj <[email protected]>
   9  *          Vishwanath Somayaji <[email protected]>
  10  */
  11
  12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13
  14 #include <linux/bitfield.h>
  15 #include <linux/debugfs.h>
  16 #include <linux/delay.h>
  17 #include <linux/dmi.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/slab.h>
  22 #include <linux/suspend.h>
  23 #include <linux/units.h>
  24
  25 #include <asm/cpu_device_id.h>
  26 #include <asm/intel-family.h>
  27 #include <asm/msr.h>
  28 #include <asm/tsc.h>
  29
  30 #include "core.h"
  31 #include "../pmt/telemetry.h"
  32
  33 /* Maximum number of modes supported by platfoms that has low power mode capability */
  34 const char *pmc_lpm_modes[] = {
  35         "S0i2.0",
  36         "S0i2.1",
  37         "S0i2.2",
  38         "S0i3.0",
  39         "S0i3.1",
  40         "S0i3.2",
  41         "S0i3.3",
  42         "S0i3.4",
  43         NULL
  44 };
  45
  46 /* PKGC MSRs are common across Intel Core SoCs */
  47 const struct pmc_bit_map msr_map[] = {
  48         {"Package C2",                  MSR_PKG_C2_RESIDENCY},
  49         {"Package C3",                  MSR_PKG_C3_RESIDENCY},
  50         {"Package C6",                  MSR_PKG_C6_RESIDENCY},
  51         {"Package C7",                  MSR_PKG_C7_RESIDENCY},
  52         {"Package C8",                  MSR_PKG_C8_RESIDENCY},
  53         {"Package C9",                  MSR_PKG_C9_RESIDENCY},
  54         {"Package C10",                 MSR_PKG_C10_RESIDENCY},
  55         {}
  56 };
  57
  58 static inline u32 pmc_core_reg_read(struct pmc *pmc, int reg_offset)
  59 {
  60         return readl(pmc->regbase + reg_offset);
  61 }
  62
  63 static inline void pmc_core_reg_write(struct pmc *pmc, int reg_offset,
  64                                       u32 val)
  65 {
  66         writel(val, pmc->regbase + reg_offset);
  67 }
  68
  69 static inline u64 pmc_core_adjust_slp_s0_step(struct pmc *pmc, u32 value)
  70 {
  71         /*
  72          * ADL PCH does not have the SLP_S0 counter and LPM Residency counters are
  73          * used as a workaround which uses 30.5 usec tick. All other client
  74          * programs have the legacy SLP_S0 residency counter that is using the 122
  75          * usec tick.
  76          */
  77         const int lpm_adj_x2 = pmc->map->lpm_res_counter_step_x2;
  78
  79         if (pmc->map == &adl_reg_map)
  80                 return (u64)value * GET_X2_COUNTER((u64)lpm_adj_x2);
  81         else
  82                 return (u64)value * pmc->map->slp_s0_res_counter_step;
  83 }
  84
  85 static int set_etr3(struct pmc_dev *pmcdev)
  86 {
  87         struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
  88         const struct pmc_reg_map *map = pmc->map;
  89         u32 reg;
  90
  91         if (!map->etr3_offset)
  92                 return -EOPNOTSUPP;
  93
  94         guard(mutex)(&pmcdev->lock);
  95
  96         /* check if CF9 is locked */
  97         reg = pmc_core_reg_read(pmc, map->etr3_offset);
  98         if (reg & ETR3_CF9LOCK)
  99                 return -EACCES;
 100
 101         /* write CF9 global reset bit */
 102         reg |= ETR3_CF9GR;
 103         pmc_core_reg_write(pmc, map->etr3_offset, reg);
 104
 105         reg = pmc_core_reg_read(pmc, map->etr3_offset);
 106         if (!(reg & ETR3_CF9GR))
 107                 return -EIO;
 108
 109         return 0;
 110 }
 111 static umode_t etr3_is_visible(struct kobject *kobj,
 112                                 struct attribute *attr,
 113                                 int idx)
 114 {
 115         struct device *dev = kobj_to_dev(kobj);
 116         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
 117         struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
 118         const struct pmc_reg_map *map = pmc->map;
 119         u32 reg;
 120
 121         scoped_guard(mutex, &pmcdev->lock)
 122                 reg = pmc_core_reg_read(pmc, map->etr3_offset);
 123
 124         return reg & ETR3_CF9LOCK ? attr->mode & (SYSFS_PREALLOC | 0444) : attr->mode;
 125 }
 126
 127 static ssize_t etr3_show(struct device *dev,
 128                                  struct device_attribute *attr, char *buf)
 129 {
 130         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
 131         struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
 132         const struct pmc_reg_map *map = pmc->map;
 133         u32 reg;
 134
 135         if (!map->etr3_offset)
 136                 return -EOPNOTSUPP;
 137
 138         scoped_guard(mutex, &pmcdev->lock) {
 139                 reg = pmc_core_reg_read(pmc, map->etr3_offset);
 140                 reg &= ETR3_CF9GR | ETR3_CF9LOCK;
 141         }
 142
 143         return sysfs_emit(buf, "0x%08x", reg);
 144 }
 145
 146 static ssize_t etr3_store(struct device *dev,
 147                                   struct device_attribute *attr,
 148                                   const char *buf, size_t len)
 149 {
 150         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
 151         int err;
 152         u32 reg;
 153
 154         err = kstrtouint(buf, 16, &reg);
 155         if (err)
 156                 return err;
 157
 158         /* allow only CF9 writes */
 159         if (reg != ETR3_CF9GR)
 160                 return -EINVAL;
 161
 162         err = set_etr3(pmcdev);
 163         if (err)
 164                 return err;
 165
 166         return len;
 167 }
 168 static DEVICE_ATTR_RW(etr3);
 169
 170 static struct attribute *pmc_attrs[] = {
 171         &dev_attr_etr3.attr,
 172         NULL
 173 };
 174
 175 static const struct attribute_group pmc_attr_group = {
 176         .attrs = pmc_attrs,
 177         .is_visible = etr3_is_visible,
 178 };
 179
 180 static const struct attribute_group *pmc_dev_groups[] = {
 181         &pmc_attr_group,
 182         NULL
 183 };
 184
 185 static int pmc_core_dev_state_get(void *data, u64 *val)
 186 {
 187         struct pmc *pmc = data;
 188         const struct pmc_reg_map *map = pmc->map;
 189         u32 value;
 190
 191         value = pmc_core_reg_read(pmc, map->slp_s0_offset);
 192         *val = pmc_core_adjust_slp_s0_step(pmc, value);
 193
 194         return 0;
 195 }
 196
 197 DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
 198
 199 static int pmc_core_pson_residency_get(void *data, u64 *val)
 200 {
 201         struct pmc *pmc = data;
 202         const struct pmc_reg_map *map = pmc->map;
 203         u32 value;
 204
 205         value = pmc_core_reg_read(pmc, map->pson_residency_offset);
 206         *val = (u64)value * map->pson_residency_counter_step;
 207
 208         return 0;
 209 }
 210
 211 DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_pson_residency, pmc_core_pson_residency_get, NULL, "%llu\n");
 212
 213 static int pmc_core_check_read_lock_bit(struct pmc *pmc)
 214 {
 215         u32 value;
 216
 217         value = pmc_core_reg_read(pmc, pmc->map->pm_cfg_offset);
 218         return value & BIT(pmc->map->pm_read_disable_bit);
 219 }
 220
 221 static void pmc_core_slps0_display(struct pmc *pmc, struct device *dev,
 222                                    struct seq_file *s)
 223 {
 224         const struct pmc_bit_map **maps = pmc->map->slps0_dbg_maps;
 225         const struct pmc_bit_map *map;
 226         int offset = pmc->map->slps0_dbg_offset;
 227         u32 data;
 228
 229         while (*maps) {
 230                 map = *maps;
 231                 data = pmc_core_reg_read(pmc, offset);
 232                 offset += 4;
 233                 while (map->name) {
 234                         if (dev)
 235                                 dev_info(dev, "SLP_S0_DBG: %-32s\tState: %s\n",
 236                                         map->name,
 237                                         data & map->bit_mask ? "Yes" : "No");
 238                         if (s)
 239                                 seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n",
 240                                            map->name,
 241                                            data & map->bit_mask ? "Yes" : "No");
 242                         ++map;
 243                 }
 244                 ++maps;
 245         }
 246 }
 247
 248 static unsigned int pmc_core_lpm_get_arr_size(const struct pmc_bit_map **maps)
 249 {
 250         unsigned int idx;
 251
 252         for (idx = 0; maps[idx]; idx++)
 253                 ;/* Nothing */
 254
 255         return idx;
 256 }
 257
 258 static void pmc_core_lpm_display(struct pmc *pmc, struct device *dev,
 259                                  struct seq_file *s, u32 offset, int pmc_index,
 260                                  const char *str,
 261                                  const struct pmc_bit_map **maps)
 262 {
 263         unsigned int index, idx, len = 32, arr_size;
 264         u32 bit_mask, *lpm_regs;
 265
 266         arr_size = pmc_core_lpm_get_arr_size(maps);
 267         lpm_regs = kmalloc_array(arr_size, sizeof(*lpm_regs), GFP_KERNEL);
 268         if (!lpm_regs)
 269                 return;
 270
 271         for (index = 0; index < arr_size; index++) {
 272                 lpm_regs[index] = pmc_core_reg_read(pmc, offset);
 273                 offset += 4;
 274         }
 275
 276         for (idx = 0; idx < arr_size; idx++) {
 277                 if (dev)
 278                         dev_info(dev, "\nPMC%d:LPM_%s_%d:\t0x%x\n", pmc_index, str, idx,
 279                                 lpm_regs[idx]);
 280                 if (s)
 281                         seq_printf(s, "\nPMC%d:LPM_%s_%d:\t0x%x\n", pmc_index, str, idx,
 282                                    lpm_regs[idx]);
 283                 for (index = 0; maps[idx][index].name && index < len; index++) {
 284                         bit_mask = maps[idx][index].bit_mask;
 285                         if (dev)
 286                                 dev_info(dev, "PMC%d:%-30s %-30d\n", pmc_index,
 287                                         maps[idx][index].name,
 288                                         lpm_regs[idx] & bit_mask ? 1 : 0);
 289                         if (s)
 290                                 seq_printf(s, "PMC%d:%-30s %-30d\n", pmc_index,
 291                                            maps[idx][index].name,
 292                                            lpm_regs[idx] & bit_mask ? 1 : 0);
 293                 }
 294         }
 295
 296         kfree(lpm_regs);
 297 }
 298
 299 static bool slps0_dbg_latch;
 300
 301 static inline u8 pmc_core_reg_read_byte(struct pmc *pmc, int offset)
 302 {
 303         return readb(pmc->regbase + offset);
 304 }
 305
 306 static void pmc_core_display_map(struct seq_file *s, int index, int idx, int ip,
 307                                  int pmc_index, u8 pf_reg, const struct pmc_bit_map **pf_map)
 308 {
 309         seq_printf(s, "PMC%d:PCH IP: %-2d - %-32s\tState: %s\n",
 310                    pmc_index, ip, pf_map[idx][index].name,
 311                    pf_map[idx][index].bit_mask & pf_reg ? "Off" : "On");
 312 }
 313
 314 static int pmc_core_ppfear_show(struct seq_file *s, void *unused)
 315 {
 316         struct pmc_dev *pmcdev = s->private;
 317         unsigned int i;
 318
 319         for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) {
 320                 struct pmc *pmc = pmcdev->pmcs[i];
 321                 const struct pmc_bit_map **maps;
 322                 u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
 323                 unsigned int index, iter, idx, ip = 0;
 324
 325                 if (!pmc)
 326                         continue;
 327
 328                 maps = pmc->map->pfear_sts;
 329                 iter = pmc->map->ppfear0_offset;
 330
 331                 for (index = 0; index < pmc->map->ppfear_buckets &&
 332                      index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
 333                         pf_regs[index] = pmc_core_reg_read_byte(pmc, iter);
 334
 335                 for (idx = 0; maps[idx]; idx++) {
 336                         for (index = 0; maps[idx][index].name &&
 337                              index < pmc->map->ppfear_buckets * 8; ip++, index++)
 338                                 pmc_core_display_map(s, index, idx, ip, i,
 339                                                      pf_regs[index / 8], maps);
 340                 }
 341         }
 342
 343         return 0;
 344 }
 345 DEFINE_SHOW_ATTRIBUTE(pmc_core_ppfear);
 346
 347 /* This function should return link status, 0 means ready */
 348 static int pmc_core_mtpmc_link_status(struct pmc *pmc)
 349 {
 350         u32 value;
 351
 352         value = pmc_core_reg_read(pmc, SPT_PMC_PM_STS_OFFSET);
 353         return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
 354 }
 355
 356 static int pmc_core_send_msg(struct pmc *pmc, u32 *addr_xram)
 357 {
 358         u32 dest;
 359         int timeout;
 360
 361         for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
 362                 if (pmc_core_mtpmc_link_status(pmc) == 0)
 363                         break;
 364                 msleep(5);
 365         }
 366
 367         if (timeout <= 0 && pmc_core_mtpmc_link_status(pmc))
 368                 return -EBUSY;
 369
 370         dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
 371         pmc_core_reg_write(pmc, SPT_PMC_MTPMC_OFFSET, dest);
 372         return 0;
 373 }
 374
 375 static int pmc_core_mphy_pg_show(struct seq_file *s, void *unused)
 376 {
 377         struct pmc_dev *pmcdev = s->private;
 378         struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
 379         const struct pmc_bit_map *map = pmc->map->mphy_sts;
 380         u32 mphy_core_reg_low, mphy_core_reg_high;
 381         u32 val_low, val_high;
 382         unsigned int index;
 383         int err = 0;
 384
 385         if (pmcdev->pmc_xram_read_bit) {
 386                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
 387                 return 0;
 388         }
 389
 390         mphy_core_reg_low  = (SPT_PMC_MPHY_CORE_STS_0 << 16);
 391         mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
 392
 393         guard(mutex)(&pmcdev->lock);
 394
 395         err = pmc_core_send_msg(pmc, &mphy_core_reg_low);
 396         if (err)
 397                 return err;
 398
 399         msleep(10);
 400         val_low = pmc_core_reg_read(pmc, SPT_PMC_MFPMC_OFFSET);
 401
 402         err = pmc_core_send_msg(pmc, &mphy_core_reg_high);
 403         if (err)
 404                 return err;
 405
 406         msleep(10);
 407         val_high = pmc_core_reg_read(pmc, SPT_PMC_MFPMC_OFFSET);
 408
 409         for (index = 0; index < 8 && map[index].name; index++) {
 410                 seq_printf(s, "%-32s\tState: %s\n",
 411                            map[index].name,
 412                            map[index].bit_mask & val_low ? "Not power gated" :
 413                            "Power gated");
 414         }
 415
 416         for (index = 8; map[index].name; index++) {
 417                 seq_printf(s, "%-32s\tState: %s\n",
 418                            map[index].name,
 419                            map[index].bit_mask & val_high ? "Not power gated" :
 420                            "Power gated");
 421         }
 422
 423         return 0;
 424 }
 425 DEFINE_SHOW_ATTRIBUTE(pmc_core_mphy_pg);
 426
 427 static int pmc_core_pll_show(struct seq_file *s, void *unused)
 428 {
 429         struct pmc_dev *pmcdev = s->private;
 430         struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
 431         const struct pmc_bit_map *map = pmc->map->pll_sts;
 432         u32 mphy_common_reg, val;
 433         unsigned int index;
 434         int err = 0;
 435
 436         if (pmcdev->pmc_xram_read_bit) {
 437                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
 438                 return 0;
 439         }
 440
 441         mphy_common_reg  = (SPT_PMC_MPHY_COM_STS_0 << 16);
 442         guard(mutex)(&pmcdev->lock);
 443
 444         err = pmc_core_send_msg(pmc, &mphy_common_reg);
 445         if (err)
 446                 return err;
 447
 448         /* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
 449         msleep(10);
 450         val = pmc_core_reg_read(pmc, SPT_PMC_MFPMC_OFFSET);
 451
 452         for (index = 0; map[index].name ; index++) {
 453                 seq_printf(s, "%-32s\tState: %s\n",
 454                            map[index].name,
 455                            map[index].bit_mask & val ? "Active" : "Idle");
 456         }
 457
 458         return 0;
 459 }
 460 DEFINE_SHOW_ATTRIBUTE(pmc_core_pll);
 461
 462 int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value, int ignore)
 463 {
 464         struct pmc *pmc;
 465         const struct pmc_reg_map *map;
 466         u32 reg;
 467         unsigned int pmc_index;
 468         int ltr_index;
 469
 470         ltr_index = value;
 471         /* For platforms with multiple pmcs, ltr index value given by user
 472          * is based on the contiguous indexes from ltr_show output.
 473          * pmc index and ltr index needs to be calculated from it.
 474          */
 475         for (pmc_index = 0; pmc_index < ARRAY_SIZE(pmcdev->pmcs) && ltr_index >= 0; pmc_index++) {
 476                 pmc = pmcdev->pmcs[pmc_index];
 477
 478                 if (!pmc)
 479                         continue;
 480
 481                 map = pmc->map;
 482                 if (ltr_index <= map->ltr_ignore_max)
 483                         break;
 484
 485                 /* Along with IP names, ltr_show map includes CURRENT_PLATFORM
 486                  * and AGGREGATED_SYSTEM values per PMC. Take these two index
 487                  * values into account in ltr_index calculation. Also, to start
 488                  * ltr index from zero for next pmc, subtract it by 1.
 489                  */
 490                 ltr_index = ltr_index - (map->ltr_ignore_max + 2) - 1;
 491         }
 492
 493         if (pmc_index >= ARRAY_SIZE(pmcdev->pmcs) || ltr_index < 0)
 494                 return -EINVAL;
 495
 496         pr_debug("ltr_ignore for pmc%d: ltr_index:%d\n", pmc_index, ltr_index);
 497
 498         guard(mutex)(&pmcdev->lock);
 499
 500         reg = pmc_core_reg_read(pmc, map->ltr_ignore_offset);
 501         if (ignore)
 502                 reg |= BIT(ltr_index);
 503         else
 504                 reg &= ~BIT(ltr_index);
 505         pmc_core_reg_write(pmc, map->ltr_ignore_offset, reg);
 506
 507         return 0;
 508 }
 509
 510 static ssize_t pmc_core_ltr_write(struct pmc_dev *pmcdev,
 511                                   const char __user *userbuf,
 512                                   size_t count, int ignore)
 513 {
 514         u32 value;
 515         int err;
 516
 517         err = kstrtou32_from_user(userbuf, count, 10, &value);
 518         if (err)
 519                 return err;
 520
 521         err = pmc_core_send_ltr_ignore(pmcdev, value, ignore);
 522
 523         return err ?: count;
 524 }
 525
 526 static ssize_t pmc_core_ltr_ignore_write(struct file *file,
 527                                          const char __user *userbuf,
 528                                          size_t count, loff_t *ppos)
 529 {
 530         struct seq_file *s = file->private_data;
 531         struct pmc_dev *pmcdev = s->private;
 532
 533         return pmc_core_ltr_write(pmcdev, userbuf, count, 1);
 534 }
 535
 536 static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
 537 {
 538         return 0;
 539 }
 540 DEFINE_SHOW_STORE_ATTRIBUTE(pmc_core_ltr_ignore);
 541
 542 static ssize_t pmc_core_ltr_restore_write(struct file *file,
 543                                           const char __user *userbuf,
 544                                           size_t count, loff_t *ppos)
 545 {
 546         struct seq_file *s = file->private_data;
 547         struct pmc_dev *pmcdev = s->private;
 548
 549         return pmc_core_ltr_write(pmcdev, userbuf, count, 0);
 550 }
 551
 552 static int pmc_core_ltr_restore_show(struct seq_file *s, void *unused)
 553 {
 554         return 0;
 555 }
 556 DEFINE_SHOW_STORE_ATTRIBUTE(pmc_core_ltr_restore);
 557
 558 static void pmc_core_slps0_dbg_latch(struct pmc_dev *pmcdev, bool reset)
 559 {
 560         struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
 561         const struct pmc_reg_map *map = pmc->map;
 562         u32 fd;
 563
 564         guard(mutex)(&pmcdev->lock);
 565
 566         if (!reset && !slps0_dbg_latch)
 567                 return;
 568
 569         fd = pmc_core_reg_read(pmc, map->slps0_dbg_offset);
 570         if (reset)
 571                 fd &= ~CNP_PMC_LATCH_SLPS0_EVENTS;
 572         else
 573                 fd |= CNP_PMC_LATCH_SLPS0_EVENTS;
 574         pmc_core_reg_write(pmc, map->slps0_dbg_offset, fd);
 575
 576         slps0_dbg_latch = false;
 577 }
 578
 579 static int pmc_core_slps0_dbg_show(struct seq_file *s, void *unused)
 580 {
 581         struct pmc_dev *pmcdev = s->private;
 582
 583         pmc_core_slps0_dbg_latch(pmcdev, false);
 584         pmc_core_slps0_display(pmcdev->pmcs[PMC_IDX_MAIN], NULL, s);
 585         pmc_core_slps0_dbg_latch(pmcdev, true);
 586
 587         return 0;
 588 }
 589 DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg);
 590
 591 static u32 convert_ltr_scale(u32 val)
 592 {
 593         /*
 594          * As per PCIE specification supporting document
 595          * ECN_LatencyTolnReporting_14Aug08.pdf the Latency
 596          * Tolerance Reporting data payload is encoded in a
 597          * 3 bit scale and 10 bit value fields. Values are
 598          * multiplied by the indicated scale to yield an absolute time
 599          * value, expressible in a range from 1 nanosecond to
 600          * 2^25*(2^10-1) = 34,326,183,936 nanoseconds.
 601          *
 602          * scale encoding is as follows:
 603          *
 604          * ----------------------------------------------
 605          * |scale factor        |       Multiplier (ns) |
 606          * ----------------------------------------------
 607          * |    0               |       1               |
 608          * |    1               |       32              |
 609          * |    2               |       1024            |
 610          * |    3               |       32768           |
 611          * |    4               |       1048576         |
 612          * |    5               |       33554432        |
 613          * |    6               |       Invalid         |
 614          * |    7               |       Invalid         |
 615          * ----------------------------------------------
 616          */
 617         if (val > 5) {
 618                 pr_warn("Invalid LTR scale factor.\n");
 619                 return 0;
 620         }
 621
 622         return 1U << (5 * val);
 623 }
 624
 625 static int pmc_core_ltr_show(struct seq_file *s, void *unused)
 626 {
 627         struct pmc_dev *pmcdev = s->private;
 628         u64 decoded_snoop_ltr, decoded_non_snoop_ltr;
 629         u32 ltr_raw_data, scale, val;
 630         u16 snoop_ltr, nonsnoop_ltr;
 631         unsigned int i, index, ltr_index = 0;
 632
 633         for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) {
 634                 struct pmc *pmc;
 635                 const struct pmc_bit_map *map;
 636                 u32 ltr_ign_reg;
 637
 638                 pmc = pmcdev->pmcs[i];
 639                 if (!pmc)
 640                         continue;
 641
 642                 scoped_guard(mutex, &pmcdev->lock)
 643                         ltr_ign_reg = pmc_core_reg_read(pmc, pmc->map->ltr_ignore_offset);
 644
 645                 map = pmc->map->ltr_show_sts;
 646                 for (index = 0; map[index].name; index++) {
 647                         bool ltr_ign_data;
 648
 649                         if (index > pmc->map->ltr_ignore_max)
 650                                 ltr_ign_data = false;
 651                         else
 652                                 ltr_ign_data = ltr_ign_reg & BIT(index);
 653
 654                         decoded_snoop_ltr = decoded_non_snoop_ltr = 0;
 655                         ltr_raw_data = pmc_core_reg_read(pmc,
 656                                                          map[index].bit_mask);
 657                         snoop_ltr = ltr_raw_data & ~MTPMC_MASK;
 658                         nonsnoop_ltr = (ltr_raw_data >> 0x10) & ~MTPMC_MASK;
 659
 660                         if (FIELD_GET(LTR_REQ_NONSNOOP, ltr_raw_data)) {
 661                                 scale = FIELD_GET(LTR_DECODED_SCALE, nonsnoop_ltr);
 662                                 val = FIELD_GET(LTR_DECODED_VAL, nonsnoop_ltr);
 663                                 decoded_non_snoop_ltr = val * convert_ltr_scale(scale);
 664                         }
 665                         if (FIELD_GET(LTR_REQ_SNOOP, ltr_raw_data)) {
 666                                 scale = FIELD_GET(LTR_DECODED_SCALE, snoop_ltr);
 667                                 val = FIELD_GET(LTR_DECODED_VAL, snoop_ltr);
 668                                 decoded_snoop_ltr = val * convert_ltr_scale(scale);
 669                         }
 670
 671                         seq_printf(s, "%d\tPMC%d:%-32s\tLTR: RAW: 0x%-16x\tNon-Snoop(ns): %-16llu\tSnoop(ns): %-16llu\tLTR_IGNORE: %d\n",
 672                                    ltr_index, i, map[index].name, ltr_raw_data,
 673                                    decoded_non_snoop_ltr,
 674                                    decoded_snoop_ltr, ltr_ign_data);
 675                         ltr_index++;
 676                 }
 677         }
 678         return 0;
 679 }
 680 DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr);
 681
 682 static int pmc_core_s0ix_blocker_show(struct seq_file *s, void *unused)
 683 {
 684         struct pmc_dev *pmcdev = s->private;
 685         unsigned int pmcidx;
 686
 687         for (pmcidx = 0; pmcidx < ARRAY_SIZE(pmcdev->pmcs); pmcidx++) {
 688                 const struct pmc_bit_map **maps;
 689                 unsigned int arr_size, r_idx;
 690                 u32 offset, counter;
 691                 struct pmc *pmc;
 692
 693                 pmc = pmcdev->pmcs[pmcidx];
 694                 if (!pmc)
 695                         continue;
 696                 maps = pmc->map->s0ix_blocker_maps;
 697                 offset = pmc->map->s0ix_blocker_offset;
 698                 arr_size = pmc_core_lpm_get_arr_size(maps);
 699
 700                 for (r_idx = 0; r_idx < arr_size; r_idx++) {
 701                         const struct pmc_bit_map *map;
 702
 703                         for (map = maps[r_idx]; map->name; map++) {
 704                                 if (!map->blk)
 705                                         continue;
 706                                 counter = pmc_core_reg_read(pmc, offset);
 707                                 seq_printf(s, "PMC%d:%-30s %-30d\n", pmcidx,
 708                                            map->name, counter);
 709                                 offset += map->blk * S0IX_BLK_SIZE;
 710                         }
 711                 }
 712         }
 713         return 0;
 714 }
 715 DEFINE_SHOW_ATTRIBUTE(pmc_core_s0ix_blocker);
 716
 717 static inline u64 adjust_lpm_residency(struct pmc *pmc, u32 offset,
 718                                        const int lpm_adj_x2)
 719 {
 720         u64 lpm_res = pmc_core_reg_read(pmc, offset);
 721
 722         return GET_X2_COUNTER((u64)lpm_adj_x2 * lpm_res);
 723 }
 724
 725 static int pmc_core_substate_res_show(struct seq_file *s, void *unused)
 726 {
 727         struct pmc_dev *pmcdev = s->private;
 728         struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
 729         const int lpm_adj_x2 = pmc->map->lpm_res_counter_step_x2;
 730         u32 offset = pmc->map->lpm_residency_offset;
 731         unsigned int i;
 732         int mode;
 733
 734         seq_printf(s, "%-10s %-15s\n", "Substate", "Residency");
 735
 736         pmc_for_each_mode(i, mode, pmcdev) {
 737                 seq_printf(s, "%-10s %-15llu\n", pmc_lpm_modes[mode],
 738                            adjust_lpm_residency(pmc, offset + (4 * mode), lpm_adj_x2));
 739         }
 740
 741         return 0;
 742 }
 743 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_res);
 744
 745 static int pmc_core_substate_sts_regs_show(struct seq_file *s, void *unused)
 746 {
 747         struct pmc_dev *pmcdev = s->private;
 748         unsigned int i;
 749
 750         for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) {
 751                 struct pmc *pmc = pmcdev->pmcs[i];
 752                 const struct pmc_bit_map **maps;
 753                 u32 offset;
 754
 755                 if (!pmc)
 756                         continue;
 757                 maps = pmc->map->lpm_sts;
 758                 offset = pmc->map->lpm_status_offset;
 759                 pmc_core_lpm_display(pmc, NULL, s, offset, i, "STATUS", maps);
 760         }
 761
 762         return 0;
 763 }
 764 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_sts_regs);
 765
 766 static int pmc_core_substate_l_sts_regs_show(struct seq_file *s, void *unused)
 767 {
 768         struct pmc_dev *pmcdev = s->private;
 769         unsigned int i;
 770
 771         for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) {
 772                 struct pmc *pmc = pmcdev->pmcs[i];
 773                 const struct pmc_bit_map **maps;
 774                 u32 offset;
 775
 776                 if (!pmc)
 777                         continue;
 778                 maps = pmc->map->lpm_sts;
 779                 offset = pmc->map->lpm_live_status_offset;
 780                 pmc_core_lpm_display(pmc, NULL, s, offset, i, "LIVE_STATUS", maps);
 781         }
 782
 783         return 0;
 784 }
 785 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_l_sts_regs);
 786
 787 static void pmc_core_substate_req_header_show(struct seq_file *s, int pmc_index)
 788 {
 789         struct pmc_dev *pmcdev = s->private;
 790         unsigned int i;
 791         int mode;
 792
 793         seq_printf(s, "%30s |", "Element");
 794         pmc_for_each_mode(i, mode, pmcdev)
 795                 seq_printf(s, " %9s |", pmc_lpm_modes[mode]);
 796
 797         seq_printf(s, " %9s |\n", "Status");
 798 }
 799
 800 static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unused)
 801 {
 802         struct pmc_dev *pmcdev = s->private;
 803         u32 sts_offset;
 804         u32 *lpm_req_regs;
 805         unsigned int mp, pmc_index;
 806         int num_maps;
 807
 808         for (pmc_index = 0; pmc_index < ARRAY_SIZE(pmcdev->pmcs); ++pmc_index) {
 809                 struct pmc *pmc = pmcdev->pmcs[pmc_index];
 810                 const struct pmc_bit_map **maps;
 811
 812                 if (!pmc)
 813                         continue;
 814
 815                 maps = pmc->map->lpm_sts;
 816                 num_maps = pmc->map->lpm_num_maps;
 817                 sts_offset = pmc->map->lpm_status_offset;
 818                 lpm_req_regs = pmc->lpm_req_regs;
 819
 820                 /*
 821                  * When there are multiple PMCs, though the PMC may exist, the
 822                  * requirement register discovery could have failed so check
 823                  * before accessing.
 824                  */
 825                 if (!lpm_req_regs)
 826                         continue;
 827
 828                 /* Display the header */
 829                 pmc_core_substate_req_header_show(s, pmc_index);
 830
 831                 /* Loop over maps */
 832                 for (mp = 0; mp < num_maps; mp++) {
 833                         u32 req_mask = 0;
 834                         u32 lpm_status;
 835                         const struct pmc_bit_map *map;
 836                         int mode, idx, i, len = 32;
 837
 838                         /*
 839                          * Capture the requirements and create a mask so that we only
 840                          * show an element if it's required for at least one of the
 841                          * enabled low power modes
 842                          */
 843                         pmc_for_each_mode(idx, mode, pmcdev)
 844                                 req_mask |= lpm_req_regs[mp + (mode * num_maps)];
 845
 846                         /* Get the last latched status for this map */
 847                         lpm_status = pmc_core_reg_read(pmc, sts_offset + (mp * 4));
 848
 849                         /*  Loop over elements in this map */
 850                         map = maps[mp];
 851                         for (i = 0; map[i].name && i < len; i++) {
 852                                 u32 bit_mask = map[i].bit_mask;
 853
 854                                 if (!(bit_mask & req_mask)) {
 855                                         /*
 856                                          * Not required for any enabled states
 857                                          * so don't display
 858                                          */
 859                                         continue;
 860                                 }
 861
 862                                 /* Display the element name in the first column */
 863                                 seq_printf(s, "pmc%d: %26s |", pmc_index, map[i].name);
 864
 865                                 /* Loop over the enabled states and display if required */
 866                                 pmc_for_each_mode(idx, mode, pmcdev) {
 867                                         bool required = lpm_req_regs[mp + (mode * num_maps)] &
 868                                                         bit_mask;
 869                                         seq_printf(s, " %9s |", required ? "Required" : " ");
 870                                 }
 871
 872                                 /* In Status column, show the last captured state of this agent */
 873                                 seq_printf(s, " %9s |", lpm_status & bit_mask ? "Yes" : " ");
 874
 875                                 seq_puts(s, "\n");
 876                         }
 877                 }
 878         }
 879         return 0;
 880 }
 881 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_req_regs);
 882
 883 static unsigned int pmc_core_get_crystal_freq(void)
 884 {
 885         unsigned int eax_denominator, ebx_numerator, ecx_hz, edx;
 886
 887         if (boot_cpu_data.cpuid_level < 0x15)
 888                 return 0;
 889
 890         eax_denominator = ebx_numerator = ecx_hz = edx = 0;
 891
 892         /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
 893         cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
 894
 895         if (ebx_numerator == 0 || eax_denominator == 0)
 896                 return 0;
 897
 898         return ecx_hz;
 899 }
 900
 901 static int pmc_core_die_c6_us_show(struct seq_file *s, void *unused)
 902 {
 903         struct pmc_dev *pmcdev = s->private;
 904         u64 die_c6_res, count;
 905         int ret;
 906
 907         if (!pmcdev->crystal_freq) {
 908                 dev_warn_once(&pmcdev->pdev->dev, "Crystal frequency unavailable\n");
 909                 return -ENXIO;
 910         }
 911
 912         ret = pmt_telem_read(pmcdev->punit_ep, pmcdev->die_c6_offset,
 913                              &count, 1);
 914         if (ret)
 915                 return ret;
 916
 917         die_c6_res = div64_u64(count * HZ_PER_MHZ, pmcdev->crystal_freq);
 918         seq_printf(s, "%llu\n", die_c6_res);
 919
 920         return 0;
 921 }
 922 DEFINE_SHOW_ATTRIBUTE(pmc_core_die_c6_us);
 923
 924 static int pmc_core_lpm_latch_mode_show(struct seq_file *s, void *unused)
 925 {
 926         struct pmc_dev *pmcdev = s->private;
 927         struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
 928         unsigned int idx;
 929         bool c10;
 930         u32 reg;
 931         int mode;
 932
 933         reg = pmc_core_reg_read(pmc, pmc->map->lpm_sts_latch_en_offset);
 934         if (reg & LPM_STS_LATCH_MODE) {
 935                 seq_puts(s, "c10");
 936                 c10 = false;
 937         } else {
 938                 seq_puts(s, "[c10]");
 939                 c10 = true;
 940         }
 941
 942         pmc_for_each_mode(idx, mode, pmcdev) {
 943                 if ((BIT(mode) & reg) && !c10)
 944                         seq_printf(s, " [%s]", pmc_lpm_modes[mode]);
 945                 else
 946                         seq_printf(s, " %s", pmc_lpm_modes[mode]);
 947         }
 948
 949         seq_puts(s, " clear\n");
 950
 951         return 0;
 952 }
 953
 954 static ssize_t pmc_core_lpm_latch_mode_write(struct file *file,
 955                                              const char __user *userbuf,
 956                                              size_t count, loff_t *ppos)
 957 {
 958         struct seq_file *s = file->private_data;
 959         struct pmc_dev *pmcdev = s->private;
 960         struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
 961         bool clear = false, c10 = false;
 962         unsigned char buf[8];
 963         unsigned int idx;
 964         int m, mode;
 965         u32 reg;
 966
 967         if (count > sizeof(buf) - 1)
 968                 return -EINVAL;
 969         if (copy_from_user(buf, userbuf, count))
 970                 return -EFAULT;
 971         buf[count] = '\0';
 972
 973         /*
 974          * Allowed strings are:
 975          *      Any enabled substate, e.g. 'S0i2.0'
 976          *      'c10'
 977          *      'clear'
 978          */
 979         mode = sysfs_match_string(pmc_lpm_modes, buf);
 980
 981         /* Check string matches enabled mode */
 982         pmc_for_each_mode(idx, m, pmcdev)
 983                 if (mode == m)
 984                         break;
 985
 986         if (mode != m || mode < 0) {
 987                 if (sysfs_streq(buf, "clear"))
 988                         clear = true;
 989                 else if (sysfs_streq(buf, "c10"))
 990                         c10 = true;
 991                 else
 992                         return -EINVAL;
 993         }
 994
 995         if (clear) {
 996                 guard(mutex)(&pmcdev->lock);
 997
 998                 reg = pmc_core_reg_read(pmc, pmc->map->etr3_offset);
 999                 reg |= ETR3_CLEAR_LPM_EVENTS;
1000                 pmc_core_reg_write(pmc, pmc->map->etr3_offset, reg);
1001
1002                 return count;
1003         }
1004
1005         if (c10) {
1006                 guard(mutex)(&pmcdev->lock);
1007
1008                 reg = pmc_core_reg_read(pmc, pmc->map->lpm_sts_latch_en_offset);
1009                 reg &= ~LPM_STS_LATCH_MODE;
1010                 pmc_core_reg_write(pmc, pmc->map->lpm_sts_latch_en_offset, reg);
1011
1012                 return count;
1013         }
1014
1015         /*
1016          * For LPM mode latching we set the latch enable bit and selected mode
1017          * and clear everything else.
1018          */
1019         reg = LPM_STS_LATCH_MODE | BIT(mode);
1020         guard(mutex)(&pmcdev->lock);
1021         pmc_core_reg_write(pmc, pmc->map->lpm_sts_latch_en_offset, reg);
1022
1023         return count;
1024 }
1025 DEFINE_PMC_CORE_ATTR_WRITE(pmc_core_lpm_latch_mode);
1026
1027 static int pmc_core_pkgc_show(struct seq_file *s, void *unused)
1028 {
1029         struct pmc *pmc = s->private;
1030         const struct pmc_bit_map *map = pmc->map->msr_sts;
1031         u64 pcstate_count;
1032         unsigned int index;
1033
1034         for (index = 0; map[index].name ; index++) {
1035                 if (rdmsrl_safe(map[index].bit_mask, &pcstate_count))
1036                         continue;
1037
1038                 pcstate_count *= 1000;
1039                 do_div(pcstate_count, tsc_khz);
1040                 seq_printf(s, "%-8s : %llu\n", map[index].name,
1041                            pcstate_count);
1042         }
1043
1044         return 0;
1045 }
1046 DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc);
1047
1048 static bool pmc_core_pri_verify(u32 lpm_pri, u8 *mode_order)
1049 {
1050         unsigned int i, j;
1051
1052         if (!lpm_pri)
1053                 return false;
1054         /*
1055          * Each byte contains the priority level for 2 modes (7:4 and 3:0).
1056          * In a 32 bit register this allows for describing 8 modes. Store the
1057          * levels and look for values out of range.
1058          */
1059         for (i = 0; i < 8; i++) {
1060                 int level = lpm_pri & GENMASK(3, 0);
1061
1062                 if (level >= LPM_MAX_NUM_MODES)
1063                         return false;
1064
1065                 mode_order[i] = level;
1066                 lpm_pri >>= 4;
1067         }
1068
1069         /* Check that we have unique values */
1070         for (i = 0; i < LPM_MAX_NUM_MODES - 1; i++)
1071                 for (j = i + 1; j < LPM_MAX_NUM_MODES; j++)
1072                         if (mode_order[i] == mode_order[j])
1073                                 return false;
1074
1075         return true;
1076 }
1077
1078 void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev)
1079 {
1080         struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
1081         u8 pri_order[LPM_MAX_NUM_MODES] = LPM_DEFAULT_PRI;
1082         u8 mode_order[LPM_MAX_NUM_MODES];
1083         u32 lpm_pri;
1084         u32 lpm_en;
1085         unsigned int i;
1086         int mode, p;
1087
1088         /* Use LPM Maps to indicate support for substates */
1089         if (!pmc->map->lpm_num_maps)
1090                 return;
1091
1092         lpm_en = pmc_core_reg_read(pmc, pmc->map->lpm_en_offset);
1093         /* For MTL, BIT 31 is not an lpm mode but a enable bit.
1094          * Lower byte is enough to cover the number of lpm modes for all
1095          * platforms and hence mask the upper 3 bytes.
1096          */
1097         pmcdev->num_lpm_modes = hweight32(lpm_en & 0xFF);
1098
1099         /* Read 32 bit LPM_PRI register */
1100         lpm_pri = pmc_core_reg_read(pmc, pmc->map->lpm_priority_offset);
1101
1102
1103         /*
1104          * If lpm_pri value passes verification, then override the default
1105          * modes here. Otherwise stick with the default.
1106          */
1107         if (pmc_core_pri_verify(lpm_pri, mode_order))
1108                 /* Get list of modes in priority order */
1109                 for (mode = 0; mode < LPM_MAX_NUM_MODES; mode++)
1110                         pri_order[mode_order[mode]] = mode;
1111         else
1112                 dev_warn(&pmcdev->pdev->dev,
1113                          "Assuming a default substate order for this platform\n");
1114
1115         /*
1116          * Loop through all modes from lowest to highest priority,
1117          * and capture all enabled modes in order
1118          */
1119         i = 0;
1120         for (p = LPM_MAX_NUM_MODES - 1; p >= 0; p--) {
1121                 int mode = pri_order[p];
1122
1123                 if (!(BIT(mode) & lpm_en))
1124                         continue;
1125
1126                 pmcdev->lpm_en_modes[i++] = mode;
1127         }
1128 }
1129
1130 int get_primary_reg_base(struct pmc *pmc)
1131 {
1132         u64 slp_s0_addr;
1133
1134         if (lpit_read_residency_count_address(&slp_s0_addr)) {
1135                 pmc->base_addr = PMC_BASE_ADDR_DEFAULT;
1136
1137                 if (page_is_ram(PHYS_PFN(pmc->base_addr)))
1138                         return -ENODEV;
1139         } else {
1140                 pmc->base_addr = slp_s0_addr - pmc->map->slp_s0_offset;
1141         }
1142
1143         pmc->regbase = ioremap(pmc->base_addr, pmc->map->regmap_length);
1144         if (!pmc->regbase)
1145                 return -ENOMEM;
1146         return 0;
1147 }
1148
1149 void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 guid)
1150 {
1151         struct telem_endpoint *ep;
1152         struct pci_dev *pcidev;
1153
1154         pcidev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(10, 0));
1155         if (!pcidev) {
1156                 dev_err(&pmcdev->pdev->dev, "PUNIT PMT device not found.");
1157                 return;
1158         }
1159
1160         ep = pmt_telem_find_and_register_endpoint(pcidev, guid, 0);
1161         pci_dev_put(pcidev);
1162         if (IS_ERR(ep)) {
1163                 dev_err(&pmcdev->pdev->dev,
1164                         "pmc_core: couldn't get DMU telem endpoint %ld",
1165                         PTR_ERR(ep));
1166                 return;
1167         }
1168
1169         pmcdev->punit_ep = ep;
1170
1171         pmcdev->has_die_c6 = true;
1172         pmcdev->die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET;
1173 }
1174
1175 void pmc_core_set_device_d3(unsigned int device)
1176 {
1177         struct pci_dev *pcidev;
1178
1179         pcidev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1180         if (pcidev) {
1181                 if (!device_trylock(&pcidev->dev)) {
1182                         pci_dev_put(pcidev);
1183                         return;
1184                 }
1185                 if (!pcidev->dev.driver) {
1186                         dev_info(&pcidev->dev, "Setting to D3hot\n");
1187                         pci_set_power_state(pcidev, PCI_D3hot);
1188                 }
1189                 device_unlock(&pcidev->dev);
1190                 pci_dev_put(pcidev);
1191         }
1192 }
1193
1194 static bool pmc_core_is_pson_residency_enabled(struct pmc_dev *pmcdev)
1195 {
1196         struct platform_device *pdev = pmcdev->pdev;
1197         struct acpi_device *adev = ACPI_COMPANION(&pdev->dev);
1198         u8 val;
1199
1200         if (!adev)
1201                 return false;
1202
1203         if (fwnode_property_read_u8(acpi_fwnode_handle(adev),
1204                                     "intel-cec-pson-switching-enabled-in-s0",
1205                                     &val))
1206                 return false;
1207
1208         return val == 1;
1209 }
1210
1211
1212 static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
1213 {
1214         debugfs_remove_recursive(pmcdev->dbgfs_dir);
1215 }
1216
1217 static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
1218 {
1219         struct pmc *primary_pmc = pmcdev->pmcs[PMC_IDX_MAIN];
1220         struct dentry *dir;
1221
1222         dir = debugfs_create_dir("pmc_core", NULL);
1223         pmcdev->dbgfs_dir = dir;
1224
1225         debugfs_create_file("slp_s0_residency_usec", 0444, dir, primary_pmc,
1226                             &pmc_core_dev_state);
1227
1228         if (primary_pmc->map->pfear_sts)
1229                 debugfs_create_file("pch_ip_power_gating_status", 0444, dir,
1230                                     pmcdev, &pmc_core_ppfear_fops);
1231
1232         debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
1233                             &pmc_core_ltr_ignore_fops);
1234
1235         debugfs_create_file("ltr_restore", 0200, dir, pmcdev, &pmc_core_ltr_restore_fops);
1236
1237         debugfs_create_file("ltr_show", 0444, dir, pmcdev, &pmc_core_ltr_fops);
1238
1239         if (primary_pmc->map->s0ix_blocker_maps)
1240                 debugfs_create_file("s0ix_blocker", 0444, dir, pmcdev, &pmc_core_s0ix_blocker_fops);
1241
1242         debugfs_create_file("package_cstate_show", 0444, dir, primary_pmc,
1243                             &pmc_core_pkgc_fops);
1244
1245         if (primary_pmc->map->pll_sts)
1246                 debugfs_create_file("pll_status", 0444, dir, pmcdev,
1247                                     &pmc_core_pll_fops);
1248
1249         if (primary_pmc->map->mphy_sts)
1250                 debugfs_create_file("mphy_core_lanes_power_gating_status",
1251                                     0444, dir, pmcdev,
1252                                     &pmc_core_mphy_pg_fops);
1253
1254         if (primary_pmc->map->slps0_dbg_maps) {
1255                 debugfs_create_file("slp_s0_debug_status", 0444,
1256                                     dir, pmcdev,
1257                                     &pmc_core_slps0_dbg_fops);
1258
1259                 debugfs_create_bool("slp_s0_dbg_latch", 0644,
1260                                     dir, &slps0_dbg_latch);
1261         }
1262
1263         if (primary_pmc->map->lpm_en_offset) {
1264                 debugfs_create_file("substate_residencies", 0444,
1265                                     pmcdev->dbgfs_dir, pmcdev,
1266                                     &pmc_core_substate_res_fops);
1267         }
1268
1269         if (primary_pmc->map->lpm_status_offset) {
1270                 debugfs_create_file("substate_status_registers", 0444,
1271                                     pmcdev->dbgfs_dir, pmcdev,
1272                                     &pmc_core_substate_sts_regs_fops);
1273                 debugfs_create_file("substate_live_status_registers", 0444,
1274                                     pmcdev->dbgfs_dir, pmcdev,
1275                                     &pmc_core_substate_l_sts_regs_fops);
1276                 debugfs_create_file("lpm_latch_mode", 0644,
1277                                     pmcdev->dbgfs_dir, pmcdev,
1278                                     &pmc_core_lpm_latch_mode_fops);
1279         }
1280
1281         if (primary_pmc->lpm_req_regs) {
1282                 debugfs_create_file("substate_requirements", 0444,
1283                                     pmcdev->dbgfs_dir, pmcdev,
1284                                     &pmc_core_substate_req_regs_fops);
1285         }
1286
1287         if (primary_pmc->map->pson_residency_offset && pmc_core_is_pson_residency_enabled(pmcdev)) {
1288                 debugfs_create_file("pson_residency_usec", 0444,
1289                                     pmcdev->dbgfs_dir, primary_pmc, &pmc_core_pson_residency);
1290         }
1291
1292         if (pmcdev->has_die_c6) {
1293                 debugfs_create_file("die_c6_us_show", 0444,
1294                                     pmcdev->dbgfs_dir, pmcdev,
1295                                     &pmc_core_die_c6_us_fops);
1296         }
1297 }
1298
1299 static const struct x86_cpu_id intel_pmc_core_ids[] = {
1300         X86_MATCH_VFM(INTEL_SKYLAKE_L,          spt_core_init),
1301         X86_MATCH_VFM(INTEL_SKYLAKE,            spt_core_init),
1302         X86_MATCH_VFM(INTEL_KABYLAKE_L,         spt_core_init),
1303         X86_MATCH_VFM(INTEL_KABYLAKE,           spt_core_init),
1304         X86_MATCH_VFM(INTEL_CANNONLAKE_L,       cnp_core_init),
1305         X86_MATCH_VFM(INTEL_ICELAKE_L,          icl_core_init),
1306         X86_MATCH_VFM(INTEL_ICELAKE_NNPI,       icl_core_init),
1307         X86_MATCH_VFM(INTEL_COMETLAKE,          cnp_core_init),
1308         X86_MATCH_VFM(INTEL_COMETLAKE_L,        cnp_core_init),
1309         X86_MATCH_VFM(INTEL_TIGERLAKE_L,        tgl_l_core_init),
1310         X86_MATCH_VFM(INTEL_TIGERLAKE,          tgl_core_init),
1311         X86_MATCH_VFM(INTEL_ATOM_TREMONT,       tgl_l_core_init),
1312         X86_MATCH_VFM(INTEL_ATOM_TREMONT_L,     icl_core_init),
1313         X86_MATCH_VFM(INTEL_ROCKETLAKE,         tgl_core_init),
1314         X86_MATCH_VFM(INTEL_ALDERLAKE_L,        tgl_l_core_init),
1315         X86_MATCH_VFM(INTEL_ATOM_GRACEMONT,     tgl_l_core_init),
1316         X86_MATCH_VFM(INTEL_ALDERLAKE,          adl_core_init),
1317         X86_MATCH_VFM(INTEL_RAPTORLAKE_P,       tgl_l_core_init),
1318         X86_MATCH_VFM(INTEL_RAPTORLAKE,         adl_core_init),
1319         X86_MATCH_VFM(INTEL_RAPTORLAKE_S,       adl_core_init),
1320         X86_MATCH_VFM(INTEL_METEORLAKE_L,       mtl_core_init),
1321         X86_MATCH_VFM(INTEL_ARROWLAKE,          arl_core_init),
1322         X86_MATCH_VFM(INTEL_LUNARLAKE_M,        lnl_core_init),
1323         {}
1324 };
1325
1326 MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
1327
1328 static const struct pci_device_id pmc_pci_ids[] = {
1329         { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID) },
1330         { }
1331 };
1332
1333 /*
1334  * This quirk can be used on those platforms where
1335  * the platform BIOS enforces 24Mhz crystal to shutdown
1336  * before PMC can assert SLP_S0#.
1337  */
1338 static bool xtal_ignore;
1339 static int quirk_xtal_ignore(const struct dmi_system_id *id)
1340 {
1341         xtal_ignore = true;
1342         return 0;
1343 }
1344
1345 static void pmc_core_xtal_ignore(struct pmc *pmc)
1346 {
1347         u32 value;
1348
1349         value = pmc_core_reg_read(pmc, pmc->map->pm_vric1_offset);
1350         /* 24MHz Crystal Shutdown Qualification Disable */
1351         value |= SPT_PMC_VRIC1_XTALSDQDIS;
1352         /* Low Voltage Mode Enable */
1353         value &= ~SPT_PMC_VRIC1_SLPS0LVEN;
1354         pmc_core_reg_write(pmc, pmc->map->pm_vric1_offset, value);
1355 }
1356
1357 static const struct dmi_system_id pmc_core_dmi_table[]  = {
1358         {
1359         .callback = quirk_xtal_ignore,
1360         .ident = "HP Elite x2 1013 G3",
1361         .matches = {
1362                 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1363                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Elite x2 1013 G3"),
1364                 },
1365         },
1366         {}
1367 };
1368
1369 static void pmc_core_do_dmi_quirks(struct pmc *pmc)
1370 {
1371         dmi_check_system(pmc_core_dmi_table);
1372
1373         if (xtal_ignore)
1374                 pmc_core_xtal_ignore(pmc);
1375 }
1376
1377 static void pmc_core_clean_structure(struct platform_device *pdev)
1378 {
1379         struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
1380         unsigned int i;
1381
1382         for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) {
1383                 struct pmc *pmc = pmcdev->pmcs[i];
1384
1385                 if (pmc)
1386                         iounmap(pmc->regbase);
1387         }
1388
1389         if (pmcdev->ssram_pcidev) {
1390                 pci_dev_put(pmcdev->ssram_pcidev);
1391                 pci_disable_device(pmcdev->ssram_pcidev);
1392         }
1393
1394         if (pmcdev->punit_ep)
1395                 pmt_telem_unregister_endpoint(pmcdev->punit_ep);
1396
1397         platform_set_drvdata(pdev, NULL);
1398         mutex_destroy(&pmcdev->lock);
1399 }
1400
1401 static int pmc_core_probe(struct platform_device *pdev)
1402 {
1403         static bool device_initialized;
1404         struct pmc_dev *pmcdev;
1405         const struct x86_cpu_id *cpu_id;
1406         int (*core_init)(struct pmc_dev *pmcdev);
1407         struct pmc *primary_pmc;
1408         int ret;
1409
1410         if (device_initialized)
1411                 return -ENODEV;
1412
1413         pmcdev = devm_kzalloc(&pdev->dev, sizeof(*pmcdev), GFP_KERNEL);
1414         if (!pmcdev)
1415                 return -ENOMEM;
1416
1417         pmcdev->crystal_freq = pmc_core_get_crystal_freq();
1418
1419         platform_set_drvdata(pdev, pmcdev);
1420         pmcdev->pdev = pdev;
1421
1422         cpu_id = x86_match_cpu(intel_pmc_core_ids);
1423         if (!cpu_id)
1424                 return -ENODEV;
1425
1426         core_init = (int (*)(struct pmc_dev *))cpu_id->driver_data;
1427
1428         /* Primary PMC */
1429         primary_pmc = devm_kzalloc(&pdev->dev, sizeof(*primary_pmc), GFP_KERNEL);
1430         if (!primary_pmc)
1431                 return -ENOMEM;
1432         pmcdev->pmcs[PMC_IDX_MAIN] = primary_pmc;
1433
1434         /* The last element in msr_map is empty */
1435         pmcdev->num_of_pkgc = ARRAY_SIZE(msr_map) - 1;
1436         pmcdev->pkgc_res_cnt = devm_kcalloc(&pdev->dev,
1437                                             pmcdev->num_of_pkgc,
1438                                             sizeof(*pmcdev->pkgc_res_cnt),
1439                                             GFP_KERNEL);
1440         if (!pmcdev->pkgc_res_cnt)
1441                 return -ENOMEM;
1442
1443         /*
1444          * Coffee Lake has CPU ID of Kaby Lake and Cannon Lake PCH. So here
1445          * Sunrisepoint PCH regmap can't be used. Use Cannon Lake PCH regmap
1446          * in this case.
1447          */
1448         if (core_init == spt_core_init && !pci_dev_present(pmc_pci_ids))
1449                 core_init = cnp_core_init;
1450
1451         mutex_init(&pmcdev->lock);
1452         ret = core_init(pmcdev);
1453         if (ret) {
1454                 pmc_core_clean_structure(pdev);
1455                 return ret;
1456         }
1457
1458         pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit(primary_pmc);
1459         pmc_core_do_dmi_quirks(primary_pmc);
1460
1461         pmc_core_dbgfs_register(pmcdev);
1462         pm_report_max_hw_sleep(FIELD_MAX(SLP_S0_RES_COUNTER_MASK) *
1463                                pmc_core_adjust_slp_s0_step(primary_pmc, 1));
1464
1465         device_initialized = true;
1466         dev_info(&pdev->dev, " initialized\n");
1467
1468         return 0;
1469 }
1470
1471 static void pmc_core_remove(struct platform_device *pdev)
1472 {
1473         struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
1474         pmc_core_dbgfs_unregister(pmcdev);
1475         pmc_core_clean_structure(pdev);
1476 }
1477
1478 static bool warn_on_s0ix_failures;
1479 module_param(warn_on_s0ix_failures, bool, 0644);
1480 MODULE_PARM_DESC(warn_on_s0ix_failures, "Check and warn for S0ix failures");
1481
1482 static __maybe_unused int pmc_core_suspend(struct device *dev)
1483 {
1484         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
1485         struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
1486         unsigned int i;
1487
1488         if (pmcdev->suspend)
1489                 pmcdev->suspend(pmcdev);
1490
1491         /* Check if the syspend will actually use S0ix */
1492         if (pm_suspend_via_firmware())
1493                 return 0;
1494
1495         /* Save PKGC residency for checking later */
1496         for (i = 0; i < pmcdev->num_of_pkgc; i++) {
1497                 if (rdmsrl_safe(msr_map[i].bit_mask, &pmcdev->pkgc_res_cnt[i]))
1498                         return -EIO;
1499         }
1500
1501         /* Save S0ix residency for checking later */
1502         if (pmc_core_dev_state_get(pmc, &pmcdev->s0ix_counter))
1503                 return -EIO;
1504
1505         return 0;
1506 }
1507
1508 static inline bool pmc_core_is_deepest_pkgc_failed(struct pmc_dev *pmcdev)
1509 {
1510         u32 deepest_pkgc_msr = msr_map[pmcdev->num_of_pkgc - 1].bit_mask;
1511         u64 deepest_pkgc_residency;
1512
1513         if (rdmsrl_safe(deepest_pkgc_msr, &deepest_pkgc_residency))
1514                 return false;
1515
1516         if (deepest_pkgc_residency == pmcdev->pkgc_res_cnt[pmcdev->num_of_pkgc - 1])
1517                 return true;
1518
1519         return false;
1520 }
1521
1522 static inline bool pmc_core_is_s0ix_failed(struct pmc_dev *pmcdev)
1523 {
1524         u64 s0ix_counter;
1525
1526         if (pmc_core_dev_state_get(pmcdev->pmcs[PMC_IDX_MAIN], &s0ix_counter))
1527                 return false;
1528
1529         pm_report_hw_sleep_time((u32)(s0ix_counter - pmcdev->s0ix_counter));
1530
1531         if (s0ix_counter == pmcdev->s0ix_counter)
1532                 return true;
1533
1534         return false;
1535 }
1536
1537 int pmc_core_resume_common(struct pmc_dev *pmcdev)
1538 {
1539         struct device *dev = &pmcdev->pdev->dev;
1540         struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
1541         const struct pmc_bit_map **maps = pmc->map->lpm_sts;
1542         int offset = pmc->map->lpm_status_offset;
1543         unsigned int i;
1544
1545         /* Check if the syspend used S0ix */
1546         if (pm_suspend_via_firmware())
1547                 return 0;
1548
1549         if (!pmc_core_is_s0ix_failed(pmcdev))
1550                 return 0;
1551
1552         if (!warn_on_s0ix_failures)
1553                 return 0;
1554
1555         if (pmc_core_is_deepest_pkgc_failed(pmcdev)) {
1556                 /* S0ix failed because of deepest PKGC entry failure */
1557                 dev_info(dev, "CPU did not enter %s!!! (%s cnt=0x%llx)\n",
1558                          msr_map[pmcdev->num_of_pkgc - 1].name,
1559                          msr_map[pmcdev->num_of_pkgc - 1].name,
1560                          pmcdev->pkgc_res_cnt[pmcdev->num_of_pkgc - 1]);
1561
1562                 for (i = 0; i < pmcdev->num_of_pkgc; i++) {
1563                         u64 pc_cnt;
1564
1565                         if (!rdmsrl_safe(msr_map[i].bit_mask, &pc_cnt)) {
1566                                 dev_info(dev, "Prev %s cnt = 0x%llx, Current %s cnt = 0x%llx\n",
1567                                          msr_map[i].name, pmcdev->pkgc_res_cnt[i],
1568                                          msr_map[i].name, pc_cnt);
1569                         }
1570                 }
1571                 return 0;
1572         }
1573
1574         /* The real interesting case - S0ix failed - lets ask PMC why. */
1575         dev_warn(dev, "CPU did not enter SLP_S0!!! (S0ix cnt=%llu)\n",
1576                  pmcdev->s0ix_counter);
1577
1578         if (pmc->map->slps0_dbg_maps)
1579                 pmc_core_slps0_display(pmc, dev, NULL);
1580
1581         for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) {
1582                 struct pmc *pmc = pmcdev->pmcs[i];
1583
1584                 if (!pmc)
1585                         continue;
1586                 if (pmc->map->lpm_sts)
1587                         pmc_core_lpm_display(pmc, dev, NULL, offset, i, "STATUS", maps);
1588         }
1589
1590         return 0;
1591 }
1592
1593 static __maybe_unused int pmc_core_resume(struct device *dev)
1594 {
1595         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
1596
1597         if (pmcdev->resume)
1598                 return pmcdev->resume(pmcdev);
1599
1600         return pmc_core_resume_common(pmcdev);
1601 }
1602
1603 static const struct dev_pm_ops pmc_core_pm_ops = {
1604         SET_LATE_SYSTEM_SLEEP_PM_OPS(pmc_core_suspend, pmc_core_resume)
1605 };
1606
1607 static const struct acpi_device_id pmc_core_acpi_ids[] = {
1608         {"INT33A1", 0}, /* _HID for Intel Power Engine, _CID PNP0D80*/
1609         { }
1610 };
1611 MODULE_DEVICE_TABLE(acpi, pmc_core_acpi_ids);
1612
1613 static struct platform_driver pmc_core_driver = {
1614         .driver = {
1615                 .name = "intel_pmc_core",
1616                 .acpi_match_table = ACPI_PTR(pmc_core_acpi_ids),
1617                 .pm = &pmc_core_pm_ops,
1618                 .dev_groups = pmc_dev_groups,
1619         },
1620         .probe = pmc_core_probe,
1621         .remove_new = pmc_core_remove,
1622 };
1623
1624 module_platform_driver(pmc_core_driver);
1625
1626 MODULE_LICENSE("GPL v2");
1627 MODULE_DESCRIPTION("Intel PMC Core Driver");