drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/string.h>
  27 #include <linux/acpi.h>
  28 #include <linux/i2c.h>
  29
  30 #include <drm/drm_atomic.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/amdgpu_drm.h>
  33 #include <drm/drm_edid.h>
  34
  35 #include "dm_services.h"
  36 #include "amdgpu.h"
  37 #include "dc.h"
  38 #include "amdgpu_dm.h"
  39 #include "amdgpu_dm_irq.h"
  40 #include "amdgpu_dm_mst_types.h"
  41 #include "dpcd_defs.h"
  42 #include "dc/inc/core_types.h"
  43
  44 #include "dm_helpers.h"
  45 #include "ddc_service_types.h"
  46
  47 static u32 edid_extract_panel_id(struct edid *edid)
  48 {
  49         return (u32)edid->mfg_id[0] << 24   |
  50                (u32)edid->mfg_id[1] << 16   |
  51                (u32)EDID_PRODUCT_ID(edid);
  52 }
  53
  54 static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps)
  55 {
  56         uint32_t panel_id = edid_extract_panel_id(edid);
  57
  58         switch (panel_id) {
  59         /* Workaround for some monitors which does not work well with FAMS */
  60         case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E):
  61         case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053):
  62         case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC):
  63                 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id);
  64                 edid_caps->panel_patch.disable_fams = true;
  65                 break;
  66         default:
  67                 return;
  68         }
  69 }
  70
  71 /**
  72  * dm_helpers_parse_edid_caps() - Parse edid caps
  73  *
  74  * @link: current detected link
  75  * @edid:       [in] pointer to edid
  76  * @edid_caps:  [in] pointer to edid caps
  77  *
  78  * Return: void
  79  */
  80 enum dc_edid_status dm_helpers_parse_edid_caps(
  81                 struct dc_link *link,
  82                 const struct dc_edid *edid,
  83                 struct dc_edid_caps *edid_caps)
  84 {
  85         struct amdgpu_dm_connector *aconnector = link->priv;
  86         struct drm_connector *connector = &aconnector->base;
  87         struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL;
  88         struct cea_sad *sads;
  89         int sad_count = -1;
  90         int sadb_count = -1;
  91         int i = 0;
  92         uint8_t *sadb = NULL;
  93
  94         enum dc_edid_status result = EDID_OK;
  95
  96         if (!edid_caps || !edid)
  97                 return EDID_BAD_INPUT;
  98
  99         if (!drm_edid_is_valid(edid_buf))
 100                 result = EDID_BAD_CHECKSUM;
 101
 102         edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
 103                                         ((uint16_t) edid_buf->mfg_id[1])<<8;
 104         edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
 105                                         ((uint16_t) edid_buf->prod_code[1])<<8;
 106         edid_caps->serial_number = edid_buf->serial;
 107         edid_caps->manufacture_week = edid_buf->mfg_week;
 108         edid_caps->manufacture_year = edid_buf->mfg_year;
 109
 110         drm_edid_get_monitor_name(edid_buf,
 111                                   edid_caps->display_name,
 112                                   AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
 113
 114         edid_caps->edid_hdmi = connector->display_info.is_hdmi;
 115
 116         sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
 117         if (sad_count <= 0)
 118                 return result;
 119
 120         edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT);
 121         for (i = 0; i < edid_caps->audio_mode_count; ++i) {
 122                 struct cea_sad *sad = &sads[i];
 123
 124                 edid_caps->audio_modes[i].format_code = sad->format;
 125                 edid_caps->audio_modes[i].channel_count = sad->channels + 1;
 126                 edid_caps->audio_modes[i].sample_rate = sad->freq;
 127                 edid_caps->audio_modes[i].sample_size = sad->byte2;
 128         }
 129
 130         sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
 131
 132         if (sadb_count < 0) {
 133                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
 134                 sadb_count = 0;
 135         }
 136
 137         if (sadb_count)
 138                 edid_caps->speaker_flags = sadb[0];
 139         else
 140                 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
 141
 142         apply_edid_quirks(edid_buf, edid_caps);
 143
 144         kfree(sads);
 145         kfree(sadb);
 146
 147         return result;
 148 }
 149
 150 static void
 151 fill_dc_mst_payload_table_from_drm(struct dc_link *link,
 152                                    bool enable,
 153                                    struct drm_dp_mst_atomic_payload *target_payload,
 154                                    struct dc_dp_mst_stream_allocation_table *table)
 155 {
 156         struct dc_dp_mst_stream_allocation_table new_table = { 0 };
 157         struct dc_dp_mst_stream_allocation *sa;
 158         struct link_mst_stream_allocation_table copy_of_link_table =
 159                                                                                 link->mst_stream_alloc_table;
 160
 161         int i;
 162         int current_hw_table_stream_cnt = copy_of_link_table.stream_count;
 163         struct link_mst_stream_allocation *dc_alloc;
 164
 165         /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/
 166         if (enable) {
 167                 dc_alloc =
 168                 &copy_of_link_table.stream_allocations[current_hw_table_stream_cnt];
 169                 dc_alloc->vcp_id = target_payload->vcpi;
 170                 dc_alloc->slot_count = target_payload->time_slots;
 171         } else {
 172                 for (i = 0; i < copy_of_link_table.stream_count; i++) {
 173                         dc_alloc =
 174                         &copy_of_link_table.stream_allocations[i];
 175
 176                         if (dc_alloc->vcp_id == target_payload->vcpi) {
 177                                 dc_alloc->vcp_id = 0;
 178                                 dc_alloc->slot_count = 0;
 179                                 break;
 180                         }
 181                 }
 182                 ASSERT(i != copy_of_link_table.stream_count);
 183         }
 184
 185         /* Fill payload info*/
 186         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
 187                 dc_alloc =
 188                         &copy_of_link_table.stream_allocations[i];
 189                 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) {
 190                         sa = &new_table.stream_allocations[new_table.stream_count];
 191                         sa->slot_count = dc_alloc->slot_count;
 192                         sa->vcp_id = dc_alloc->vcp_id;
 193                         new_table.stream_count++;
 194                 }
 195         }
 196
 197         /* Overwrite the old table */
 198         *table = new_table;
 199 }
 200
 201 void dm_helpers_dp_update_branch_info(
 202         struct dc_context *ctx,
 203         const struct dc_link *link)
 204 {}
 205
 206 static void dm_helpers_construct_old_payload(
 207                         struct dc_link *link,
 208                         int pbn_per_slot,
 209                         struct drm_dp_mst_atomic_payload *new_payload,
 210                         struct drm_dp_mst_atomic_payload *old_payload)
 211 {
 212         struct link_mst_stream_allocation_table current_link_table =
 213                                                                         link->mst_stream_alloc_table;
 214         struct link_mst_stream_allocation *dc_alloc;
 215         int i;
 216
 217         *old_payload = *new_payload;
 218
 219         /* Set correct time_slots/PBN of old payload.
 220          * other fields (delete & dsc_enabled) in
 221          * struct drm_dp_mst_atomic_payload are don't care fields
 222          * while calling drm_dp_remove_payload_part2()
 223          */
 224         for (i = 0; i < current_link_table.stream_count; i++) {
 225                 dc_alloc =
 226                         &current_link_table.stream_allocations[i];
 227
 228                 if (dc_alloc->vcp_id == new_payload->vcpi) {
 229                         old_payload->time_slots = dc_alloc->slot_count;
 230                         old_payload->pbn = dc_alloc->slot_count * pbn_per_slot;
 231                         break;
 232                 }
 233         }
 234
 235         /* make sure there is an old payload*/
 236         ASSERT(i != current_link_table.stream_count);
 237
 238 }
 239
 240 /*
 241  * Writes payload allocation table in immediate downstream device.
 242  */
 243 bool dm_helpers_dp_mst_write_payload_allocation_table(
 244                 struct dc_context *ctx,
 245                 const struct dc_stream_state *stream,
 246                 struct dc_dp_mst_stream_allocation_table *proposed_table,
 247                 bool enable)
 248 {
 249         struct amdgpu_dm_connector *aconnector;
 250         struct drm_dp_mst_topology_state *mst_state;
 251         struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload;
 252         struct drm_dp_mst_topology_mgr *mst_mgr;
 253
 254         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 255         /* Accessing the connector state is required for vcpi_slots allocation
 256          * and directly relies on behaviour in commit check
 257          * that blocks before commit guaranteeing that the state
 258          * is not gonna be swapped while still in use in commit tail
 259          */
 260
 261         if (!aconnector || !aconnector->mst_root)
 262                 return false;
 263
 264         mst_mgr = &aconnector->mst_root->mst_mgr;
 265         mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 266         new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 267
 268         if (enable) {
 269                 target_payload = new_payload;
 270
 271                 /* It's OK for this to fail */
 272                 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload);
 273         } else {
 274                 /* construct old payload by VCPI*/
 275                 dm_helpers_construct_old_payload(stream->link, mst_state->pbn_div,
 276                                                 new_payload, &old_payload);
 277                 target_payload = &old_payload;
 278
 279                 drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload);
 280         }
 281
 282         /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
 283          * AUX message. The sequence is slot 1-63 allocated sequence for each
 284          * stream. AMD ASIC stream slot allocation should follow the same
 285          * sequence. copy DRM MST allocation to dc
 286          */
 287         fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table);
 288
 289         return true;
 290 }
 291
 292 /*
 293  * poll pending down reply
 294  */
 295 void dm_helpers_dp_mst_poll_pending_down_reply(
 296         struct dc_context *ctx,
 297         const struct dc_link *link)
 298 {}
 299
 300 /*
 301  * Clear payload allocation table before enable MST DP link.
 302  */
 303 void dm_helpers_dp_mst_clear_payload_allocation_table(
 304         struct dc_context *ctx,
 305         const struct dc_link *link)
 306 {}
 307
 308 /*
 309  * Polls for ACT (allocation change trigger) handled and sends
 310  * ALLOCATE_PAYLOAD message.
 311  */
 312 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
 313                 struct dc_context *ctx,
 314                 const struct dc_stream_state *stream)
 315 {
 316         struct amdgpu_dm_connector *aconnector;
 317         struct drm_dp_mst_topology_mgr *mst_mgr;
 318         int ret;
 319
 320         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 321
 322         if (!aconnector || !aconnector->mst_root)
 323                 return ACT_FAILED;
 324
 325         mst_mgr = &aconnector->mst_root->mst_mgr;
 326
 327         if (!mst_mgr->mst_state)
 328                 return ACT_FAILED;
 329
 330         ret = drm_dp_check_act_status(mst_mgr);
 331
 332         if (ret)
 333                 return ACT_FAILED;
 334
 335         return ACT_SUCCESS;
 336 }
 337
 338 bool dm_helpers_dp_mst_send_payload_allocation(
 339                 struct dc_context *ctx,
 340                 const struct dc_stream_state *stream,
 341                 bool enable)
 342 {
 343         struct amdgpu_dm_connector *aconnector;
 344         struct drm_dp_mst_topology_state *mst_state;
 345         struct drm_dp_mst_topology_mgr *mst_mgr;
 346         struct drm_dp_mst_atomic_payload *new_payload, *old_payload;
 347         enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;
 348         enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 349         int ret = 0;
 350
 351         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 352
 353         if (!aconnector || !aconnector->mst_root)
 354                 return false;
 355
 356         mst_mgr = &aconnector->mst_root->mst_mgr;
 357         mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 358
 359         new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 360
 361         if (!enable) {
 362                 set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 363                 clr_flag = MST_ALLOCATE_NEW_PAYLOAD;
 364         }
 365
 366         if (enable) {
 367                 ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, new_payload);
 368         } else {
 369                 dm_helpers_construct_old_payload(stream->link, mst_state->pbn_div,
 370                                                  new_payload, old_payload);
 371                 drm_dp_remove_payload_part2(mst_mgr, mst_state, old_payload, new_payload);
 372         }
 373
 374         if (ret) {
 375                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 376                         set_flag, false);
 377         } else {
 378                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 379                         set_flag, true);
 380                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 381                         clr_flag, false);
 382         }
 383
 384         return true;
 385 }
 386
 387 void dm_dtn_log_begin(struct dc_context *ctx,
 388         struct dc_log_buffer_ctx *log_ctx)
 389 {
 390         static const char msg[] = "[dtn begin]\n";
 391
 392         if (!log_ctx) {
 393                 pr_info("%s", msg);
 394                 return;
 395         }
 396
 397         dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 398 }
 399
 400 __printf(3, 4)
 401 void dm_dtn_log_append_v(struct dc_context *ctx,
 402         struct dc_log_buffer_ctx *log_ctx,
 403         const char *msg, ...)
 404 {
 405         va_list args;
 406         size_t total;
 407         int n;
 408
 409         if (!log_ctx) {
 410                 /* No context, redirect to dmesg. */
 411                 struct va_format vaf;
 412
 413                 vaf.fmt = msg;
 414                 vaf.va = &args;
 415
 416                 va_start(args, msg);
 417                 pr_info("%pV", &vaf);
 418                 va_end(args);
 419
 420                 return;
 421         }
 422
 423         /* Measure the output. */
 424         va_start(args, msg);
 425         n = vsnprintf(NULL, 0, msg, args);
 426         va_end(args);
 427
 428         if (n <= 0)
 429                 return;
 430
 431         /* Reallocate the string buffer as needed. */
 432         total = log_ctx->pos + n + 1;
 433
 434         if (total > log_ctx->size) {
 435                 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL);
 436
 437                 if (buf) {
 438                         memcpy(buf, log_ctx->buf, log_ctx->pos);
 439                         kfree(log_ctx->buf);
 440
 441                         log_ctx->buf = buf;
 442                         log_ctx->size = total;
 443                 }
 444         }
 445
 446         if (!log_ctx->buf)
 447                 return;
 448
 449         /* Write the formatted string to the log buffer. */
 450         va_start(args, msg);
 451         n = vscnprintf(
 452                 log_ctx->buf + log_ctx->pos,
 453                 log_ctx->size - log_ctx->pos,
 454                 msg,
 455                 args);
 456         va_end(args);
 457
 458         if (n > 0)
 459                 log_ctx->pos += n;
 460 }
 461
 462 void dm_dtn_log_end(struct dc_context *ctx,
 463         struct dc_log_buffer_ctx *log_ctx)
 464 {
 465         static const char msg[] = "[dtn end]\n";
 466
 467         if (!log_ctx) {
 468                 pr_info("%s", msg);
 469                 return;
 470         }
 471
 472         dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 473 }
 474
 475 bool dm_helpers_dp_mst_start_top_mgr(
 476                 struct dc_context *ctx,
 477                 const struct dc_link *link,
 478                 bool boot)
 479 {
 480         struct amdgpu_dm_connector *aconnector = link->priv;
 481         int ret;
 482
 483         if (!aconnector) {
 484                 DRM_ERROR("Failed to find connector for link!");
 485                 return false;
 486         }
 487
 488         if (boot) {
 489                 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
 490                                         aconnector, aconnector->base.base.id);
 491                 return true;
 492         }
 493
 494         DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 495                         aconnector, aconnector->base.base.id);
 496
 497         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 498         if (ret < 0) {
 499                 DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
 500                 return false;
 501         }
 502
 503         DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0],
 504                 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK);
 505
 506         return true;
 507 }
 508
 509 bool dm_helpers_dp_mst_stop_top_mgr(
 510                 struct dc_context *ctx,
 511                 struct dc_link *link)
 512 {
 513         struct amdgpu_dm_connector *aconnector = link->priv;
 514
 515         if (!aconnector) {
 516                 DRM_ERROR("Failed to find connector for link!");
 517                 return false;
 518         }
 519
 520         DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
 521                         aconnector, aconnector->base.base.id);
 522
 523         if (aconnector->mst_mgr.mst_state == true) {
 524                 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
 525                 link->cur_link_settings.lane_count = 0;
 526         }
 527
 528         return false;
 529 }
 530
 531 bool dm_helpers_dp_read_dpcd(
 532                 struct dc_context *ctx,
 533                 const struct dc_link *link,
 534                 uint32_t address,
 535                 uint8_t *data,
 536                 uint32_t size)
 537 {
 538
 539         struct amdgpu_dm_connector *aconnector = link->priv;
 540
 541         if (!aconnector) {
 542                 DC_LOG_DC("Failed to find connector for link!\n");
 543                 return false;
 544         }
 545
 546         return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data,
 547                                 size) == size;
 548 }
 549
 550 bool dm_helpers_dp_write_dpcd(
 551                 struct dc_context *ctx,
 552                 const struct dc_link *link,
 553                 uint32_t address,
 554                 const uint8_t *data,
 555                 uint32_t size)
 556 {
 557         struct amdgpu_dm_connector *aconnector = link->priv;
 558
 559         if (!aconnector) {
 560                 DRM_ERROR("Failed to find connector for link!");
 561                 return false;
 562         }
 563
 564         return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
 565                         address, (uint8_t *)data, size) > 0;
 566 }
 567
 568 bool dm_helpers_submit_i2c(
 569                 struct dc_context *ctx,
 570                 const struct dc_link *link,
 571                 struct i2c_command *cmd)
 572 {
 573         struct amdgpu_dm_connector *aconnector = link->priv;
 574         struct i2c_msg *msgs;
 575         int i = 0;
 576         int num = cmd->number_of_payloads;
 577         bool result;
 578
 579         if (!aconnector) {
 580                 DRM_ERROR("Failed to find connector for link!");
 581                 return false;
 582         }
 583
 584         msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);
 585
 586         if (!msgs)
 587                 return false;
 588
 589         for (i = 0; i < num; i++) {
 590                 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
 591                 msgs[i].addr = cmd->payloads[i].address;
 592                 msgs[i].len = cmd->payloads[i].length;
 593                 msgs[i].buf = cmd->payloads[i].data;
 594         }
 595
 596         result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
 597
 598         kfree(msgs);
 599
 600         return result;
 601 }
 602
 603 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,
 604                 bool is_write_cmd,
 605                 unsigned char cmd,
 606                 unsigned int length,
 607                 unsigned int offset,
 608                 unsigned char *data)
 609 {
 610         bool success = false;
 611         unsigned char rc_data[16] = {0};
 612         unsigned char rc_offset[4] = {0};
 613         unsigned char rc_length[2] = {0};
 614         unsigned char rc_cmd = 0;
 615         unsigned char rc_result = 0xFF;
 616         unsigned char i = 0;
 617         int ret;
 618
 619         if (is_write_cmd) {
 620                 // write rc data
 621                 memmove(rc_data, data, length);
 622                 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data));
 623         }
 624
 625         // write rc offset
 626         rc_offset[0] = (unsigned char) offset & 0xFF;
 627         rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF;
 628         rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF;
 629         rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF;
 630         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset));
 631
 632         // write rc length
 633         rc_length[0] = (unsigned char) length & 0xFF;
 634         rc_length[1] = (unsigned char) (length >> 8) & 0xFF;
 635         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length));
 636
 637         // write rc cmd
 638         rc_cmd = cmd | 0x80;
 639         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 640
 641         if (ret < 0) {
 642                 DRM_ERROR("%s: write cmd ..., err = %d\n",  __func__, ret);
 643                 return false;
 644         }
 645
 646         // poll until active is 0
 647         for (i = 0; i < 10; i++) {
 648                 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 649                 if (rc_cmd == cmd)
 650                         // active is 0
 651                         break;
 652                 msleep(10);
 653         }
 654
 655         // read rc result
 656         drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result));
 657         success = (rc_result == 0);
 658
 659         if (success && !is_write_cmd) {
 660                 // read rc data
 661                 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length);
 662         }
 663
 664         DC_LOG_DC("%s: success = %d\n", __func__, success);
 665
 666         return success;
 667 }
 668
 669 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux)
 670 {
 671         unsigned char data[16] = {0};
 672
 673         DC_LOG_DC("Start %s\n", __func__);
 674
 675         // Step 2
 676         data[0] = 'P';
 677         data[1] = 'R';
 678         data[2] = 'I';
 679         data[3] = 'U';
 680         data[4] = 'S';
 681
 682         if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data))
 683                 return;
 684
 685         // Step 3 and 4
 686         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 687                 return;
 688
 689         data[0] &= (~(1 << 1)); // set bit 1 to 0
 690         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 691                 return;
 692
 693         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 694                 return;
 695
 696         data[0] &= (~(1 << 1)); // set bit 1 to 0
 697         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data))
 698                 return;
 699
 700         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 701                 return;
 702
 703         data[0] &= (~(1 << 1)); // set bit 1 to 0
 704         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 705                 return;
 706
 707         // Step 3 and 5
 708         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 709                 return;
 710
 711         data[0] |= (1 << 1); // set bit 1 to 1
 712         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 713                 return;
 714
 715         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 716                 return;
 717
 718         data[0] |= (1 << 1); // set bit 1 to 1
 719
 720         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 721                 return;
 722
 723         data[0] |= (1 << 1); // set bit 1 to 1
 724         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 725                 return;
 726
 727         // Step 6
 728         if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL))
 729                 return;
 730
 731         DC_LOG_DC("Done %s\n", __func__);
 732 }
 733
 734 /* MST Dock */
 735 static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
 736
 737 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 738                 struct drm_dp_aux *aux,
 739                 const struct dc_stream_state *stream,
 740                 bool enable)
 741 {
 742         uint8_t ret = 0;
 743
 744         DC_LOG_DC("Configure DSC to non-virtual dpcd synaptics\n");
 745
 746         if (enable) {
 747                 /* When DSC is enabled on previous boot and reboot with the hub,
 748                  * there is a chance that Synaptics hub gets stuck during reboot sequence.
 749                  * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream
 750                  */
 751                 if (!stream->link->link_status.link_active &&
 752                         memcmp(stream->link->dpcd_caps.branch_dev_name,
 753                                 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0)
 754                         apply_synaptics_fifo_reset_wa(aux);
 755
 756                 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 757                 DRM_INFO("Send DSC enable to synaptics\n");
 758
 759         } else {
 760                 /* Synaptics hub not support virtual dpcd,
 761                  * external monitor occur garbage while disable DSC,
 762                  * Disable DSC only when entire link status turn to false,
 763                  */
 764                 if (!stream->link->link_status.link_active) {
 765                         ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 766                         DRM_INFO("Send DSC disable to synaptics\n");
 767                 }
 768         }
 769
 770         return ret;
 771 }
 772
 773 bool dm_helpers_dp_write_dsc_enable(
 774                 struct dc_context *ctx,
 775                 const struct dc_stream_state *stream,
 776                 bool enable)
 777 {
 778         static const uint8_t DSC_DISABLE;
 779         static const uint8_t DSC_DECODING = 0x01;
 780         static const uint8_t DSC_PASSTHROUGH = 0x02;
 781
 782         struct amdgpu_dm_connector *aconnector;
 783         struct drm_dp_mst_port *port;
 784         uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE;
 785         uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;
 786         uint8_t ret = 0;
 787
 788         if (!stream)
 789                 return false;
 790
 791         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 792                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 793
 794                 if (!aconnector->dsc_aux)
 795                         return false;
 796
 797                 // apply w/a to synaptics
 798                 if (needs_dsc_aux_workaround(aconnector->dc_link) &&
 799                     (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3)
 800                         return write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 801                                 aconnector->dsc_aux, stream, enable_dsc);
 802
 803                 port = aconnector->mst_output_port;
 804
 805                 if (enable) {
 806                         if (port->passthrough_aux) {
 807                                 ret = drm_dp_dpcd_write(port->passthrough_aux,
 808                                                         DP_DSC_ENABLE,
 809                                                         &enable_passthrough, 1);
 810                                 DC_LOG_DC("Sent DSC pass-through enable to virtual dpcd port, ret = %u\n",
 811                                           ret);
 812                         }
 813
 814                         ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 815                                                 DP_DSC_ENABLE, &enable_dsc, 1);
 816                         DC_LOG_DC("Sent DSC decoding enable to %s port, ret = %u\n",
 817                                   (port->passthrough_aux) ? "remote RX" :
 818                                   "virtual dpcd",
 819                                   ret);
 820                 } else {
 821                         ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 822                                                 DP_DSC_ENABLE, &enable_dsc, 1);
 823                         DC_LOG_DC("Sent DSC decoding disable to %s port, ret = %u\n",
 824                                   (port->passthrough_aux) ? "remote RX" :
 825                                   "virtual dpcd",
 826                                   ret);
 827
 828                         if (port->passthrough_aux) {
 829                                 ret = drm_dp_dpcd_write(port->passthrough_aux,
 830                                                         DP_DSC_ENABLE,
 831                                                         &enable_passthrough, 1);
 832                                 DC_LOG_DC("Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",
 833                                           ret);
 834                         }
 835                 }
 836         }
 837
 838         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) {
 839                 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
 840                         ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 841                         DC_LOG_DC("Send DSC %s to SST RX\n", enable_dsc ? "enable" : "disable");
 842                 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
 843                         ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 844                         DC_LOG_DC("Send DSC %s to DP-HDMI PCON\n", enable_dsc ? "enable" : "disable");
 845                 }
 846         }
 847
 848         return ret;
 849 }
 850
 851 bool dm_helpers_is_dp_sink_present(struct dc_link *link)
 852 {
 853         bool dp_sink_present;
 854         struct amdgpu_dm_connector *aconnector = link->priv;
 855
 856         if (!aconnector) {
 857                 BUG_ON("Failed to find connector for link!");
 858                 return true;
 859         }
 860
 861         mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
 862         dp_sink_present = dc_link_is_dp_sink_present(link);
 863         mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
 864         return dp_sink_present;
 865 }
 866
 867 enum dc_edid_status dm_helpers_read_local_edid(
 868                 struct dc_context *ctx,
 869                 struct dc_link *link,
 870                 struct dc_sink *sink)
 871 {
 872         struct amdgpu_dm_connector *aconnector = link->priv;
 873         struct drm_connector *connector = &aconnector->base;
 874         struct i2c_adapter *ddc;
 875         int retry = 3;
 876         enum dc_edid_status edid_status;
 877         struct edid *edid;
 878
 879         if (link->aux_mode)
 880                 ddc = &aconnector->dm_dp_aux.aux.ddc;
 881         else
 882                 ddc = &aconnector->i2c->base;
 883
 884         /* some dongles read edid incorrectly the first time,
 885          * do check sum and retry to make sure read correct edid.
 886          */
 887         do {
 888
 889                 edid = drm_get_edid(&aconnector->base, ddc);
 890
 891                 /* DP Compliance Test 4.2.2.6 */
 892                 if (link->aux_mode && connector->edid_corrupt)
 893                         drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum);
 894
 895                 if (!edid && connector->edid_corrupt) {
 896                         connector->edid_corrupt = false;
 897                         return EDID_BAD_CHECKSUM;
 898                 }
 899
 900                 if (!edid)
 901                         return EDID_NO_RESPONSE;
 902
 903                 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
 904                 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
 905
 906                 /* We don't need the original edid anymore */
 907                 kfree(edid);
 908
 909                 edid_status = dm_helpers_parse_edid_caps(
 910                                                 link,
 911                                                 &sink->dc_edid,
 912                                                 &sink->edid_caps);
 913
 914         } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
 915
 916         if (edid_status != EDID_OK)
 917                 DRM_ERROR("EDID err: %d, on connector: %s",
 918                                 edid_status,
 919                                 aconnector->base.name);
 920         if (link->aux_mode) {
 921                 union test_request test_request = {0};
 922                 union test_response test_response = {0};
 923
 924                 dm_helpers_dp_read_dpcd(ctx,
 925                                         link,
 926                                         DP_TEST_REQUEST,
 927                                         &test_request.raw,
 928                                         sizeof(union test_request));
 929
 930                 if (!test_request.bits.EDID_READ)
 931                         return edid_status;
 932
 933                 test_response.bits.EDID_CHECKSUM_WRITE = 1;
 934
 935                 dm_helpers_dp_write_dpcd(ctx,
 936                                         link,
 937                                         DP_TEST_EDID_CHECKSUM,
 938                                         &sink->dc_edid.raw_edid[sink->dc_edid.length-1],
 939                                         1);
 940
 941                 dm_helpers_dp_write_dpcd(ctx,
 942                                         link,
 943                                         DP_TEST_RESPONSE,
 944                                         &test_response.raw,
 945                                         sizeof(test_response));
 946
 947         }
 948
 949         return edid_status;
 950 }
 951 int dm_helper_dmub_aux_transfer_sync(
 952                 struct dc_context *ctx,
 953                 const struct dc_link *link,
 954                 struct aux_payload *payload,
 955                 enum aux_return_code_type *operation_result)
 956 {
 957         return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload,
 958                         operation_result);
 959 }
 960
 961 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,
 962                 const struct dc_link *link,
 963                 struct set_config_cmd_payload *payload,
 964                 enum set_config_status *operation_result)
 965 {
 966         return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload,
 967                         operation_result);
 968 }
 969
 970 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
 971 {
 972         /* TODO: something */
 973 }
 974
 975 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)
 976 {
 977         // TODO:
 978         //amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
 979 }
 980
 981 void dm_helpers_init_panel_settings(
 982         struct dc_context *ctx,
 983         struct dc_panel_config *panel_config,
 984         struct dc_sink *sink)
 985 {
 986         // Extra Panel Power Sequence
 987         panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms;
 988         panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms;
 989         panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off;
 990         panel_config->pps.extra_post_t7_ms = 0;
 991         panel_config->pps.extra_pre_t11_ms = 0;
 992         panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms;
 993         panel_config->pps.extra_post_OUI_ms = 0;
 994         // Feature DSC
 995         panel_config->dsc.disable_dsc_edp = false;
 996         panel_config->dsc.force_dsc_edp_policy = 0;
 997 }
 998
 999 void dm_helpers_override_panel_settings(
1000         struct dc_context *ctx,
1001         struct dc_panel_config *panel_config)
1002 {
1003         // Feature DSC
1004         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1005                 panel_config->dsc.disable_dsc_edp = true;
1006 }
1007
1008 void *dm_helpers_allocate_gpu_mem(
1009                 struct dc_context *ctx,
1010                 enum dc_gpu_mem_alloc_type type,
1011                 size_t size,
1012                 long long *addr)
1013 {
1014         struct amdgpu_device *adev = ctx->driver_context;
1015         struct dal_allocation *da;
1016         u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?
1017                 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM;
1018         int ret;
1019
1020         da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);
1021         if (!da)
1022                 return NULL;
1023
1024         ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
1025                                       domain, &da->bo,
1026                                       &da->gpu_addr, &da->cpu_ptr);
1027
1028         *addr = da->gpu_addr;
1029
1030         if (ret) {
1031                 kfree(da);
1032                 return NULL;
1033         }
1034
1035         /* add da to list in dm */
1036         list_add(&da->list, &adev->dm.da_list);
1037
1038         return da->cpu_ptr;
1039 }
1040
1041 void dm_helpers_free_gpu_mem(
1042                 struct dc_context *ctx,
1043                 enum dc_gpu_mem_alloc_type type,
1044                 void *pvMem)
1045 {
1046         struct amdgpu_device *adev = ctx->driver_context;
1047         struct dal_allocation *da;
1048
1049         /* walk the da list in DM */
1050         list_for_each_entry(da, &adev->dm.da_list, list) {
1051                 if (pvMem == da->cpu_ptr) {
1052                         amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);
1053                         list_del(&da->list);
1054                         kfree(da);
1055                         break;
1056                 }
1057         }
1058 }
1059
1060 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)
1061 {
1062         enum dc_irq_source irq_source;
1063         bool ret;
1064
1065         irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
1066
1067         ret = dc_interrupt_set(ctx->dc, irq_source, enable);
1068
1069         DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n",
1070                          enable ? "en" : "dis", ret);
1071         return ret;
1072 }
1073
1074 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream)
1075 {
1076         /* TODO: virtual DPCD */
1077         struct dc_link *link = stream->link;
1078         union down_spread_ctrl old_downspread;
1079         union down_spread_ctrl new_downspread;
1080
1081         if (link->aux_access_disabled)
1082                 return;
1083
1084         if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1085                                      &old_downspread.raw,
1086                                      sizeof(old_downspread)))
1087                 return;
1088
1089         new_downspread.raw = old_downspread.raw;
1090         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1091                 (stream->ignore_msa_timing_param) ? 1 : 0;
1092
1093         if (new_downspread.raw != old_downspread.raw)
1094                 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1095                                          &new_downspread.raw,
1096                                          sizeof(new_downspread));
1097 }
1098
1099 bool dm_helpers_dp_handle_test_pattern_request(
1100                 struct dc_context *ctx,
1101                 const struct dc_link *link,
1102                 union link_test_pattern dpcd_test_pattern,
1103                 union test_misc dpcd_test_params)
1104 {
1105         enum dp_test_pattern test_pattern;
1106         enum dp_test_pattern_color_space test_pattern_color_space =
1107                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
1108         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
1109         enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED;
1110         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
1111         struct pipe_ctx *pipe_ctx = NULL;
1112         struct amdgpu_dm_connector *aconnector = link->priv;
1113         int i;
1114
1115         for (i = 0; i < MAX_PIPES; i++) {
1116                 if (pipes[i].stream == NULL)
1117                         continue;
1118
1119                 if (pipes[i].stream->link == link && !pipes[i].top_pipe &&
1120                         !pipes[i].prev_odm_pipe) {
1121                         pipe_ctx = &pipes[i];
1122                         break;
1123                 }
1124         }
1125
1126         if (pipe_ctx == NULL)
1127                 return false;
1128
1129         switch (dpcd_test_pattern.bits.PATTERN) {
1130         case LINK_TEST_PATTERN_COLOR_RAMP:
1131                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1132         break;
1133         case LINK_TEST_PATTERN_VERTICAL_BARS:
1134                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1135         break; /* black and white */
1136         case LINK_TEST_PATTERN_COLOR_SQUARES:
1137                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1138                                 TEST_DYN_RANGE_VESA ?
1139                                 DP_TEST_PATTERN_COLOR_SQUARES :
1140                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1141         break;
1142         default:
1143                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1144         break;
1145         }
1146
1147         if (dpcd_test_params.bits.CLR_FORMAT == 0)
1148                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
1149         else
1150                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
1151                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
1152                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
1153
1154         switch (dpcd_test_params.bits.BPC) {
1155         case 0: // 6 bits
1156                 requestColorDepth = COLOR_DEPTH_666;
1157                 break;
1158         case 1: // 8 bits
1159                 requestColorDepth = COLOR_DEPTH_888;
1160                 break;
1161         case 2: // 10 bits
1162                 requestColorDepth = COLOR_DEPTH_101010;
1163                 break;
1164         case 3: // 12 bits
1165                 requestColorDepth = COLOR_DEPTH_121212;
1166                 break;
1167         default:
1168                 break;
1169         }
1170
1171         switch (dpcd_test_params.bits.CLR_FORMAT) {
1172         case 0:
1173                 requestPixelEncoding = PIXEL_ENCODING_RGB;
1174                 break;
1175         case 1:
1176                 requestPixelEncoding = PIXEL_ENCODING_YCBCR422;
1177                 break;
1178         case 2:
1179                 requestPixelEncoding = PIXEL_ENCODING_YCBCR444;
1180                 break;
1181         default:
1182                 requestPixelEncoding = PIXEL_ENCODING_RGB;
1183                 break;
1184         }
1185
1186         if ((requestColorDepth != COLOR_DEPTH_UNDEFINED
1187                 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth)
1188                 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED
1189                 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {
1190                 DC_LOG_DEBUG("%s: original bpc %d pix encoding %d, changing to %d  %d\n",
1191                                 __func__,
1192                                 pipe_ctx->stream->timing.display_color_depth,
1193                                 pipe_ctx->stream->timing.pixel_encoding,
1194                                 requestColorDepth,
1195                                 requestPixelEncoding);
1196                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
1197                 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;
1198
1199                 dc_link_update_dsc_config(pipe_ctx);
1200
1201                 aconnector->timing_changed = true;
1202                 /* store current timing */
1203                 if (aconnector->timing_requested)
1204                         *aconnector->timing_requested = pipe_ctx->stream->timing;
1205                 else
1206                         DC_LOG_ERROR("%s: timing storage failed\n", __func__);
1207
1208         }
1209
1210         dc_link_dp_set_test_pattern(
1211                 (struct dc_link *) link,
1212                 test_pattern,
1213                 test_pattern_color_space,
1214                 NULL,
1215                 NULL,
1216                 0);
1217
1218         return false;
1219 }
1220
1221 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)
1222 {
1223        // TODO
1224 }
1225
1226 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
1227 {
1228         /* TODO: add periodic detection implementation */
1229 }
1230
1231 void dm_helpers_dp_mst_update_branch_bandwidth(
1232                 struct dc_context *ctx,
1233                 struct dc_link *link)
1234 {
1235         // TODO
1236 }
1237
1238 static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id)
1239 {
1240         bool ret_val = false;
1241
1242         switch (branch_dev_id) {
1243         case DP_BRANCH_DEVICE_ID_0060AD:
1244         case DP_BRANCH_DEVICE_ID_00E04C:
1245         case DP_BRANCH_DEVICE_ID_90CC24:
1246                 ret_val = true;
1247                 break;
1248         default:
1249                 break;
1250         }
1251
1252         return ret_val;
1253 }
1254
1255 enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link)
1256 {
1257         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
1258         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
1259
1260         switch (dpcd_caps->dongle_type) {
1261         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
1262                 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true &&
1263                         dpcd_caps->allow_invalid_MSA_timing_param == true &&
1264                         dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id))
1265                         as_type = FREESYNC_TYPE_PCON_IN_WHITELIST;
1266                 break;
1267         default:
1268                 break;
1269         }
1270
1271         return as_type;
1272 }