2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the separate driver.
12 * derived from pxamci.c by Russell King
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/highmem.h>
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/blkdev.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/delay.h>
32 #include <linux/clk.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/dmaengine.h>
36 #include <linux/types.h>
38 #include <linux/of_device.h>
39 #include <linux/of_dma.h>
40 #include <linux/mmc/slot-gpio.h>
44 #include <linux/platform_data/mmc-mxcmmc.h>
46 #include <linux/platform_data/dma-imx.h>
48 #define DRIVER_NAME "mxc-mmc"
49 #define MXCMCI_TIMEOUT_MS 10000
51 #define MMC_REG_STR_STP_CLK 0x00
52 #define MMC_REG_STATUS 0x04
53 #define MMC_REG_CLK_RATE 0x08
54 #define MMC_REG_CMD_DAT_CONT 0x0C
55 #define MMC_REG_RES_TO 0x10
56 #define MMC_REG_READ_TO 0x14
57 #define MMC_REG_BLK_LEN 0x18
58 #define MMC_REG_NOB 0x1C
59 #define MMC_REG_REV_NO 0x20
60 #define MMC_REG_INT_CNTR 0x24
61 #define MMC_REG_CMD 0x28
62 #define MMC_REG_ARG 0x2C
63 #define MMC_REG_RES_FIFO 0x34
64 #define MMC_REG_BUFFER_ACCESS 0x38
66 #define STR_STP_CLK_RESET (1 << 3)
67 #define STR_STP_CLK_START_CLK (1 << 1)
68 #define STR_STP_CLK_STOP_CLK (1 << 0)
70 #define STATUS_CARD_INSERTION (1 << 31)
71 #define STATUS_CARD_REMOVAL (1 << 30)
72 #define STATUS_YBUF_EMPTY (1 << 29)
73 #define STATUS_XBUF_EMPTY (1 << 28)
74 #define STATUS_YBUF_FULL (1 << 27)
75 #define STATUS_XBUF_FULL (1 << 26)
76 #define STATUS_BUF_UND_RUN (1 << 25)
77 #define STATUS_BUF_OVFL (1 << 24)
78 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
79 #define STATUS_END_CMD_RESP (1 << 13)
80 #define STATUS_WRITE_OP_DONE (1 << 12)
81 #define STATUS_DATA_TRANS_DONE (1 << 11)
82 #define STATUS_READ_OP_DONE (1 << 11)
83 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
84 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
85 #define STATUS_BUF_READ_RDY (1 << 7)
86 #define STATUS_BUF_WRITE_RDY (1 << 6)
87 #define STATUS_RESP_CRC_ERR (1 << 5)
88 #define STATUS_CRC_READ_ERR (1 << 3)
89 #define STATUS_CRC_WRITE_ERR (1 << 2)
90 #define STATUS_TIME_OUT_RESP (1 << 1)
91 #define STATUS_TIME_OUT_READ (1 << 0)
92 #define STATUS_ERR_MASK 0x2f
94 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
95 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
96 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
97 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
98 #define CMD_DAT_CONT_INIT (1 << 7)
99 #define CMD_DAT_CONT_WRITE (1 << 4)
100 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
101 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
102 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
103 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
105 #define INT_SDIO_INT_WKP_EN (1 << 18)
106 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
107 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
108 #define INT_CARD_INSERTION_EN (1 << 15)
109 #define INT_CARD_REMOVAL_EN (1 << 14)
110 #define INT_SDIO_IRQ_EN (1 << 13)
111 #define INT_DAT0_EN (1 << 12)
112 #define INT_BUF_READ_EN (1 << 4)
113 #define INT_BUF_WRITE_EN (1 << 3)
114 #define INT_END_CMD_RES_EN (1 << 2)
115 #define INT_WRITE_OP_DONE_EN (1 << 1)
116 #define INT_READ_OP_EN (1 << 0)
125 struct mmc_host *mmc;
127 dma_addr_t phys_base;
129 struct dma_chan *dma;
130 struct dma_async_tx_descriptor *desc;
132 int default_irq_mask;
134 unsigned int power_mode;
135 struct imxmmc_platform_data *pdata;
137 struct mmc_request *req;
138 struct mmc_command *cmd;
139 struct mmc_data *data;
141 unsigned int datasize;
142 unsigned int dma_dir;
152 struct work_struct datawork;
157 struct dma_slave_config dma_slave_config;
158 struct imx_dma_data dma_data;
160 struct timer_list watchdog;
161 enum mxcmci_type devtype;
164 static const struct platform_device_id mxcmci_devtype[] = {
167 .driver_data = IMX21_MMC,
170 .driver_data = IMX31_MMC,
172 .name = "mpc512x-sdhc",
173 .driver_data = MPC512X_MMC,
178 MODULE_DEVICE_TABLE(platform, mxcmci_devtype);
180 static const struct of_device_id mxcmci_of_match[] = {
182 .compatible = "fsl,imx21-mmc",
183 .data = &mxcmci_devtype[IMX21_MMC],
185 .compatible = "fsl,imx31-mmc",
186 .data = &mxcmci_devtype[IMX31_MMC],
188 .compatible = "fsl,mpc5121-sdhc",
189 .data = &mxcmci_devtype[MPC512X_MMC],
194 MODULE_DEVICE_TABLE(of, mxcmci_of_match);
196 static inline int is_imx31_mmc(struct mxcmci_host *host)
198 return host->devtype == IMX31_MMC;
201 static inline int is_mpc512x_mmc(struct mxcmci_host *host)
203 return host->devtype == MPC512X_MMC;
206 static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
208 if (IS_ENABLED(CONFIG_PPC_MPC512x))
209 return ioread32be(host->base + reg);
211 return readl(host->base + reg);
214 static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
216 if (IS_ENABLED(CONFIG_PPC_MPC512x))
217 iowrite32be(val, host->base + reg);
219 writel(val, host->base + reg);
222 static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
224 if (IS_ENABLED(CONFIG_PPC_MPC512x))
225 return ioread32be(host->base + reg);
227 return readw(host->base + reg);
230 static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
232 if (IS_ENABLED(CONFIG_PPC_MPC512x))
233 iowrite32be(val, host->base + reg);
235 writew(val, host->base + reg);
238 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
240 static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
242 if (!IS_ERR(host->mmc->supply.vmmc)) {
243 if (host->power_mode == MMC_POWER_UP)
244 mmc_regulator_set_ocr(host->mmc,
245 host->mmc->supply.vmmc, vdd);
246 else if (host->power_mode == MMC_POWER_OFF)
247 mmc_regulator_set_ocr(host->mmc,
248 host->mmc->supply.vmmc, 0);
251 if (host->pdata && host->pdata->setpower)
252 host->pdata->setpower(mmc_dev(host->mmc), vdd);
255 static inline int mxcmci_use_dma(struct mxcmci_host *host)
260 static void mxcmci_softreset(struct mxcmci_host *host)
264 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
267 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
268 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
269 MMC_REG_STR_STP_CLK);
271 for (i = 0; i < 8; i++)
272 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
274 mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
277 #if IS_ENABLED(CONFIG_PPC_MPC512x)
278 static inline void buffer_swap32(u32 *buf, int len)
282 for (i = 0; i < ((len + 3) / 4); i++) {
288 static void mxcmci_swap_buffers(struct mmc_data *data)
290 struct scatterlist *sg;
293 for_each_sg(data->sg, sg, data->sg_len, i)
294 buffer_swap32(sg_virt(sg), sg->length);
297 static inline void mxcmci_swap_buffers(struct mmc_data *data) {}
300 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
302 unsigned int nob = data->blocks;
303 unsigned int blksz = data->blksz;
304 unsigned int datasize = nob * blksz;
305 struct scatterlist *sg;
306 enum dma_transfer_direction slave_dirn;
310 data->bytes_xfered = 0;
312 mxcmci_writew(host, nob, MMC_REG_NOB);
313 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
314 host->datasize = datasize;
316 if (!mxcmci_use_dma(host))
319 for_each_sg(data->sg, sg, data->sg_len, i) {
320 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
326 if (data->flags & MMC_DATA_READ) {
327 host->dma_dir = DMA_FROM_DEVICE;
328 slave_dirn = DMA_DEV_TO_MEM;
330 host->dma_dir = DMA_TO_DEVICE;
331 slave_dirn = DMA_MEM_TO_DEV;
333 mxcmci_swap_buffers(data);
336 nents = dma_map_sg(host->dma->device->dev, data->sg,
337 data->sg_len, host->dma_dir);
338 if (nents != data->sg_len)
341 host->desc = dmaengine_prep_slave_sg(host->dma,
342 data->sg, data->sg_len, slave_dirn,
343 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
346 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
349 return 0; /* Fall back to PIO */
353 dmaengine_submit(host->desc);
354 dma_async_issue_pending(host->dma);
356 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
361 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
362 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
364 static void mxcmci_dma_callback(void *data)
366 struct mxcmci_host *host = data;
369 del_timer(&host->watchdog);
371 stat = mxcmci_readl(host, MMC_REG_STATUS);
373 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
375 mxcmci_data_done(host, stat);
378 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
381 u32 int_cntr = host->default_irq_mask;
384 WARN_ON(host->cmd != NULL);
387 switch (mmc_resp_type(cmd)) {
388 case MMC_RSP_R1: /* short CRC, OPCODE */
389 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
390 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
392 case MMC_RSP_R2: /* long 136 bit + CRC */
393 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
395 case MMC_RSP_R3: /* short */
396 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
401 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
403 cmd->error = -EINVAL;
407 int_cntr = INT_END_CMD_RES_EN;
409 if (mxcmci_use_dma(host)) {
410 if (host->dma_dir == DMA_FROM_DEVICE) {
411 host->desc->callback = mxcmci_dma_callback;
412 host->desc->callback_param = host;
414 int_cntr |= INT_WRITE_OP_DONE_EN;
418 spin_lock_irqsave(&host->lock, flags);
420 int_cntr |= INT_SDIO_IRQ_EN;
421 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
422 spin_unlock_irqrestore(&host->lock, flags);
424 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
425 mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
426 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
431 static void mxcmci_finish_request(struct mxcmci_host *host,
432 struct mmc_request *req)
434 u32 int_cntr = host->default_irq_mask;
437 spin_lock_irqsave(&host->lock, flags);
439 int_cntr |= INT_SDIO_IRQ_EN;
440 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
441 spin_unlock_irqrestore(&host->lock, flags);
447 mmc_request_done(host->mmc, req);
450 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
452 struct mmc_data *data = host->data;
455 if (mxcmci_use_dma(host)) {
456 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
458 mxcmci_swap_buffers(data);
461 if (stat & STATUS_ERR_MASK) {
462 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
464 if (stat & STATUS_CRC_READ_ERR) {
465 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
466 data->error = -EILSEQ;
467 } else if (stat & STATUS_CRC_WRITE_ERR) {
468 u32 err_code = (stat >> 9) & 0x3;
469 if (err_code == 2) { /* No CRC response */
470 dev_err(mmc_dev(host->mmc),
471 "%s: No CRC -ETIMEDOUT\n", __func__);
472 data->error = -ETIMEDOUT;
474 dev_err(mmc_dev(host->mmc),
475 "%s: -EILSEQ\n", __func__);
476 data->error = -EILSEQ;
478 } else if (stat & STATUS_TIME_OUT_READ) {
479 dev_err(mmc_dev(host->mmc),
480 "%s: read -ETIMEDOUT\n", __func__);
481 data->error = -ETIMEDOUT;
483 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
487 data->bytes_xfered = host->datasize;
490 data_error = data->error;
497 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
499 struct mmc_command *cmd = host->cmd;
506 if (stat & STATUS_TIME_OUT_RESP) {
507 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
508 cmd->error = -ETIMEDOUT;
509 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
510 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
511 cmd->error = -EILSEQ;
514 if (cmd->flags & MMC_RSP_PRESENT) {
515 if (cmd->flags & MMC_RSP_136) {
516 for (i = 0; i < 4; i++) {
517 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
518 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
519 cmd->resp[i] = a << 16 | b;
522 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
523 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
524 c = mxcmci_readw(host, MMC_REG_RES_FIFO);
525 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
530 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
533 unsigned long timeout = jiffies + HZ;
536 stat = mxcmci_readl(host, MMC_REG_STATUS);
537 if (stat & STATUS_ERR_MASK)
539 if (time_after(jiffies, timeout)) {
540 mxcmci_softreset(host);
541 mxcmci_set_clk_rate(host, host->clock);
542 return STATUS_TIME_OUT_READ;
550 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
556 stat = mxcmci_poll_status(host,
557 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
560 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
568 stat = mxcmci_poll_status(host,
569 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
572 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
573 memcpy(b, &tmp, bytes);
579 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
585 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
588 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
596 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
600 memcpy(&tmp, b, bytes);
601 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
604 return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
607 static int mxcmci_transfer_data(struct mxcmci_host *host)
609 struct mmc_data *data = host->req->data;
610 struct scatterlist *sg;
616 if (data->flags & MMC_DATA_READ) {
617 for_each_sg(data->sg, sg, data->sg_len, i) {
618 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
621 host->datasize += sg->length;
624 for_each_sg(data->sg, sg, data->sg_len, i) {
625 stat = mxcmci_push(host, sg_virt(sg), sg->length);
628 host->datasize += sg->length;
630 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
637 static void mxcmci_datawork(struct work_struct *work)
639 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
641 int datastat = mxcmci_transfer_data(host);
643 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
645 mxcmci_finish_data(host, datastat);
647 if (host->req->stop) {
648 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
649 mxcmci_finish_request(host, host->req);
653 mxcmci_finish_request(host, host->req);
657 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
659 struct mmc_request *req;
663 spin_lock_irqsave(&host->lock, flags);
666 spin_unlock_irqrestore(&host->lock, flags);
671 spin_unlock_irqrestore(&host->lock, flags);
677 host->req = NULL; /* we will handle finish req below */
679 data_error = mxcmci_finish_data(host, stat);
681 spin_unlock_irqrestore(&host->lock, flags);
686 mxcmci_read_response(host, stat);
690 if (mxcmci_start_cmd(host, req->stop, 0)) {
691 mxcmci_finish_request(host, req);
695 mxcmci_finish_request(host, req);
699 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
701 mxcmci_read_response(host, stat);
704 if (!host->data && host->req) {
705 mxcmci_finish_request(host, host->req);
709 /* For the DMA case the DMA engine handles the data transfer
710 * automatically. For non DMA we have to do it ourselves.
711 * Don't do it in interrupt context though.
713 if (!mxcmci_use_dma(host) && host->data)
714 schedule_work(&host->datawork);
718 static irqreturn_t mxcmci_irq(int irq, void *devid)
720 struct mxcmci_host *host = devid;
724 stat = mxcmci_readl(host, MMC_REG_STATUS);
726 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
727 STATUS_WRITE_OP_DONE),
730 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
732 spin_lock(&host->lock);
733 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
734 spin_unlock(&host->lock);
736 if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE)))
737 mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS);
740 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
741 mmc_signal_sdio_irq(host->mmc);
744 if (stat & STATUS_END_CMD_RESP)
745 mxcmci_cmd_done(host, stat);
747 if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) {
748 del_timer(&host->watchdog);
749 mxcmci_data_done(host, stat);
752 if (host->default_irq_mask &&
753 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
754 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
759 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
761 struct mxcmci_host *host = mmc_priv(mmc);
762 unsigned int cmdat = host->cmdat;
765 WARN_ON(host->req != NULL);
768 host->cmdat &= ~CMD_DAT_CONT_INIT;
774 error = mxcmci_setup_data(host, req->data);
776 req->cmd->error = error;
781 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
783 if (req->data->flags & MMC_DATA_WRITE)
784 cmdat |= CMD_DAT_CONT_WRITE;
787 error = mxcmci_start_cmd(host, req->cmd, cmdat);
791 mxcmci_finish_request(host, req);
794 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
796 unsigned int divider;
798 unsigned int clk_in = clk_get_rate(host->clk_per);
800 while (prescaler <= 0x800) {
801 for (divider = 1; divider <= 0xF; divider++) {
804 x = (clk_in / (divider + 1));
807 x /= (prescaler * 2);
821 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
823 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
824 prescaler, divider, clk_in, clk_ios);
827 static int mxcmci_setup_dma(struct mmc_host *mmc)
829 struct mxcmci_host *host = mmc_priv(mmc);
830 struct dma_slave_config *config = &host->dma_slave_config;
832 config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
833 config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
834 config->dst_addr_width = 4;
835 config->src_addr_width = 4;
836 config->dst_maxburst = host->burstlen;
837 config->src_maxburst = host->burstlen;
838 config->device_fc = false;
840 return dmaengine_slave_config(host->dma, config);
843 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
845 struct mxcmci_host *host = mmc_priv(mmc);
849 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
850 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
852 if (ios->bus_width == MMC_BUS_WIDTH_4)
857 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
858 host->burstlen = burstlen;
859 ret = mxcmci_setup_dma(mmc);
861 dev_err(mmc_dev(host->mmc),
862 "failed to config DMA channel. Falling back to PIO\n");
863 dma_release_channel(host->dma);
869 if (ios->bus_width == MMC_BUS_WIDTH_4)
870 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
872 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
874 if (host->power_mode != ios->power_mode) {
875 host->power_mode = ios->power_mode;
876 mxcmci_set_power(host, ios->vdd);
878 if (ios->power_mode == MMC_POWER_ON)
879 host->cmdat |= CMD_DAT_CONT_INIT;
883 mxcmci_set_clk_rate(host, ios->clock);
884 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
886 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
889 host->clock = ios->clock;
892 static irqreturn_t mxcmci_detect_irq(int irq, void *data)
894 struct mmc_host *mmc = data;
896 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
898 mmc_detect_change(mmc, msecs_to_jiffies(250));
902 static int mxcmci_get_ro(struct mmc_host *mmc)
904 struct mxcmci_host *host = mmc_priv(mmc);
906 if (host->pdata && host->pdata->get_ro)
907 return !!host->pdata->get_ro(mmc_dev(mmc));
909 * If board doesn't support read only detection (no mmc_gpio
910 * context or gpio is invalid), then let the mmc core decide
913 return mmc_gpio_get_ro(mmc);
916 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
918 struct mxcmci_host *host = mmc_priv(mmc);
922 spin_lock_irqsave(&host->lock, flags);
923 host->use_sdio = enable;
924 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
927 int_cntr |= INT_SDIO_IRQ_EN;
929 int_cntr &= ~INT_SDIO_IRQ_EN;
931 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
932 spin_unlock_irqrestore(&host->lock, flags);
935 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
937 struct mxcmci_host *mxcmci = mmc_priv(host);
940 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
941 * multi-block transfers when connected SDIO peripheral doesn't
942 * drive the BUSY line as required by the specs.
943 * One way to prevent this is to only allow 1-bit transfers.
946 if (is_imx31_mmc(mxcmci) && card->type == MMC_TYPE_SDIO)
947 host->caps &= ~MMC_CAP_4_BIT_DATA;
949 host->caps |= MMC_CAP_4_BIT_DATA;
952 static bool filter(struct dma_chan *chan, void *param)
954 struct mxcmci_host *host = param;
956 if (!imx_dma_is_general_purpose(chan))
959 chan->private = &host->dma_data;
964 static void mxcmci_watchdog(struct timer_list *t)
966 struct mxcmci_host *host = from_timer(host, t, watchdog);
967 struct mmc_request *req = host->req;
968 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
970 if (host->dma_dir == DMA_FROM_DEVICE) {
971 dmaengine_terminate_all(host->dma);
972 dev_err(mmc_dev(host->mmc),
973 "%s: read time out (status = 0x%08x)\n",
976 dev_err(mmc_dev(host->mmc),
977 "%s: write time out (status = 0x%08x)\n",
979 mxcmci_softreset(host);
982 /* Mark transfer as erroneus and inform the upper layers */
985 host->data->error = -ETIMEDOUT;
989 mmc_request_done(host->mmc, req);
992 static const struct mmc_host_ops mxcmci_ops = {
993 .request = mxcmci_request,
994 .set_ios = mxcmci_set_ios,
995 .get_ro = mxcmci_get_ro,
996 .enable_sdio_irq = mxcmci_enable_sdio_irq,
997 .init_card = mxcmci_init_card,
1000 static int mxcmci_probe(struct platform_device *pdev)
1002 struct mmc_host *mmc;
1003 struct mxcmci_host *host;
1004 struct resource *res;
1006 bool dat3_card_detect = false;
1007 dma_cap_mask_t mask;
1008 const struct of_device_id *of_id;
1009 struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
1011 pr_info("i.MX/MPC512x SDHC driver\n");
1013 of_id = of_match_device(mxcmci_of_match, &pdev->dev);
1015 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1016 irq = platform_get_irq(pdev, 0);
1018 dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq);
1022 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1026 host = mmc_priv(mmc);
1028 host->base = devm_ioremap_resource(&pdev->dev, res);
1029 if (IS_ERR(host->base)) {
1030 ret = PTR_ERR(host->base);
1034 host->phys_base = res->start;
1036 ret = mmc_of_parse(mmc);
1039 mmc->ops = &mxcmci_ops;
1041 /* For devicetree parsing, the bus width is read from devicetree */
1043 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1045 mmc->caps |= MMC_CAP_SDIO_IRQ;
1047 /* MMC core transfer sizes tunable parameters */
1048 mmc->max_blk_size = 2048;
1049 mmc->max_blk_count = 65535;
1050 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1051 mmc->max_seg_size = mmc->max_req_size;
1054 const struct platform_device_id *id_entry = of_id->data;
1055 host->devtype = id_entry->driver_data;
1057 host->devtype = pdev->id_entry->driver_data;
1060 /* adjust max_segs after devtype detection */
1061 if (!is_mpc512x_mmc(host))
1065 host->pdata = pdata;
1066 spin_lock_init(&host->lock);
1069 dat3_card_detect = pdata->dat3_card_detect;
1070 else if (mmc_card_is_removable(mmc)
1071 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1072 dat3_card_detect = true;
1074 ret = mmc_regulator_get_supply(mmc);
1078 if (!mmc->ocr_avail) {
1079 if (pdata && pdata->ocr_avail)
1080 mmc->ocr_avail = pdata->ocr_avail;
1082 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1085 if (dat3_card_detect)
1086 host->default_irq_mask =
1087 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1089 host->default_irq_mask = 0;
1091 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1092 if (IS_ERR(host->clk_ipg)) {
1093 ret = PTR_ERR(host->clk_ipg);
1097 host->clk_per = devm_clk_get(&pdev->dev, "per");
1098 if (IS_ERR(host->clk_per)) {
1099 ret = PTR_ERR(host->clk_per);
1103 ret = clk_prepare_enable(host->clk_per);
1107 ret = clk_prepare_enable(host->clk_ipg);
1109 goto out_clk_per_put;
1111 mxcmci_softreset(host);
1113 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
1114 if (host->rev_no != 0x400) {
1116 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1121 mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1122 mmc->f_max = clk_get_rate(host->clk_per) >> 1;
1124 /* recommended in data sheet */
1125 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
1127 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
1130 host->dma = dma_request_slave_channel(&pdev->dev, "rx-tx");
1132 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1134 host->dmareq = res->start;
1135 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1136 host->dma_data.priority = DMA_PRIO_LOW;
1137 host->dma_data.dma_request = host->dmareq;
1139 dma_cap_set(DMA_SLAVE, mask);
1140 host->dma = dma_request_channel(mask, filter, host);
1144 mmc->max_seg_size = dma_get_max_seg_size(
1145 host->dma->device->dev);
1147 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
1149 INIT_WORK(&host->datawork, mxcmci_datawork);
1151 ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0,
1152 dev_name(&pdev->dev), host);
1156 platform_set_drvdata(pdev, mmc);
1158 if (host->pdata && host->pdata->init) {
1159 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1165 timer_setup(&host->watchdog, mxcmci_watchdog, 0);
1173 dma_release_channel(host->dma);
1176 clk_disable_unprepare(host->clk_ipg);
1178 clk_disable_unprepare(host->clk_per);
1186 static int mxcmci_remove(struct platform_device *pdev)
1188 struct mmc_host *mmc = platform_get_drvdata(pdev);
1189 struct mxcmci_host *host = mmc_priv(mmc);
1191 mmc_remove_host(mmc);
1193 if (host->pdata && host->pdata->exit)
1194 host->pdata->exit(&pdev->dev, mmc);
1197 dma_release_channel(host->dma);
1199 clk_disable_unprepare(host->clk_per);
1200 clk_disable_unprepare(host->clk_ipg);
1207 #ifdef CONFIG_PM_SLEEP
1208 static int mxcmci_suspend(struct device *dev)
1210 struct mmc_host *mmc = dev_get_drvdata(dev);
1211 struct mxcmci_host *host = mmc_priv(mmc);
1213 clk_disable_unprepare(host->clk_per);
1214 clk_disable_unprepare(host->clk_ipg);
1218 static int mxcmci_resume(struct device *dev)
1220 struct mmc_host *mmc = dev_get_drvdata(dev);
1221 struct mxcmci_host *host = mmc_priv(mmc);
1224 ret = clk_prepare_enable(host->clk_per);
1228 ret = clk_prepare_enable(host->clk_ipg);
1230 clk_disable_unprepare(host->clk_per);
1236 static SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume);
1238 static struct platform_driver mxcmci_driver = {
1239 .probe = mxcmci_probe,
1240 .remove = mxcmci_remove,
1241 .id_table = mxcmci_devtype,
1243 .name = DRIVER_NAME,
1244 .pm = &mxcmci_pm_ops,
1245 .of_match_table = mxcmci_of_match,
1249 module_platform_driver(mxcmci_driver);
1251 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1252 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1253 MODULE_LICENSE("GPL");
1254 MODULE_ALIAS("platform:mxc-mmc");