drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/string.h>
  27 #include <linux/acpi.h>
  28 #include <linux/i2c.h>
  29
  30 #include <drm/drm_atomic.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/amdgpu_drm.h>
  33 #include <drm/drm_edid.h>
  34
  35 #include "dm_services.h"
  36 #include "amdgpu.h"
  37 #include "dc.h"
  38 #include "amdgpu_dm.h"
  39 #include "amdgpu_dm_irq.h"
  40 #include "amdgpu_dm_mst_types.h"
  41 #include "dpcd_defs.h"
  42 #include "dc/inc/core_types.h"
  43
  44 #include "dm_helpers.h"
  45 #include "ddc_service_types.h"
  46
  47 /* dm_helpers_parse_edid_caps
  48  *
  49  * Parse edid caps
  50  *
  51  * @edid:       [in] pointer to edid
  52  *  edid_caps:  [in] pointer to edid caps
  53  * @return
  54  *      void
  55  * */
  56 enum dc_edid_status dm_helpers_parse_edid_caps(
  57                 struct dc_link *link,
  58                 const struct dc_edid *edid,
  59                 struct dc_edid_caps *edid_caps)
  60 {
  61         struct amdgpu_dm_connector *aconnector = link->priv;
  62         struct drm_connector *connector = &aconnector->base;
  63         struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL;
  64         struct cea_sad *sads;
  65         int sad_count = -1;
  66         int sadb_count = -1;
  67         int i = 0;
  68         uint8_t *sadb = NULL;
  69
  70         enum dc_edid_status result = EDID_OK;
  71
  72         if (!edid_caps || !edid)
  73                 return EDID_BAD_INPUT;
  74
  75         if (!drm_edid_is_valid(edid_buf))
  76                 result = EDID_BAD_CHECKSUM;
  77
  78         edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
  79                                         ((uint16_t) edid_buf->mfg_id[1])<<8;
  80         edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
  81                                         ((uint16_t) edid_buf->prod_code[1])<<8;
  82         edid_caps->serial_number = edid_buf->serial;
  83         edid_caps->manufacture_week = edid_buf->mfg_week;
  84         edid_caps->manufacture_year = edid_buf->mfg_year;
  85
  86         drm_edid_get_monitor_name(edid_buf,
  87                                   edid_caps->display_name,
  88                                   AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
  89
  90         edid_caps->edid_hdmi = connector->display_info.is_hdmi;
  91
  92         sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
  93         if (sad_count <= 0)
  94                 return result;
  95
  96         edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT;
  97         for (i = 0; i < edid_caps->audio_mode_count; ++i) {
  98                 struct cea_sad *sad = &sads[i];
  99
 100                 edid_caps->audio_modes[i].format_code = sad->format;
 101                 edid_caps->audio_modes[i].channel_count = sad->channels + 1;
 102                 edid_caps->audio_modes[i].sample_rate = sad->freq;
 103                 edid_caps->audio_modes[i].sample_size = sad->byte2;
 104         }
 105
 106         sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
 107
 108         if (sadb_count < 0) {
 109                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
 110                 sadb_count = 0;
 111         }
 112
 113         if (sadb_count)
 114                 edid_caps->speaker_flags = sadb[0];
 115         else
 116                 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
 117
 118         kfree(sads);
 119         kfree(sadb);
 120
 121         return result;
 122 }
 123
 124 static void
 125 fill_dc_mst_payload_table_from_drm(struct dc_link *link,
 126                                    bool enable,
 127                                    struct drm_dp_mst_atomic_payload *target_payload,
 128                                    struct dc_dp_mst_stream_allocation_table *table)
 129 {
 130         struct dc_dp_mst_stream_allocation_table new_table = { 0 };
 131         struct dc_dp_mst_stream_allocation *sa;
 132         struct link_mst_stream_allocation_table copy_of_link_table =
 133                                                                                 link->mst_stream_alloc_table;
 134
 135         int i;
 136         int current_hw_table_stream_cnt = copy_of_link_table.stream_count;
 137         struct link_mst_stream_allocation *dc_alloc;
 138
 139         /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/
 140         if (enable) {
 141                 dc_alloc =
 142                 &copy_of_link_table.stream_allocations[current_hw_table_stream_cnt];
 143                 dc_alloc->vcp_id = target_payload->vcpi;
 144                 dc_alloc->slot_count = target_payload->time_slots;
 145         } else {
 146                 for (i = 0; i < copy_of_link_table.stream_count; i++) {
 147                         dc_alloc =
 148                         &copy_of_link_table.stream_allocations[i];
 149
 150                         if (dc_alloc->vcp_id == target_payload->vcpi) {
 151                                 dc_alloc->vcp_id = 0;
 152                                 dc_alloc->slot_count = 0;
 153                                 break;
 154                         }
 155                 }
 156                 ASSERT(i != copy_of_link_table.stream_count);
 157         }
 158
 159         /* Fill payload info*/
 160         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
 161                 dc_alloc =
 162                         &copy_of_link_table.stream_allocations[i];
 163                 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) {
 164                         sa = &new_table.stream_allocations[new_table.stream_count];
 165                         sa->slot_count = dc_alloc->slot_count;
 166                         sa->vcp_id = dc_alloc->vcp_id;
 167                         new_table.stream_count++;
 168                 }
 169         }
 170
 171         /* Overwrite the old table */
 172         *table = new_table;
 173 }
 174
 175 void dm_helpers_dp_update_branch_info(
 176         struct dc_context *ctx,
 177         const struct dc_link *link)
 178 {}
 179
 180 /*
 181  * Writes payload allocation table in immediate downstream device.
 182  */
 183 bool dm_helpers_dp_mst_write_payload_allocation_table(
 184                 struct dc_context *ctx,
 185                 const struct dc_stream_state *stream,
 186                 struct dc_dp_mst_stream_allocation_table *proposed_table,
 187                 bool enable)
 188 {
 189         struct amdgpu_dm_connector *aconnector;
 190         struct drm_dp_mst_topology_state *mst_state;
 191         struct drm_dp_mst_atomic_payload *payload;
 192         struct drm_dp_mst_topology_mgr *mst_mgr;
 193
 194         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 195         /* Accessing the connector state is required for vcpi_slots allocation
 196          * and directly relies on behaviour in commit check
 197          * that blocks before commit guaranteeing that the state
 198          * is not gonna be swapped while still in use in commit tail */
 199
 200         if (!aconnector || !aconnector->mst_root)
 201                 return false;
 202
 203         mst_mgr = &aconnector->mst_root->mst_mgr;
 204         mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 205
 206         /* It's OK for this to fail */
 207         payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 208         if (enable)
 209                 drm_dp_add_payload_part1(mst_mgr, mst_state, payload);
 210         else
 211                 drm_dp_remove_payload(mst_mgr, mst_state, payload, payload);
 212
 213         /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
 214          * AUX message. The sequence is slot 1-63 allocated sequence for each
 215          * stream. AMD ASIC stream slot allocation should follow the same
 216          * sequence. copy DRM MST allocation to dc */
 217         fill_dc_mst_payload_table_from_drm(stream->link, enable, payload, proposed_table);
 218
 219         return true;
 220 }
 221
 222 /*
 223  * poll pending down reply
 224  */
 225 void dm_helpers_dp_mst_poll_pending_down_reply(
 226         struct dc_context *ctx,
 227         const struct dc_link *link)
 228 {}
 229
 230 /*
 231  * Clear payload allocation table before enable MST DP link.
 232  */
 233 void dm_helpers_dp_mst_clear_payload_allocation_table(
 234         struct dc_context *ctx,
 235         const struct dc_link *link)
 236 {}
 237
 238 /*
 239  * Polls for ACT (allocation change trigger) handled and sends
 240  * ALLOCATE_PAYLOAD message.
 241  */
 242 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
 243                 struct dc_context *ctx,
 244                 const struct dc_stream_state *stream)
 245 {
 246         struct amdgpu_dm_connector *aconnector;
 247         struct drm_dp_mst_topology_mgr *mst_mgr;
 248         int ret;
 249
 250         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 251
 252         if (!aconnector || !aconnector->mst_root)
 253                 return ACT_FAILED;
 254
 255         mst_mgr = &aconnector->mst_root->mst_mgr;
 256
 257         if (!mst_mgr->mst_state)
 258                 return ACT_FAILED;
 259
 260         ret = drm_dp_check_act_status(mst_mgr);
 261
 262         if (ret)
 263                 return ACT_FAILED;
 264
 265         return ACT_SUCCESS;
 266 }
 267
 268 bool dm_helpers_dp_mst_send_payload_allocation(
 269                 struct dc_context *ctx,
 270                 const struct dc_stream_state *stream,
 271                 bool enable)
 272 {
 273         struct amdgpu_dm_connector *aconnector;
 274         struct drm_dp_mst_topology_state *mst_state;
 275         struct drm_dp_mst_topology_mgr *mst_mgr;
 276         struct drm_dp_mst_atomic_payload *payload;
 277         enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;
 278         enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 279         int ret = 0;
 280
 281         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 282
 283         if (!aconnector || !aconnector->mst_root)
 284                 return false;
 285
 286         mst_mgr = &aconnector->mst_root->mst_mgr;
 287         mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 288
 289         payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 290
 291         if (!enable) {
 292                 set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 293                 clr_flag = MST_ALLOCATE_NEW_PAYLOAD;
 294         }
 295
 296         if (enable)
 297                 ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, payload);
 298
 299         if (ret) {
 300                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 301                         set_flag, false);
 302         } else {
 303                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 304                         set_flag, true);
 305                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 306                         clr_flag, false);
 307         }
 308
 309         return true;
 310 }
 311
 312 void dm_dtn_log_begin(struct dc_context *ctx,
 313         struct dc_log_buffer_ctx *log_ctx)
 314 {
 315         static const char msg[] = "[dtn begin]\n";
 316
 317         if (!log_ctx) {
 318                 pr_info("%s", msg);
 319                 return;
 320         }
 321
 322         dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 323 }
 324
 325 __printf(3, 4)
 326 void dm_dtn_log_append_v(struct dc_context *ctx,
 327         struct dc_log_buffer_ctx *log_ctx,
 328         const char *msg, ...)
 329 {
 330         va_list args;
 331         size_t total;
 332         int n;
 333
 334         if (!log_ctx) {
 335                 /* No context, redirect to dmesg. */
 336                 struct va_format vaf;
 337
 338                 vaf.fmt = msg;
 339                 vaf.va = &args;
 340
 341                 va_start(args, msg);
 342                 pr_info("%pV", &vaf);
 343                 va_end(args);
 344
 345                 return;
 346         }
 347
 348         /* Measure the output. */
 349         va_start(args, msg);
 350         n = vsnprintf(NULL, 0, msg, args);
 351         va_end(args);
 352
 353         if (n <= 0)
 354                 return;
 355
 356         /* Reallocate the string buffer as needed. */
 357         total = log_ctx->pos + n + 1;
 358
 359         if (total > log_ctx->size) {
 360                 char *buf = (char *)kvcalloc(total, sizeof(char), GFP_KERNEL);
 361
 362                 if (buf) {
 363                         memcpy(buf, log_ctx->buf, log_ctx->pos);
 364                         kfree(log_ctx->buf);
 365
 366                         log_ctx->buf = buf;
 367                         log_ctx->size = total;
 368                 }
 369         }
 370
 371         if (!log_ctx->buf)
 372                 return;
 373
 374         /* Write the formatted string to the log buffer. */
 375         va_start(args, msg);
 376         n = vscnprintf(
 377                 log_ctx->buf + log_ctx->pos,
 378                 log_ctx->size - log_ctx->pos,
 379                 msg,
 380                 args);
 381         va_end(args);
 382
 383         if (n > 0)
 384                 log_ctx->pos += n;
 385 }
 386
 387 void dm_dtn_log_end(struct dc_context *ctx,
 388         struct dc_log_buffer_ctx *log_ctx)
 389 {
 390         static const char msg[] = "[dtn end]\n";
 391
 392         if (!log_ctx) {
 393                 pr_info("%s", msg);
 394                 return;
 395         }
 396
 397         dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 398 }
 399
 400 bool dm_helpers_dp_mst_start_top_mgr(
 401                 struct dc_context *ctx,
 402                 const struct dc_link *link,
 403                 bool boot)
 404 {
 405         struct amdgpu_dm_connector *aconnector = link->priv;
 406         int ret;
 407
 408         if (!aconnector) {
 409                 DRM_ERROR("Failed to find connector for link!");
 410                 return false;
 411         }
 412
 413         if (boot) {
 414                 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
 415                                         aconnector, aconnector->base.base.id);
 416                 return true;
 417         }
 418
 419         DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 420                         aconnector, aconnector->base.base.id);
 421
 422         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 423         if (ret < 0) {
 424                 DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
 425                 return false;
 426         }
 427
 428         DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0],
 429                 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK);
 430
 431         return true;
 432 }
 433
 434 bool dm_helpers_dp_mst_stop_top_mgr(
 435                 struct dc_context *ctx,
 436                 struct dc_link *link)
 437 {
 438         struct amdgpu_dm_connector *aconnector = link->priv;
 439
 440         if (!aconnector) {
 441                 DRM_ERROR("Failed to find connector for link!");
 442                 return false;
 443         }
 444
 445         DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
 446                         aconnector, aconnector->base.base.id);
 447
 448         if (aconnector->mst_mgr.mst_state == true) {
 449                 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
 450                 link->cur_link_settings.lane_count = 0;
 451         }
 452
 453         return false;
 454 }
 455
 456 bool dm_helpers_dp_read_dpcd(
 457                 struct dc_context *ctx,
 458                 const struct dc_link *link,
 459                 uint32_t address,
 460                 uint8_t *data,
 461                 uint32_t size)
 462 {
 463
 464         struct amdgpu_dm_connector *aconnector = link->priv;
 465
 466         if (!aconnector) {
 467                 DC_LOG_DC("Failed to find connector for link!\n");
 468                 return false;
 469         }
 470
 471         return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address,
 472                         data, size) > 0;
 473 }
 474
 475 bool dm_helpers_dp_write_dpcd(
 476                 struct dc_context *ctx,
 477                 const struct dc_link *link,
 478                 uint32_t address,
 479                 const uint8_t *data,
 480                 uint32_t size)
 481 {
 482         struct amdgpu_dm_connector *aconnector = link->priv;
 483
 484         if (!aconnector) {
 485                 DRM_ERROR("Failed to find connector for link!");
 486                 return false;
 487         }
 488
 489         return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
 490                         address, (uint8_t *)data, size) > 0;
 491 }
 492
 493 bool dm_helpers_submit_i2c(
 494                 struct dc_context *ctx,
 495                 const struct dc_link *link,
 496                 struct i2c_command *cmd)
 497 {
 498         struct amdgpu_dm_connector *aconnector = link->priv;
 499         struct i2c_msg *msgs;
 500         int i = 0;
 501         int num = cmd->number_of_payloads;
 502         bool result;
 503
 504         if (!aconnector) {
 505                 DRM_ERROR("Failed to find connector for link!");
 506                 return false;
 507         }
 508
 509         msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);
 510
 511         if (!msgs)
 512                 return false;
 513
 514         for (i = 0; i < num; i++) {
 515                 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
 516                 msgs[i].addr = cmd->payloads[i].address;
 517                 msgs[i].len = cmd->payloads[i].length;
 518                 msgs[i].buf = cmd->payloads[i].data;
 519         }
 520
 521         result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
 522
 523         kfree(msgs);
 524
 525         return result;
 526 }
 527
 528 #if defined(CONFIG_DRM_AMD_DC_DCN)
 529 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,
 530                 bool is_write_cmd,
 531                 unsigned char cmd,
 532                 unsigned int length,
 533                 unsigned int offset,
 534                 unsigned char *data)
 535 {
 536         bool success = false;
 537         unsigned char rc_data[16] = {0};
 538         unsigned char rc_offset[4] = {0};
 539         unsigned char rc_length[2] = {0};
 540         unsigned char rc_cmd = 0;
 541         unsigned char rc_result = 0xFF;
 542         unsigned char i = 0;
 543         int ret;
 544
 545         if (is_write_cmd) {
 546                 // write rc data
 547                 memmove(rc_data, data, length);
 548                 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data));
 549         }
 550
 551         // write rc offset
 552         rc_offset[0] = (unsigned char) offset & 0xFF;
 553         rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF;
 554         rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF;
 555         rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF;
 556         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset));
 557
 558         // write rc length
 559         rc_length[0] = (unsigned char) length & 0xFF;
 560         rc_length[1] = (unsigned char) (length >> 8) & 0xFF;
 561         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length));
 562
 563         // write rc cmd
 564         rc_cmd = cmd | 0x80;
 565         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 566
 567         if (ret < 0) {
 568                 DRM_ERROR("     execute_synaptics_rc_command - write cmd ..., err = %d\n", ret);
 569                 return false;
 570         }
 571
 572         // poll until active is 0
 573         for (i = 0; i < 10; i++) {
 574                 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 575                 if (rc_cmd == cmd)
 576                         // active is 0
 577                         break;
 578                 msleep(10);
 579         }
 580
 581         // read rc result
 582         drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result));
 583         success = (rc_result == 0);
 584
 585         if (success && !is_write_cmd) {
 586                 // read rc data
 587                 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length);
 588         }
 589
 590         DC_LOG_DC("     execute_synaptics_rc_command - success = %d\n", success);
 591
 592         return success;
 593 }
 594
 595 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux)
 596 {
 597         unsigned char data[16] = {0};
 598
 599         DC_LOG_DC("Start apply_synaptics_fifo_reset_wa\n");
 600
 601         // Step 2
 602         data[0] = 'P';
 603         data[1] = 'R';
 604         data[2] = 'I';
 605         data[3] = 'U';
 606         data[4] = 'S';
 607
 608         if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data))
 609                 return;
 610
 611         // Step 3 and 4
 612         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 613                 return;
 614
 615         data[0] &= (~(1 << 1)); // set bit 1 to 0
 616         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 617                 return;
 618
 619         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 620                 return;
 621
 622         data[0] &= (~(1 << 1)); // set bit 1 to 0
 623         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data))
 624                 return;
 625
 626         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 627                 return;
 628
 629         data[0] &= (~(1 << 1)); // set bit 1 to 0
 630         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 631                 return;
 632
 633         // Step 3 and 5
 634         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 635                 return;
 636
 637         data[0] |= (1 << 1); // set bit 1 to 1
 638         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 639                 return;
 640
 641         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 642                 return;
 643
 644         data[0] |= (1 << 1); // set bit 1 to 1
 645                 return;
 646
 647         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 648                 return;
 649
 650         data[0] |= (1 << 1); // set bit 1 to 1
 651         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 652                 return;
 653
 654         // Step 6
 655         if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL))
 656                 return;
 657
 658         DC_LOG_DC("Done apply_synaptics_fifo_reset_wa\n");
 659 }
 660
 661 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 662                 struct drm_dp_aux *aux,
 663                 const struct dc_stream_state *stream,
 664                 bool enable)
 665 {
 666         uint8_t ret = 0;
 667
 668         DC_LOG_DC("Configure DSC to non-virtual dpcd synaptics\n");
 669
 670         if (enable) {
 671                 /* When DSC is enabled on previous boot and reboot with the hub,
 672                  * there is a chance that Synaptics hub gets stuck during reboot sequence.
 673                  * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream
 674                  */
 675                 if (!stream->link->link_status.link_active &&
 676                         memcmp(stream->link->dpcd_caps.branch_dev_name,
 677                                 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0)
 678                         apply_synaptics_fifo_reset_wa(aux);
 679
 680                 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 681                 DRM_INFO("Send DSC enable to synaptics\n");
 682
 683         } else {
 684                 /* Synaptics hub not support virtual dpcd,
 685                  * external monitor occur garbage while disable DSC,
 686                  * Disable DSC only when entire link status turn to false,
 687                  */
 688                 if (!stream->link->link_status.link_active) {
 689                         ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 690                         DRM_INFO("Send DSC disable to synaptics\n");
 691                 }
 692         }
 693
 694         return ret;
 695 }
 696 #endif
 697
 698 bool dm_helpers_dp_write_dsc_enable(
 699                 struct dc_context *ctx,
 700                 const struct dc_stream_state *stream,
 701                 bool enable)
 702 {
 703         static const uint8_t DSC_DISABLE;
 704         static const uint8_t DSC_DECODING = 0x01;
 705         static const uint8_t DSC_PASSTHROUGH = 0x02;
 706
 707         struct amdgpu_dm_connector *aconnector;
 708         struct drm_dp_mst_port *port;
 709         uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE;
 710         uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;
 711         uint8_t ret = 0;
 712
 713         if (!stream)
 714                 return false;
 715
 716         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 717                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 718
 719                 if (!aconnector->dsc_aux)
 720                         return false;
 721
 722 #if defined(CONFIG_DRM_AMD_DC_DCN)
 723                 // apply w/a to synaptics
 724                 if (needs_dsc_aux_workaround(aconnector->dc_link) &&
 725                     (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3)
 726                         return write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 727                                 aconnector->dsc_aux, stream, enable_dsc);
 728 #endif
 729
 730                 port = aconnector->mst_output_port;
 731
 732                 if (enable) {
 733                         if (port->passthrough_aux) {
 734                                 ret = drm_dp_dpcd_write(port->passthrough_aux,
 735                                                         DP_DSC_ENABLE,
 736                                                         &enable_passthrough, 1);
 737                                 DC_LOG_DC("Sent DSC pass-through enable to virtual dpcd port, ret = %u\n",
 738                                           ret);
 739                         }
 740
 741                         ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 742                                                 DP_DSC_ENABLE, &enable_dsc, 1);
 743                         DC_LOG_DC("Sent DSC decoding enable to %s port, ret = %u\n",
 744                                   (port->passthrough_aux) ? "remote RX" :
 745                                   "virtual dpcd",
 746                                   ret);
 747                 } else {
 748                         ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 749                                                 DP_DSC_ENABLE, &enable_dsc, 1);
 750                         DC_LOG_DC("Sent DSC decoding disable to %s port, ret = %u\n",
 751                                   (port->passthrough_aux) ? "remote RX" :
 752                                   "virtual dpcd",
 753                                   ret);
 754
 755                         if (port->passthrough_aux) {
 756                                 ret = drm_dp_dpcd_write(port->passthrough_aux,
 757                                                         DP_DSC_ENABLE,
 758                                                         &enable_passthrough, 1);
 759                                 DC_LOG_DC("Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",
 760                                           ret);
 761                         }
 762                 }
 763         }
 764
 765         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) {
 766 #if defined(CONFIG_DRM_AMD_DC_DCN)
 767                 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
 768 #endif
 769                         ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 770                         DC_LOG_DC("Send DSC %s to SST RX\n", enable_dsc ? "enable" : "disable");
 771 #if defined(CONFIG_DRM_AMD_DC_DCN)
 772                 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
 773                         ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 774                         DC_LOG_DC("Send DSC %s to DP-HDMI PCON\n", enable_dsc ? "enable" : "disable");
 775                 }
 776 #endif
 777         }
 778
 779         return ret;
 780 }
 781
 782 bool dm_helpers_is_dp_sink_present(struct dc_link *link)
 783 {
 784         bool dp_sink_present;
 785         struct amdgpu_dm_connector *aconnector = link->priv;
 786
 787         if (!aconnector) {
 788                 BUG_ON("Failed to find connector for link!");
 789                 return true;
 790         }
 791
 792         mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
 793         dp_sink_present = dc_link_is_dp_sink_present(link);
 794         mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
 795         return dp_sink_present;
 796 }
 797
 798 enum dc_edid_status dm_helpers_read_local_edid(
 799                 struct dc_context *ctx,
 800                 struct dc_link *link,
 801                 struct dc_sink *sink)
 802 {
 803         struct amdgpu_dm_connector *aconnector = link->priv;
 804         struct drm_connector *connector = &aconnector->base;
 805         struct i2c_adapter *ddc;
 806         int retry = 3;
 807         enum dc_edid_status edid_status;
 808         struct edid *edid;
 809
 810         if (link->aux_mode)
 811                 ddc = &aconnector->dm_dp_aux.aux.ddc;
 812         else
 813                 ddc = &aconnector->i2c->base;
 814
 815         /* some dongles read edid incorrectly the first time,
 816          * do check sum and retry to make sure read correct edid.
 817          */
 818         do {
 819
 820                 edid = drm_get_edid(&aconnector->base, ddc);
 821
 822                 /* DP Compliance Test 4.2.2.6 */
 823                 if (link->aux_mode && connector->edid_corrupt)
 824                         drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum);
 825
 826                 if (!edid && connector->edid_corrupt) {
 827                         connector->edid_corrupt = false;
 828                         return EDID_BAD_CHECKSUM;
 829                 }
 830
 831                 if (!edid)
 832                         return EDID_NO_RESPONSE;
 833
 834                 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
 835                 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
 836
 837                 /* We don't need the original edid anymore */
 838                 kfree(edid);
 839
 840                 edid_status = dm_helpers_parse_edid_caps(
 841                                                 link,
 842                                                 &sink->dc_edid,
 843                                                 &sink->edid_caps);
 844
 845         } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
 846
 847         if (edid_status != EDID_OK)
 848                 DRM_ERROR("EDID err: %d, on connector: %s",
 849                                 edid_status,
 850                                 aconnector->base.name);
 851
 852         /* DP Compliance Test 4.2.2.3 */
 853         if (link->aux_mode)
 854                 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, sink->dc_edid.raw_edid[sink->dc_edid.length-1]);
 855
 856         return edid_status;
 857 }
 858 int dm_helper_dmub_aux_transfer_sync(
 859                 struct dc_context *ctx,
 860                 const struct dc_link *link,
 861                 struct aux_payload *payload,
 862                 enum aux_return_code_type *operation_result)
 863 {
 864         return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload,
 865                         operation_result);
 866 }
 867
 868 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,
 869                 const struct dc_link *link,
 870                 struct set_config_cmd_payload *payload,
 871                 enum set_config_status *operation_result)
 872 {
 873         return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload,
 874                         operation_result);
 875 }
 876
 877 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
 878 {
 879         /* TODO: something */
 880 }
 881
 882 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)
 883 {
 884         // TODO:
 885         //amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
 886 }
 887
 888 void dm_helpers_init_panel_settings(
 889         struct dc_context *ctx,
 890         struct dc_panel_config *panel_config,
 891         struct dc_sink *sink)
 892 {
 893         // Extra Panel Power Sequence
 894         panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms;
 895         panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms;
 896         panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off;
 897         panel_config->pps.extra_post_t7_ms = 0;
 898         panel_config->pps.extra_pre_t11_ms = 0;
 899         panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms;
 900         panel_config->pps.extra_post_OUI_ms = 0;
 901         // Feature DSC
 902         panel_config->dsc.disable_dsc_edp = false;
 903         panel_config->dsc.force_dsc_edp_policy = 0;
 904 }
 905
 906 void dm_helpers_override_panel_settings(
 907         struct dc_context *ctx,
 908         struct dc_panel_config *panel_config)
 909 {
 910         // Feature DSC
 911         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
 912                 panel_config->dsc.disable_dsc_edp = true;
 913         }
 914 }
 915
 916 void *dm_helpers_allocate_gpu_mem(
 917                 struct dc_context *ctx,
 918                 enum dc_gpu_mem_alloc_type type,
 919                 size_t size,
 920                 long long *addr)
 921 {
 922         struct amdgpu_device *adev = ctx->driver_context;
 923         struct dal_allocation *da;
 924         u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?
 925                 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM;
 926         int ret;
 927
 928         da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);
 929         if (!da)
 930                 return NULL;
 931
 932         ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
 933                                       domain, &da->bo,
 934                                       &da->gpu_addr, &da->cpu_ptr);
 935
 936         *addr = da->gpu_addr;
 937
 938         if (ret) {
 939                 kfree(da);
 940                 return NULL;
 941         }
 942
 943         /* add da to list in dm */
 944         list_add(&da->list, &adev->dm.da_list);
 945
 946         return da->cpu_ptr;
 947 }
 948
 949 void dm_helpers_free_gpu_mem(
 950                 struct dc_context *ctx,
 951                 enum dc_gpu_mem_alloc_type type,
 952                 void *pvMem)
 953 {
 954         struct amdgpu_device *adev = ctx->driver_context;
 955         struct dal_allocation *da;
 956
 957         /* walk the da list in DM */
 958         list_for_each_entry(da, &adev->dm.da_list, list) {
 959                 if (pvMem == da->cpu_ptr) {
 960                         amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);
 961                         list_del(&da->list);
 962                         kfree(da);
 963                         break;
 964                 }
 965         }
 966 }
 967
 968 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)
 969 {
 970         enum dc_irq_source irq_source;
 971         bool ret;
 972
 973         irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
 974
 975         ret = dc_interrupt_set(ctx->dc, irq_source, enable);
 976
 977         DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n",
 978                          enable ? "en" : "dis", ret);
 979         return ret;
 980 }
 981
 982 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream)
 983 {
 984         /* TODO: virtual DPCD */
 985         struct dc_link *link = stream->link;
 986         union down_spread_ctrl old_downspread;
 987         union down_spread_ctrl new_downspread;
 988
 989         if (link->aux_access_disabled)
 990                 return;
 991
 992         if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
 993                                      &old_downspread.raw,
 994                                      sizeof(old_downspread)))
 995                 return;
 996
 997         new_downspread.raw = old_downspread.raw;
 998         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
 999                 (stream->ignore_msa_timing_param) ? 1 : 0;
1000
1001         if (new_downspread.raw != old_downspread.raw)
1002                 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1003                                          &new_downspread.raw,
1004                                          sizeof(new_downspread));
1005 }
1006
1007 bool dm_helpers_dp_handle_test_pattern_request(
1008                 struct dc_context *ctx,
1009                 const struct dc_link *link,
1010                 union link_test_pattern dpcd_test_pattern,
1011                 union test_misc dpcd_test_params)
1012 {
1013         enum dp_test_pattern test_pattern;
1014         enum dp_test_pattern_color_space test_pattern_color_space =
1015                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
1016         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
1017         enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED;
1018         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
1019         struct pipe_ctx *pipe_ctx = NULL;
1020         struct amdgpu_dm_connector *aconnector = link->priv;
1021         int i;
1022
1023         for (i = 0; i < MAX_PIPES; i++) {
1024                 if (pipes[i].stream == NULL)
1025                         continue;
1026
1027                 if (pipes[i].stream->link == link && !pipes[i].top_pipe &&
1028                         !pipes[i].prev_odm_pipe) {
1029                         pipe_ctx = &pipes[i];
1030                         break;
1031                 }
1032         }
1033
1034         if (pipe_ctx == NULL)
1035                 return false;
1036
1037         switch (dpcd_test_pattern.bits.PATTERN) {
1038         case LINK_TEST_PATTERN_COLOR_RAMP:
1039                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1040         break;
1041         case LINK_TEST_PATTERN_VERTICAL_BARS:
1042                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1043         break; /* black and white */
1044         case LINK_TEST_PATTERN_COLOR_SQUARES:
1045                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1046                                 TEST_DYN_RANGE_VESA ?
1047                                 DP_TEST_PATTERN_COLOR_SQUARES :
1048                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1049         break;
1050         default:
1051                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1052         break;
1053         }
1054
1055         if (dpcd_test_params.bits.CLR_FORMAT == 0)
1056                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
1057         else
1058                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
1059                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
1060                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
1061
1062         switch (dpcd_test_params.bits.BPC) {
1063         case 0: // 6 bits
1064                 requestColorDepth = COLOR_DEPTH_666;
1065                 break;
1066         case 1: // 8 bits
1067                 requestColorDepth = COLOR_DEPTH_888;
1068                 break;
1069         case 2: // 10 bits
1070                 requestColorDepth = COLOR_DEPTH_101010;
1071                 break;
1072         case 3: // 12 bits
1073                 requestColorDepth = COLOR_DEPTH_121212;
1074                 break;
1075         default:
1076                 break;
1077         }
1078
1079         switch (dpcd_test_params.bits.CLR_FORMAT) {
1080         case 0:
1081                 requestPixelEncoding = PIXEL_ENCODING_RGB;
1082                 break;
1083         case 1:
1084                 requestPixelEncoding = PIXEL_ENCODING_YCBCR422;
1085                 break;
1086         case 2:
1087                 requestPixelEncoding = PIXEL_ENCODING_YCBCR444;
1088                 break;
1089         default:
1090                 requestPixelEncoding = PIXEL_ENCODING_RGB;
1091                 break;
1092         }
1093
1094         if ((requestColorDepth != COLOR_DEPTH_UNDEFINED
1095                 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth)
1096                 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED
1097                 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {
1098                 DC_LOG_DEBUG("%s: original bpc %d pix encoding %d, changing to %d  %d\n",
1099                                 __func__,
1100                                 pipe_ctx->stream->timing.display_color_depth,
1101                                 pipe_ctx->stream->timing.pixel_encoding,
1102                                 requestColorDepth,
1103                                 requestPixelEncoding);
1104                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
1105                 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;
1106
1107                 dp_update_dsc_config(pipe_ctx);
1108
1109                 aconnector->timing_changed = true;
1110                 /* store current timing */
1111                 if (aconnector->timing_requested)
1112                         *aconnector->timing_requested = pipe_ctx->stream->timing;
1113                 else
1114                         DC_LOG_ERROR("%s: timing storage failed\n", __func__);
1115
1116         }
1117
1118         dc_link_dp_set_test_pattern(
1119                 (struct dc_link *) link,
1120                 test_pattern,
1121                 test_pattern_color_space,
1122                 NULL,
1123                 NULL,
1124                 0);
1125
1126         return false;
1127 }
1128
1129 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)
1130 {
1131        // TODO
1132 }
1133
1134 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
1135 {
1136         /* TODO: add periodic detection implementation */
1137 }
1138
1139 void dm_helpers_dp_mst_update_branch_bandwidth(
1140                 struct dc_context *ctx,
1141                 struct dc_link *link)
1142 {
1143         // TODO
1144 }
1145
1146 static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id)
1147 {
1148         bool ret_val = false;
1149
1150         switch (branch_dev_id) {
1151         case DP_BRANCH_DEVICE_ID_0060AD:
1152                 ret_val = true;
1153                 break;
1154         default:
1155                 break;
1156         }
1157
1158         return ret_val;
1159 }
1160
1161 enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link)
1162 {
1163         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
1164         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
1165
1166         switch (dpcd_caps->dongle_type) {
1167         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
1168                 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true &&
1169                         dpcd_caps->allow_invalid_MSA_timing_param == true &&
1170                         dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id))
1171                         as_type = FREESYNC_TYPE_PCON_IN_WHITELIST;
1172                 break;
1173         default:
1174                 break;
1175         }
1176
1177         return as_type;
1178 }