drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/amdgpu_drm.h>
  25 #include "amdgpu.h"
  26 #include "atomfirmware.h"
  27 #include "amdgpu_atomfirmware.h"
  28 #include "atom.h"
  29 #include "atombios.h"
  30 #include "soc15_hw_ip.h"
  31
  32 union firmware_info {
  33         struct atom_firmware_info_v3_1 v31;
  34         struct atom_firmware_info_v3_2 v32;
  35         struct atom_firmware_info_v3_3 v33;
  36         struct atom_firmware_info_v3_4 v34;
  37         struct atom_firmware_info_v3_5 v35;
  38 };
  39
  40 /*
  41  * Helper function to query firmware capability
  42  *
  43  * @adev: amdgpu_device pointer
  44  *
  45  * Return firmware_capability in firmwareinfo table on success or 0 if not
  46  */
  47 uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev)
  48 {
  49         struct amdgpu_mode_info *mode_info = &adev->mode_info;
  50         int index;
  51         u16 data_offset, size;
  52         union firmware_info *firmware_info;
  53         u8 frev, crev;
  54         u32 fw_cap = 0;
  55
  56         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  57                         firmwareinfo);
  58
  59         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
  60                                 index, &size, &frev, &crev, &data_offset)) {
  61                 /* support firmware_info 3.1 + */
  62                 if ((frev == 3 && crev >= 1) || (frev > 3)) {
  63                         firmware_info = (union firmware_info *)
  64                                 (mode_info->atom_context->bios + data_offset);
  65                         fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability);
  66                 }
  67         }
  68
  69         return fw_cap;
  70 }
  71
  72 /*
  73  * Helper function to query gpu virtualizaiton capability
  74  *
  75  * @adev: amdgpu_device pointer
  76  *
  77  * Return true if gpu virtualization is supported or false if not
  78  */
  79 bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev)
  80 {
  81         u32 fw_cap;
  82
  83         fw_cap = adev->mode_info.firmware_flags;
  84
  85         return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false;
  86 }
  87
  88 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
  89 {
  90         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  91                                                 firmwareinfo);
  92         uint16_t data_offset;
  93
  94         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  95                                           NULL, NULL, &data_offset)) {
  96                 struct atom_firmware_info_v3_1 *firmware_info =
  97                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  98                                                            data_offset);
  99
 100                 adev->bios_scratch_reg_offset =
 101                         le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
 102         }
 103 }
 104
 105 static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev,
 106         struct vram_usagebyfirmware_v2_1 *fw_usage, int *usage_bytes)
 107 {
 108         u32 start_addr, fw_size, drv_size;
 109
 110         start_addr = le32_to_cpu(fw_usage->start_address_in_kb);
 111         fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
 112         drv_size = le16_to_cpu(fw_usage->used_by_driver_in_kb);
 113
 114         DRM_DEBUG("atom firmware v2_1 requested %08x %dkb fw %dkb drv\n",
 115                           start_addr,
 116                           fw_size,
 117                           drv_size);
 118
 119         if ((start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
 120                 (u32)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
 121                 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
 122                 /* Firmware request VRAM reservation for SR-IOV */
 123                 adev->mman.fw_vram_usage_start_offset = (start_addr &
 124                         (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
 125                 adev->mman.fw_vram_usage_size = fw_size << 10;
 126                 /* Use the default scratch size */
 127                 *usage_bytes = 0;
 128         } else {
 129                 *usage_bytes = drv_size << 10;
 130         }
 131         return 0;
 132 }
 133
 134 static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev,
 135                 struct vram_usagebyfirmware_v2_2 *fw_usage, int *usage_bytes)
 136 {
 137         u32 fw_start_addr, fw_size, drv_start_addr, drv_size;
 138
 139         fw_start_addr = le32_to_cpu(fw_usage->fw_region_start_address_in_kb);
 140         fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
 141
 142         drv_start_addr = le32_to_cpu(fw_usage->driver_region0_start_address_in_kb);
 143         drv_size = le32_to_cpu(fw_usage->used_by_driver_region0_in_kb);
 144
 145         DRM_DEBUG("atom requested fw start at %08x %dkb and drv start at %08x %dkb\n",
 146                           fw_start_addr,
 147                           fw_size,
 148                           drv_start_addr,
 149                           drv_size);
 150
 151         if (amdgpu_sriov_vf(adev) &&
 152             ((fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
 153                 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
 154                 /* Firmware request VRAM reservation for SR-IOV */
 155                 adev->mman.fw_vram_usage_start_offset = (fw_start_addr &
 156                         (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
 157                 adev->mman.fw_vram_usage_size = fw_size << 10;
 158         }
 159
 160         if (amdgpu_sriov_vf(adev) &&
 161             ((drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
 162                 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
 163                 /* driver request VRAM reservation for SR-IOV */
 164                 adev->mman.drv_vram_usage_start_offset = (drv_start_addr &
 165                         (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
 166                 adev->mman.drv_vram_usage_size = drv_size << 10;
 167         }
 168
 169         *usage_bytes = 0;
 170         return 0;
 171 }
 172
 173 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
 174 {
 175         struct atom_context *ctx = adev->mode_info.atom_context;
 176         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 177                                                 vram_usagebyfirmware);
 178         struct vram_usagebyfirmware_v2_1 *fw_usage_v2_1;
 179         struct vram_usagebyfirmware_v2_2 *fw_usage_v2_2;
 180         u16 data_offset;
 181         u8 frev, crev;
 182         int usage_bytes = 0;
 183
 184         if (amdgpu_atom_parse_data_header(ctx, index, NULL, &frev, &crev, &data_offset)) {
 185                 if (frev == 2 && crev == 1) {
 186                         fw_usage_v2_1 =
 187                                 (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
 188                         amdgpu_atomfirmware_allocate_fb_v2_1(adev,
 189                                         fw_usage_v2_1,
 190                                         &usage_bytes);
 191                 } else if (frev >= 2 && crev >= 2) {
 192                         fw_usage_v2_2 =
 193                                 (struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset);
 194                         amdgpu_atomfirmware_allocate_fb_v2_2(adev,
 195                                         fw_usage_v2_2,
 196                                         &usage_bytes);
 197                 }
 198         }
 199
 200         ctx->scratch_size_bytes = 0;
 201         if (usage_bytes == 0)
 202                 usage_bytes = 20 * 1024;
 203         /* allocate some scratch memory */
 204         ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
 205         if (!ctx->scratch)
 206                 return -ENOMEM;
 207         ctx->scratch_size_bytes = usage_bytes;
 208         return 0;
 209 }
 210
 211 union igp_info {
 212         struct atom_integrated_system_info_v1_11 v11;
 213         struct atom_integrated_system_info_v1_12 v12;
 214         struct atom_integrated_system_info_v2_1 v21;
 215         struct atom_integrated_system_info_v2_3 v23;
 216 };
 217
 218 union umc_info {
 219         struct atom_umc_info_v3_1 v31;
 220         struct atom_umc_info_v3_2 v32;
 221         struct atom_umc_info_v3_3 v33;
 222         struct atom_umc_info_v4_0 v40;
 223 };
 224
 225 union vram_info {
 226         struct atom_vram_info_header_v2_3 v23;
 227         struct atom_vram_info_header_v2_4 v24;
 228         struct atom_vram_info_header_v2_5 v25;
 229         struct atom_vram_info_header_v2_6 v26;
 230         struct atom_vram_info_header_v3_0 v30;
 231 };
 232
 233 union vram_module {
 234         struct atom_vram_module_v9 v9;
 235         struct atom_vram_module_v10 v10;
 236         struct atom_vram_module_v11 v11;
 237         struct atom_vram_module_v3_0 v30;
 238 };
 239
 240 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
 241                                               int atom_mem_type)
 242 {
 243         int vram_type;
 244
 245         if (adev->flags & AMD_IS_APU) {
 246                 switch (atom_mem_type) {
 247                 case Ddr2MemType:
 248                 case LpDdr2MemType:
 249                         vram_type = AMDGPU_VRAM_TYPE_DDR2;
 250                         break;
 251                 case Ddr3MemType:
 252                 case LpDdr3MemType:
 253                         vram_type = AMDGPU_VRAM_TYPE_DDR3;
 254                         break;
 255                 case Ddr4MemType:
 256                         vram_type = AMDGPU_VRAM_TYPE_DDR4;
 257                         break;
 258                 case LpDdr4MemType:
 259                         vram_type = AMDGPU_VRAM_TYPE_LPDDR4;
 260                         break;
 261                 case Ddr5MemType:
 262                         vram_type = AMDGPU_VRAM_TYPE_DDR5;
 263                         break;
 264                 case LpDdr5MemType:
 265                         vram_type = AMDGPU_VRAM_TYPE_LPDDR5;
 266                         break;
 267                 default:
 268                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 269                         break;
 270                 }
 271         } else {
 272                 switch (atom_mem_type) {
 273                 case ATOM_DGPU_VRAM_TYPE_GDDR5:
 274                         vram_type = AMDGPU_VRAM_TYPE_GDDR5;
 275                         break;
 276                 case ATOM_DGPU_VRAM_TYPE_HBM2:
 277                 case ATOM_DGPU_VRAM_TYPE_HBM2E:
 278                 case ATOM_DGPU_VRAM_TYPE_HBM3:
 279                         vram_type = AMDGPU_VRAM_TYPE_HBM;
 280                         break;
 281                 case ATOM_DGPU_VRAM_TYPE_GDDR6:
 282                         vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 283                         break;
 284                 default:
 285                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 286                         break;
 287                 }
 288         }
 289
 290         return vram_type;
 291 }
 292
 293
 294 int
 295 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
 296                                   int *vram_width, int *vram_type,
 297                                   int *vram_vendor)
 298 {
 299         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 300         int index, i = 0;
 301         u16 data_offset, size;
 302         union igp_info *igp_info;
 303         union vram_info *vram_info;
 304         union vram_module *vram_module;
 305         u8 frev, crev;
 306         u8 mem_type;
 307         u8 mem_vendor;
 308         u32 mem_channel_number;
 309         u32 mem_channel_width;
 310         u32 module_id;
 311
 312         if (adev->flags & AMD_IS_APU)
 313                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 314                                                     integratedsysteminfo);
 315         else
 316                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 317                                                     vram_info);
 318
 319         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 320                                           index, &size,
 321                                           &frev, &crev, &data_offset)) {
 322                 if (adev->flags & AMD_IS_APU) {
 323                         igp_info = (union igp_info *)
 324                                 (mode_info->atom_context->bios + data_offset);
 325                         switch (frev) {
 326                         case 1:
 327                                 switch (crev) {
 328                                 case 11:
 329                                 case 12:
 330                                         mem_channel_number = igp_info->v11.umachannelnumber;
 331                                         if (!mem_channel_number)
 332                                                 mem_channel_number = 1;
 333                                         mem_type = igp_info->v11.memorytype;
 334                                         if (mem_type == LpDdr5MemType)
 335                                                 mem_channel_width = 32;
 336                                         else
 337                                                 mem_channel_width = 64;
 338                                         if (vram_width)
 339                                                 *vram_width = mem_channel_number * mem_channel_width;
 340                                         if (vram_type)
 341                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 342                                         break;
 343                                 default:
 344                                         return -EINVAL;
 345                                 }
 346                                 break;
 347                         case 2:
 348                                 switch (crev) {
 349                                 case 1:
 350                                 case 2:
 351                                         mem_channel_number = igp_info->v21.umachannelnumber;
 352                                         if (!mem_channel_number)
 353                                                 mem_channel_number = 1;
 354                                         mem_type = igp_info->v21.memorytype;
 355                                         if (mem_type == LpDdr5MemType)
 356                                                 mem_channel_width = 32;
 357                                         else
 358                                                 mem_channel_width = 64;
 359                                         if (vram_width)
 360                                                 *vram_width = mem_channel_number * mem_channel_width;
 361                                         if (vram_type)
 362                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 363                                         break;
 364                                 case 3:
 365                                         mem_channel_number = igp_info->v23.umachannelnumber;
 366                                         if (!mem_channel_number)
 367                                                 mem_channel_number = 1;
 368                                         mem_type = igp_info->v23.memorytype;
 369                                         if (mem_type == LpDdr5MemType)
 370                                                 mem_channel_width = 32;
 371                                         else
 372                                                 mem_channel_width = 64;
 373                                         if (vram_width)
 374                                                 *vram_width = mem_channel_number * mem_channel_width;
 375                                         if (vram_type)
 376                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 377                                         break;
 378                                 default:
 379                                         return -EINVAL;
 380                                 }
 381                                 break;
 382                         default:
 383                                 return -EINVAL;
 384                         }
 385                 } else {
 386                         vram_info = (union vram_info *)
 387                                 (mode_info->atom_context->bios + data_offset);
 388                         module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
 389                         if (frev == 3) {
 390                                 switch (crev) {
 391                                 /* v30 */
 392                                 case 0:
 393                                         vram_module = (union vram_module *)vram_info->v30.vram_module;
 394                                         mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF;
 395                                         if (vram_vendor)
 396                                                 *vram_vendor = mem_vendor;
 397                                         mem_type = vram_info->v30.memory_type;
 398                                         if (vram_type)
 399                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 400                                         mem_channel_number = vram_info->v30.channel_num;
 401                                         mem_channel_width = vram_info->v30.channel_width;
 402                                         if (vram_width)
 403                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 404                                         break;
 405                                 default:
 406                                         return -EINVAL;
 407                                 }
 408                         } else if (frev == 2) {
 409                                 switch (crev) {
 410                                 /* v23 */
 411                                 case 3:
 412                                         if (module_id > vram_info->v23.vram_module_num)
 413                                                 module_id = 0;
 414                                         vram_module = (union vram_module *)vram_info->v23.vram_module;
 415                                         while (i < module_id) {
 416                                                 vram_module = (union vram_module *)
 417                                                         ((u8 *)vram_module + vram_module->v9.vram_module_size);
 418                                                 i++;
 419                                         }
 420                                         mem_type = vram_module->v9.memory_type;
 421                                         if (vram_type)
 422                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 423                                         mem_channel_number = vram_module->v9.channel_num;
 424                                         mem_channel_width = vram_module->v9.channel_width;
 425                                         if (vram_width)
 426                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 427                                         mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 428                                         if (vram_vendor)
 429                                                 *vram_vendor = mem_vendor;
 430                                         break;
 431                                 /* v24 */
 432                                 case 4:
 433                                         if (module_id > vram_info->v24.vram_module_num)
 434                                                 module_id = 0;
 435                                         vram_module = (union vram_module *)vram_info->v24.vram_module;
 436                                         while (i < module_id) {
 437                                                 vram_module = (union vram_module *)
 438                                                         ((u8 *)vram_module + vram_module->v10.vram_module_size);
 439                                                 i++;
 440                                         }
 441                                         mem_type = vram_module->v10.memory_type;
 442                                         if (vram_type)
 443                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 444                                         mem_channel_number = vram_module->v10.channel_num;
 445                                         mem_channel_width = vram_module->v10.channel_width;
 446                                         if (vram_width)
 447                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 448                                         mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
 449                                         if (vram_vendor)
 450                                                 *vram_vendor = mem_vendor;
 451                                         break;
 452                                 /* v25 */
 453                                 case 5:
 454                                         if (module_id > vram_info->v25.vram_module_num)
 455                                                 module_id = 0;
 456                                         vram_module = (union vram_module *)vram_info->v25.vram_module;
 457                                         while (i < module_id) {
 458                                                 vram_module = (union vram_module *)
 459                                                         ((u8 *)vram_module + vram_module->v11.vram_module_size);
 460                                                 i++;
 461                                         }
 462                                         mem_type = vram_module->v11.memory_type;
 463                                         if (vram_type)
 464                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 465                                         mem_channel_number = vram_module->v11.channel_num;
 466                                         mem_channel_width = vram_module->v11.channel_width;
 467                                         if (vram_width)
 468                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 469                                         mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
 470                                         if (vram_vendor)
 471                                                 *vram_vendor = mem_vendor;
 472                                         break;
 473                                 /* v26 */
 474                                 case 6:
 475                                         if (module_id > vram_info->v26.vram_module_num)
 476                                                 module_id = 0;
 477                                         vram_module = (union vram_module *)vram_info->v26.vram_module;
 478                                         while (i < module_id) {
 479                                                 vram_module = (union vram_module *)
 480                                                         ((u8 *)vram_module + vram_module->v9.vram_module_size);
 481                                                 i++;
 482                                         }
 483                                         mem_type = vram_module->v9.memory_type;
 484                                         if (vram_type)
 485                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 486                                         mem_channel_number = vram_module->v9.channel_num;
 487                                         mem_channel_width = vram_module->v9.channel_width;
 488                                         if (vram_width)
 489                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 490                                         mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 491                                         if (vram_vendor)
 492                                                 *vram_vendor = mem_vendor;
 493                                         break;
 494                                 default:
 495                                         return -EINVAL;
 496                                 }
 497                         } else {
 498                                 /* invalid frev */
 499                                 return -EINVAL;
 500                         }
 501                 }
 502
 503         }
 504
 505         return 0;
 506 }
 507
 508 /*
 509  * Return true if vbios enabled ecc by default, if umc info table is available
 510  * or false if ecc is not enabled or umc info table is not available
 511  */
 512 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 513 {
 514         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 515         int index;
 516         u16 data_offset, size;
 517         union umc_info *umc_info;
 518         u8 frev, crev;
 519         bool ecc_default_enabled = false;
 520         u8 umc_config;
 521         u32 umc_config1;
 522
 523         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 524                         umc_info);
 525
 526         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 527                                 index, &size, &frev, &crev, &data_offset)) {
 528                 umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset);
 529                 if (frev == 3) {
 530                         switch (crev) {
 531                         case 1:
 532                                 umc_config = le32_to_cpu(umc_info->v31.umc_config);
 533                                 ecc_default_enabled =
 534                                         (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 535                                 break;
 536                         case 2:
 537                                 umc_config = le32_to_cpu(umc_info->v32.umc_config);
 538                                 ecc_default_enabled =
 539                                         (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 540                                 break;
 541                         case 3:
 542                                 umc_config = le32_to_cpu(umc_info->v33.umc_config);
 543                                 umc_config1 = le32_to_cpu(umc_info->v33.umc_config1);
 544                                 ecc_default_enabled =
 545                                         ((umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ||
 546                                          (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false;
 547                                 break;
 548                         default:
 549                                 /* unsupported crev */
 550                                 return false;
 551                         }
 552                 } else if (frev == 4) {
 553                         switch (crev) {
 554                         case 0:
 555                                 umc_config1 = le32_to_cpu(umc_info->v40.umc_config1);
 556                                 ecc_default_enabled =
 557                                         (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false;
 558                                 break;
 559                         default:
 560                                 /* unsupported crev */
 561                                 return false;
 562                         }
 563                 } else {
 564                         /* unsupported frev */
 565                         return false;
 566                 }
 567         }
 568
 569         return ecc_default_enabled;
 570 }
 571
 572 /*
 573  * Helper function to query sram ecc capablity
 574  *
 575  * @adev: amdgpu_device pointer
 576  *
 577  * Return true if vbios supports sram ecc or false if not
 578  */
 579 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
 580 {
 581         u32 fw_cap;
 582
 583         fw_cap = adev->mode_info.firmware_flags;
 584
 585         return (fw_cap & ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
 586 }
 587
 588 /*
 589  * Helper function to query dynamic boot config capability
 590  *
 591  * @adev: amdgpu_device pointer
 592  *
 593  * Return true if vbios supports dynamic boot config or false if not
 594  */
 595 bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev)
 596 {
 597         u32 fw_cap;
 598
 599         fw_cap = adev->mode_info.firmware_flags;
 600
 601         return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false;
 602 }
 603
 604 /**
 605  * amdgpu_atomfirmware_ras_rom_addr -- Get the RAS EEPROM addr from VBIOS
 606  * @adev: amdgpu_device pointer
 607  * @i2c_address: pointer to u8; if not NULL, will contain
 608  *    the RAS EEPROM address if the function returns true
 609  *
 610  * Return true if VBIOS supports RAS EEPROM address reporting,
 611  * else return false. If true and @i2c_address is not NULL,
 612  * will contain the RAS ROM address.
 613  */
 614 bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev,
 615                                       u8 *i2c_address)
 616 {
 617         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 618         int index;
 619         u16 data_offset, size;
 620         union firmware_info *firmware_info;
 621         u8 frev, crev;
 622
 623         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 624                                             firmwareinfo);
 625
 626         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
 627                                           index, &size, &frev, &crev,
 628                                           &data_offset)) {
 629                 /* support firmware_info 3.4 + */
 630                 if ((frev == 3 && crev >= 4) || (frev > 3)) {
 631                         firmware_info = (union firmware_info *)
 632                                 (mode_info->atom_context->bios + data_offset);
 633                         /* The ras_rom_i2c_slave_addr should ideally
 634                          * be a 19-bit EEPROM address, which would be
 635                          * used as is by the driver; see top of
 636                          * amdgpu_eeprom.c.
 637                          *
 638                          * When this is the case, 0 is of course a
 639                          * valid RAS EEPROM address, in which case,
 640                          * we'll drop the first "if (firm...)" and only
 641                          * leave the check for the pointer.
 642                          *
 643                          * The reason this works right now is because
 644                          * ras_rom_i2c_slave_addr contains the EEPROM
 645                          * device type qualifier 1010b in the top 4
 646                          * bits.
 647                          */
 648                         if (firmware_info->v34.ras_rom_i2c_slave_addr) {
 649                                 if (i2c_address)
 650                                         *i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr;
 651                                 return true;
 652                         }
 653                 }
 654         }
 655
 656         return false;
 657 }
 658
 659
 660 union smu_info {
 661         struct atom_smu_info_v3_1 v31;
 662         struct atom_smu_info_v4_0 v40;
 663 };
 664
 665 union gfx_info {
 666         struct atom_gfx_info_v2_2 v22;
 667         struct atom_gfx_info_v2_4 v24;
 668         struct atom_gfx_info_v2_7 v27;
 669         struct atom_gfx_info_v3_0 v30;
 670 };
 671
 672 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 673 {
 674         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 675         struct amdgpu_pll *spll = &adev->clock.spll;
 676         struct amdgpu_pll *mpll = &adev->clock.mpll;
 677         uint8_t frev, crev;
 678         uint16_t data_offset;
 679         int ret = -EINVAL, index;
 680
 681         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 682                                             firmwareinfo);
 683         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 684                                    &frev, &crev, &data_offset)) {
 685                 union firmware_info *firmware_info =
 686                         (union firmware_info *)(mode_info->atom_context->bios +
 687                                                 data_offset);
 688
 689                 adev->clock.default_sclk =
 690                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 691                 adev->clock.default_mclk =
 692                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 693
 694                 adev->pm.current_sclk = adev->clock.default_sclk;
 695                 adev->pm.current_mclk = adev->clock.default_mclk;
 696
 697                 ret = 0;
 698         }
 699
 700         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 701                                             smu_info);
 702         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 703                                    &frev, &crev, &data_offset)) {
 704                 union smu_info *smu_info =
 705                         (union smu_info *)(mode_info->atom_context->bios +
 706                                            data_offset);
 707
 708                 /* system clock */
 709                 if (frev == 3)
 710                         spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
 711                 else if (frev == 4)
 712                         spll->reference_freq = le32_to_cpu(smu_info->v40.core_refclk_10khz);
 713
 714                 spll->reference_div = 0;
 715                 spll->min_post_div = 1;
 716                 spll->max_post_div = 1;
 717                 spll->min_ref_div = 2;
 718                 spll->max_ref_div = 0xff;
 719                 spll->min_feedback_div = 4;
 720                 spll->max_feedback_div = 0xff;
 721                 spll->best_vco = 0;
 722
 723                 ret = 0;
 724         }
 725
 726         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 727                                             umc_info);
 728         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 729                                    &frev, &crev, &data_offset)) {
 730                 union umc_info *umc_info =
 731                         (union umc_info *)(mode_info->atom_context->bios +
 732                                            data_offset);
 733
 734                 /* memory clock */
 735                 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
 736
 737                 mpll->reference_div = 0;
 738                 mpll->min_post_div = 1;
 739                 mpll->max_post_div = 1;
 740                 mpll->min_ref_div = 2;
 741                 mpll->max_ref_div = 0xff;
 742                 mpll->min_feedback_div = 4;
 743                 mpll->max_feedback_div = 0xff;
 744                 mpll->best_vco = 0;
 745
 746                 ret = 0;
 747         }
 748
 749         /* if asic is Navi+, the rlc reference clock is used for system clock
 750          * from vbios gfx_info table */
 751         if (adev->asic_type >= CHIP_NAVI10) {
 752                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 753                                                    gfx_info);
 754                 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 755                                           &frev, &crev, &data_offset)) {
 756                         union gfx_info *gfx_info = (union gfx_info *)
 757                                 (mode_info->atom_context->bios + data_offset);
 758                         if ((frev == 3) ||
 759                             (frev == 2 && crev == 6)) {
 760                                 spll->reference_freq = le32_to_cpu(gfx_info->v30.golden_tsc_count_lower_refclk);
 761                                 ret = 0;
 762                         } else if ((frev == 2) &&
 763                                    (crev >= 2) &&
 764                                    (crev != 6)) {
 765                                 spll->reference_freq = le32_to_cpu(gfx_info->v22.rlc_gpu_timer_refclk);
 766                                 ret = 0;
 767                         } else {
 768                                 BUG();
 769                         }
 770                 }
 771         }
 772
 773         return ret;
 774 }
 775
 776 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
 777 {
 778         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 779         int index;
 780         uint8_t frev, crev;
 781         uint16_t data_offset;
 782
 783         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 784                                             gfx_info);
 785         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 786                                    &frev, &crev, &data_offset)) {
 787                 union gfx_info *gfx_info = (union gfx_info *)
 788                         (mode_info->atom_context->bios + data_offset);
 789                 if (frev == 2) {
 790                         switch (crev) {
 791                         case 4:
 792                                 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
 793                                 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
 794                                 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
 795                                 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
 796                                 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
 797                                 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
 798                                 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
 799                                 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
 800                                 adev->gfx.config.gs_prim_buffer_depth =
 801                                         le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
 802                                 adev->gfx.config.double_offchip_lds_buf =
 803                                         gfx_info->v24.gc_double_offchip_lds_buffer;
 804                                 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
 805                                 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
 806                                 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
 807                                 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
 808                                 return 0;
 809                         case 7:
 810                                 adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines;
 811                                 adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh;
 812                                 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se;
 813                                 adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se;
 814                                 adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches;
 815                                 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs);
 816                                 adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds;
 817                                 adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth;
 818                                 adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth);
 819                                 adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer;
 820                                 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size);
 821                                 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd);
 822                                 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu;
 823                                 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size);
 824                                 return 0;
 825                         default:
 826                                 return -EINVAL;
 827                         }
 828                 } else if (frev == 3) {
 829                         switch (crev) {
 830                         case 0:
 831                                 adev->gfx.config.max_shader_engines = gfx_info->v30.max_shader_engines;
 832                                 adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh;
 833                                 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se;
 834                                 adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se;
 835                                 adev->gfx.config.max_texture_channel_caches = gfx_info->v30.max_texture_channel_caches;
 836                                 return 0;
 837                         default:
 838                                 return -EINVAL;
 839                         }
 840                 } else {
 841                         return -EINVAL;
 842                 }
 843
 844         }
 845         return -EINVAL;
 846 }
 847
 848 /*
 849  * Helper function to query two stage mem training capability
 850  *
 851  * @adev: amdgpu_device pointer
 852  *
 853  * Return true if two stage mem training is supported or false if not
 854  */
 855 bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev)
 856 {
 857         u32 fw_cap;
 858
 859         fw_cap = adev->mode_info.firmware_flags;
 860
 861         return (fw_cap & ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) ? true : false;
 862 }
 863
 864 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
 865 {
 866         struct atom_context *ctx = adev->mode_info.atom_context;
 867         union firmware_info *firmware_info;
 868         int index;
 869         u16 data_offset, size;
 870         u8 frev, crev;
 871         int fw_reserved_fb_size;
 872
 873         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 874                         firmwareinfo);
 875
 876         if (!amdgpu_atom_parse_data_header(ctx, index, &size,
 877                                 &frev, &crev, &data_offset))
 878                 /* fail to parse data_header */
 879                 return 0;
 880
 881         firmware_info = (union firmware_info *)(ctx->bios + data_offset);
 882
 883         if (frev != 3)
 884                 return -EINVAL;
 885
 886         switch (crev) {
 887         case 4:
 888                 fw_reserved_fb_size =
 889                         (firmware_info->v34.fw_reserved_size_in_kb << 10);
 890                 break;
 891         case 5:
 892                 fw_reserved_fb_size =
 893                         (firmware_info->v35.fw_reserved_size_in_kb << 10);
 894                 break;
 895         default:
 896                 fw_reserved_fb_size = 0;
 897                 break;
 898         }
 899
 900         return fw_reserved_fb_size;
 901 }
 902
 903 /*
 904  * Helper function to execute asic_init table
 905  *
 906  * @adev: amdgpu_device pointer
 907  * @fb_reset: flag to indicate whether fb is reset or not
 908  *
 909  * Return 0 if succeed, otherwise failed
 910  */
 911 int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset)
 912 {
 913         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 914         struct atom_context *ctx;
 915         uint8_t frev, crev;
 916         uint16_t data_offset;
 917         uint32_t bootup_sclk_in10khz, bootup_mclk_in10khz;
 918         struct asic_init_ps_allocation_v2_1 asic_init_ps_v2_1;
 919         int index;
 920
 921         if (!mode_info)
 922                 return -EINVAL;
 923
 924         ctx = mode_info->atom_context;
 925         if (!ctx)
 926                 return -EINVAL;
 927
 928         /* query bootup sclk/mclk from firmware_info table */
 929         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 930                                             firmwareinfo);
 931         if (amdgpu_atom_parse_data_header(ctx, index, NULL,
 932                                 &frev, &crev, &data_offset)) {
 933                 union firmware_info *firmware_info =
 934                         (union firmware_info *)(ctx->bios +
 935                                                 data_offset);
 936
 937                 bootup_sclk_in10khz =
 938                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 939                 bootup_mclk_in10khz =
 940                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 941         } else {
 942                 return -EINVAL;
 943         }
 944
 945         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 946                                         asic_init);
 947         if (amdgpu_atom_parse_cmd_header(mode_info->atom_context, index, &frev, &crev)) {
 948                 if (frev == 2 && crev >= 1) {
 949                         memset(&asic_init_ps_v2_1, 0, sizeof(asic_init_ps_v2_1));
 950                         asic_init_ps_v2_1.param.engineparam.sclkfreqin10khz = bootup_sclk_in10khz;
 951                         asic_init_ps_v2_1.param.memparam.mclkfreqin10khz = bootup_mclk_in10khz;
 952                         asic_init_ps_v2_1.param.engineparam.engineflag = b3NORMAL_ENGINE_INIT;
 953                         if (!fb_reset)
 954                                 asic_init_ps_v2_1.param.memparam.memflag = b3DRAM_SELF_REFRESH_EXIT;
 955                         else
 956                                 asic_init_ps_v2_1.param.memparam.memflag = 0;
 957                 } else {
 958                         return -EINVAL;
 959                 }
 960         } else {
 961                 return -EINVAL;
 962         }
 963
 964         return amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, (uint32_t *)&asic_init_ps_v2_1,
 965                 sizeof(asic_init_ps_v2_1));
 966 }