2 * CAN bus driver for Bosch C_CAN controller
4 * Copyright (C) 2010 ST Microelectronics
7 * Borrowed heavily from the C_CAN driver originally written by:
12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver
18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19 * Bosch C_CAN user manual can be obtained from:
20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21 * users_manual_c_can.pdf
23 * This file is licensed under the terms of the GNU General Public
24 * License version 2. This program is licensed "as is" without any
25 * warranty of any kind, whether express or implied.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/netdevice.h>
33 #include <linux/if_arp.h>
34 #include <linux/if_ether.h>
35 #include <linux/list.h>
37 #include <linux/pm_runtime.h>
39 #include <linux/can.h>
40 #include <linux/can/dev.h>
41 #include <linux/can/error.h>
42 #include <linux/can/led.h>
46 /* Number of interface registers */
47 #define IF_ENUM_REG_LEN 11
48 #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
50 /* control extension register D_CAN specific */
51 #define CONTROL_EX_PDR BIT(8)
53 /* control register */
54 #define CONTROL_TEST BIT(7)
55 #define CONTROL_CCE BIT(6)
56 #define CONTROL_DISABLE_AR BIT(5)
57 #define CONTROL_ENABLE_AR (0 << 5)
58 #define CONTROL_EIE BIT(3)
59 #define CONTROL_SIE BIT(2)
60 #define CONTROL_IE BIT(1)
61 #define CONTROL_INIT BIT(0)
64 #define TEST_RX BIT(7)
65 #define TEST_TX1 BIT(6)
66 #define TEST_TX2 BIT(5)
67 #define TEST_LBACK BIT(4)
68 #define TEST_SILENT BIT(3)
69 #define TEST_BASIC BIT(2)
72 #define STATUS_PDA BIT(10)
73 #define STATUS_BOFF BIT(7)
74 #define STATUS_EWARN BIT(6)
75 #define STATUS_EPASS BIT(5)
76 #define STATUS_RXOK BIT(4)
77 #define STATUS_TXOK BIT(3)
79 /* error counter register */
80 #define ERR_CNT_TEC_MASK 0xff
81 #define ERR_CNT_TEC_SHIFT 0
82 #define ERR_CNT_REC_SHIFT 8
83 #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
84 #define ERR_CNT_RP_SHIFT 15
85 #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
87 /* bit-timing register */
88 #define BTR_BRP_MASK 0x3f
89 #define BTR_BRP_SHIFT 0
90 #define BTR_SJW_SHIFT 6
91 #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
92 #define BTR_TSEG1_SHIFT 8
93 #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
94 #define BTR_TSEG2_SHIFT 12
95 #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
97 /* brp extension register */
98 #define BRP_EXT_BRPE_MASK 0x0f
99 #define BRP_EXT_BRPE_SHIFT 0
101 /* IFx command request */
102 #define IF_COMR_BUSY BIT(15)
104 /* IFx command mask */
105 #define IF_COMM_WR BIT(7)
106 #define IF_COMM_MASK BIT(6)
107 #define IF_COMM_ARB BIT(5)
108 #define IF_COMM_CONTROL BIT(4)
109 #define IF_COMM_CLR_INT_PND BIT(3)
110 #define IF_COMM_TXRQST BIT(2)
111 #define IF_COMM_DATAA BIT(1)
112 #define IF_COMM_DATAB BIT(0)
113 #define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \
114 IF_COMM_CONTROL | IF_COMM_TXRQST | \
115 IF_COMM_DATAA | IF_COMM_DATAB)
117 /* IFx arbitration */
118 #define IF_ARB_MSGVAL BIT(15)
119 #define IF_ARB_MSGXTD BIT(14)
120 #define IF_ARB_TRANSMIT BIT(13)
122 /* IFx message control */
123 #define IF_MCONT_NEWDAT BIT(15)
124 #define IF_MCONT_MSGLST BIT(14)
125 #define IF_MCONT_CLR_MSGLST (0 << 14)
126 #define IF_MCONT_INTPND BIT(13)
127 #define IF_MCONT_UMASK BIT(12)
128 #define IF_MCONT_TXIE BIT(11)
129 #define IF_MCONT_RXIE BIT(10)
130 #define IF_MCONT_RMTEN BIT(9)
131 #define IF_MCONT_TXRQST BIT(8)
132 #define IF_MCONT_EOB BIT(7)
133 #define IF_MCONT_DLC_MASK 0xf
136 * IFx register masks:
137 * allow easy operation on 16-bit registers when the
138 * argument is 32-bit instead
140 #define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF)
141 #define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16)
143 /* message object split */
144 #define C_CAN_NO_OF_OBJECTS 32
145 #define C_CAN_MSG_OBJ_RX_NUM 16
146 #define C_CAN_MSG_OBJ_TX_NUM 16
148 #define C_CAN_MSG_OBJ_RX_FIRST 1
149 #define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \
150 C_CAN_MSG_OBJ_RX_NUM - 1)
152 #define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1)
153 #define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \
154 C_CAN_MSG_OBJ_TX_NUM - 1)
156 #define C_CAN_MSG_OBJ_RX_SPLIT 9
157 #define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1)
159 #define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1)
160 #define RECEIVE_OBJECT_BITS 0x0000ffff
162 /* status interrupt */
163 #define STATUS_INTERRUPT 0x8000
165 /* global interrupt masks */
166 #define ENABLE_ALL_INTERRUPTS 1
167 #define DISABLE_ALL_INTERRUPTS 0
169 /* minimum timeout for checking BUSY status */
170 #define MIN_TIMEOUT_VALUE 6
172 /* Wait for ~1 sec for INIT bit */
173 #define INIT_WAIT_MS 1000
176 #define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
178 /* c_can lec values */
179 enum c_can_lec_type {
192 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
194 enum c_can_bus_error_types {
201 static const struct can_bittiming_const c_can_bittiming_const = {
202 .name = KBUILD_MODNAME,
203 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
205 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
209 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
213 static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv)
216 pm_runtime_enable(priv->device);
219 static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv)
222 pm_runtime_disable(priv->device);
225 static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv)
228 pm_runtime_get_sync(priv->device);
231 static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv)
234 pm_runtime_put_sync(priv->device);
237 static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable)
240 priv->raminit(priv, enable);
243 static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
245 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
246 C_CAN_MSG_OBJ_TX_FIRST;
249 static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv)
251 return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) +
252 C_CAN_MSG_OBJ_TX_FIRST;
255 static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index)
257 u32 val = priv->read_reg(priv, index);
258 val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
262 static void c_can_enable_all_interrupts(struct c_can_priv *priv,
265 unsigned int cntrl_save = priv->read_reg(priv,
269 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE);
271 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE);
273 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save);
276 static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface)
278 int count = MIN_TIMEOUT_VALUE;
280 while (count && priv->read_reg(priv,
281 C_CAN_IFACE(COMREQ_REG, iface)) &
293 static inline void c_can_object_get(struct net_device *dev,
294 int iface, int objno, int mask)
296 struct c_can_priv *priv = netdev_priv(dev);
299 * As per specs, after writting the message object number in the
300 * IF command request register the transfer b/w interface
301 * register and message RAM must be complete in 6 CAN-CLK
304 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface),
305 IFX_WRITE_LOW_16BIT(mask));
306 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
307 IFX_WRITE_LOW_16BIT(objno));
309 if (c_can_msg_obj_is_busy(priv, iface))
310 netdev_err(dev, "timed out in object get\n");
313 static inline void c_can_object_put(struct net_device *dev,
314 int iface, int objno, int mask)
316 struct c_can_priv *priv = netdev_priv(dev);
319 * As per specs, after writting the message object number in the
320 * IF command request register the transfer b/w interface
321 * register and message RAM must be complete in 6 CAN-CLK
324 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface),
325 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask)));
326 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
327 IFX_WRITE_LOW_16BIT(objno));
329 if (c_can_msg_obj_is_busy(priv, iface))
330 netdev_err(dev, "timed out in object put\n");
333 static void c_can_write_msg_object(struct net_device *dev,
334 int iface, struct can_frame *frame, int objno)
339 struct c_can_priv *priv = netdev_priv(dev);
341 if (!(frame->can_id & CAN_RTR_FLAG))
342 flags |= IF_ARB_TRANSMIT;
344 if (frame->can_id & CAN_EFF_FLAG) {
345 id = frame->can_id & CAN_EFF_MASK;
346 flags |= IF_ARB_MSGXTD;
348 id = ((frame->can_id & CAN_SFF_MASK) << 18);
350 flags |= IF_ARB_MSGVAL;
352 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface),
353 IFX_WRITE_LOW_16BIT(id));
354 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags |
355 IFX_WRITE_HIGH_16BIT(id));
357 for (i = 0; i < frame->can_dlc; i += 2) {
358 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2,
359 frame->data[i] | (frame->data[i + 1] << 8));
362 /* enable interrupt for this message object */
363 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
364 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB |
366 c_can_object_put(dev, iface, objno, IF_COMM_ALL);
369 static inline void c_can_mark_rx_msg_obj(struct net_device *dev,
370 int iface, int ctrl_mask,
373 struct c_can_priv *priv = netdev_priv(dev);
375 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
376 ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND));
377 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
381 static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev,
386 struct c_can_priv *priv = netdev_priv(dev);
388 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) {
389 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
390 ctrl_mask & ~(IF_MCONT_MSGLST |
391 IF_MCONT_INTPND | IF_MCONT_NEWDAT));
392 c_can_object_put(dev, iface, i, IF_COMM_CONTROL);
396 static inline void c_can_activate_rx_msg_obj(struct net_device *dev,
397 int iface, int ctrl_mask,
400 struct c_can_priv *priv = netdev_priv(dev);
402 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
403 ctrl_mask & ~(IF_MCONT_MSGLST |
404 IF_MCONT_INTPND | IF_MCONT_NEWDAT));
405 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
408 static void c_can_handle_lost_msg_obj(struct net_device *dev,
409 int iface, int objno)
411 struct c_can_priv *priv = netdev_priv(dev);
412 struct net_device_stats *stats = &dev->stats;
414 struct can_frame *frame;
416 netdev_err(dev, "msg lost in buffer %d\n", objno);
418 c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
420 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
421 IF_MCONT_CLR_MSGLST);
423 c_can_object_put(dev, 0, objno, IF_COMM_CONTROL);
425 /* create an error msg */
426 skb = alloc_can_err_skb(dev, &frame);
430 frame->can_id |= CAN_ERR_CRTL;
431 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
433 stats->rx_over_errors++;
435 netif_receive_skb(skb);
438 static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl)
443 struct c_can_priv *priv = netdev_priv(dev);
444 struct net_device_stats *stats = &dev->stats;
446 struct can_frame *frame;
448 skb = alloc_can_skb(dev, &frame);
454 frame->can_dlc = get_can_dlc(ctrl & 0x0F);
456 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface));
457 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) |
460 if (flags & IF_ARB_MSGXTD)
461 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG;
463 frame->can_id = (val >> 18) & CAN_SFF_MASK;
465 if (flags & IF_ARB_TRANSMIT)
466 frame->can_id |= CAN_RTR_FLAG;
468 for (i = 0; i < frame->can_dlc; i += 2) {
469 data = priv->read_reg(priv,
470 C_CAN_IFACE(DATA1_REG, iface) + i / 2);
471 frame->data[i] = data;
472 frame->data[i + 1] = data >> 8;
476 netif_receive_skb(skb);
479 stats->rx_bytes += frame->can_dlc;
481 can_led_event(dev, CAN_LED_EVENT_RX);
486 static void c_can_setup_receive_object(struct net_device *dev, int iface,
487 int objno, unsigned int mask,
488 unsigned int id, unsigned int mcont)
490 struct c_can_priv *priv = netdev_priv(dev);
492 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface),
493 IFX_WRITE_LOW_16BIT(mask));
495 /* According to C_CAN documentation, the reserved bit
496 * in IFx_MASK2 register is fixed 1
498 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface),
499 IFX_WRITE_HIGH_16BIT(mask) | BIT(13));
501 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface),
502 IFX_WRITE_LOW_16BIT(id));
503 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface),
504 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id)));
506 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
507 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
509 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
510 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG));
513 static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno)
515 struct c_can_priv *priv = netdev_priv(dev);
517 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
518 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0);
519 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
521 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL);
523 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
524 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG));
527 static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno)
529 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
532 * as transmission request register's bit n-1 corresponds to
533 * message object n, we need to handle the same properly.
535 if (val & (1 << (objno - 1)))
541 static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
542 struct net_device *dev)
545 struct c_can_priv *priv = netdev_priv(dev);
546 struct can_frame *frame = (struct can_frame *)skb->data;
548 if (can_dropped_invalid_skb(dev, skb))
551 msg_obj_no = get_tx_next_msg_obj(priv);
553 /* prepare message object for transmission */
554 c_can_write_msg_object(dev, 0, frame, msg_obj_no);
555 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
558 * we have to stop the queue in case of a wrap around or
559 * if the next TX message object is still in use
562 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) ||
563 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0)
564 netif_stop_queue(dev);
569 static int c_can_set_bittiming(struct net_device *dev)
571 unsigned int reg_btr, reg_brpe, ctrl_save;
572 u8 brp, brpe, sjw, tseg1, tseg2;
574 struct c_can_priv *priv = netdev_priv(dev);
575 const struct can_bittiming *bt = &priv->can.bittiming;
577 /* c_can provides a 6-bit brp and 4-bit brpe fields */
578 ten_bit_brp = bt->brp - 1;
579 brp = ten_bit_brp & BTR_BRP_MASK;
580 brpe = ten_bit_brp >> 6;
583 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
584 tseg2 = bt->phase_seg2 - 1;
585 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
586 (tseg2 << BTR_TSEG2_SHIFT);
587 reg_brpe = brpe & BRP_EXT_BRPE_MASK;
590 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
592 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
593 priv->write_reg(priv, C_CAN_CTRL_REG,
594 ctrl_save | CONTROL_CCE | CONTROL_INIT);
595 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr);
596 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe);
597 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save);
603 * Configure C_CAN message objects for Tx and Rx purposes:
604 * C_CAN provides a total of 32 message objects that can be configured
605 * either for Tx or Rx purposes. Here the first 16 message objects are used as
606 * a reception FIFO. The end of reception FIFO is signified by the EoB bit
607 * being SET. The remaining 16 message objects are kept aside for Tx purposes.
608 * See user guide document for further details on configuring message
611 static void c_can_configure_msg_objects(struct net_device *dev)
615 /* first invalidate all message objects */
616 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++)
617 c_can_inval_msg_object(dev, 0, i);
619 /* setup receive message objects */
620 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++)
621 c_can_setup_receive_object(dev, 0, i, 0, 0,
622 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB);
624 c_can_setup_receive_object(dev, 0, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
625 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK);
629 * Configure C_CAN chip:
630 * - enable/disable auto-retransmission
631 * - set operating mode
632 * - configure message objects
634 static void c_can_chip_config(struct net_device *dev)
636 struct c_can_priv *priv = netdev_priv(dev);
638 /* enable automatic retransmission */
639 priv->write_reg(priv, C_CAN_CTRL_REG,
642 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) &&
643 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) {
644 /* loopback + silent mode : useful for hot self-test */
645 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
646 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
647 priv->write_reg(priv, C_CAN_TEST_REG,
648 TEST_LBACK | TEST_SILENT);
649 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
650 /* loopback mode : useful for self-test function */
651 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
652 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
653 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
654 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
655 /* silent mode : bus-monitoring mode */
656 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
657 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
658 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
661 priv->write_reg(priv, C_CAN_CTRL_REG,
662 CONTROL_EIE | CONTROL_SIE | CONTROL_IE);
664 /* configure message objects */
665 c_can_configure_msg_objects(dev);
667 /* set a `lec` value so that we can check for updates later */
668 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
670 /* set bittiming params */
671 c_can_set_bittiming(dev);
674 static void c_can_start(struct net_device *dev)
676 struct c_can_priv *priv = netdev_priv(dev);
678 /* basic c_can configuration */
679 c_can_chip_config(dev);
681 priv->can.state = CAN_STATE_ERROR_ACTIVE;
683 /* reset tx helper pointers */
684 priv->tx_next = priv->tx_echo = 0;
686 /* enable status change, error and module interrupts */
687 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
690 static void c_can_stop(struct net_device *dev)
692 struct c_can_priv *priv = netdev_priv(dev);
694 /* disable all interrupts */
695 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
697 /* set the state as STOPPED */
698 priv->can.state = CAN_STATE_STOPPED;
701 static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
706 netif_wake_queue(dev);
715 static int c_can_get_berr_counter(const struct net_device *dev,
716 struct can_berr_counter *bec)
718 unsigned int reg_err_counter;
719 struct c_can_priv *priv = netdev_priv(dev);
721 c_can_pm_runtime_get_sync(priv);
723 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
724 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
726 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
728 c_can_pm_runtime_put_sync(priv);
734 * theory of operation:
736 * priv->tx_echo holds the number of the oldest can_frame put for
737 * transmission into the hardware, but not yet ACKed by the CAN tx
740 * We iterate from priv->tx_echo to priv->tx_next and check if the
741 * packet has been transmitted, echo it back to the CAN framework.
742 * If we discover a not yet transmitted packet, stop looking for more.
744 static void c_can_do_tx(struct net_device *dev)
748 struct c_can_priv *priv = netdev_priv(dev);
749 struct net_device_stats *stats = &dev->stats;
751 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
752 msg_obj_no = get_tx_echo_msg_obj(priv);
753 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
754 if (!(val & (1 << (msg_obj_no - 1)))) {
755 can_get_echo_skb(dev,
756 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
757 stats->tx_bytes += priv->read_reg(priv,
758 C_CAN_IFACE(MSGCTRL_REG, 0))
761 can_led_event(dev, CAN_LED_EVENT_TX);
762 c_can_inval_msg_object(dev, 0, msg_obj_no);
768 /* restart queue if wrap-up or if queue stalled on last pkt */
769 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) ||
770 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0))
771 netif_wake_queue(dev);
775 * theory of operation:
777 * c_can core saves a received CAN message into the first free message
778 * object it finds free (starting with the lowest). Bits NEWDAT and
779 * INTPND are set for this message object indicating that a new message
780 * has arrived. To work-around this issue, we keep two groups of message
781 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
783 * To ensure in-order frame reception we use the following
784 * approach while re-activating a message object to receive further
786 * - if the current message object number is lower than
787 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing
789 * - if the current message object number is equal to
790 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower
791 * receive message objects.
792 * - if the current message object number is greater than
793 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of
794 * only this message object.
796 static int c_can_do_rx_poll(struct net_device *dev, int quota)
799 unsigned int msg_obj, msg_ctrl_save;
800 struct c_can_priv *priv = netdev_priv(dev);
801 u32 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG);
803 for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST;
804 msg_obj <= C_CAN_MSG_OBJ_RX_LAST && quota > 0;
805 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG),
808 * as interrupt pending register's bit n-1 corresponds to
809 * message object n, we need to handle the same properly.
811 if (val & (1 << (msg_obj - 1))) {
812 c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL &
814 msg_ctrl_save = priv->read_reg(priv,
815 C_CAN_IFACE(MSGCTRL_REG, 0));
817 if (msg_ctrl_save & IF_MCONT_EOB)
820 if (msg_ctrl_save & IF_MCONT_MSGLST) {
821 c_can_handle_lost_msg_obj(dev, 0, msg_obj);
827 if (!(msg_ctrl_save & IF_MCONT_NEWDAT))
830 /* read the data from the message object */
831 c_can_read_msg_object(dev, 0, msg_ctrl_save);
833 if (msg_obj < C_CAN_MSG_RX_LOW_LAST)
834 c_can_mark_rx_msg_obj(dev, 0,
835 msg_ctrl_save, msg_obj);
836 else if (msg_obj > C_CAN_MSG_RX_LOW_LAST)
837 /* activate this msg obj */
838 c_can_activate_rx_msg_obj(dev, 0,
839 msg_ctrl_save, msg_obj);
840 else if (msg_obj == C_CAN_MSG_RX_LOW_LAST)
841 /* activate all lower message objects */
842 c_can_activate_all_lower_rx_msg_obj(dev,
853 static inline int c_can_has_and_handle_berr(struct c_can_priv *priv)
855 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
856 (priv->current_status & LEC_UNUSED);
859 static int c_can_handle_state_change(struct net_device *dev,
860 enum c_can_bus_error_types error_type)
862 unsigned int reg_err_counter;
863 unsigned int rx_err_passive;
864 struct c_can_priv *priv = netdev_priv(dev);
865 struct net_device_stats *stats = &dev->stats;
866 struct can_frame *cf;
868 struct can_berr_counter bec;
870 /* propagate the error condition to the CAN stack */
871 skb = alloc_can_err_skb(dev, &cf);
875 c_can_get_berr_counter(dev, &bec);
876 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
877 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
880 switch (error_type) {
881 case C_CAN_ERROR_WARNING:
882 /* error warning state */
883 priv->can.can_stats.error_warning++;
884 priv->can.state = CAN_STATE_ERROR_WARNING;
885 cf->can_id |= CAN_ERR_CRTL;
886 cf->data[1] = (bec.txerr > bec.rxerr) ?
887 CAN_ERR_CRTL_TX_WARNING :
888 CAN_ERR_CRTL_RX_WARNING;
889 cf->data[6] = bec.txerr;
890 cf->data[7] = bec.rxerr;
893 case C_CAN_ERROR_PASSIVE:
894 /* error passive state */
895 priv->can.can_stats.error_passive++;
896 priv->can.state = CAN_STATE_ERROR_PASSIVE;
897 cf->can_id |= CAN_ERR_CRTL;
899 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
901 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
903 cf->data[6] = bec.txerr;
904 cf->data[7] = bec.rxerr;
908 priv->can.state = CAN_STATE_BUS_OFF;
909 cf->can_id |= CAN_ERR_BUSOFF;
911 * disable all interrupts in bus-off mode to ensure that
912 * the CPU is not hogged down
914 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
921 netif_receive_skb(skb);
923 stats->rx_bytes += cf->can_dlc;
928 static int c_can_handle_bus_err(struct net_device *dev,
929 enum c_can_lec_type lec_type)
931 struct c_can_priv *priv = netdev_priv(dev);
932 struct net_device_stats *stats = &dev->stats;
933 struct can_frame *cf;
937 * early exit if no lec update or no error.
938 * no lec update means that no CAN bus event has been detected
939 * since CPU wrote 0x7 value to status reg.
941 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
944 /* propagate the error condition to the CAN stack */
945 skb = alloc_can_err_skb(dev, &cf);
950 * check for 'last error code' which tells us the
951 * type of the last error to occur on the CAN bus
954 /* common for all type of bus errors */
955 priv->can.can_stats.bus_error++;
957 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
958 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
961 case LEC_STUFF_ERROR:
962 netdev_dbg(dev, "stuff error\n");
963 cf->data[2] |= CAN_ERR_PROT_STUFF;
966 netdev_dbg(dev, "form error\n");
967 cf->data[2] |= CAN_ERR_PROT_FORM;
970 netdev_dbg(dev, "ack error\n");
971 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK |
972 CAN_ERR_PROT_LOC_ACK_DEL);
975 netdev_dbg(dev, "bit1 error\n");
976 cf->data[2] |= CAN_ERR_PROT_BIT1;
979 netdev_dbg(dev, "bit0 error\n");
980 cf->data[2] |= CAN_ERR_PROT_BIT0;
983 netdev_dbg(dev, "CRC error\n");
984 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
985 CAN_ERR_PROT_LOC_CRC_DEL);
991 /* set a `lec` value so that we can check for updates later */
992 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
994 netif_receive_skb(skb);
996 stats->rx_bytes += cf->can_dlc;
1001 static int c_can_poll(struct napi_struct *napi, int quota)
1006 struct net_device *dev = napi->dev;
1007 struct c_can_priv *priv = netdev_priv(dev);
1009 irqstatus = priv->irqstatus;
1013 /* status events have the highest priority */
1014 if (irqstatus == STATUS_INTERRUPT) {
1015 priv->current_status = priv->read_reg(priv,
1018 /* handle Tx/Rx events */
1019 if (priv->current_status & STATUS_TXOK)
1020 priv->write_reg(priv, C_CAN_STS_REG,
1021 priv->current_status & ~STATUS_TXOK);
1023 if (priv->current_status & STATUS_RXOK)
1024 priv->write_reg(priv, C_CAN_STS_REG,
1025 priv->current_status & ~STATUS_RXOK);
1027 /* handle state changes */
1028 if ((priv->current_status & STATUS_EWARN) &&
1029 (!(priv->last_status & STATUS_EWARN))) {
1030 netdev_dbg(dev, "entered error warning state\n");
1031 work_done += c_can_handle_state_change(dev,
1032 C_CAN_ERROR_WARNING);
1034 if ((priv->current_status & STATUS_EPASS) &&
1035 (!(priv->last_status & STATUS_EPASS))) {
1036 netdev_dbg(dev, "entered error passive state\n");
1037 work_done += c_can_handle_state_change(dev,
1038 C_CAN_ERROR_PASSIVE);
1040 if ((priv->current_status & STATUS_BOFF) &&
1041 (!(priv->last_status & STATUS_BOFF))) {
1042 netdev_dbg(dev, "entered bus off state\n");
1043 work_done += c_can_handle_state_change(dev,
1047 /* handle bus recovery events */
1048 if ((!(priv->current_status & STATUS_BOFF)) &&
1049 (priv->last_status & STATUS_BOFF)) {
1050 netdev_dbg(dev, "left bus off state\n");
1051 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1053 if ((!(priv->current_status & STATUS_EPASS)) &&
1054 (priv->last_status & STATUS_EPASS)) {
1055 netdev_dbg(dev, "left error passive state\n");
1056 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1059 priv->last_status = priv->current_status;
1061 /* handle lec errors on the bus */
1062 lec_type = c_can_has_and_handle_berr(priv);
1064 work_done += c_can_handle_bus_err(dev, lec_type);
1065 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) &&
1066 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) {
1067 /* handle events corresponding to receive message objects */
1068 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1069 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) &&
1070 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) {
1071 /* handle events corresponding to transmit message objects */
1076 if (work_done < quota) {
1077 napi_complete(napi);
1078 /* enable all IRQs */
1079 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
1085 static irqreturn_t c_can_isr(int irq, void *dev_id)
1087 struct net_device *dev = (struct net_device *)dev_id;
1088 struct c_can_priv *priv = netdev_priv(dev);
1090 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG);
1091 if (!priv->irqstatus)
1094 /* disable all interrupts and schedule the NAPI */
1095 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
1096 napi_schedule(&priv->napi);
1101 static int c_can_open(struct net_device *dev)
1104 struct c_can_priv *priv = netdev_priv(dev);
1106 c_can_pm_runtime_get_sync(priv);
1107 c_can_reset_ram(priv, true);
1109 /* open the can device */
1110 err = open_candev(dev);
1112 netdev_err(dev, "failed to open can device\n");
1113 goto exit_open_fail;
1116 /* register interrupt handler */
1117 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1120 netdev_err(dev, "failed to request interrupt\n");
1124 napi_enable(&priv->napi);
1126 can_led_event(dev, CAN_LED_EVENT_OPEN);
1128 /* start the c_can controller */
1131 netif_start_queue(dev);
1138 c_can_reset_ram(priv, false);
1139 c_can_pm_runtime_put_sync(priv);
1143 static int c_can_close(struct net_device *dev)
1145 struct c_can_priv *priv = netdev_priv(dev);
1147 netif_stop_queue(dev);
1148 napi_disable(&priv->napi);
1150 free_irq(dev->irq, dev);
1153 c_can_reset_ram(priv, false);
1154 c_can_pm_runtime_put_sync(priv);
1156 can_led_event(dev, CAN_LED_EVENT_STOP);
1161 struct net_device *alloc_c_can_dev(void)
1163 struct net_device *dev;
1164 struct c_can_priv *priv;
1166 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM);
1170 priv = netdev_priv(dev);
1171 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
1174 priv->can.bittiming_const = &c_can_bittiming_const;
1175 priv->can.do_set_mode = c_can_set_mode;
1176 priv->can.do_get_berr_counter = c_can_get_berr_counter;
1177 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1178 CAN_CTRLMODE_LISTENONLY |
1179 CAN_CTRLMODE_BERR_REPORTING;
1183 EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1186 int c_can_power_down(struct net_device *dev)
1189 unsigned long time_out;
1190 struct c_can_priv *priv = netdev_priv(dev);
1192 if (!(dev->flags & IFF_UP))
1195 WARN_ON(priv->type != BOSCH_D_CAN);
1197 /* set PDR value so the device goes to power down mode */
1198 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1199 val |= CONTROL_EX_PDR;
1200 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1202 /* Wait for the PDA bit to get set */
1203 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1204 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1205 time_after(time_out, jiffies))
1208 if (time_after(jiffies, time_out))
1213 c_can_reset_ram(priv, false);
1214 c_can_pm_runtime_put_sync(priv);
1218 EXPORT_SYMBOL_GPL(c_can_power_down);
1220 int c_can_power_up(struct net_device *dev)
1223 unsigned long time_out;
1224 struct c_can_priv *priv = netdev_priv(dev);
1226 if (!(dev->flags & IFF_UP))
1229 WARN_ON(priv->type != BOSCH_D_CAN);
1231 c_can_pm_runtime_get_sync(priv);
1232 c_can_reset_ram(priv, true);
1234 /* Clear PDR and INIT bits */
1235 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1236 val &= ~CONTROL_EX_PDR;
1237 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1238 val = priv->read_reg(priv, C_CAN_CTRL_REG);
1239 val &= ~CONTROL_INIT;
1240 priv->write_reg(priv, C_CAN_CTRL_REG, val);
1242 /* Wait for the PDA bit to get clear */
1243 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1244 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1245 time_after(time_out, jiffies))
1248 if (time_after(jiffies, time_out))
1255 EXPORT_SYMBOL_GPL(c_can_power_up);
1258 void free_c_can_dev(struct net_device *dev)
1262 EXPORT_SYMBOL_GPL(free_c_can_dev);
1264 static const struct net_device_ops c_can_netdev_ops = {
1265 .ndo_open = c_can_open,
1266 .ndo_stop = c_can_close,
1267 .ndo_start_xmit = c_can_start_xmit,
1270 int register_c_can_dev(struct net_device *dev)
1272 struct c_can_priv *priv = netdev_priv(dev);
1275 c_can_pm_runtime_enable(priv);
1277 dev->flags |= IFF_ECHO; /* we support local echo */
1278 dev->netdev_ops = &c_can_netdev_ops;
1280 err = register_candev(dev);
1282 c_can_pm_runtime_disable(priv);
1284 devm_can_led_init(dev);
1288 EXPORT_SYMBOL_GPL(register_c_can_dev);
1290 void unregister_c_can_dev(struct net_device *dev)
1292 struct c_can_priv *priv = netdev_priv(dev);
1294 unregister_candev(dev);
1296 c_can_pm_runtime_disable(priv);
1298 EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1301 MODULE_LICENSE("GPL v2");
1302 MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");