drivers/net/dsa/lantiq_gswip.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Lantiq / Intel GSWIP switch driver for VRX200 SoCs
   4  *
   5  * Copyright (C) 2010 Lantiq Deutschland
   6  * Copyright (C) 2012 John Crispin <[email protected]>
   7  * Copyright (C) 2017 - 2019 Hauke Mehrtens <[email protected]>
   8  *
   9  * The VLAN and bridge model the GSWIP hardware uses does not directly
  10  * matches the model DSA uses.
  11  *
  12  * The hardware has 64 possible table entries for bridges with one VLAN
  13  * ID, one flow id and a list of ports for each bridge. All entries which
  14  * match the same flow ID are combined in the mac learning table, they
  15  * act as one global bridge.
  16  * The hardware does not support VLAN filter on the port, but on the
  17  * bridge, this driver converts the DSA model to the hardware.
  18  *
  19  * The CPU gets all the exception frames which do not match any forwarding
  20  * rule and the CPU port is also added to all bridges. This makes it possible
  21  * to handle all the special cases easily in software.
  22  * At the initialization the driver allocates one bridge table entry for
  23  * each switch port which is used when the port is used without an
  24  * explicit bridge. This prevents the frames from being forwarded
  25  * between all LAN ports by default.
  26  */
  27
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/firmware.h>
  32 #include <linux/if_bridge.h>
  33 #include <linux/if_vlan.h>
  34 #include <linux/iopoll.h>
  35 #include <linux/mfd/syscon.h>
  36 #include <linux/module.h>
  37 #include <linux/of_mdio.h>
  38 #include <linux/of_net.h>
  39 #include <linux/of_platform.h>
  40 #include <linux/phy.h>
  41 #include <linux/phylink.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/regmap.h>
  44 #include <linux/reset.h>
  45 #include <net/dsa.h>
  46 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
  47
  48 #include "lantiq_pce.h"
  49
  50 /* GSWIP MDIO Registers */
  51 #define GSWIP_MDIO_GLOB                 0x00
  52 #define  GSWIP_MDIO_GLOB_ENABLE         BIT(15)
  53 #define GSWIP_MDIO_CTRL                 0x08
  54 #define  GSWIP_MDIO_CTRL_BUSY           BIT(12)
  55 #define  GSWIP_MDIO_CTRL_RD             BIT(11)
  56 #define  GSWIP_MDIO_CTRL_WR             BIT(10)
  57 #define  GSWIP_MDIO_CTRL_PHYAD_MASK     0x1f
  58 #define  GSWIP_MDIO_CTRL_PHYAD_SHIFT    5
  59 #define  GSWIP_MDIO_CTRL_REGAD_MASK     0x1f
  60 #define GSWIP_MDIO_READ                 0x09
  61 #define GSWIP_MDIO_WRITE                0x0A
  62 #define GSWIP_MDIO_MDC_CFG0             0x0B
  63 #define GSWIP_MDIO_MDC_CFG1             0x0C
  64 #define GSWIP_MDIO_PHYp(p)              (0x15 - (p))
  65 #define  GSWIP_MDIO_PHY_LINK_MASK       0x6000
  66 #define  GSWIP_MDIO_PHY_LINK_AUTO       0x0000
  67 #define  GSWIP_MDIO_PHY_LINK_DOWN       0x4000
  68 #define  GSWIP_MDIO_PHY_LINK_UP         0x2000
  69 #define  GSWIP_MDIO_PHY_SPEED_MASK      0x1800
  70 #define  GSWIP_MDIO_PHY_SPEED_AUTO      0x1800
  71 #define  GSWIP_MDIO_PHY_SPEED_M10       0x0000
  72 #define  GSWIP_MDIO_PHY_SPEED_M100      0x0800
  73 #define  GSWIP_MDIO_PHY_SPEED_G1        0x1000
  74 #define  GSWIP_MDIO_PHY_FDUP_MASK       0x0600
  75 #define  GSWIP_MDIO_PHY_FDUP_AUTO       0x0000
  76 #define  GSWIP_MDIO_PHY_FDUP_EN         0x0200
  77 #define  GSWIP_MDIO_PHY_FDUP_DIS        0x0600
  78 #define  GSWIP_MDIO_PHY_FCONTX_MASK     0x0180
  79 #define  GSWIP_MDIO_PHY_FCONTX_AUTO     0x0000
  80 #define  GSWIP_MDIO_PHY_FCONTX_EN       0x0100
  81 #define  GSWIP_MDIO_PHY_FCONTX_DIS      0x0180
  82 #define  GSWIP_MDIO_PHY_FCONRX_MASK     0x0060
  83 #define  GSWIP_MDIO_PHY_FCONRX_AUTO     0x0000
  84 #define  GSWIP_MDIO_PHY_FCONRX_EN       0x0020
  85 #define  GSWIP_MDIO_PHY_FCONRX_DIS      0x0060
  86 #define  GSWIP_MDIO_PHY_ADDR_MASK       0x001f
  87 #define  GSWIP_MDIO_PHY_MASK            (GSWIP_MDIO_PHY_ADDR_MASK | \
  88                                          GSWIP_MDIO_PHY_FCONRX_MASK | \
  89                                          GSWIP_MDIO_PHY_FCONTX_MASK | \
  90                                          GSWIP_MDIO_PHY_LINK_MASK | \
  91                                          GSWIP_MDIO_PHY_SPEED_MASK | \
  92                                          GSWIP_MDIO_PHY_FDUP_MASK)
  93
  94 /* GSWIP MII Registers */
  95 #define GSWIP_MII_CFG0                  0x00
  96 #define GSWIP_MII_CFG1                  0x02
  97 #define GSWIP_MII_CFG5                  0x04
  98 #define  GSWIP_MII_CFG_EN               BIT(14)
  99 #define  GSWIP_MII_CFG_LDCLKDIS         BIT(12)
 100 #define  GSWIP_MII_CFG_MODE_MIIP        0x0
 101 #define  GSWIP_MII_CFG_MODE_MIIM        0x1
 102 #define  GSWIP_MII_CFG_MODE_RMIIP       0x2
 103 #define  GSWIP_MII_CFG_MODE_RMIIM       0x3
 104 #define  GSWIP_MII_CFG_MODE_RGMII       0x4
 105 #define  GSWIP_MII_CFG_MODE_MASK        0xf
 106 #define  GSWIP_MII_CFG_RATE_M2P5        0x00
 107 #define  GSWIP_MII_CFG_RATE_M25 0x10
 108 #define  GSWIP_MII_CFG_RATE_M125        0x20
 109 #define  GSWIP_MII_CFG_RATE_M50 0x30
 110 #define  GSWIP_MII_CFG_RATE_AUTO        0x40
 111 #define  GSWIP_MII_CFG_RATE_MASK        0x70
 112 #define GSWIP_MII_PCDU0                 0x01
 113 #define GSWIP_MII_PCDU1                 0x03
 114 #define GSWIP_MII_PCDU5                 0x05
 115 #define  GSWIP_MII_PCDU_TXDLY_MASK      GENMASK(2, 0)
 116 #define  GSWIP_MII_PCDU_RXDLY_MASK      GENMASK(9, 7)
 117
 118 /* GSWIP Core Registers */
 119 #define GSWIP_SWRES                     0x000
 120 #define  GSWIP_SWRES_R1                 BIT(1)  /* GSWIP Software reset */
 121 #define  GSWIP_SWRES_R0                 BIT(0)  /* GSWIP Hardware reset */
 122 #define GSWIP_VERSION                   0x013
 123 #define  GSWIP_VERSION_REV_SHIFT        0
 124 #define  GSWIP_VERSION_REV_MASK         GENMASK(7, 0)
 125 #define  GSWIP_VERSION_MOD_SHIFT        8
 126 #define  GSWIP_VERSION_MOD_MASK         GENMASK(15, 8)
 127 #define   GSWIP_VERSION_2_0             0x100
 128 #define   GSWIP_VERSION_2_1             0x021
 129 #define   GSWIP_VERSION_2_2             0x122
 130 #define   GSWIP_VERSION_2_2_ETC         0x022
 131
 132 #define GSWIP_BM_RAM_VAL(x)             (0x043 - (x))
 133 #define GSWIP_BM_RAM_ADDR               0x044
 134 #define GSWIP_BM_RAM_CTRL               0x045
 135 #define  GSWIP_BM_RAM_CTRL_BAS          BIT(15)
 136 #define  GSWIP_BM_RAM_CTRL_OPMOD        BIT(5)
 137 #define  GSWIP_BM_RAM_CTRL_ADDR_MASK    GENMASK(4, 0)
 138 #define GSWIP_BM_QUEUE_GCTRL            0x04A
 139 #define  GSWIP_BM_QUEUE_GCTRL_GL_MOD    BIT(10)
 140 /* buffer management Port Configuration Register */
 141 #define GSWIP_BM_PCFGp(p)               (0x080 + ((p) * 2))
 142 #define  GSWIP_BM_PCFG_CNTEN            BIT(0)  /* RMON Counter Enable */
 143 #define  GSWIP_BM_PCFG_IGCNT            BIT(1)  /* Ingres Special Tag RMON count */
 144 /* buffer management Port Control Register */
 145 #define GSWIP_BM_RMON_CTRLp(p)          (0x81 + ((p) * 2))
 146 #define  GSWIP_BM_CTRL_RMON_RAM1_RES    BIT(0)  /* Software Reset for RMON RAM 1 */
 147 #define  GSWIP_BM_CTRL_RMON_RAM2_RES    BIT(1)  /* Software Reset for RMON RAM 2 */
 148
 149 /* PCE */
 150 #define GSWIP_PCE_TBL_KEY(x)            (0x447 - (x))
 151 #define GSWIP_PCE_TBL_MASK              0x448
 152 #define GSWIP_PCE_TBL_VAL(x)            (0x44D - (x))
 153 #define GSWIP_PCE_TBL_ADDR              0x44E
 154 #define GSWIP_PCE_TBL_CTRL              0x44F
 155 #define  GSWIP_PCE_TBL_CTRL_BAS         BIT(15)
 156 #define  GSWIP_PCE_TBL_CTRL_TYPE        BIT(13)
 157 #define  GSWIP_PCE_TBL_CTRL_VLD         BIT(12)
 158 #define  GSWIP_PCE_TBL_CTRL_KEYFORM     BIT(11)
 159 #define  GSWIP_PCE_TBL_CTRL_GMAP_MASK   GENMASK(10, 7)
 160 #define  GSWIP_PCE_TBL_CTRL_OPMOD_MASK  GENMASK(6, 5)
 161 #define  GSWIP_PCE_TBL_CTRL_OPMOD_ADRD  0x00
 162 #define  GSWIP_PCE_TBL_CTRL_OPMOD_ADWR  0x20
 163 #define  GSWIP_PCE_TBL_CTRL_OPMOD_KSRD  0x40
 164 #define  GSWIP_PCE_TBL_CTRL_OPMOD_KSWR  0x60
 165 #define  GSWIP_PCE_TBL_CTRL_ADDR_MASK   GENMASK(4, 0)
 166 #define GSWIP_PCE_PMAP1                 0x453   /* Monitoring port map */
 167 #define GSWIP_PCE_PMAP2                 0x454   /* Default Multicast port map */
 168 #define GSWIP_PCE_PMAP3                 0x455   /* Default Unknown Unicast port map */
 169 #define GSWIP_PCE_GCTRL_0               0x456
 170 #define  GSWIP_PCE_GCTRL_0_MTFL         BIT(0)  /* MAC Table Flushing */
 171 #define  GSWIP_PCE_GCTRL_0_MC_VALID     BIT(3)
 172 #define  GSWIP_PCE_GCTRL_0_VLAN         BIT(14) /* VLAN aware Switching */
 173 #define GSWIP_PCE_GCTRL_1               0x457
 174 #define  GSWIP_PCE_GCTRL_1_MAC_GLOCK    BIT(2)  /* MAC Address table lock */
 175 #define  GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD        BIT(3) /* Mac address table lock forwarding mode */
 176 #define GSWIP_PCE_PCTRL_0p(p)           (0x480 + ((p) * 0xA))
 177 #define  GSWIP_PCE_PCTRL_0_TVM          BIT(5)  /* Transparent VLAN mode */
 178 #define  GSWIP_PCE_PCTRL_0_VREP         BIT(6)  /* VLAN Replace Mode */
 179 #define  GSWIP_PCE_PCTRL_0_INGRESS      BIT(11) /* Accept special tag in ingress */
 180 #define  GSWIP_PCE_PCTRL_0_PSTATE_LISTEN        0x0
 181 #define  GSWIP_PCE_PCTRL_0_PSTATE_RX            0x1
 182 #define  GSWIP_PCE_PCTRL_0_PSTATE_TX            0x2
 183 #define  GSWIP_PCE_PCTRL_0_PSTATE_LEARNING      0x3
 184 #define  GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING    0x7
 185 #define  GSWIP_PCE_PCTRL_0_PSTATE_MASK  GENMASK(2, 0)
 186 #define GSWIP_PCE_VCTRL(p)              (0x485 + ((p) * 0xA))
 187 #define  GSWIP_PCE_VCTRL_UVR            BIT(0)  /* Unknown VLAN Rule */
 188 #define  GSWIP_PCE_VCTRL_VIMR           BIT(3)  /* VLAN Ingress Member violation rule */
 189 #define  GSWIP_PCE_VCTRL_VEMR           BIT(4)  /* VLAN Egress Member violation rule */
 190 #define  GSWIP_PCE_VCTRL_VSR            BIT(5)  /* VLAN Security */
 191 #define  GSWIP_PCE_VCTRL_VID0           BIT(6)  /* Priority Tagged Rule */
 192 #define GSWIP_PCE_DEFPVID(p)            (0x486 + ((p) * 0xA))
 193
 194 #define GSWIP_MAC_FLEN                  0x8C5
 195 #define GSWIP_MAC_CTRL_2p(p)            (0x905 + ((p) * 0xC))
 196 #define GSWIP_MAC_CTRL_2_MLEN           BIT(3) /* Maximum Untagged Frame Lnegth */
 197
 198 /* Ethernet Switch Fetch DMA Port Control Register */
 199 #define GSWIP_FDMA_PCTRLp(p)            (0xA80 + ((p) * 0x6))
 200 #define  GSWIP_FDMA_PCTRL_EN            BIT(0)  /* FDMA Port Enable */
 201 #define  GSWIP_FDMA_PCTRL_STEN          BIT(1)  /* Special Tag Insertion Enable */
 202 #define  GSWIP_FDMA_PCTRL_VLANMOD_MASK  GENMASK(4, 3)   /* VLAN Modification Control */
 203 #define  GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3       /* VLAN Modification Control */
 204 #define  GSWIP_FDMA_PCTRL_VLANMOD_DIS   (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
 205 #define  GSWIP_FDMA_PCTRL_VLANMOD_PRIO  (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
 206 #define  GSWIP_FDMA_PCTRL_VLANMOD_ID    (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
 207 #define  GSWIP_FDMA_PCTRL_VLANMOD_BOTH  (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
 208
 209 /* Ethernet Switch Store DMA Port Control Register */
 210 #define GSWIP_SDMA_PCTRLp(p)            (0xBC0 + ((p) * 0x6))
 211 #define  GSWIP_SDMA_PCTRL_EN            BIT(0)  /* SDMA Port Enable */
 212 #define  GSWIP_SDMA_PCTRL_FCEN          BIT(1)  /* Flow Control Enable */
 213 #define  GSWIP_SDMA_PCTRL_PAUFWD        BIT(1)  /* Pause Frame Forwarding */
 214
 215 #define GSWIP_TABLE_ACTIVE_VLAN         0x01
 216 #define GSWIP_TABLE_VLAN_MAPPING        0x02
 217 #define GSWIP_TABLE_MAC_BRIDGE          0x0b
 218 #define  GSWIP_TABLE_MAC_BRIDGE_STATIC  0x01    /* Static not, aging entry */
 219
 220 #define XRX200_GPHY_FW_ALIGN    (16 * 1024)
 221
 222 struct gswip_hw_info {
 223         int max_ports;
 224         int cpu_port;
 225 };
 226
 227 struct xway_gphy_match_data {
 228         char *fe_firmware_name;
 229         char *ge_firmware_name;
 230 };
 231
 232 struct gswip_gphy_fw {
 233         struct clk *clk_gate;
 234         struct reset_control *reset;
 235         u32 fw_addr_offset;
 236         char *fw_name;
 237 };
 238
 239 struct gswip_vlan {
 240         struct net_device *bridge;
 241         u16 vid;
 242         u8 fid;
 243 };
 244
 245 struct gswip_priv {
 246         __iomem void *gswip;
 247         __iomem void *mdio;
 248         __iomem void *mii;
 249         const struct gswip_hw_info *hw_info;
 250         const struct xway_gphy_match_data *gphy_fw_name_cfg;
 251         struct dsa_switch *ds;
 252         struct device *dev;
 253         struct regmap *rcu_regmap;
 254         struct gswip_vlan vlans[64];
 255         int num_gphy_fw;
 256         struct gswip_gphy_fw *gphy_fw;
 257         u32 port_vlan_filter;
 258 };
 259
 260 struct gswip_pce_table_entry {
 261         u16 index;      // PCE_TBL_ADDR.ADDR = pData->table_index
 262         u16 table;      // PCE_TBL_CTRL.ADDR = pData->table
 263         u16 key[8];
 264         u16 val[5];
 265         u16 mask;
 266         u8 gmap;
 267         bool type;
 268         bool valid;
 269         bool key_mode;
 270 };
 271
 272 struct gswip_rmon_cnt_desc {
 273         unsigned int size;
 274         unsigned int offset;
 275         const char *name;
 276 };
 277
 278 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
 279
 280 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = {
 281         /** Receive Packet Count (only packets that are accepted and not discarded). */
 282         MIB_DESC(1, 0x1F, "RxGoodPkts"),
 283         MIB_DESC(1, 0x23, "RxUnicastPkts"),
 284         MIB_DESC(1, 0x22, "RxMulticastPkts"),
 285         MIB_DESC(1, 0x21, "RxFCSErrorPkts"),
 286         MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"),
 287         MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"),
 288         MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"),
 289         MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"),
 290         MIB_DESC(1, 0x20, "RxGoodPausePkts"),
 291         MIB_DESC(1, 0x1A, "RxAlignErrorPkts"),
 292         MIB_DESC(1, 0x12, "Rx64BytePkts"),
 293         MIB_DESC(1, 0x13, "Rx127BytePkts"),
 294         MIB_DESC(1, 0x14, "Rx255BytePkts"),
 295         MIB_DESC(1, 0x15, "Rx511BytePkts"),
 296         MIB_DESC(1, 0x16, "Rx1023BytePkts"),
 297         /** Receive Size 1024-1522 (or more, if configured) Packet Count. */
 298         MIB_DESC(1, 0x17, "RxMaxBytePkts"),
 299         MIB_DESC(1, 0x18, "RxDroppedPkts"),
 300         MIB_DESC(1, 0x19, "RxFilteredPkts"),
 301         MIB_DESC(2, 0x24, "RxGoodBytes"),
 302         MIB_DESC(2, 0x26, "RxBadBytes"),
 303         MIB_DESC(1, 0x11, "TxAcmDroppedPkts"),
 304         MIB_DESC(1, 0x0C, "TxGoodPkts"),
 305         MIB_DESC(1, 0x06, "TxUnicastPkts"),
 306         MIB_DESC(1, 0x07, "TxMulticastPkts"),
 307         MIB_DESC(1, 0x00, "Tx64BytePkts"),
 308         MIB_DESC(1, 0x01, "Tx127BytePkts"),
 309         MIB_DESC(1, 0x02, "Tx255BytePkts"),
 310         MIB_DESC(1, 0x03, "Tx511BytePkts"),
 311         MIB_DESC(1, 0x04, "Tx1023BytePkts"),
 312         /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */
 313         MIB_DESC(1, 0x05, "TxMaxBytePkts"),
 314         MIB_DESC(1, 0x08, "TxSingleCollCount"),
 315         MIB_DESC(1, 0x09, "TxMultCollCount"),
 316         MIB_DESC(1, 0x0A, "TxLateCollCount"),
 317         MIB_DESC(1, 0x0B, "TxExcessCollCount"),
 318         MIB_DESC(1, 0x0D, "TxPauseCount"),
 319         MIB_DESC(1, 0x10, "TxDroppedPkts"),
 320         MIB_DESC(2, 0x0E, "TxGoodBytes"),
 321 };
 322
 323 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset)
 324 {
 325         return __raw_readl(priv->gswip + (offset * 4));
 326 }
 327
 328 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset)
 329 {
 330         __raw_writel(val, priv->gswip + (offset * 4));
 331 }
 332
 333 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set,
 334                               u32 offset)
 335 {
 336         u32 val = gswip_switch_r(priv, offset);
 337
 338         val &= ~(clear);
 339         val |= set;
 340         gswip_switch_w(priv, val, offset);
 341 }
 342
 343 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset,
 344                                   u32 cleared)
 345 {
 346         u32 val;
 347
 348         return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val,
 349                                   (val & cleared) == 0, 20, 50000);
 350 }
 351
 352 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset)
 353 {
 354         return __raw_readl(priv->mdio + (offset * 4));
 355 }
 356
 357 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset)
 358 {
 359         __raw_writel(val, priv->mdio + (offset * 4));
 360 }
 361
 362 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set,
 363                             u32 offset)
 364 {
 365         u32 val = gswip_mdio_r(priv, offset);
 366
 367         val &= ~(clear);
 368         val |= set;
 369         gswip_mdio_w(priv, val, offset);
 370 }
 371
 372 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset)
 373 {
 374         return __raw_readl(priv->mii + (offset * 4));
 375 }
 376
 377 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset)
 378 {
 379         __raw_writel(val, priv->mii + (offset * 4));
 380 }
 381
 382 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set,
 383                            u32 offset)
 384 {
 385         u32 val = gswip_mii_r(priv, offset);
 386
 387         val &= ~(clear);
 388         val |= set;
 389         gswip_mii_w(priv, val, offset);
 390 }
 391
 392 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
 393                                int port)
 394 {
 395         switch (port) {
 396         case 0:
 397                 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG0);
 398                 break;
 399         case 1:
 400                 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG1);
 401                 break;
 402         case 5:
 403                 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG5);
 404                 break;
 405         }
 406 }
 407
 408 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
 409                                 int port)
 410 {
 411         switch (port) {
 412         case 0:
 413                 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0);
 414                 break;
 415         case 1:
 416                 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1);
 417                 break;
 418         case 5:
 419                 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5);
 420                 break;
 421         }
 422 }
 423
 424 static int gswip_mdio_poll(struct gswip_priv *priv)
 425 {
 426         int cnt = 100;
 427
 428         while (likely(cnt--)) {
 429                 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL);
 430
 431                 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0)
 432                         return 0;
 433                 usleep_range(20, 40);
 434         }
 435
 436         return -ETIMEDOUT;
 437 }
 438
 439 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
 440 {
 441         struct gswip_priv *priv = bus->priv;
 442         int err;
 443
 444         err = gswip_mdio_poll(priv);
 445         if (err) {
 446                 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
 447                 return err;
 448         }
 449
 450         gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE);
 451         gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR |
 452                 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
 453                 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
 454                 GSWIP_MDIO_CTRL);
 455
 456         return 0;
 457 }
 458
 459 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg)
 460 {
 461         struct gswip_priv *priv = bus->priv;
 462         int err;
 463
 464         err = gswip_mdio_poll(priv);
 465         if (err) {
 466                 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
 467                 return err;
 468         }
 469
 470         gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD |
 471                 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
 472                 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
 473                 GSWIP_MDIO_CTRL);
 474
 475         err = gswip_mdio_poll(priv);
 476         if (err) {
 477                 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
 478                 return err;
 479         }
 480
 481         return gswip_mdio_r(priv, GSWIP_MDIO_READ);
 482 }
 483
 484 static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np)
 485 {
 486         struct dsa_switch *ds = priv->ds;
 487
 488         ds->slave_mii_bus = devm_mdiobus_alloc(priv->dev);
 489         if (!ds->slave_mii_bus)
 490                 return -ENOMEM;
 491
 492         ds->slave_mii_bus->priv = priv;
 493         ds->slave_mii_bus->read = gswip_mdio_rd;
 494         ds->slave_mii_bus->write = gswip_mdio_wr;
 495         ds->slave_mii_bus->name = "lantiq,xrx200-mdio";
 496         snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii",
 497                  dev_name(priv->dev));
 498         ds->slave_mii_bus->parent = priv->dev;
 499         ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask;
 500
 501         return of_mdiobus_register(ds->slave_mii_bus, mdio_np);
 502 }
 503
 504 static int gswip_pce_table_entry_read(struct gswip_priv *priv,
 505                                       struct gswip_pce_table_entry *tbl)
 506 {
 507         int i;
 508         int err;
 509         u16 crtl;
 510         u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD :
 511                                         GSWIP_PCE_TBL_CTRL_OPMOD_ADRD;
 512
 513         err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
 514                                      GSWIP_PCE_TBL_CTRL_BAS);
 515         if (err)
 516                 return err;
 517
 518         gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
 519         gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
 520                                 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
 521                           tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS,
 522                           GSWIP_PCE_TBL_CTRL);
 523
 524         err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
 525                                      GSWIP_PCE_TBL_CTRL_BAS);
 526         if (err)
 527                 return err;
 528
 529         for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
 530                 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i));
 531
 532         for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
 533                 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i));
 534
 535         tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK);
 536
 537         crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
 538
 539         tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE);
 540         tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD);
 541         tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7;
 542
 543         return 0;
 544 }
 545
 546 static int gswip_pce_table_entry_write(struct gswip_priv *priv,
 547                                        struct gswip_pce_table_entry *tbl)
 548 {
 549         int i;
 550         int err;
 551         u16 crtl;
 552         u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR :
 553                                         GSWIP_PCE_TBL_CTRL_OPMOD_ADWR;
 554
 555         err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
 556                                      GSWIP_PCE_TBL_CTRL_BAS);
 557         if (err)
 558                 return err;
 559
 560         gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
 561         gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
 562                                 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
 563                           tbl->table | addr_mode,
 564                           GSWIP_PCE_TBL_CTRL);
 565
 566         for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
 567                 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i));
 568
 569         for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
 570                 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i));
 571
 572         gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
 573                                 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
 574                           tbl->table | addr_mode,
 575                           GSWIP_PCE_TBL_CTRL);
 576
 577         gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK);
 578
 579         crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
 580         crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD |
 581                   GSWIP_PCE_TBL_CTRL_GMAP_MASK);
 582         if (tbl->type)
 583                 crtl |= GSWIP_PCE_TBL_CTRL_TYPE;
 584         if (tbl->valid)
 585                 crtl |= GSWIP_PCE_TBL_CTRL_VLD;
 586         crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK;
 587         crtl |= GSWIP_PCE_TBL_CTRL_BAS;
 588         gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL);
 589
 590         return gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
 591                                       GSWIP_PCE_TBL_CTRL_BAS);
 592 }
 593
 594 /* Add the LAN port into a bridge with the CPU port by
 595  * default. This prevents automatic forwarding of
 596  * packages between the LAN ports when no explicit
 597  * bridge is configured.
 598  */
 599 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add)
 600 {
 601         struct gswip_pce_table_entry vlan_active = {0,};
 602         struct gswip_pce_table_entry vlan_mapping = {0,};
 603         unsigned int cpu_port = priv->hw_info->cpu_port;
 604         unsigned int max_ports = priv->hw_info->max_ports;
 605         int err;
 606
 607         if (port >= max_ports) {
 608                 dev_err(priv->dev, "single port for %i supported\n", port);
 609                 return -EIO;
 610         }
 611
 612         vlan_active.index = port + 1;
 613         vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
 614         vlan_active.key[0] = 0; /* vid */
 615         vlan_active.val[0] = port + 1 /* fid */;
 616         vlan_active.valid = add;
 617         err = gswip_pce_table_entry_write(priv, &vlan_active);
 618         if (err) {
 619                 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
 620                 return err;
 621         }
 622
 623         if (!add)
 624                 return 0;
 625
 626         vlan_mapping.index = port + 1;
 627         vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
 628         vlan_mapping.val[0] = 0 /* vid */;
 629         vlan_mapping.val[1] = BIT(port) | BIT(cpu_port);
 630         vlan_mapping.val[2] = 0;
 631         err = gswip_pce_table_entry_write(priv, &vlan_mapping);
 632         if (err) {
 633                 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
 634                 return err;
 635         }
 636
 637         return 0;
 638 }
 639
 640 static int gswip_port_enable(struct dsa_switch *ds, int port,
 641                              struct phy_device *phydev)
 642 {
 643         struct gswip_priv *priv = ds->priv;
 644         int err;
 645
 646         if (!dsa_is_user_port(ds, port))
 647                 return 0;
 648
 649         if (!dsa_is_cpu_port(ds, port)) {
 650                 err = gswip_add_single_port_br(priv, port, true);
 651                 if (err)
 652                         return err;
 653         }
 654
 655         /* RMON Counter Enable for port */
 656         gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port));
 657
 658         /* enable port fetch/store dma & VLAN Modification */
 659         gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN |
 660                                    GSWIP_FDMA_PCTRL_VLANMOD_BOTH,
 661                          GSWIP_FDMA_PCTRLp(port));
 662         gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
 663                           GSWIP_SDMA_PCTRLp(port));
 664
 665         if (!dsa_is_cpu_port(ds, port)) {
 666                 u32 macconf = GSWIP_MDIO_PHY_LINK_AUTO |
 667                               GSWIP_MDIO_PHY_SPEED_AUTO |
 668                               GSWIP_MDIO_PHY_FDUP_AUTO |
 669                               GSWIP_MDIO_PHY_FCONTX_AUTO |
 670                               GSWIP_MDIO_PHY_FCONRX_AUTO |
 671                               (phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK);
 672
 673                 gswip_mdio_w(priv, macconf, GSWIP_MDIO_PHYp(port));
 674                 /* Activate MDIO auto polling */
 675                 gswip_mdio_mask(priv, 0, BIT(port), GSWIP_MDIO_MDC_CFG0);
 676         }
 677
 678         return 0;
 679 }
 680
 681 static void gswip_port_disable(struct dsa_switch *ds, int port)
 682 {
 683         struct gswip_priv *priv = ds->priv;
 684
 685         if (!dsa_is_user_port(ds, port))
 686                 return;
 687
 688         if (!dsa_is_cpu_port(ds, port)) {
 689                 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_DOWN,
 690                                 GSWIP_MDIO_PHY_LINK_MASK,
 691                                 GSWIP_MDIO_PHYp(port));
 692                 /* Deactivate MDIO auto polling */
 693                 gswip_mdio_mask(priv, BIT(port), 0, GSWIP_MDIO_MDC_CFG0);
 694         }
 695
 696         gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
 697                           GSWIP_FDMA_PCTRLp(port));
 698         gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
 699                           GSWIP_SDMA_PCTRLp(port));
 700 }
 701
 702 static int gswip_pce_load_microcode(struct gswip_priv *priv)
 703 {
 704         int i;
 705         int err;
 706
 707         gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
 708                                 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
 709                           GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL);
 710         gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK);
 711
 712         for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) {
 713                 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR);
 714                 gswip_switch_w(priv, gswip_pce_microcode[i].val_0,
 715                                GSWIP_PCE_TBL_VAL(0));
 716                 gswip_switch_w(priv, gswip_pce_microcode[i].val_1,
 717                                GSWIP_PCE_TBL_VAL(1));
 718                 gswip_switch_w(priv, gswip_pce_microcode[i].val_2,
 719                                GSWIP_PCE_TBL_VAL(2));
 720                 gswip_switch_w(priv, gswip_pce_microcode[i].val_3,
 721                                GSWIP_PCE_TBL_VAL(3));
 722
 723                 /* start the table access: */
 724                 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS,
 725                                   GSWIP_PCE_TBL_CTRL);
 726                 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
 727                                              GSWIP_PCE_TBL_CTRL_BAS);
 728                 if (err)
 729                         return err;
 730         }
 731
 732         /* tell the switch that the microcode is loaded */
 733         gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID,
 734                           GSWIP_PCE_GCTRL_0);
 735
 736         return 0;
 737 }
 738
 739 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port,
 740                                      bool vlan_filtering,
 741                                      struct switchdev_trans *trans)
 742 {
 743         struct gswip_priv *priv = ds->priv;
 744
 745         /* Do not allow changing the VLAN filtering options while in bridge */
 746         if (switchdev_trans_ph_prepare(trans)) {
 747                 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
 748
 749                 if (!bridge)
 750                         return 0;
 751
 752                 if (!!(priv->port_vlan_filter & BIT(port)) != vlan_filtering)
 753                         return -EIO;
 754
 755                 return 0;
 756         }
 757
 758         if (vlan_filtering) {
 759                 /* Use port based VLAN tag */
 760                 gswip_switch_mask(priv,
 761                                   GSWIP_PCE_VCTRL_VSR,
 762                                   GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
 763                                   GSWIP_PCE_VCTRL_VEMR,
 764                                   GSWIP_PCE_VCTRL(port));
 765                 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
 766                                   GSWIP_PCE_PCTRL_0p(port));
 767         } else {
 768                 /* Use port based VLAN tag */
 769                 gswip_switch_mask(priv,
 770                                   GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
 771                                   GSWIP_PCE_VCTRL_VEMR,
 772                                   GSWIP_PCE_VCTRL_VSR,
 773                                   GSWIP_PCE_VCTRL(port));
 774                 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM,
 775                                   GSWIP_PCE_PCTRL_0p(port));
 776         }
 777
 778         return 0;
 779 }
 780
 781 static int gswip_setup(struct dsa_switch *ds)
 782 {
 783         struct gswip_priv *priv = ds->priv;
 784         unsigned int cpu_port = priv->hw_info->cpu_port;
 785         int i;
 786         int err;
 787
 788         gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES);
 789         usleep_range(5000, 10000);
 790         gswip_switch_w(priv, 0, GSWIP_SWRES);
 791
 792         /* disable port fetch/store dma on all ports */
 793         for (i = 0; i < priv->hw_info->max_ports; i++) {
 794                 struct switchdev_trans trans;
 795
 796                 /* Skip the prepare phase, this shouldn't return an error
 797                  * during setup.
 798                  */
 799                 trans.ph_prepare = false;
 800
 801                 gswip_port_disable(ds, i);
 802                 gswip_port_vlan_filtering(ds, i, false, &trans);
 803         }
 804
 805         /* enable Switch */
 806         gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB);
 807
 808         err = gswip_pce_load_microcode(priv);
 809         if (err) {
 810                 dev_err(priv->dev, "writing PCE microcode failed, %i", err);
 811                 return err;
 812         }
 813
 814         /* Default unknown Broadcast/Multicast/Unicast port maps */
 815         gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1);
 816         gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2);
 817         gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3);
 818
 819         /* disable PHY auto polling */
 820         gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0);
 821         /* Configure the MDIO Clock 2.5 MHz */
 822         gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1);
 823
 824         /* Disable the xMII link */
 825         gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 0);
 826         gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 1);
 827         gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 5);
 828
 829         /* enable special tag insertion on cpu port */
 830         gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN,
 831                           GSWIP_FDMA_PCTRLp(cpu_port));
 832
 833         /* accept special tag in ingress direction */
 834         gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS,
 835                           GSWIP_PCE_PCTRL_0p(cpu_port));
 836
 837         gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN,
 838                           GSWIP_MAC_CTRL_2p(cpu_port));
 839         gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8, GSWIP_MAC_FLEN);
 840         gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD,
 841                           GSWIP_BM_QUEUE_GCTRL);
 842
 843         /* VLAN aware Switching */
 844         gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0);
 845
 846         /* Flush MAC Table */
 847         gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0);
 848
 849         err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0,
 850                                      GSWIP_PCE_GCTRL_0_MTFL);
 851         if (err) {
 852                 dev_err(priv->dev, "MAC flushing didn't finish\n");
 853                 return err;
 854         }
 855
 856         gswip_port_enable(ds, cpu_port, NULL);
 857         return 0;
 858 }
 859
 860 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds,
 861                                                     int port,
 862                                                     enum dsa_tag_protocol mp)
 863 {
 864         return DSA_TAG_PROTO_GSWIP;
 865 }
 866
 867 static int gswip_vlan_active_create(struct gswip_priv *priv,
 868                                     struct net_device *bridge,
 869                                     int fid, u16 vid)
 870 {
 871         struct gswip_pce_table_entry vlan_active = {0,};
 872         unsigned int max_ports = priv->hw_info->max_ports;
 873         int idx = -1;
 874         int err;
 875         int i;
 876
 877         /* Look for a free slot */
 878         for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
 879                 if (!priv->vlans[i].bridge) {
 880                         idx = i;
 881                         break;
 882                 }
 883         }
 884
 885         if (idx == -1)
 886                 return -ENOSPC;
 887
 888         if (fid == -1)
 889                 fid = idx;
 890
 891         vlan_active.index = idx;
 892         vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
 893         vlan_active.key[0] = vid;
 894         vlan_active.val[0] = fid;
 895         vlan_active.valid = true;
 896
 897         err = gswip_pce_table_entry_write(priv, &vlan_active);
 898         if (err) {
 899                 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
 900                 return err;
 901         }
 902
 903         priv->vlans[idx].bridge = bridge;
 904         priv->vlans[idx].vid = vid;
 905         priv->vlans[idx].fid = fid;
 906
 907         return idx;
 908 }
 909
 910 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx)
 911 {
 912         struct gswip_pce_table_entry vlan_active = {0,};
 913         int err;
 914
 915         vlan_active.index = idx;
 916         vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
 917         vlan_active.valid = false;
 918         err = gswip_pce_table_entry_write(priv, &vlan_active);
 919         if (err)
 920                 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err);
 921         priv->vlans[idx].bridge = NULL;
 922
 923         return err;
 924 }
 925
 926 static int gswip_vlan_add_unaware(struct gswip_priv *priv,
 927                                   struct net_device *bridge, int port)
 928 {
 929         struct gswip_pce_table_entry vlan_mapping = {0,};
 930         unsigned int max_ports = priv->hw_info->max_ports;
 931         unsigned int cpu_port = priv->hw_info->cpu_port;
 932         bool active_vlan_created = false;
 933         int idx = -1;
 934         int i;
 935         int err;
 936
 937         /* Check if there is already a page for this bridge */
 938         for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
 939                 if (priv->vlans[i].bridge == bridge) {
 940                         idx = i;
 941                         break;
 942                 }
 943         }
 944
 945         /* If this bridge is not programmed yet, add a Active VLAN table
 946          * entry in a free slot and prepare the VLAN mapping table entry.
 947          */
 948         if (idx == -1) {
 949                 idx = gswip_vlan_active_create(priv, bridge, -1, 0);
 950                 if (idx < 0)
 951                         return idx;
 952                 active_vlan_created = true;
 953
 954                 vlan_mapping.index = idx;
 955                 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
 956                 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
 957                 vlan_mapping.val[0] = 0;
 958         } else {
 959                 /* Read the existing VLAN mapping entry from the switch */
 960                 vlan_mapping.index = idx;
 961                 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
 962                 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
 963                 if (err) {
 964                         dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
 965                                 err);
 966                         return err;
 967                 }
 968         }
 969
 970         /* Update the VLAN mapping entry and write it to the switch */
 971         vlan_mapping.val[1] |= BIT(cpu_port);
 972         vlan_mapping.val[1] |= BIT(port);
 973         err = gswip_pce_table_entry_write(priv, &vlan_mapping);
 974         if (err) {
 975                 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
 976                 /* In case an Active VLAN was creaetd delete it again */
 977                 if (active_vlan_created)
 978                         gswip_vlan_active_remove(priv, idx);
 979                 return err;
 980         }
 981
 982         gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
 983         return 0;
 984 }
 985
 986 static int gswip_vlan_add_aware(struct gswip_priv *priv,
 987                                 struct net_device *bridge, int port,
 988                                 u16 vid, bool untagged,
 989                                 bool pvid)
 990 {
 991         struct gswip_pce_table_entry vlan_mapping = {0,};
 992         unsigned int max_ports = priv->hw_info->max_ports;
 993         unsigned int cpu_port = priv->hw_info->cpu_port;
 994         bool active_vlan_created = false;
 995         int idx = -1;
 996         int fid = -1;
 997         int i;
 998         int err;
 999
1000         /* Check if there is already a page for this bridge */
1001         for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1002                 if (priv->vlans[i].bridge == bridge) {
1003                         if (fid != -1 && fid != priv->vlans[i].fid)
1004                                 dev_err(priv->dev, "one bridge with multiple flow ids\n");
1005                         fid = priv->vlans[i].fid;
1006                         if (priv->vlans[i].vid == vid) {
1007                                 idx = i;
1008                                 break;
1009                         }
1010                 }
1011         }
1012
1013         /* If this bridge is not programmed yet, add a Active VLAN table
1014          * entry in a free slot and prepare the VLAN mapping table entry.
1015          */
1016         if (idx == -1) {
1017                 idx = gswip_vlan_active_create(priv, bridge, fid, vid);
1018                 if (idx < 0)
1019                         return idx;
1020                 active_vlan_created = true;
1021
1022                 vlan_mapping.index = idx;
1023                 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1024                 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
1025                 vlan_mapping.val[0] = vid;
1026         } else {
1027                 /* Read the existing VLAN mapping entry from the switch */
1028                 vlan_mapping.index = idx;
1029                 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1030                 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1031                 if (err) {
1032                         dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
1033                                 err);
1034                         return err;
1035                 }
1036         }
1037
1038         vlan_mapping.val[0] = vid;
1039         /* Update the VLAN mapping entry and write it to the switch */
1040         vlan_mapping.val[1] |= BIT(cpu_port);
1041         vlan_mapping.val[2] |= BIT(cpu_port);
1042         vlan_mapping.val[1] |= BIT(port);
1043         if (untagged)
1044                 vlan_mapping.val[2] &= ~BIT(port);
1045         else
1046                 vlan_mapping.val[2] |= BIT(port);
1047         err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1048         if (err) {
1049                 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1050                 /* In case an Active VLAN was creaetd delete it again */
1051                 if (active_vlan_created)
1052                         gswip_vlan_active_remove(priv, idx);
1053                 return err;
1054         }
1055
1056         if (pvid)
1057                 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port));
1058
1059         return 0;
1060 }
1061
1062 static int gswip_vlan_remove(struct gswip_priv *priv,
1063                              struct net_device *bridge, int port,
1064                              u16 vid, bool pvid, bool vlan_aware)
1065 {
1066         struct gswip_pce_table_entry vlan_mapping = {0,};
1067         unsigned int max_ports = priv->hw_info->max_ports;
1068         unsigned int cpu_port = priv->hw_info->cpu_port;
1069         int idx = -1;
1070         int i;
1071         int err;
1072
1073         /* Check if there is already a page for this bridge */
1074         for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1075                 if (priv->vlans[i].bridge == bridge &&
1076                     (!vlan_aware || priv->vlans[i].vid == vid)) {
1077                         idx = i;
1078                         break;
1079                 }
1080         }
1081
1082         if (idx == -1) {
1083                 dev_err(priv->dev, "bridge to leave does not exists\n");
1084                 return -ENOENT;
1085         }
1086
1087         vlan_mapping.index = idx;
1088         vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1089         err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1090         if (err) {
1091                 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err);
1092                 return err;
1093         }
1094
1095         vlan_mapping.val[1] &= ~BIT(port);
1096         vlan_mapping.val[2] &= ~BIT(port);
1097         err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1098         if (err) {
1099                 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1100                 return err;
1101         }
1102
1103         /* In case all ports are removed from the bridge, remove the VLAN */
1104         if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) {
1105                 err = gswip_vlan_active_remove(priv, idx);
1106                 if (err) {
1107                         dev_err(priv->dev, "failed to write active VLAN: %d\n",
1108                                 err);
1109                         return err;
1110                 }
1111         }
1112
1113         /* GSWIP 2.2 (GRX300) and later program here the VID directly. */
1114         if (pvid)
1115                 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
1116
1117         return 0;
1118 }
1119
1120 static int gswip_port_bridge_join(struct dsa_switch *ds, int port,
1121                                   struct net_device *bridge)
1122 {
1123         struct gswip_priv *priv = ds->priv;
1124         int err;
1125
1126         /* When the bridge uses VLAN filtering we have to configure VLAN
1127          * specific bridges. No bridge is configured here.
1128          */
1129         if (!br_vlan_enabled(bridge)) {
1130                 err = gswip_vlan_add_unaware(priv, bridge, port);
1131                 if (err)
1132                         return err;
1133                 priv->port_vlan_filter &= ~BIT(port);
1134         } else {
1135                 priv->port_vlan_filter |= BIT(port);
1136         }
1137         return gswip_add_single_port_br(priv, port, false);
1138 }
1139
1140 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port,
1141                                     struct net_device *bridge)
1142 {
1143         struct gswip_priv *priv = ds->priv;
1144
1145         gswip_add_single_port_br(priv, port, true);
1146
1147         /* When the bridge uses VLAN filtering we have to configure VLAN
1148          * specific bridges. No bridge is configured here.
1149          */
1150         if (!br_vlan_enabled(bridge))
1151                 gswip_vlan_remove(priv, bridge, port, 0, true, false);
1152 }
1153
1154 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port,
1155                                    const struct switchdev_obj_port_vlan *vlan)
1156 {
1157         struct gswip_priv *priv = ds->priv;
1158         struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1159         unsigned int max_ports = priv->hw_info->max_ports;
1160         u16 vid;
1161         int i;
1162         int pos = max_ports;
1163
1164         /* We only support VLAN filtering on bridges */
1165         if (!dsa_is_cpu_port(ds, port) && !bridge)
1166                 return -EOPNOTSUPP;
1167
1168         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1169                 int idx = -1;
1170
1171                 /* Check if there is already a page for this VLAN */
1172                 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1173                         if (priv->vlans[i].bridge == bridge &&
1174                             priv->vlans[i].vid == vid) {
1175                                 idx = i;
1176                                 break;
1177                         }
1178                 }
1179
1180                 /* If this VLAN is not programmed yet, we have to reserve
1181                  * one entry in the VLAN table. Make sure we start at the
1182                  * next position round.
1183                  */
1184                 if (idx == -1) {
1185                         /* Look for a free slot */
1186                         for (; pos < ARRAY_SIZE(priv->vlans); pos++) {
1187                                 if (!priv->vlans[pos].bridge) {
1188                                         idx = pos;
1189                                         pos++;
1190                                         break;
1191                                 }
1192                         }
1193
1194                         if (idx == -1)
1195                                 return -ENOSPC;
1196                 }
1197         }
1198
1199         return 0;
1200 }
1201
1202 static void gswip_port_vlan_add(struct dsa_switch *ds, int port,
1203                                 const struct switchdev_obj_port_vlan *vlan)
1204 {
1205         struct gswip_priv *priv = ds->priv;
1206         struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1207         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1208         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1209         u16 vid;
1210
1211         /* We have to receive all packets on the CPU port and should not
1212          * do any VLAN filtering here. This is also called with bridge
1213          * NULL and then we do not know for which bridge to configure
1214          * this.
1215          */
1216         if (dsa_is_cpu_port(ds, port))
1217                 return;
1218
1219         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1220                 gswip_vlan_add_aware(priv, bridge, port, vid, untagged, pvid);
1221 }
1222
1223 static int gswip_port_vlan_del(struct dsa_switch *ds, int port,
1224                                const struct switchdev_obj_port_vlan *vlan)
1225 {
1226         struct gswip_priv *priv = ds->priv;
1227         struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1228         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1229         u16 vid;
1230         int err;
1231
1232         /* We have to receive all packets on the CPU port and should not
1233          * do any VLAN filtering here. This is also called with bridge
1234          * NULL and then we do not know for which bridge to configure
1235          * this.
1236          */
1237         if (dsa_is_cpu_port(ds, port))
1238                 return 0;
1239
1240         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1241                 err = gswip_vlan_remove(priv, bridge, port, vid, pvid, true);
1242                 if (err)
1243                         return err;
1244         }
1245
1246         return 0;
1247 }
1248
1249 static void gswip_port_fast_age(struct dsa_switch *ds, int port)
1250 {
1251         struct gswip_priv *priv = ds->priv;
1252         struct gswip_pce_table_entry mac_bridge = {0,};
1253         int i;
1254         int err;
1255
1256         for (i = 0; i < 2048; i++) {
1257                 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1258                 mac_bridge.index = i;
1259
1260                 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1261                 if (err) {
1262                         dev_err(priv->dev, "failed to read mac bridge: %d\n",
1263                                 err);
1264                         return;
1265                 }
1266
1267                 if (!mac_bridge.valid)
1268                         continue;
1269
1270                 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC)
1271                         continue;
1272
1273                 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port)
1274                         continue;
1275
1276                 mac_bridge.valid = false;
1277                 err = gswip_pce_table_entry_write(priv, &mac_bridge);
1278                 if (err) {
1279                         dev_err(priv->dev, "failed to write mac bridge: %d\n",
1280                                 err);
1281                         return;
1282                 }
1283         }
1284 }
1285
1286 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1287 {
1288         struct gswip_priv *priv = ds->priv;
1289         u32 stp_state;
1290
1291         switch (state) {
1292         case BR_STATE_DISABLED:
1293                 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
1294                                   GSWIP_SDMA_PCTRLp(port));
1295                 return;
1296         case BR_STATE_BLOCKING:
1297         case BR_STATE_LISTENING:
1298                 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN;
1299                 break;
1300         case BR_STATE_LEARNING:
1301                 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING;
1302                 break;
1303         case BR_STATE_FORWARDING:
1304                 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING;
1305                 break;
1306         default:
1307                 dev_err(priv->dev, "invalid STP state: %d\n", state);
1308                 return;
1309         }
1310
1311         gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
1312                           GSWIP_SDMA_PCTRLp(port));
1313         gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state,
1314                           GSWIP_PCE_PCTRL_0p(port));
1315 }
1316
1317 static int gswip_port_fdb(struct dsa_switch *ds, int port,
1318                           const unsigned char *addr, u16 vid, bool add)
1319 {
1320         struct gswip_priv *priv = ds->priv;
1321         struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1322         struct gswip_pce_table_entry mac_bridge = {0,};
1323         unsigned int cpu_port = priv->hw_info->cpu_port;
1324         int fid = -1;
1325         int i;
1326         int err;
1327
1328         if (!bridge)
1329                 return -EINVAL;
1330
1331         for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) {
1332                 if (priv->vlans[i].bridge == bridge) {
1333                         fid = priv->vlans[i].fid;
1334                         break;
1335                 }
1336         }
1337
1338         if (fid == -1) {
1339                 dev_err(priv->dev, "Port not part of a bridge\n");
1340                 return -EINVAL;
1341         }
1342
1343         mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1344         mac_bridge.key_mode = true;
1345         mac_bridge.key[0] = addr[5] | (addr[4] << 8);
1346         mac_bridge.key[1] = addr[3] | (addr[2] << 8);
1347         mac_bridge.key[2] = addr[1] | (addr[0] << 8);
1348         mac_bridge.key[3] = fid;
1349         mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
1350         mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC;
1351         mac_bridge.valid = add;
1352
1353         err = gswip_pce_table_entry_write(priv, &mac_bridge);
1354         if (err)
1355                 dev_err(priv->dev, "failed to write mac bridge: %d\n", err);
1356
1357         return err;
1358 }
1359
1360 static int gswip_port_fdb_add(struct dsa_switch *ds, int port,
1361                               const unsigned char *addr, u16 vid)
1362 {
1363         return gswip_port_fdb(ds, port, addr, vid, true);
1364 }
1365
1366 static int gswip_port_fdb_del(struct dsa_switch *ds, int port,
1367                               const unsigned char *addr, u16 vid)
1368 {
1369         return gswip_port_fdb(ds, port, addr, vid, false);
1370 }
1371
1372 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port,
1373                                dsa_fdb_dump_cb_t *cb, void *data)
1374 {
1375         struct gswip_priv *priv = ds->priv;
1376         struct gswip_pce_table_entry mac_bridge = {0,};
1377         unsigned char addr[6];
1378         int i;
1379         int err;
1380
1381         for (i = 0; i < 2048; i++) {
1382                 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1383                 mac_bridge.index = i;
1384
1385                 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1386                 if (err) {
1387                         dev_err(priv->dev, "failed to write mac bridge: %d\n",
1388                                 err);
1389                         return err;
1390                 }
1391
1392                 if (!mac_bridge.valid)
1393                         continue;
1394
1395                 addr[5] = mac_bridge.key[0] & 0xff;
1396                 addr[4] = (mac_bridge.key[0] >> 8) & 0xff;
1397                 addr[3] = mac_bridge.key[1] & 0xff;
1398                 addr[2] = (mac_bridge.key[1] >> 8) & 0xff;
1399                 addr[1] = mac_bridge.key[2] & 0xff;
1400                 addr[0] = (mac_bridge.key[2] >> 8) & 0xff;
1401                 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) {
1402                         if (mac_bridge.val[0] & BIT(port))
1403                                 cb(addr, 0, true, data);
1404                 } else {
1405                         if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port)
1406                                 cb(addr, 0, false, data);
1407                 }
1408         }
1409         return 0;
1410 }
1411
1412 static void gswip_phylink_validate(struct dsa_switch *ds, int port,
1413                                    unsigned long *supported,
1414                                    struct phylink_link_state *state)
1415 {
1416         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1417
1418         switch (port) {
1419         case 0:
1420         case 1:
1421                 if (!phy_interface_mode_is_rgmii(state->interface) &&
1422                     state->interface != PHY_INTERFACE_MODE_MII &&
1423                     state->interface != PHY_INTERFACE_MODE_REVMII &&
1424                     state->interface != PHY_INTERFACE_MODE_RMII)
1425                         goto unsupported;
1426                 break;
1427         case 2:
1428         case 3:
1429         case 4:
1430                 if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
1431                         goto unsupported;
1432                 break;
1433         case 5:
1434                 if (!phy_interface_mode_is_rgmii(state->interface) &&
1435                     state->interface != PHY_INTERFACE_MODE_INTERNAL)
1436                         goto unsupported;
1437                 break;
1438         default:
1439                 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1440                 dev_err(ds->dev, "Unsupported port: %i\n", port);
1441                 return;
1442         }
1443
1444         /* Allow all the expected bits */
1445         phylink_set(mask, Autoneg);
1446         phylink_set_port_modes(mask);
1447         phylink_set(mask, Pause);
1448         phylink_set(mask, Asym_Pause);
1449
1450         /* With the exclusion of MII and Reverse MII, we support Gigabit,
1451          * including Half duplex
1452          */
1453         if (state->interface != PHY_INTERFACE_MODE_MII &&
1454             state->interface != PHY_INTERFACE_MODE_REVMII) {
1455                 phylink_set(mask, 1000baseT_Full);
1456                 phylink_set(mask, 1000baseT_Half);
1457         }
1458
1459         phylink_set(mask, 10baseT_Half);
1460         phylink_set(mask, 10baseT_Full);
1461         phylink_set(mask, 100baseT_Half);
1462         phylink_set(mask, 100baseT_Full);
1463
1464         bitmap_and(supported, supported, mask,
1465                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1466         bitmap_and(state->advertising, state->advertising, mask,
1467                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1468         return;
1469
1470 unsupported:
1471         bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1472         dev_err(ds->dev, "Unsupported interface '%s' for port %d\n",
1473                 phy_modes(state->interface), port);
1474         return;
1475 }
1476
1477 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port,
1478                                      unsigned int mode,
1479                                      const struct phylink_link_state *state)
1480 {
1481         struct gswip_priv *priv = ds->priv;
1482         u32 miicfg = 0;
1483
1484         miicfg |= GSWIP_MII_CFG_LDCLKDIS;
1485
1486         switch (state->interface) {
1487         case PHY_INTERFACE_MODE_MII:
1488         case PHY_INTERFACE_MODE_INTERNAL:
1489                 miicfg |= GSWIP_MII_CFG_MODE_MIIM;
1490                 break;
1491         case PHY_INTERFACE_MODE_REVMII:
1492                 miicfg |= GSWIP_MII_CFG_MODE_MIIP;
1493                 break;
1494         case PHY_INTERFACE_MODE_RMII:
1495                 miicfg |= GSWIP_MII_CFG_MODE_RMIIM;
1496                 break;
1497         case PHY_INTERFACE_MODE_RGMII:
1498         case PHY_INTERFACE_MODE_RGMII_ID:
1499         case PHY_INTERFACE_MODE_RGMII_RXID:
1500         case PHY_INTERFACE_MODE_RGMII_TXID:
1501                 miicfg |= GSWIP_MII_CFG_MODE_RGMII;
1502                 break;
1503         default:
1504                 dev_err(ds->dev,
1505                         "Unsupported interface: %d\n", state->interface);
1506                 return;
1507         }
1508         gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_MODE_MASK, miicfg, port);
1509
1510         switch (state->interface) {
1511         case PHY_INTERFACE_MODE_RGMII_ID:
1512                 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK |
1513                                           GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1514                 break;
1515         case PHY_INTERFACE_MODE_RGMII_RXID:
1516                 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1517                 break;
1518         case PHY_INTERFACE_MODE_RGMII_TXID:
1519                 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port);
1520                 break;
1521         default:
1522                 break;
1523         }
1524 }
1525
1526 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port,
1527                                         unsigned int mode,
1528                                         phy_interface_t interface)
1529 {
1530         struct gswip_priv *priv = ds->priv;
1531
1532         gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port);
1533 }
1534
1535 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port,
1536                                       unsigned int mode,
1537                                       phy_interface_t interface,
1538                                       struct phy_device *phydev,
1539                                       int speed, int duplex,
1540                                       bool tx_pause, bool rx_pause)
1541 {
1542         struct gswip_priv *priv = ds->priv;
1543
1544         /* Enable the xMII interface only for the external PHY */
1545         if (interface != PHY_INTERFACE_MODE_INTERNAL)
1546                 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port);
1547 }
1548
1549 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset,
1550                               uint8_t *data)
1551 {
1552         int i;
1553
1554         if (stringset != ETH_SS_STATS)
1555                 return;
1556
1557         for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++)
1558                 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name,
1559                         ETH_GSTRING_LEN);
1560 }
1561
1562 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table,
1563                                     u32 index)
1564 {
1565         u32 result;
1566         int err;
1567
1568         gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR);
1569         gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK |
1570                                 GSWIP_BM_RAM_CTRL_OPMOD,
1571                               table | GSWIP_BM_RAM_CTRL_BAS,
1572                               GSWIP_BM_RAM_CTRL);
1573
1574         err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL,
1575                                      GSWIP_BM_RAM_CTRL_BAS);
1576         if (err) {
1577                 dev_err(priv->dev, "timeout while reading table: %u, index: %u",
1578                         table, index);
1579                 return 0;
1580         }
1581
1582         result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0));
1583         result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16;
1584
1585         return result;
1586 }
1587
1588 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port,
1589                                     uint64_t *data)
1590 {
1591         struct gswip_priv *priv = ds->priv;
1592         const struct gswip_rmon_cnt_desc *rmon_cnt;
1593         int i;
1594         u64 high;
1595
1596         for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) {
1597                 rmon_cnt = &gswip_rmon_cnt[i];
1598
1599                 data[i] = gswip_bcm_ram_entry_read(priv, port,
1600                                                    rmon_cnt->offset);
1601                 if (rmon_cnt->size == 2) {
1602                         high = gswip_bcm_ram_entry_read(priv, port,
1603                                                         rmon_cnt->offset + 1);
1604                         data[i] |= high << 32;
1605                 }
1606         }
1607 }
1608
1609 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset)
1610 {
1611         if (sset != ETH_SS_STATS)
1612                 return 0;
1613
1614         return ARRAY_SIZE(gswip_rmon_cnt);
1615 }
1616
1617 static const struct dsa_switch_ops gswip_switch_ops = {
1618         .get_tag_protocol       = gswip_get_tag_protocol,
1619         .setup                  = gswip_setup,
1620         .port_enable            = gswip_port_enable,
1621         .port_disable           = gswip_port_disable,
1622         .port_bridge_join       = gswip_port_bridge_join,
1623         .port_bridge_leave      = gswip_port_bridge_leave,
1624         .port_fast_age          = gswip_port_fast_age,
1625         .port_vlan_filtering    = gswip_port_vlan_filtering,
1626         .port_vlan_prepare      = gswip_port_vlan_prepare,
1627         .port_vlan_add          = gswip_port_vlan_add,
1628         .port_vlan_del          = gswip_port_vlan_del,
1629         .port_stp_state_set     = gswip_port_stp_state_set,
1630         .port_fdb_add           = gswip_port_fdb_add,
1631         .port_fdb_del           = gswip_port_fdb_del,
1632         .port_fdb_dump          = gswip_port_fdb_dump,
1633         .phylink_validate       = gswip_phylink_validate,
1634         .phylink_mac_config     = gswip_phylink_mac_config,
1635         .phylink_mac_link_down  = gswip_phylink_mac_link_down,
1636         .phylink_mac_link_up    = gswip_phylink_mac_link_up,
1637         .get_strings            = gswip_get_strings,
1638         .get_ethtool_stats      = gswip_get_ethtool_stats,
1639         .get_sset_count         = gswip_get_sset_count,
1640 };
1641
1642 static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
1643         .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
1644         .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
1645 };
1646
1647 static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
1648         .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
1649         .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
1650 };
1651
1652 static const struct xway_gphy_match_data xrx300_gphy_data = {
1653         .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
1654         .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
1655 };
1656
1657 static const struct of_device_id xway_gphy_match[] = {
1658         { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL },
1659         { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data },
1660         { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data },
1661         { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data },
1662         { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data },
1663         {},
1664 };
1665
1666 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw)
1667 {
1668         struct device *dev = priv->dev;
1669         const struct firmware *fw;
1670         void *fw_addr;
1671         dma_addr_t dma_addr;
1672         dma_addr_t dev_addr;
1673         size_t size;
1674         int ret;
1675
1676         ret = clk_prepare_enable(gphy_fw->clk_gate);
1677         if (ret)
1678                 return ret;
1679
1680         reset_control_assert(gphy_fw->reset);
1681
1682         ret = request_firmware(&fw, gphy_fw->fw_name, dev);
1683         if (ret) {
1684                 dev_err(dev, "failed to load firmware: %s, error: %i\n",
1685                         gphy_fw->fw_name, ret);
1686                 return ret;
1687         }
1688
1689         /* GPHY cores need the firmware code in a persistent and contiguous
1690          * memory area with a 16 kB boundary aligned start address.
1691          */
1692         size = fw->size + XRX200_GPHY_FW_ALIGN;
1693
1694         fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
1695         if (fw_addr) {
1696                 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
1697                 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
1698                 memcpy(fw_addr, fw->data, fw->size);
1699         } else {
1700                 dev_err(dev, "failed to alloc firmware memory\n");
1701                 release_firmware(fw);
1702                 return -ENOMEM;
1703         }
1704
1705         release_firmware(fw);
1706
1707         ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr);
1708         if (ret)
1709                 return ret;
1710
1711         reset_control_deassert(gphy_fw->reset);
1712
1713         return ret;
1714 }
1715
1716 static int gswip_gphy_fw_probe(struct gswip_priv *priv,
1717                                struct gswip_gphy_fw *gphy_fw,
1718                                struct device_node *gphy_fw_np, int i)
1719 {
1720         struct device *dev = priv->dev;
1721         u32 gphy_mode;
1722         int ret;
1723         char gphyname[10];
1724
1725         snprintf(gphyname, sizeof(gphyname), "gphy%d", i);
1726
1727         gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
1728         if (IS_ERR(gphy_fw->clk_gate)) {
1729                 dev_err(dev, "Failed to lookup gate clock\n");
1730                 return PTR_ERR(gphy_fw->clk_gate);
1731         }
1732
1733         ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
1734         if (ret)
1735                 return ret;
1736
1737         ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode);
1738         /* Default to GE mode */
1739         if (ret)
1740                 gphy_mode = GPHY_MODE_GE;
1741
1742         switch (gphy_mode) {
1743         case GPHY_MODE_FE:
1744                 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name;
1745                 break;
1746         case GPHY_MODE_GE:
1747                 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
1748                 break;
1749         default:
1750                 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
1751                 return -EINVAL;
1752         }
1753
1754         gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
1755         if (IS_ERR(gphy_fw->reset)) {
1756                 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER)
1757                         dev_err(dev, "Failed to lookup gphy reset\n");
1758                 return PTR_ERR(gphy_fw->reset);
1759         }
1760
1761         return gswip_gphy_fw_load(priv, gphy_fw);
1762 }
1763
1764 static void gswip_gphy_fw_remove(struct gswip_priv *priv,
1765                                  struct gswip_gphy_fw *gphy_fw)
1766 {
1767         int ret;
1768
1769         /* check if the device was fully probed */
1770         if (!gphy_fw->fw_name)
1771                 return;
1772
1773         ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0);
1774         if (ret)
1775                 dev_err(priv->dev, "can not reset GPHY FW pointer");
1776
1777         clk_disable_unprepare(gphy_fw->clk_gate);
1778
1779         reset_control_put(gphy_fw->reset);
1780 }
1781
1782 static int gswip_gphy_fw_list(struct gswip_priv *priv,
1783                               struct device_node *gphy_fw_list_np, u32 version)
1784 {
1785         struct device *dev = priv->dev;
1786         struct device_node *gphy_fw_np;
1787         const struct of_device_id *match;
1788         int err;
1789         int i = 0;
1790
1791         /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older
1792          * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also
1793          * needs a different GPHY firmware.
1794          */
1795         if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) {
1796                 switch (version) {
1797                 case GSWIP_VERSION_2_0:
1798                         priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data;
1799                         break;
1800                 case GSWIP_VERSION_2_1:
1801                         priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
1802                         break;
1803                 default:
1804                         dev_err(dev, "unknown GSWIP version: 0x%x", version);
1805                         return -ENOENT;
1806                 }
1807         }
1808
1809         match = of_match_node(xway_gphy_match, gphy_fw_list_np);
1810         if (match && match->data)
1811                 priv->gphy_fw_name_cfg = match->data;
1812
1813         if (!priv->gphy_fw_name_cfg) {
1814                 dev_err(dev, "GPHY compatible type not supported");
1815                 return -ENOENT;
1816         }
1817
1818         priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
1819         if (!priv->num_gphy_fw)
1820                 return -ENOENT;
1821
1822         priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np,
1823                                                            "lantiq,rcu");
1824         if (IS_ERR(priv->rcu_regmap))
1825                 return PTR_ERR(priv->rcu_regmap);
1826
1827         priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw,
1828                                            sizeof(*priv->gphy_fw),
1829                                            GFP_KERNEL | __GFP_ZERO);
1830         if (!priv->gphy_fw)
1831                 return -ENOMEM;
1832
1833         for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) {
1834                 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i],
1835                                           gphy_fw_np, i);
1836                 if (err)
1837                         goto remove_gphy;
1838                 i++;
1839         }
1840
1841         /* The standalone PHY11G requires 300ms to be fully
1842          * initialized and ready for any MDIO communication after being
1843          * taken out of reset. For the SoC-internal GPHY variant there
1844          * is no (known) documentation for the minimum time after a
1845          * reset. Use the same value as for the standalone variant as
1846          * some users have reported internal PHYs not being detected
1847          * without any delay.
1848          */
1849         msleep(300);
1850
1851         return 0;
1852
1853 remove_gphy:
1854         for (i = 0; i < priv->num_gphy_fw; i++)
1855                 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
1856         return err;
1857 }
1858
1859 static int gswip_probe(struct platform_device *pdev)
1860 {
1861         struct gswip_priv *priv;
1862         struct device_node *mdio_np, *gphy_fw_np;
1863         struct device *dev = &pdev->dev;
1864         int err;
1865         int i;
1866         u32 version;
1867
1868         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1869         if (!priv)
1870                 return -ENOMEM;
1871
1872         priv->gswip = devm_platform_ioremap_resource(pdev, 0);
1873         if (IS_ERR(priv->gswip))
1874                 return PTR_ERR(priv->gswip);
1875
1876         priv->mdio = devm_platform_ioremap_resource(pdev, 1);
1877         if (IS_ERR(priv->mdio))
1878                 return PTR_ERR(priv->mdio);
1879
1880         priv->mii = devm_platform_ioremap_resource(pdev, 2);
1881         if (IS_ERR(priv->mii))
1882                 return PTR_ERR(priv->mii);
1883
1884         priv->hw_info = of_device_get_match_data(dev);
1885         if (!priv->hw_info)
1886                 return -EINVAL;
1887
1888         priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
1889         if (!priv->ds)
1890                 return -ENOMEM;
1891
1892         priv->ds->dev = dev;
1893         priv->ds->num_ports = priv->hw_info->max_ports;
1894         priv->ds->priv = priv;
1895         priv->ds->ops = &gswip_switch_ops;
1896         priv->dev = dev;
1897         version = gswip_switch_r(priv, GSWIP_VERSION);
1898
1899         /* bring up the mdio bus */
1900         gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw");
1901         if (gphy_fw_np) {
1902                 err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
1903                 of_node_put(gphy_fw_np);
1904                 if (err) {
1905                         dev_err(dev, "gphy fw probe failed\n");
1906                         return err;
1907                 }
1908         }
1909
1910         /* bring up the mdio bus */
1911         mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio");
1912         if (mdio_np) {
1913                 err = gswip_mdio(priv, mdio_np);
1914                 if (err) {
1915                         dev_err(dev, "mdio probe failed\n");
1916                         goto put_mdio_node;
1917                 }
1918         }
1919
1920         err = dsa_register_switch(priv->ds);
1921         if (err) {
1922                 dev_err(dev, "dsa switch register failed: %i\n", err);
1923                 goto mdio_bus;
1924         }
1925         if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
1926                 dev_err(dev, "wrong CPU port defined, HW only supports port: %i",
1927                         priv->hw_info->cpu_port);
1928                 err = -EINVAL;
1929                 goto disable_switch;
1930         }
1931
1932         platform_set_drvdata(pdev, priv);
1933
1934         dev_info(dev, "probed GSWIP version %lx mod %lx\n",
1935                  (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT,
1936                  (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT);
1937         return 0;
1938
1939 disable_switch:
1940         gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
1941         dsa_unregister_switch(priv->ds);
1942 mdio_bus:
1943         if (mdio_np)
1944                 mdiobus_unregister(priv->ds->slave_mii_bus);
1945 put_mdio_node:
1946         of_node_put(mdio_np);
1947         for (i = 0; i < priv->num_gphy_fw; i++)
1948                 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
1949         return err;
1950 }
1951
1952 static int gswip_remove(struct platform_device *pdev)
1953 {
1954         struct gswip_priv *priv = platform_get_drvdata(pdev);
1955         int i;
1956
1957         /* disable the switch */
1958         gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
1959
1960         dsa_unregister_switch(priv->ds);
1961
1962         if (priv->ds->slave_mii_bus) {
1963                 mdiobus_unregister(priv->ds->slave_mii_bus);
1964                 of_node_put(priv->ds->slave_mii_bus->dev.of_node);
1965         }
1966
1967         for (i = 0; i < priv->num_gphy_fw; i++)
1968                 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
1969
1970         return 0;
1971 }
1972
1973 static const struct gswip_hw_info gswip_xrx200 = {
1974         .max_ports = 7,
1975         .cpu_port = 6,
1976 };
1977
1978 static const struct of_device_id gswip_of_match[] = {
1979         { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 },
1980         {},
1981 };
1982 MODULE_DEVICE_TABLE(of, gswip_of_match);
1983
1984 static struct platform_driver gswip_driver = {
1985         .probe = gswip_probe,
1986         .remove = gswip_remove,
1987         .driver = {
1988                 .name = "gswip",
1989                 .of_match_table = gswip_of_match,
1990         },
1991 };
1992
1993 module_platform_driver(gswip_driver);
1994
1995 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
1996 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
1997 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
1998 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
1999 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
2000 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
2001 MODULE_AUTHOR("Hauke Mehrtens <[email protected]>");
2002 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver");
2003 MODULE_LICENSE("GPL v2");