drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_i2c.h"
  30 #include "atom.h"
  31 #include "amdgpu_connectors.h"
  32 #include <asm/div64.h>
  33
  34 #include <linux/pm_runtime.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_edid.h>
  37
  38 static void amdgpu_flip_wait_fence(struct amdgpu_device *adev,
  39                                    struct fence **f)
  40 {
  41         struct amdgpu_fence *fence;
  42         long r;
  43
  44         if (*f == NULL)
  45                 return;
  46
  47         fence = to_amdgpu_fence(*f);
  48         if (fence) {
  49                 r = fence_wait(&fence->base, false);
  50                 if (r == -EDEADLK) {
  51                         up_read(&adev->exclusive_lock);
  52                         r = amdgpu_gpu_reset(adev);
  53                         down_read(&adev->exclusive_lock);
  54                 }
  55         } else
  56                 r = fence_wait(*f, false);
  57
  58         if (r)
  59                 DRM_ERROR("failed to wait on page flip fence (%ld)!\n", r);
  60
  61         /* We continue with the page flip even if we failed to wait on
  62          * the fence, otherwise the DRM core and userspace will be
  63          * confused about which BO the CRTC is scanning out
  64          */
  65         fence_put(*f);
  66         *f = NULL;
  67 }
  68
  69 static void amdgpu_flip_work_func(struct work_struct *__work)
  70 {
  71         struct amdgpu_flip_work *work =
  72                 container_of(__work, struct amdgpu_flip_work, flip_work);
  73         struct amdgpu_device *adev = work->adev;
  74         struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id];
  75
  76         struct drm_crtc *crtc = &amdgpuCrtc->base;
  77         unsigned long flags;
  78         unsigned i;
  79
  80         down_read(&adev->exclusive_lock);
  81         amdgpu_flip_wait_fence(adev, &work->excl);
  82         for (i = 0; i < work->shared_count; ++i)
  83                 amdgpu_flip_wait_fence(adev, &work->shared[i]);
  84
  85         /* We borrow the event spin lock for protecting flip_status */
  86         spin_lock_irqsave(&crtc->dev->event_lock, flags);
  87
  88         /* set the proper interrupt */
  89         amdgpu_irq_get(adev, &adev->pageflip_irq, work->crtc_id);
  90         /* do the flip (mmio) */
  91         adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base);
  92         /* set the flip status */
  93         amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
  94
  95         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  96         up_read(&adev->exclusive_lock);
  97 }
  98
  99 /*
 100  * Handle unpin events outside the interrupt handler proper.
 101  */
 102 static void amdgpu_unpin_work_func(struct work_struct *__work)
 103 {
 104         struct amdgpu_flip_work *work =
 105                 container_of(__work, struct amdgpu_flip_work, unpin_work);
 106         int r;
 107
 108         /* unpin of the old buffer */
 109         r = amdgpu_bo_reserve(work->old_rbo, false);
 110         if (likely(r == 0)) {
 111                 r = amdgpu_bo_unpin(work->old_rbo);
 112                 if (unlikely(r != 0)) {
 113                         DRM_ERROR("failed to unpin buffer after flip\n");
 114                 }
 115                 amdgpu_bo_unreserve(work->old_rbo);
 116         } else
 117                 DRM_ERROR("failed to reserve buffer after flip\n");
 118
 119         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 120         kfree(work->shared);
 121         kfree(work);
 122 }
 123
 124 int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
 125                           struct drm_framebuffer *fb,
 126                           struct drm_pending_vblank_event *event,
 127                           uint32_t page_flip_flags)
 128 {
 129         struct drm_device *dev = crtc->dev;
 130         struct amdgpu_device *adev = dev->dev_private;
 131         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 132         struct amdgpu_framebuffer *old_amdgpu_fb;
 133         struct amdgpu_framebuffer *new_amdgpu_fb;
 134         struct drm_gem_object *obj;
 135         struct amdgpu_flip_work *work;
 136         struct amdgpu_bo *new_rbo;
 137         unsigned long flags;
 138         u64 tiling_flags;
 139         u64 base;
 140         int i, r;
 141
 142         work = kzalloc(sizeof *work, GFP_KERNEL);
 143         if (work == NULL)
 144                 return -ENOMEM;
 145
 146         INIT_WORK(&work->flip_work, amdgpu_flip_work_func);
 147         INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func);
 148
 149         work->event = event;
 150         work->adev = adev;
 151         work->crtc_id = amdgpu_crtc->crtc_id;
 152
 153         /* schedule unpin of the old buffer */
 154         old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
 155         obj = old_amdgpu_fb->obj;
 156
 157         /* take a reference to the old object */
 158         drm_gem_object_reference(obj);
 159         work->old_rbo = gem_to_amdgpu_bo(obj);
 160
 161         new_amdgpu_fb = to_amdgpu_framebuffer(fb);
 162         obj = new_amdgpu_fb->obj;
 163         new_rbo = gem_to_amdgpu_bo(obj);
 164
 165         /* pin the new buffer */
 166         r = amdgpu_bo_reserve(new_rbo, false);
 167         if (unlikely(r != 0)) {
 168                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 169                 goto cleanup;
 170         }
 171
 172         r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base);
 173         if (unlikely(r != 0)) {
 174                 amdgpu_bo_unreserve(new_rbo);
 175                 r = -EINVAL;
 176                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 177                 goto cleanup;
 178         }
 179
 180         r = reservation_object_get_fences_rcu(new_rbo->tbo.resv, &work->excl,
 181                                               &work->shared_count,
 182                                               &work->shared);
 183         if (unlikely(r != 0)) {
 184                 amdgpu_bo_unreserve(new_rbo);
 185                 DRM_ERROR("failed to get fences for buffer\n");
 186                 goto cleanup;
 187         }
 188
 189         fence_get(work->excl);
 190         for (i = 0; i < work->shared_count; ++i)
 191                 fence_get(work->shared[i]);
 192
 193         amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags);
 194         amdgpu_bo_unreserve(new_rbo);
 195
 196         work->base = base;
 197
 198         r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id);
 199         if (r) {
 200                 DRM_ERROR("failed to get vblank before flip\n");
 201                 goto pflip_cleanup;
 202         }
 203
 204         /* we borrow the event spin lock for protecting flip_wrok */
 205         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 206         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
 207                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 208                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 209                 r = -EBUSY;
 210                 goto vblank_cleanup;
 211         }
 212
 213         amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
 214         amdgpu_crtc->pflip_works = work;
 215
 216         /* update crtc fb */
 217         crtc->primary->fb = fb;
 218         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 219         queue_work(amdgpu_crtc->pflip_queue, &work->flip_work);
 220         return 0;
 221
 222 vblank_cleanup:
 223         drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id);
 224
 225 pflip_cleanup:
 226         if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) {
 227                 DRM_ERROR("failed to reserve new rbo in error path\n");
 228                 goto cleanup;
 229         }
 230         if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) {
 231                 DRM_ERROR("failed to unpin new rbo in error path\n");
 232         }
 233         amdgpu_bo_unreserve(new_rbo);
 234
 235 cleanup:
 236         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 237         fence_put(work->excl);
 238         for (i = 0; i < work->shared_count; ++i)
 239                 fence_put(work->shared[i]);
 240         kfree(work->shared);
 241         kfree(work);
 242
 243         return r;
 244 }
 245
 246 int amdgpu_crtc_set_config(struct drm_mode_set *set)
 247 {
 248         struct drm_device *dev;
 249         struct amdgpu_device *adev;
 250         struct drm_crtc *crtc;
 251         bool active = false;
 252         int ret;
 253
 254         if (!set || !set->crtc)
 255                 return -EINVAL;
 256
 257         dev = set->crtc->dev;
 258
 259         ret = pm_runtime_get_sync(dev->dev);
 260         if (ret < 0)
 261                 return ret;
 262
 263         ret = drm_crtc_helper_set_config(set);
 264
 265         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 266                 if (crtc->enabled)
 267                         active = true;
 268
 269         pm_runtime_mark_last_busy(dev->dev);
 270
 271         adev = dev->dev_private;
 272         /* if we have active crtcs and we don't have a power ref,
 273            take the current one */
 274         if (active && !adev->have_disp_power_ref) {
 275                 adev->have_disp_power_ref = true;
 276                 return ret;
 277         }
 278         /* if we have no active crtcs, then drop the power ref
 279            we got before */
 280         if (!active && adev->have_disp_power_ref) {
 281                 pm_runtime_put_autosuspend(dev->dev);
 282                 adev->have_disp_power_ref = false;
 283         }
 284
 285         /* drop the power reference we got coming in here */
 286         pm_runtime_put_autosuspend(dev->dev);
 287         return ret;
 288 }
 289
 290 static const char *encoder_names[38] = {
 291         "NONE",
 292         "INTERNAL_LVDS",
 293         "INTERNAL_TMDS1",
 294         "INTERNAL_TMDS2",
 295         "INTERNAL_DAC1",
 296         "INTERNAL_DAC2",
 297         "INTERNAL_SDVOA",
 298         "INTERNAL_SDVOB",
 299         "SI170B",
 300         "CH7303",
 301         "CH7301",
 302         "INTERNAL_DVO1",
 303         "EXTERNAL_SDVOA",
 304         "EXTERNAL_SDVOB",
 305         "TITFP513",
 306         "INTERNAL_LVTM1",
 307         "VT1623",
 308         "HDMI_SI1930",
 309         "HDMI_INTERNAL",
 310         "INTERNAL_KLDSCP_TMDS1",
 311         "INTERNAL_KLDSCP_DVO1",
 312         "INTERNAL_KLDSCP_DAC1",
 313         "INTERNAL_KLDSCP_DAC2",
 314         "SI178",
 315         "MVPU_FPGA",
 316         "INTERNAL_DDI",
 317         "VT1625",
 318         "HDMI_SI1932",
 319         "DP_AN9801",
 320         "DP_DP501",
 321         "INTERNAL_UNIPHY",
 322         "INTERNAL_KLDSCP_LVTMA",
 323         "INTERNAL_UNIPHY1",
 324         "INTERNAL_UNIPHY2",
 325         "NUTMEG",
 326         "TRAVIS",
 327         "INTERNAL_VCE",
 328         "INTERNAL_UNIPHY3",
 329 };
 330
 331 static const char *hpd_names[6] = {
 332         "HPD1",
 333         "HPD2",
 334         "HPD3",
 335         "HPD4",
 336         "HPD5",
 337         "HPD6",
 338 };
 339
 340 void amdgpu_print_display_setup(struct drm_device *dev)
 341 {
 342         struct drm_connector *connector;
 343         struct amdgpu_connector *amdgpu_connector;
 344         struct drm_encoder *encoder;
 345         struct amdgpu_encoder *amdgpu_encoder;
 346         uint32_t devices;
 347         int i = 0;
 348
 349         DRM_INFO("AMDGPU Display Connectors\n");
 350         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 351                 amdgpu_connector = to_amdgpu_connector(connector);
 352                 DRM_INFO("Connector %d:\n", i);
 353                 DRM_INFO("  %s\n", connector->name);
 354                 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
 355                         DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
 356                 if (amdgpu_connector->ddc_bus) {
 357                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 358                                  amdgpu_connector->ddc_bus->rec.mask_clk_reg,
 359                                  amdgpu_connector->ddc_bus->rec.mask_data_reg,
 360                                  amdgpu_connector->ddc_bus->rec.a_clk_reg,
 361                                  amdgpu_connector->ddc_bus->rec.a_data_reg,
 362                                  amdgpu_connector->ddc_bus->rec.en_clk_reg,
 363                                  amdgpu_connector->ddc_bus->rec.en_data_reg,
 364                                  amdgpu_connector->ddc_bus->rec.y_clk_reg,
 365                                  amdgpu_connector->ddc_bus->rec.y_data_reg);
 366                         if (amdgpu_connector->router.ddc_valid)
 367                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 368                                          amdgpu_connector->router.ddc_mux_control_pin,
 369                                          amdgpu_connector->router.ddc_mux_state);
 370                         if (amdgpu_connector->router.cd_valid)
 371                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 372                                          amdgpu_connector->router.cd_mux_control_pin,
 373                                          amdgpu_connector->router.cd_mux_state);
 374                 } else {
 375                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 376                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 377                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 378                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 379                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 380                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 381                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to [email protected]\n");
 382                 }
 383                 DRM_INFO("  Encoders:\n");
 384                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 385                         amdgpu_encoder = to_amdgpu_encoder(encoder);
 386                         devices = amdgpu_encoder->devices & amdgpu_connector->devices;
 387                         if (devices) {
 388                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 389                                         DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 390                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 391                                         DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 392                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 393                                         DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 394                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 395                                         DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 396                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 397                                         DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 398                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 399                                         DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 400                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 401                                         DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 402                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 403                                         DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 404                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 405                                         DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 406                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 407                                         DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 408                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 409                                         DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 410                         }
 411                 }
 412                 i++;
 413         }
 414 }
 415
 416 /**
 417  * amdgpu_ddc_probe
 418  *
 419  */
 420 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector,
 421                        bool use_aux)
 422 {
 423         u8 out = 0x0;
 424         u8 buf[8];
 425         int ret;
 426         struct i2c_msg msgs[] = {
 427                 {
 428                         .addr = DDC_ADDR,
 429                         .flags = 0,
 430                         .len = 1,
 431                         .buf = &out,
 432                 },
 433                 {
 434                         .addr = DDC_ADDR,
 435                         .flags = I2C_M_RD,
 436                         .len = 8,
 437                         .buf = buf,
 438                 }
 439         };
 440
 441         /* on hw with routers, select right port */
 442         if (amdgpu_connector->router.ddc_valid)
 443                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 444
 445         if (use_aux) {
 446                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
 447         } else {
 448                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
 449         }
 450
 451         if (ret != 2)
 452                 /* Couldn't find an accessible DDC on this connector */
 453                 return false;
 454         /* Probe also for valid EDID header
 455          * EDID header starts with:
 456          * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
 457          * Only the first 6 bytes must be valid as
 458          * drm_edid_block_valid() can fix the last 2 bytes */
 459         if (drm_edid_header_is_valid(buf) < 6) {
 460                 /* Couldn't find an accessible EDID on this
 461                  * connector */
 462                 return false;
 463         }
 464         return true;
 465 }
 466
 467 static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb)
 468 {
 469         struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
 470
 471         if (amdgpu_fb->obj) {
 472                 drm_gem_object_unreference_unlocked(amdgpu_fb->obj);
 473         }
 474         drm_framebuffer_cleanup(fb);
 475         kfree(amdgpu_fb);
 476 }
 477
 478 static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb,
 479                                                   struct drm_file *file_priv,
 480                                                   unsigned int *handle)
 481 {
 482         struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
 483
 484         return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle);
 485 }
 486
 487 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
 488         .destroy = amdgpu_user_framebuffer_destroy,
 489         .create_handle = amdgpu_user_framebuffer_create_handle,
 490 };
 491
 492 int
 493 amdgpu_framebuffer_init(struct drm_device *dev,
 494                         struct amdgpu_framebuffer *rfb,
 495                         struct drm_mode_fb_cmd2 *mode_cmd,
 496                         struct drm_gem_object *obj)
 497 {
 498         int ret;
 499         rfb->obj = obj;
 500         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
 501         ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
 502         if (ret) {
 503                 rfb->obj = NULL;
 504                 return ret;
 505         }
 506         return 0;
 507 }
 508
 509 static struct drm_framebuffer *
 510 amdgpu_user_framebuffer_create(struct drm_device *dev,
 511                                struct drm_file *file_priv,
 512                                struct drm_mode_fb_cmd2 *mode_cmd)
 513 {
 514         struct drm_gem_object *obj;
 515         struct amdgpu_framebuffer *amdgpu_fb;
 516         int ret;
 517
 518         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
 519         if (obj ==  NULL) {
 520                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
 521                         "can't create framebuffer\n", mode_cmd->handles[0]);
 522                 return ERR_PTR(-ENOENT);
 523         }
 524
 525         amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
 526         if (amdgpu_fb == NULL) {
 527                 drm_gem_object_unreference_unlocked(obj);
 528                 return ERR_PTR(-ENOMEM);
 529         }
 530
 531         ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj);
 532         if (ret) {
 533                 kfree(amdgpu_fb);
 534                 drm_gem_object_unreference_unlocked(obj);
 535                 return ERR_PTR(ret);
 536         }
 537
 538         return &amdgpu_fb->base;
 539 }
 540
 541 static void amdgpu_output_poll_changed(struct drm_device *dev)
 542 {
 543         struct amdgpu_device *adev = dev->dev_private;
 544         amdgpu_fb_output_poll_changed(adev);
 545 }
 546
 547 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
 548         .fb_create = amdgpu_user_framebuffer_create,
 549         .output_poll_changed = amdgpu_output_poll_changed
 550 };
 551
 552 static struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
 553 {       { UNDERSCAN_OFF, "off" },
 554         { UNDERSCAN_ON, "on" },
 555         { UNDERSCAN_AUTO, "auto" },
 556 };
 557
 558 static struct drm_prop_enum_list amdgpu_audio_enum_list[] =
 559 {       { AMDGPU_AUDIO_DISABLE, "off" },
 560         { AMDGPU_AUDIO_ENABLE, "on" },
 561         { AMDGPU_AUDIO_AUTO, "auto" },
 562 };
 563
 564 /* XXX support different dither options? spatial, temporal, both, etc. */
 565 static struct drm_prop_enum_list amdgpu_dither_enum_list[] =
 566 {       { AMDGPU_FMT_DITHER_DISABLE, "off" },
 567         { AMDGPU_FMT_DITHER_ENABLE, "on" },
 568 };
 569
 570 int amdgpu_modeset_create_props(struct amdgpu_device *adev)
 571 {
 572         int sz;
 573
 574         if (adev->is_atom_bios) {
 575                 adev->mode_info.coherent_mode_property =
 576                         drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1);
 577                 if (!adev->mode_info.coherent_mode_property)
 578                         return -ENOMEM;
 579         }
 580
 581         adev->mode_info.load_detect_property =
 582                 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1);
 583         if (!adev->mode_info.load_detect_property)
 584                 return -ENOMEM;
 585
 586         drm_mode_create_scaling_mode_property(adev->ddev);
 587
 588         sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
 589         adev->mode_info.underscan_property =
 590                 drm_property_create_enum(adev->ddev, 0,
 591                                     "underscan",
 592                                     amdgpu_underscan_enum_list, sz);
 593
 594         adev->mode_info.underscan_hborder_property =
 595                 drm_property_create_range(adev->ddev, 0,
 596                                         "underscan hborder", 0, 128);
 597         if (!adev->mode_info.underscan_hborder_property)
 598                 return -ENOMEM;
 599
 600         adev->mode_info.underscan_vborder_property =
 601                 drm_property_create_range(adev->ddev, 0,
 602                                         "underscan vborder", 0, 128);
 603         if (!adev->mode_info.underscan_vborder_property)
 604                 return -ENOMEM;
 605
 606         sz = ARRAY_SIZE(amdgpu_audio_enum_list);
 607         adev->mode_info.audio_property =
 608                 drm_property_create_enum(adev->ddev, 0,
 609                                          "audio",
 610                                          amdgpu_audio_enum_list, sz);
 611
 612         sz = ARRAY_SIZE(amdgpu_dither_enum_list);
 613         adev->mode_info.dither_property =
 614                 drm_property_create_enum(adev->ddev, 0,
 615                                          "dither",
 616                                          amdgpu_dither_enum_list, sz);
 617
 618         return 0;
 619 }
 620
 621 void amdgpu_update_display_priority(struct amdgpu_device *adev)
 622 {
 623         /* adjustment options for the display watermarks */
 624         if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
 625                 adev->mode_info.disp_priority = 0;
 626         else
 627                 adev->mode_info.disp_priority = amdgpu_disp_priority;
 628
 629 }
 630
 631 static bool is_hdtv_mode(const struct drm_display_mode *mode)
 632 {
 633         /* try and guess if this is a tv or a monitor */
 634         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
 635             (mode->vdisplay == 576) || /* 576p */
 636             (mode->vdisplay == 720) || /* 720p */
 637             (mode->vdisplay == 1080)) /* 1080p */
 638                 return true;
 639         else
 640                 return false;
 641 }
 642
 643 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 644                                     const struct drm_display_mode *mode,
 645                                     struct drm_display_mode *adjusted_mode)
 646 {
 647         struct drm_device *dev = crtc->dev;
 648         struct drm_encoder *encoder;
 649         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 650         struct amdgpu_encoder *amdgpu_encoder;
 651         struct drm_connector *connector;
 652         struct amdgpu_connector *amdgpu_connector;
 653         u32 src_v = 1, dst_v = 1;
 654         u32 src_h = 1, dst_h = 1;
 655
 656         amdgpu_crtc->h_border = 0;
 657         amdgpu_crtc->v_border = 0;
 658
 659         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 660                 if (encoder->crtc != crtc)
 661                         continue;
 662                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 663                 connector = amdgpu_get_connector_for_encoder(encoder);
 664                 amdgpu_connector = to_amdgpu_connector(connector);
 665
 666                 /* set scaling */
 667                 if (amdgpu_encoder->rmx_type == RMX_OFF)
 668                         amdgpu_crtc->rmx_type = RMX_OFF;
 669                 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
 670                          mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
 671                         amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
 672                 else
 673                         amdgpu_crtc->rmx_type = RMX_OFF;
 674                 /* copy native mode */
 675                 memcpy(&amdgpu_crtc->native_mode,
 676                        &amdgpu_encoder->native_mode,
 677                        sizeof(struct drm_display_mode));
 678                 src_v = crtc->mode.vdisplay;
 679                 dst_v = amdgpu_crtc->native_mode.vdisplay;
 680                 src_h = crtc->mode.hdisplay;
 681                 dst_h = amdgpu_crtc->native_mode.hdisplay;
 682
 683                 /* fix up for overscan on hdmi */
 684                 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
 685                     ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
 686                      ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
 687                       drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
 688                       is_hdtv_mode(mode)))) {
 689                         if (amdgpu_encoder->underscan_hborder != 0)
 690                                 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
 691                         else
 692                                 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
 693                         if (amdgpu_encoder->underscan_vborder != 0)
 694                                 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
 695                         else
 696                                 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
 697                         amdgpu_crtc->rmx_type = RMX_FULL;
 698                         src_v = crtc->mode.vdisplay;
 699                         dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
 700                         src_h = crtc->mode.hdisplay;
 701                         dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
 702                 }
 703         }
 704         if (amdgpu_crtc->rmx_type != RMX_OFF) {
 705                 fixed20_12 a, b;
 706                 a.full = dfixed_const(src_v);
 707                 b.full = dfixed_const(dst_v);
 708                 amdgpu_crtc->vsc.full = dfixed_div(a, b);
 709                 a.full = dfixed_const(src_h);
 710                 b.full = dfixed_const(dst_h);
 711                 amdgpu_crtc->hsc.full = dfixed_div(a, b);
 712         } else {
 713                 amdgpu_crtc->vsc.full = dfixed_const(1);
 714                 amdgpu_crtc->hsc.full = dfixed_const(1);
 715         }
 716         return true;
 717 }
 718
 719 /*
 720  * Retrieve current video scanout position of crtc on a given gpu, and
 721  * an optional accurate timestamp of when query happened.
 722  *
 723  * \param dev Device to query.
 724  * \param crtc Crtc to query.
 725  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
 726  * \param *vpos Location where vertical scanout position should be stored.
 727  * \param *hpos Location where horizontal scanout position should go.
 728  * \param *stime Target location for timestamp taken immediately before
 729  *               scanout position query. Can be NULL to skip timestamp.
 730  * \param *etime Target location for timestamp taken immediately after
 731  *               scanout position query. Can be NULL to skip timestamp.
 732  *
 733  * Returns vpos as a positive number while in active scanout area.
 734  * Returns vpos as a negative number inside vblank, counting the number
 735  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
 736  * until start of active scanout / end of vblank."
 737  *
 738  * \return Flags, or'ed together as follows:
 739  *
 740  * DRM_SCANOUTPOS_VALID = Query successful.
 741  * DRM_SCANOUTPOS_INVBL = Inside vblank.
 742  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
 743  * this flag means that returned position may be offset by a constant but
 744  * unknown small number of scanlines wrt. real scanout position.
 745  *
 746  */
 747 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
 748                                int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
 749 {
 750         u32 vbl = 0, position = 0;
 751         int vbl_start, vbl_end, vtotal, ret = 0;
 752         bool in_vbl = true;
 753
 754         struct amdgpu_device *adev = dev->dev_private;
 755
 756         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 757
 758         /* Get optional system timestamp before query. */
 759         if (stime)
 760                 *stime = ktime_get();
 761
 762         if (amdgpu_display_page_flip_get_scanoutpos(adev, crtc, &vbl, &position) == 0)
 763                 ret |= DRM_SCANOUTPOS_VALID;
 764
 765         /* Get optional system timestamp after query. */
 766         if (etime)
 767                 *etime = ktime_get();
 768
 769         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 770
 771         /* Decode into vertical and horizontal scanout position. */
 772         *vpos = position & 0x1fff;
 773         *hpos = (position >> 16) & 0x1fff;
 774
 775         /* Valid vblank area boundaries from gpu retrieved? */
 776         if (vbl > 0) {
 777                 /* Yes: Decode. */
 778                 ret |= DRM_SCANOUTPOS_ACCURATE;
 779                 vbl_start = vbl & 0x1fff;
 780                 vbl_end = (vbl >> 16) & 0x1fff;
 781         }
 782         else {
 783                 /* No: Fake something reasonable which gives at least ok results. */
 784                 vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
 785                 vbl_end = 0;
 786         }
 787
 788         /* Test scanout position against vblank region. */
 789         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
 790                 in_vbl = false;
 791
 792         /* Check if inside vblank area and apply corrective offsets:
 793          * vpos will then be >=0 in video scanout area, but negative
 794          * within vblank area, counting down the number of lines until
 795          * start of scanout.
 796          */
 797
 798         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
 799         if (in_vbl && (*vpos >= vbl_start)) {
 800                 vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
 801                 *vpos = *vpos - vtotal;
 802         }
 803
 804         /* Correct for shifted end of vbl at vbl_end. */
 805         *vpos = *vpos - vbl_end;
 806
 807         /* In vblank? */
 808         if (in_vbl)
 809                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 810
 811         /* Is vpos outside nominal vblank area, but less than
 812          * 1/100 of a frame height away from start of vblank?
 813          * If so, assume this isn't a massively delayed vblank
 814          * interrupt, but a vblank interrupt that fired a few
 815          * microseconds before true start of vblank. Compensate
 816          * by adding a full frame duration to the final timestamp.
 817          * Happens, e.g., on ATI R500, R600.
 818          *
 819          * We only do this if DRM_CALLED_FROM_VBLIRQ.
 820          */
 821         if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
 822                 vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
 823                 vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
 824
 825                 if (vbl_start - *vpos < vtotal / 100) {
 826                         *vpos -= vtotal;
 827
 828                         /* Signal this correction as "applied". */
 829                         ret |= 0x8;
 830                 }
 831         }
 832
 833         return ret;
 834 }
 835
 836 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
 837 {
 838         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
 839                 return AMDGPU_CRTC_IRQ_NONE;
 840
 841         switch (crtc) {
 842         case 0:
 843                 return AMDGPU_CRTC_IRQ_VBLANK1;
 844         case 1:
 845                 return AMDGPU_CRTC_IRQ_VBLANK2;
 846         case 2:
 847                 return AMDGPU_CRTC_IRQ_VBLANK3;
 848         case 3:
 849                 return AMDGPU_CRTC_IRQ_VBLANK4;
 850         case 4:
 851                 return AMDGPU_CRTC_IRQ_VBLANK5;
 852         case 5:
 853                 return AMDGPU_CRTC_IRQ_VBLANK6;
 854         default:
 855                 return AMDGPU_CRTC_IRQ_NONE;
 856         }
 857 }