drivers/thunderbolt/nhi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Thunderbolt driver - NHI driver
   4  *
   5  * The NHI (native host interface) is the pci device that allows us to send and
   6  * receive frames from the thunderbolt bus.
   7  *
   8  * Copyright (c) 2014 Andreas Noever <[email protected]>
   9  * Copyright (C) 2018, Intel Corporation
  10  */
  11
  12 #include <linux/pm_runtime.h>
  13 #include <linux/slab.h>
  14 #include <linux/errno.h>
  15 #include <linux/pci.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/module.h>
  18 #include <linux/delay.h>
  19 #include <linux/property.h>
  20 #include <linux/platform_data/x86/apple.h>
  21
  22 #include "nhi.h"
  23 #include "nhi_regs.h"
  24 #include "tb.h"
  25
  26 #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
  27
  28 #define RING_FIRST_USABLE_HOPID 1
  29
  30 /*
  31  * Minimal number of vectors when we use MSI-X. Two for control channel
  32  * Rx/Tx and the rest four are for cross domain DMA paths.
  33  */
  34 #define MSIX_MIN_VECS           6
  35 #define MSIX_MAX_VECS           16
  36
  37 #define NHI_MAILBOX_TIMEOUT     500 /* ms */
  38
  39 static int ring_interrupt_index(struct tb_ring *ring)
  40 {
  41         int bit = ring->hop;
  42         if (!ring->is_tx)
  43                 bit += ring->nhi->hop_count;
  44         return bit;
  45 }
  46
  47 /**
  48  * ring_interrupt_active() - activate/deactivate interrupts for a single ring
  49  *
  50  * ring->nhi->lock must be held.
  51  */
  52 static void ring_interrupt_active(struct tb_ring *ring, bool active)
  53 {
  54         int reg = REG_RING_INTERRUPT_BASE +
  55                   ring_interrupt_index(ring) / 32 * 4;
  56         int bit = ring_interrupt_index(ring) & 31;
  57         int mask = 1 << bit;
  58         u32 old, new;
  59
  60         if (ring->irq > 0) {
  61                 u32 step, shift, ivr, misc;
  62                 void __iomem *ivr_base;
  63                 int index;
  64
  65                 if (ring->is_tx)
  66                         index = ring->hop;
  67                 else
  68                         index = ring->hop + ring->nhi->hop_count;
  69
  70                 /*
  71                  * Ask the hardware to clear interrupt status bits automatically
  72                  * since we already know which interrupt was triggered.
  73                  */
  74                 misc = ioread32(ring->nhi->iobase + REG_DMA_MISC);
  75                 if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) {
  76                         misc |= REG_DMA_MISC_INT_AUTO_CLEAR;
  77                         iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC);
  78                 }
  79
  80                 ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE;
  81                 step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
  82                 shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
  83                 ivr = ioread32(ivr_base + step);
  84                 ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift);
  85                 if (active)
  86                         ivr |= ring->vector << shift;
  87                 iowrite32(ivr, ivr_base + step);
  88         }
  89
  90         old = ioread32(ring->nhi->iobase + reg);
  91         if (active)
  92                 new = old | mask;
  93         else
  94                 new = old & ~mask;
  95
  96         dev_dbg(&ring->nhi->pdev->dev,
  97                 "%s interrupt at register %#x bit %d (%#x -> %#x)\n",
  98                 active ? "enabling" : "disabling", reg, bit, old, new);
  99
 100         if (new == old)
 101                 dev_WARN(&ring->nhi->pdev->dev,
 102                                          "interrupt for %s %d is already %s\n",
 103                                          RING_TYPE(ring), ring->hop,
 104                                          active ? "enabled" : "disabled");
 105         iowrite32(new, ring->nhi->iobase + reg);
 106 }
 107
 108 /**
 109  * nhi_disable_interrupts() - disable interrupts for all rings
 110  *
 111  * Use only during init and shutdown.
 112  */
 113 static void nhi_disable_interrupts(struct tb_nhi *nhi)
 114 {
 115         int i = 0;
 116         /* disable interrupts */
 117         for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++)
 118                 iowrite32(0, nhi->iobase + REG_RING_INTERRUPT_BASE + 4 * i);
 119
 120         /* clear interrupt status bits */
 121         for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++)
 122                 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + 4 * i);
 123 }
 124
 125 /* ring helper methods */
 126
 127 static void __iomem *ring_desc_base(struct tb_ring *ring)
 128 {
 129         void __iomem *io = ring->nhi->iobase;
 130         io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE;
 131         io += ring->hop * 16;
 132         return io;
 133 }
 134
 135 static void __iomem *ring_options_base(struct tb_ring *ring)
 136 {
 137         void __iomem *io = ring->nhi->iobase;
 138         io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE;
 139         io += ring->hop * 32;
 140         return io;
 141 }
 142
 143 static void ring_iowrite_cons(struct tb_ring *ring, u16 cons)
 144 {
 145         /*
 146          * The other 16-bits in the register is read-only and writes to it
 147          * are ignored by the hardware so we can save one ioread32() by
 148          * filling the read-only bits with zeroes.
 149          */
 150         iowrite32(cons, ring_desc_base(ring) + 8);
 151 }
 152
 153 static void ring_iowrite_prod(struct tb_ring *ring, u16 prod)
 154 {
 155         /* See ring_iowrite_cons() above for explanation */
 156         iowrite32(prod << 16, ring_desc_base(ring) + 8);
 157 }
 158
 159 static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset)
 160 {
 161         iowrite32(value, ring_desc_base(ring) + offset);
 162 }
 163
 164 static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset)
 165 {
 166         iowrite32(value, ring_desc_base(ring) + offset);
 167         iowrite32(value >> 32, ring_desc_base(ring) + offset + 4);
 168 }
 169
 170 static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset)
 171 {
 172         iowrite32(value, ring_options_base(ring) + offset);
 173 }
 174
 175 static bool ring_full(struct tb_ring *ring)
 176 {
 177         return ((ring->head + 1) % ring->size) == ring->tail;
 178 }
 179
 180 static bool ring_empty(struct tb_ring *ring)
 181 {
 182         return ring->head == ring->tail;
 183 }
 184
 185 /**
 186  * ring_write_descriptors() - post frames from ring->queue to the controller
 187  *
 188  * ring->lock is held.
 189  */
 190 static void ring_write_descriptors(struct tb_ring *ring)
 191 {
 192         struct ring_frame *frame, *n;
 193         struct ring_desc *descriptor;
 194         list_for_each_entry_safe(frame, n, &ring->queue, list) {
 195                 if (ring_full(ring))
 196                         break;
 197                 list_move_tail(&frame->list, &ring->in_flight);
 198                 descriptor = &ring->descriptors[ring->head];
 199                 descriptor->phys = frame->buffer_phy;
 200                 descriptor->time = 0;
 201                 descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT;
 202                 if (ring->is_tx) {
 203                         descriptor->length = frame->size;
 204                         descriptor->eof = frame->eof;
 205                         descriptor->sof = frame->sof;
 206                 }
 207                 ring->head = (ring->head + 1) % ring->size;
 208                 if (ring->is_tx)
 209                         ring_iowrite_prod(ring, ring->head);
 210                 else
 211                         ring_iowrite_cons(ring, ring->head);
 212         }
 213 }
 214
 215 /**
 216  * ring_work() - progress completed frames
 217  *
 218  * If the ring is shutting down then all frames are marked as canceled and
 219  * their callbacks are invoked.
 220  *
 221  * Otherwise we collect all completed frame from the ring buffer, write new
 222  * frame to the ring buffer and invoke the callbacks for the completed frames.
 223  */
 224 static void ring_work(struct work_struct *work)
 225 {
 226         struct tb_ring *ring = container_of(work, typeof(*ring), work);
 227         struct ring_frame *frame;
 228         bool canceled = false;
 229         unsigned long flags;
 230         LIST_HEAD(done);
 231
 232         spin_lock_irqsave(&ring->lock, flags);
 233
 234         if (!ring->running) {
 235                 /*  Move all frames to done and mark them as canceled. */
 236                 list_splice_tail_init(&ring->in_flight, &done);
 237                 list_splice_tail_init(&ring->queue, &done);
 238                 canceled = true;
 239                 goto invoke_callback;
 240         }
 241
 242         while (!ring_empty(ring)) {
 243                 if (!(ring->descriptors[ring->tail].flags
 244                                 & RING_DESC_COMPLETED))
 245                         break;
 246                 frame = list_first_entry(&ring->in_flight, typeof(*frame),
 247                                          list);
 248                 list_move_tail(&frame->list, &done);
 249                 if (!ring->is_tx) {
 250                         frame->size = ring->descriptors[ring->tail].length;
 251                         frame->eof = ring->descriptors[ring->tail].eof;
 252                         frame->sof = ring->descriptors[ring->tail].sof;
 253                         frame->flags = ring->descriptors[ring->tail].flags;
 254                 }
 255                 ring->tail = (ring->tail + 1) % ring->size;
 256         }
 257         ring_write_descriptors(ring);
 258
 259 invoke_callback:
 260         /* allow callbacks to schedule new work */
 261         spin_unlock_irqrestore(&ring->lock, flags);
 262         while (!list_empty(&done)) {
 263                 frame = list_first_entry(&done, typeof(*frame), list);
 264                 /*
 265                  * The callback may reenqueue or delete frame.
 266                  * Do not hold on to it.
 267                  */
 268                 list_del_init(&frame->list);
 269                 if (frame->callback)
 270                         frame->callback(ring, frame, canceled);
 271         }
 272 }
 273
 274 int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame)
 275 {
 276         unsigned long flags;
 277         int ret = 0;
 278
 279         spin_lock_irqsave(&ring->lock, flags);
 280         if (ring->running) {
 281                 list_add_tail(&frame->list, &ring->queue);
 282                 ring_write_descriptors(ring);
 283         } else {
 284                 ret = -ESHUTDOWN;
 285         }
 286         spin_unlock_irqrestore(&ring->lock, flags);
 287         return ret;
 288 }
 289 EXPORT_SYMBOL_GPL(__tb_ring_enqueue);
 290
 291 /**
 292  * tb_ring_poll() - Poll one completed frame from the ring
 293  * @ring: Ring to poll
 294  *
 295  * This function can be called when @start_poll callback of the @ring
 296  * has been called. It will read one completed frame from the ring and
 297  * return it to the caller. Returns %NULL if there is no more completed
 298  * frames.
 299  */
 300 struct ring_frame *tb_ring_poll(struct tb_ring *ring)
 301 {
 302         struct ring_frame *frame = NULL;
 303         unsigned long flags;
 304
 305         spin_lock_irqsave(&ring->lock, flags);
 306         if (!ring->running)
 307                 goto unlock;
 308         if (ring_empty(ring))
 309                 goto unlock;
 310
 311         if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) {
 312                 frame = list_first_entry(&ring->in_flight, typeof(*frame),
 313                                          list);
 314                 list_del_init(&frame->list);
 315
 316                 if (!ring->is_tx) {
 317                         frame->size = ring->descriptors[ring->tail].length;
 318                         frame->eof = ring->descriptors[ring->tail].eof;
 319                         frame->sof = ring->descriptors[ring->tail].sof;
 320                         frame->flags = ring->descriptors[ring->tail].flags;
 321                 }
 322
 323                 ring->tail = (ring->tail + 1) % ring->size;
 324         }
 325
 326 unlock:
 327         spin_unlock_irqrestore(&ring->lock, flags);
 328         return frame;
 329 }
 330 EXPORT_SYMBOL_GPL(tb_ring_poll);
 331
 332 static void __ring_interrupt_mask(struct tb_ring *ring, bool mask)
 333 {
 334         int idx = ring_interrupt_index(ring);
 335         int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4;
 336         int bit = idx % 32;
 337         u32 val;
 338
 339         val = ioread32(ring->nhi->iobase + reg);
 340         if (mask)
 341                 val &= ~BIT(bit);
 342         else
 343                 val |= BIT(bit);
 344         iowrite32(val, ring->nhi->iobase + reg);
 345 }
 346
 347 /* Both @nhi->lock and @ring->lock should be held */
 348 static void __ring_interrupt(struct tb_ring *ring)
 349 {
 350         if (!ring->running)
 351                 return;
 352
 353         if (ring->start_poll) {
 354                 __ring_interrupt_mask(ring, true);
 355                 ring->start_poll(ring->poll_data);
 356         } else {
 357                 schedule_work(&ring->work);
 358         }
 359 }
 360
 361 /**
 362  * tb_ring_poll_complete() - Re-start interrupt for the ring
 363  * @ring: Ring to re-start the interrupt
 364  *
 365  * This will re-start (unmask) the ring interrupt once the user is done
 366  * with polling.
 367  */
 368 void tb_ring_poll_complete(struct tb_ring *ring)
 369 {
 370         unsigned long flags;
 371
 372         spin_lock_irqsave(&ring->nhi->lock, flags);
 373         spin_lock(&ring->lock);
 374         if (ring->start_poll)
 375                 __ring_interrupt_mask(ring, false);
 376         spin_unlock(&ring->lock);
 377         spin_unlock_irqrestore(&ring->nhi->lock, flags);
 378 }
 379 EXPORT_SYMBOL_GPL(tb_ring_poll_complete);
 380
 381 static irqreturn_t ring_msix(int irq, void *data)
 382 {
 383         struct tb_ring *ring = data;
 384
 385         spin_lock(&ring->nhi->lock);
 386         spin_lock(&ring->lock);
 387         __ring_interrupt(ring);
 388         spin_unlock(&ring->lock);
 389         spin_unlock(&ring->nhi->lock);
 390
 391         return IRQ_HANDLED;
 392 }
 393
 394 static int ring_request_msix(struct tb_ring *ring, bool no_suspend)
 395 {
 396         struct tb_nhi *nhi = ring->nhi;
 397         unsigned long irqflags;
 398         int ret;
 399
 400         if (!nhi->pdev->msix_enabled)
 401                 return 0;
 402
 403         ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL);
 404         if (ret < 0)
 405                 return ret;
 406
 407         ring->vector = ret;
 408
 409         ret = pci_irq_vector(ring->nhi->pdev, ring->vector);
 410         if (ret < 0)
 411                 goto err_ida_remove;
 412
 413         ring->irq = ret;
 414
 415         irqflags = no_suspend ? IRQF_NO_SUSPEND : 0;
 416         ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring);
 417         if (ret)
 418                 goto err_ida_remove;
 419
 420         return 0;
 421
 422 err_ida_remove:
 423         ida_simple_remove(&nhi->msix_ida, ring->vector);
 424
 425         return ret;
 426 }
 427
 428 static void ring_release_msix(struct tb_ring *ring)
 429 {
 430         if (ring->irq <= 0)
 431                 return;
 432
 433         free_irq(ring->irq, ring);
 434         ida_simple_remove(&ring->nhi->msix_ida, ring->vector);
 435         ring->vector = 0;
 436         ring->irq = 0;
 437 }
 438
 439 static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring)
 440 {
 441         int ret = 0;
 442
 443         spin_lock_irq(&nhi->lock);
 444
 445         if (ring->hop < 0) {
 446                 unsigned int i;
 447
 448                 /*
 449                  * Automatically allocate HopID from the non-reserved
 450                  * range 1 .. hop_count - 1.
 451                  */
 452                 for (i = RING_FIRST_USABLE_HOPID; i < nhi->hop_count; i++) {
 453                         if (ring->is_tx) {
 454                                 if (!nhi->tx_rings[i]) {
 455                                         ring->hop = i;
 456                                         break;
 457                                 }
 458                         } else {
 459                                 if (!nhi->rx_rings[i]) {
 460                                         ring->hop = i;
 461                                         break;
 462                                 }
 463                         }
 464                 }
 465         }
 466
 467         if (ring->hop < 0 || ring->hop >= nhi->hop_count) {
 468                 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
 469                 ret = -EINVAL;
 470                 goto err_unlock;
 471         }
 472         if (ring->is_tx && nhi->tx_rings[ring->hop]) {
 473                 dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n",
 474                          ring->hop);
 475                 ret = -EBUSY;
 476                 goto err_unlock;
 477         } else if (!ring->is_tx && nhi->rx_rings[ring->hop]) {
 478                 dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n",
 479                          ring->hop);
 480                 ret = -EBUSY;
 481                 goto err_unlock;
 482         }
 483
 484         if (ring->is_tx)
 485                 nhi->tx_rings[ring->hop] = ring;
 486         else
 487                 nhi->rx_rings[ring->hop] = ring;
 488
 489 err_unlock:
 490         spin_unlock_irq(&nhi->lock);
 491
 492         return ret;
 493 }
 494
 495 static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size,
 496                                      bool transmit, unsigned int flags,
 497                                      int e2e_tx_hop, u16 sof_mask, u16 eof_mask,
 498                                      void (*start_poll)(void *),
 499                                      void *poll_data)
 500 {
 501         struct tb_ring *ring = NULL;
 502
 503         dev_dbg(&nhi->pdev->dev, "allocating %s ring %d of size %d\n",
 504                 transmit ? "TX" : "RX", hop, size);
 505
 506         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 507         if (!ring)
 508                 return NULL;
 509
 510         spin_lock_init(&ring->lock);
 511         INIT_LIST_HEAD(&ring->queue);
 512         INIT_LIST_HEAD(&ring->in_flight);
 513         INIT_WORK(&ring->work, ring_work);
 514
 515         ring->nhi = nhi;
 516         ring->hop = hop;
 517         ring->is_tx = transmit;
 518         ring->size = size;
 519         ring->flags = flags;
 520         ring->e2e_tx_hop = e2e_tx_hop;
 521         ring->sof_mask = sof_mask;
 522         ring->eof_mask = eof_mask;
 523         ring->head = 0;
 524         ring->tail = 0;
 525         ring->running = false;
 526         ring->start_poll = start_poll;
 527         ring->poll_data = poll_data;
 528
 529         ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev,
 530                         size * sizeof(*ring->descriptors),
 531                         &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO);
 532         if (!ring->descriptors)
 533                 goto err_free_ring;
 534
 535         if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND))
 536                 goto err_free_descs;
 537
 538         if (nhi_alloc_hop(nhi, ring))
 539                 goto err_release_msix;
 540
 541         return ring;
 542
 543 err_release_msix:
 544         ring_release_msix(ring);
 545 err_free_descs:
 546         dma_free_coherent(&ring->nhi->pdev->dev,
 547                           ring->size * sizeof(*ring->descriptors),
 548                           ring->descriptors, ring->descriptors_dma);
 549 err_free_ring:
 550         kfree(ring);
 551
 552         return NULL;
 553 }
 554
 555 /**
 556  * tb_ring_alloc_tx() - Allocate DMA ring for transmit
 557  * @nhi: Pointer to the NHI the ring is to be allocated
 558  * @hop: HopID (ring) to allocate
 559  * @size: Number of entries in the ring
 560  * @flags: Flags for the ring
 561  */
 562 struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size,
 563                                  unsigned int flags)
 564 {
 565         return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, 0, NULL, NULL);
 566 }
 567 EXPORT_SYMBOL_GPL(tb_ring_alloc_tx);
 568
 569 /**
 570  * tb_ring_alloc_rx() - Allocate DMA ring for receive
 571  * @nhi: Pointer to the NHI the ring is to be allocated
 572  * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation.
 573  * @size: Number of entries in the ring
 574  * @flags: Flags for the ring
 575  * @e2e_tx_hop: Transmit HopID when E2E is enabled in @flags
 576  * @sof_mask: Mask of PDF values that start a frame
 577  * @eof_mask: Mask of PDF values that end a frame
 578  * @start_poll: If not %NULL the ring will call this function when an
 579  *              interrupt is triggered and masked, instead of callback
 580  *              in each Rx frame.
 581  * @poll_data: Optional data passed to @start_poll
 582  */
 583 struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size,
 584                                  unsigned int flags, int e2e_tx_hop,
 585                                  u16 sof_mask, u16 eof_mask,
 586                                  void (*start_poll)(void *), void *poll_data)
 587 {
 588         return tb_ring_alloc(nhi, hop, size, false, flags, e2e_tx_hop, sof_mask, eof_mask,
 589                              start_poll, poll_data);
 590 }
 591 EXPORT_SYMBOL_GPL(tb_ring_alloc_rx);
 592
 593 /**
 594  * tb_ring_start() - enable a ring
 595  *
 596  * Must not be invoked in parallel with tb_ring_stop().
 597  */
 598 void tb_ring_start(struct tb_ring *ring)
 599 {
 600         u16 frame_size;
 601         u32 flags;
 602
 603         spin_lock_irq(&ring->nhi->lock);
 604         spin_lock(&ring->lock);
 605         if (ring->nhi->going_away)
 606                 goto err;
 607         if (ring->running) {
 608                 dev_WARN(&ring->nhi->pdev->dev, "ring already started\n");
 609                 goto err;
 610         }
 611         dev_dbg(&ring->nhi->pdev->dev, "starting %s %d\n",
 612                 RING_TYPE(ring), ring->hop);
 613
 614         if (ring->flags & RING_FLAG_FRAME) {
 615                 /* Means 4096 */
 616                 frame_size = 0;
 617                 flags = RING_FLAG_ENABLE;
 618         } else {
 619                 frame_size = TB_FRAME_SIZE;
 620                 flags = RING_FLAG_ENABLE | RING_FLAG_RAW;
 621         }
 622
 623         ring_iowrite64desc(ring, ring->descriptors_dma, 0);
 624         if (ring->is_tx) {
 625                 ring_iowrite32desc(ring, ring->size, 12);
 626                 ring_iowrite32options(ring, 0, 4); /* time releated ? */
 627                 ring_iowrite32options(ring, flags, 0);
 628         } else {
 629                 u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask;
 630
 631                 ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12);
 632                 ring_iowrite32options(ring, sof_eof_mask, 4);
 633                 ring_iowrite32options(ring, flags, 0);
 634         }
 635
 636         /*
 637          * Now that the ring valid bit is set we can configure E2E if
 638          * enabled for the ring.
 639          */
 640         if (ring->flags & RING_FLAG_E2E) {
 641                 if (!ring->is_tx) {
 642                         u32 hop;
 643
 644                         hop = ring->e2e_tx_hop << REG_RX_OPTIONS_E2E_HOP_SHIFT;
 645                         hop &= REG_RX_OPTIONS_E2E_HOP_MASK;
 646                         flags |= hop;
 647
 648                         dev_dbg(&ring->nhi->pdev->dev,
 649                                 "enabling E2E for %s %d with TX HopID %d\n",
 650                                 RING_TYPE(ring), ring->hop, ring->e2e_tx_hop);
 651                 } else {
 652                         dev_dbg(&ring->nhi->pdev->dev, "enabling E2E for %s %d\n",
 653                                 RING_TYPE(ring), ring->hop);
 654                 }
 655
 656                 flags |= RING_FLAG_E2E_FLOW_CONTROL;
 657                 ring_iowrite32options(ring, flags, 0);
 658         }
 659
 660         ring_interrupt_active(ring, true);
 661         ring->running = true;
 662 err:
 663         spin_unlock(&ring->lock);
 664         spin_unlock_irq(&ring->nhi->lock);
 665 }
 666 EXPORT_SYMBOL_GPL(tb_ring_start);
 667
 668 /**
 669  * tb_ring_stop() - shutdown a ring
 670  *
 671  * Must not be invoked from a callback.
 672  *
 673  * This method will disable the ring. Further calls to
 674  * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been
 675  * called.
 676  *
 677  * All enqueued frames will be canceled and their callbacks will be executed
 678  * with frame->canceled set to true (on the callback thread). This method
 679  * returns only after all callback invocations have finished.
 680  */
 681 void tb_ring_stop(struct tb_ring *ring)
 682 {
 683         spin_lock_irq(&ring->nhi->lock);
 684         spin_lock(&ring->lock);
 685         dev_dbg(&ring->nhi->pdev->dev, "stopping %s %d\n",
 686                 RING_TYPE(ring), ring->hop);
 687         if (ring->nhi->going_away)
 688                 goto err;
 689         if (!ring->running) {
 690                 dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n",
 691                          RING_TYPE(ring), ring->hop);
 692                 goto err;
 693         }
 694         ring_interrupt_active(ring, false);
 695
 696         ring_iowrite32options(ring, 0, 0);
 697         ring_iowrite64desc(ring, 0, 0);
 698         ring_iowrite32desc(ring, 0, 8);
 699         ring_iowrite32desc(ring, 0, 12);
 700         ring->head = 0;
 701         ring->tail = 0;
 702         ring->running = false;
 703
 704 err:
 705         spin_unlock(&ring->lock);
 706         spin_unlock_irq(&ring->nhi->lock);
 707
 708         /*
 709          * schedule ring->work to invoke callbacks on all remaining frames.
 710          */
 711         schedule_work(&ring->work);
 712         flush_work(&ring->work);
 713 }
 714 EXPORT_SYMBOL_GPL(tb_ring_stop);
 715
 716 /*
 717  * tb_ring_free() - free ring
 718  *
 719  * When this method returns all invocations of ring->callback will have
 720  * finished.
 721  *
 722  * Ring must be stopped.
 723  *
 724  * Must NOT be called from ring_frame->callback!
 725  */
 726 void tb_ring_free(struct tb_ring *ring)
 727 {
 728         spin_lock_irq(&ring->nhi->lock);
 729         /*
 730          * Dissociate the ring from the NHI. This also ensures that
 731          * nhi_interrupt_work cannot reschedule ring->work.
 732          */
 733         if (ring->is_tx)
 734                 ring->nhi->tx_rings[ring->hop] = NULL;
 735         else
 736                 ring->nhi->rx_rings[ring->hop] = NULL;
 737
 738         if (ring->running) {
 739                 dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n",
 740                          RING_TYPE(ring), ring->hop);
 741         }
 742         spin_unlock_irq(&ring->nhi->lock);
 743
 744         ring_release_msix(ring);
 745
 746         dma_free_coherent(&ring->nhi->pdev->dev,
 747                           ring->size * sizeof(*ring->descriptors),
 748                           ring->descriptors, ring->descriptors_dma);
 749
 750         ring->descriptors = NULL;
 751         ring->descriptors_dma = 0;
 752
 753
 754         dev_dbg(&ring->nhi->pdev->dev, "freeing %s %d\n", RING_TYPE(ring),
 755                 ring->hop);
 756
 757         /**
 758          * ring->work can no longer be scheduled (it is scheduled only
 759          * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it
 760          * to finish before freeing the ring.
 761          */
 762         flush_work(&ring->work);
 763         kfree(ring);
 764 }
 765 EXPORT_SYMBOL_GPL(tb_ring_free);
 766
 767 /**
 768  * nhi_mailbox_cmd() - Send a command through NHI mailbox
 769  * @nhi: Pointer to the NHI structure
 770  * @cmd: Command to send
 771  * @data: Data to be send with the command
 772  *
 773  * Sends mailbox command to the firmware running on NHI. Returns %0 in
 774  * case of success and negative errno in case of failure.
 775  */
 776 int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data)
 777 {
 778         ktime_t timeout;
 779         u32 val;
 780
 781         iowrite32(data, nhi->iobase + REG_INMAIL_DATA);
 782
 783         val = ioread32(nhi->iobase + REG_INMAIL_CMD);
 784         val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR);
 785         val |= REG_INMAIL_OP_REQUEST | cmd;
 786         iowrite32(val, nhi->iobase + REG_INMAIL_CMD);
 787
 788         timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT);
 789         do {
 790                 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
 791                 if (!(val & REG_INMAIL_OP_REQUEST))
 792                         break;
 793                 usleep_range(10, 20);
 794         } while (ktime_before(ktime_get(), timeout));
 795
 796         if (val & REG_INMAIL_OP_REQUEST)
 797                 return -ETIMEDOUT;
 798         if (val & REG_INMAIL_ERROR)
 799                 return -EIO;
 800
 801         return 0;
 802 }
 803
 804 /**
 805  * nhi_mailbox_mode() - Return current firmware operation mode
 806  * @nhi: Pointer to the NHI structure
 807  *
 808  * The function reads current firmware operation mode using NHI mailbox
 809  * registers and returns it to the caller.
 810  */
 811 enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi)
 812 {
 813         u32 val;
 814
 815         val = ioread32(nhi->iobase + REG_OUTMAIL_CMD);
 816         val &= REG_OUTMAIL_CMD_OPMODE_MASK;
 817         val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT;
 818
 819         return (enum nhi_fw_mode)val;
 820 }
 821
 822 static void nhi_interrupt_work(struct work_struct *work)
 823 {
 824         struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work);
 825         int value = 0; /* Suppress uninitialized usage warning. */
 826         int bit;
 827         int hop = -1;
 828         int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */
 829         struct tb_ring *ring;
 830
 831         spin_lock_irq(&nhi->lock);
 832
 833         /*
 834          * Starting at REG_RING_NOTIFY_BASE there are three status bitfields
 835          * (TX, RX, RX overflow). We iterate over the bits and read a new
 836          * dwords as required. The registers are cleared on read.
 837          */
 838         for (bit = 0; bit < 3 * nhi->hop_count; bit++) {
 839                 if (bit % 32 == 0)
 840                         value = ioread32(nhi->iobase
 841                                          + REG_RING_NOTIFY_BASE
 842                                          + 4 * (bit / 32));
 843                 if (++hop == nhi->hop_count) {
 844                         hop = 0;
 845                         type++;
 846                 }
 847                 if ((value & (1 << (bit % 32))) == 0)
 848                         continue;
 849                 if (type == 2) {
 850                         dev_warn(&nhi->pdev->dev,
 851                                  "RX overflow for ring %d\n",
 852                                  hop);
 853                         continue;
 854                 }
 855                 if (type == 0)
 856                         ring = nhi->tx_rings[hop];
 857                 else
 858                         ring = nhi->rx_rings[hop];
 859                 if (ring == NULL) {
 860                         dev_warn(&nhi->pdev->dev,
 861                                  "got interrupt for inactive %s ring %d\n",
 862                                  type ? "RX" : "TX",
 863                                  hop);
 864                         continue;
 865                 }
 866
 867                 spin_lock(&ring->lock);
 868                 __ring_interrupt(ring);
 869                 spin_unlock(&ring->lock);
 870         }
 871         spin_unlock_irq(&nhi->lock);
 872 }
 873
 874 static irqreturn_t nhi_msi(int irq, void *data)
 875 {
 876         struct tb_nhi *nhi = data;
 877         schedule_work(&nhi->interrupt_work);
 878         return IRQ_HANDLED;
 879 }
 880
 881 static int __nhi_suspend_noirq(struct device *dev, bool wakeup)
 882 {
 883         struct pci_dev *pdev = to_pci_dev(dev);
 884         struct tb *tb = pci_get_drvdata(pdev);
 885         struct tb_nhi *nhi = tb->nhi;
 886         int ret;
 887
 888         ret = tb_domain_suspend_noirq(tb);
 889         if (ret)
 890                 return ret;
 891
 892         if (nhi->ops && nhi->ops->suspend_noirq) {
 893                 ret = nhi->ops->suspend_noirq(tb->nhi, wakeup);
 894                 if (ret)
 895                         return ret;
 896         }
 897
 898         return 0;
 899 }
 900
 901 static int nhi_suspend_noirq(struct device *dev)
 902 {
 903         return __nhi_suspend_noirq(dev, device_may_wakeup(dev));
 904 }
 905
 906 static int nhi_freeze_noirq(struct device *dev)
 907 {
 908         struct pci_dev *pdev = to_pci_dev(dev);
 909         struct tb *tb = pci_get_drvdata(pdev);
 910
 911         return tb_domain_freeze_noirq(tb);
 912 }
 913
 914 static int nhi_thaw_noirq(struct device *dev)
 915 {
 916         struct pci_dev *pdev = to_pci_dev(dev);
 917         struct tb *tb = pci_get_drvdata(pdev);
 918
 919         return tb_domain_thaw_noirq(tb);
 920 }
 921
 922 static bool nhi_wake_supported(struct pci_dev *pdev)
 923 {
 924         u8 val;
 925
 926         /*
 927          * If power rails are sustainable for wakeup from S4 this
 928          * property is set by the BIOS.
 929          */
 930         if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val))
 931                 return !!val;
 932
 933         return true;
 934 }
 935
 936 static int nhi_poweroff_noirq(struct device *dev)
 937 {
 938         struct pci_dev *pdev = to_pci_dev(dev);
 939         bool wakeup;
 940
 941         wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev);
 942         return __nhi_suspend_noirq(dev, wakeup);
 943 }
 944
 945 static void nhi_enable_int_throttling(struct tb_nhi *nhi)
 946 {
 947         /* Throttling is specified in 256ns increments */
 948         u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256);
 949         unsigned int i;
 950
 951         /*
 952          * Configure interrupt throttling for all vectors even if we
 953          * only use few.
 954          */
 955         for (i = 0; i < MSIX_MAX_VECS; i++) {
 956                 u32 reg = REG_INT_THROTTLING_RATE + i * 4;
 957                 iowrite32(throttle, nhi->iobase + reg);
 958         }
 959 }
 960
 961 static int nhi_resume_noirq(struct device *dev)
 962 {
 963         struct pci_dev *pdev = to_pci_dev(dev);
 964         struct tb *tb = pci_get_drvdata(pdev);
 965         struct tb_nhi *nhi = tb->nhi;
 966         int ret;
 967
 968         /*
 969          * Check that the device is still there. It may be that the user
 970          * unplugged last device which causes the host controller to go
 971          * away on PCs.
 972          */
 973         if (!pci_device_is_present(pdev)) {
 974                 nhi->going_away = true;
 975         } else {
 976                 if (nhi->ops && nhi->ops->resume_noirq) {
 977                         ret = nhi->ops->resume_noirq(nhi);
 978                         if (ret)
 979                                 return ret;
 980                 }
 981                 nhi_enable_int_throttling(tb->nhi);
 982         }
 983
 984         return tb_domain_resume_noirq(tb);
 985 }
 986
 987 static int nhi_suspend(struct device *dev)
 988 {
 989         struct pci_dev *pdev = to_pci_dev(dev);
 990         struct tb *tb = pci_get_drvdata(pdev);
 991
 992         return tb_domain_suspend(tb);
 993 }
 994
 995 static void nhi_complete(struct device *dev)
 996 {
 997         struct pci_dev *pdev = to_pci_dev(dev);
 998         struct tb *tb = pci_get_drvdata(pdev);
 999
1000         /*
1001          * If we were runtime suspended when system suspend started,
1002          * schedule runtime resume now. It should bring the domain back
1003          * to functional state.
1004          */
1005         if (pm_runtime_suspended(&pdev->dev))
1006                 pm_runtime_resume(&pdev->dev);
1007         else
1008                 tb_domain_complete(tb);
1009 }
1010
1011 static int nhi_runtime_suspend(struct device *dev)
1012 {
1013         struct pci_dev *pdev = to_pci_dev(dev);
1014         struct tb *tb = pci_get_drvdata(pdev);
1015         struct tb_nhi *nhi = tb->nhi;
1016         int ret;
1017
1018         ret = tb_domain_runtime_suspend(tb);
1019         if (ret)
1020                 return ret;
1021
1022         if (nhi->ops && nhi->ops->runtime_suspend) {
1023                 ret = nhi->ops->runtime_suspend(tb->nhi);
1024                 if (ret)
1025                         return ret;
1026         }
1027         return 0;
1028 }
1029
1030 static int nhi_runtime_resume(struct device *dev)
1031 {
1032         struct pci_dev *pdev = to_pci_dev(dev);
1033         struct tb *tb = pci_get_drvdata(pdev);
1034         struct tb_nhi *nhi = tb->nhi;
1035         int ret;
1036
1037         if (nhi->ops && nhi->ops->runtime_resume) {
1038                 ret = nhi->ops->runtime_resume(nhi);
1039                 if (ret)
1040                         return ret;
1041         }
1042
1043         nhi_enable_int_throttling(nhi);
1044         return tb_domain_runtime_resume(tb);
1045 }
1046
1047 static void nhi_shutdown(struct tb_nhi *nhi)
1048 {
1049         int i;
1050
1051         dev_dbg(&nhi->pdev->dev, "shutdown\n");
1052
1053         for (i = 0; i < nhi->hop_count; i++) {
1054                 if (nhi->tx_rings[i])
1055                         dev_WARN(&nhi->pdev->dev,
1056                                  "TX ring %d is still active\n", i);
1057                 if (nhi->rx_rings[i])
1058                         dev_WARN(&nhi->pdev->dev,
1059                                  "RX ring %d is still active\n", i);
1060         }
1061         nhi_disable_interrupts(nhi);
1062         /*
1063          * We have to release the irq before calling flush_work. Otherwise an
1064          * already executing IRQ handler could call schedule_work again.
1065          */
1066         if (!nhi->pdev->msix_enabled) {
1067                 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
1068                 flush_work(&nhi->interrupt_work);
1069         }
1070         ida_destroy(&nhi->msix_ida);
1071
1072         if (nhi->ops && nhi->ops->shutdown)
1073                 nhi->ops->shutdown(nhi);
1074 }
1075
1076 static int nhi_init_msi(struct tb_nhi *nhi)
1077 {
1078         struct pci_dev *pdev = nhi->pdev;
1079         int res, irq, nvec;
1080
1081         /* In case someone left them on. */
1082         nhi_disable_interrupts(nhi);
1083
1084         nhi_enable_int_throttling(nhi);
1085
1086         ida_init(&nhi->msix_ida);
1087
1088         /*
1089          * The NHI has 16 MSI-X vectors or a single MSI. We first try to
1090          * get all MSI-X vectors and if we succeed, each ring will have
1091          * one MSI-X. If for some reason that does not work out, we
1092          * fallback to a single MSI.
1093          */
1094         nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS,
1095                                      PCI_IRQ_MSIX);
1096         if (nvec < 0) {
1097                 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1098                 if (nvec < 0)
1099                         return nvec;
1100
1101                 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
1102
1103                 irq = pci_irq_vector(nhi->pdev, 0);
1104                 if (irq < 0)
1105                         return irq;
1106
1107                 res = devm_request_irq(&pdev->dev, irq, nhi_msi,
1108                                        IRQF_NO_SUSPEND, "thunderbolt", nhi);
1109                 if (res) {
1110                         dev_err(&pdev->dev, "request_irq failed, aborting\n");
1111                         return res;
1112                 }
1113         }
1114
1115         return 0;
1116 }
1117
1118 static bool nhi_imr_valid(struct pci_dev *pdev)
1119 {
1120         u8 val;
1121
1122         if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val))
1123                 return !!val;
1124
1125         return true;
1126 }
1127
1128 /*
1129  * During suspend the Thunderbolt controller is reset and all PCIe
1130  * tunnels are lost. The NHI driver will try to reestablish all tunnels
1131  * during resume. This adds device links between the tunneled PCIe
1132  * downstream ports and the NHI so that the device core will make sure
1133  * NHI is resumed first before the rest.
1134  */
1135 static void tb_apple_add_links(struct tb_nhi *nhi)
1136 {
1137         struct pci_dev *upstream, *pdev;
1138
1139         if (!x86_apple_machine)
1140                 return;
1141
1142         switch (nhi->pdev->device) {
1143         case PCI_DEVICE_ID_INTEL_LIGHT_RIDGE:
1144         case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C:
1145         case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI:
1146         case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI:
1147                 break;
1148         default:
1149                 return;
1150         }
1151
1152         upstream = pci_upstream_bridge(nhi->pdev);
1153         while (upstream) {
1154                 if (!pci_is_pcie(upstream))
1155                         return;
1156                 if (pci_pcie_type(upstream) == PCI_EXP_TYPE_UPSTREAM)
1157                         break;
1158                 upstream = pci_upstream_bridge(upstream);
1159         }
1160
1161         if (!upstream)
1162                 return;
1163
1164         /*
1165          * For each hotplug downstream port, create add device link
1166          * back to NHI so that PCIe tunnels can be re-established after
1167          * sleep.
1168          */
1169         for_each_pci_bridge(pdev, upstream->subordinate) {
1170                 const struct device_link *link;
1171
1172                 if (!pci_is_pcie(pdev))
1173                         continue;
1174                 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM ||
1175                     !pdev->is_hotplug_bridge)
1176                         continue;
1177
1178                 link = device_link_add(&pdev->dev, &nhi->pdev->dev,
1179                                        DL_FLAG_AUTOREMOVE_SUPPLIER |
1180                                        DL_FLAG_PM_RUNTIME);
1181                 if (link) {
1182                         dev_dbg(&nhi->pdev->dev, "created link from %s\n",
1183                                 dev_name(&pdev->dev));
1184                 } else {
1185                         dev_warn(&nhi->pdev->dev, "device link creation from %s failed\n",
1186                                  dev_name(&pdev->dev));
1187                 }
1188         }
1189 }
1190
1191 static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1192 {
1193         struct tb_nhi *nhi;
1194         struct tb *tb;
1195         int res;
1196
1197         if (!nhi_imr_valid(pdev)) {
1198                 dev_warn(&pdev->dev, "firmware image not valid, aborting\n");
1199                 return -ENODEV;
1200         }
1201
1202         res = pcim_enable_device(pdev);
1203         if (res) {
1204                 dev_err(&pdev->dev, "cannot enable PCI device, aborting\n");
1205                 return res;
1206         }
1207
1208         res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt");
1209         if (res) {
1210                 dev_err(&pdev->dev, "cannot obtain PCI resources, aborting\n");
1211                 return res;
1212         }
1213
1214         nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL);
1215         if (!nhi)
1216                 return -ENOMEM;
1217
1218         nhi->pdev = pdev;
1219         nhi->ops = (const struct tb_nhi_ops *)id->driver_data;
1220         /* cannot fail - table is allocated bin pcim_iomap_regions */
1221         nhi->iobase = pcim_iomap_table(pdev)[0];
1222         nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff;
1223         dev_dbg(&pdev->dev, "total paths: %d\n", nhi->hop_count);
1224
1225         nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1226                                      sizeof(*nhi->tx_rings), GFP_KERNEL);
1227         nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1228                                      sizeof(*nhi->rx_rings), GFP_KERNEL);
1229         if (!nhi->tx_rings || !nhi->rx_rings)
1230                 return -ENOMEM;
1231
1232         res = nhi_init_msi(nhi);
1233         if (res) {
1234                 dev_err(&pdev->dev, "cannot enable MSI, aborting\n");
1235                 return res;
1236         }
1237
1238         spin_lock_init(&nhi->lock);
1239
1240         res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1241         if (res)
1242                 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1243         if (res) {
1244                 dev_err(&pdev->dev, "failed to set DMA mask\n");
1245                 return res;
1246         }
1247
1248         pci_set_master(pdev);
1249
1250         if (nhi->ops && nhi->ops->init) {
1251                 res = nhi->ops->init(nhi);
1252                 if (res)
1253                         return res;
1254         }
1255
1256         tb_apple_add_links(nhi);
1257         tb_acpi_add_links(nhi);
1258
1259         tb = icm_probe(nhi);
1260         if (!tb)
1261                 tb = tb_probe(nhi);
1262         if (!tb) {
1263                 dev_err(&nhi->pdev->dev,
1264                         "failed to determine connection manager, aborting\n");
1265                 return -ENODEV;
1266         }
1267
1268         dev_dbg(&nhi->pdev->dev, "NHI initialized, starting thunderbolt\n");
1269
1270         res = tb_domain_add(tb);
1271         if (res) {
1272                 /*
1273                  * At this point the RX/TX rings might already have been
1274                  * activated. Do a proper shutdown.
1275                  */
1276                 tb_domain_put(tb);
1277                 nhi_shutdown(nhi);
1278                 return res;
1279         }
1280         pci_set_drvdata(pdev, tb);
1281
1282         device_wakeup_enable(&pdev->dev);
1283
1284         pm_runtime_allow(&pdev->dev);
1285         pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY);
1286         pm_runtime_use_autosuspend(&pdev->dev);
1287         pm_runtime_put_autosuspend(&pdev->dev);
1288
1289         return 0;
1290 }
1291
1292 static void nhi_remove(struct pci_dev *pdev)
1293 {
1294         struct tb *tb = pci_get_drvdata(pdev);
1295         struct tb_nhi *nhi = tb->nhi;
1296
1297         pm_runtime_get_sync(&pdev->dev);
1298         pm_runtime_dont_use_autosuspend(&pdev->dev);
1299         pm_runtime_forbid(&pdev->dev);
1300
1301         tb_domain_remove(tb);
1302         nhi_shutdown(nhi);
1303 }
1304
1305 /*
1306  * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable
1307  * the tunnels asap. A corresponding pci quirk blocks the downstream bridges
1308  * resume_noirq until we are done.
1309  */
1310 static const struct dev_pm_ops nhi_pm_ops = {
1311         .suspend_noirq = nhi_suspend_noirq,
1312         .resume_noirq = nhi_resume_noirq,
1313         .freeze_noirq = nhi_freeze_noirq,  /*
1314                                             * we just disable hotplug, the
1315                                             * pci-tunnels stay alive.
1316                                             */
1317         .thaw_noirq = nhi_thaw_noirq,
1318         .restore_noirq = nhi_resume_noirq,
1319         .suspend = nhi_suspend,
1320         .poweroff_noirq = nhi_poweroff_noirq,
1321         .poweroff = nhi_suspend,
1322         .complete = nhi_complete,
1323         .runtime_suspend = nhi_runtime_suspend,
1324         .runtime_resume = nhi_runtime_resume,
1325 };
1326
1327 static struct pci_device_id nhi_ids[] = {
1328         /*
1329          * We have to specify class, the TB bridges use the same device and
1330          * vendor (sub)id on gen 1 and gen 2 controllers.
1331          */
1332         {
1333                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1334                 .vendor = PCI_VENDOR_ID_INTEL,
1335                 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
1336                 .subvendor = 0x2222, .subdevice = 0x1111,
1337         },
1338         {
1339                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1340                 .vendor = PCI_VENDOR_ID_INTEL,
1341                 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
1342                 .subvendor = 0x2222, .subdevice = 0x1111,
1343         },
1344         {
1345                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1346                 .vendor = PCI_VENDOR_ID_INTEL,
1347                 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI,
1348                 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1349         },
1350         {
1351                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1352                 .vendor = PCI_VENDOR_ID_INTEL,
1353                 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
1354                 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1355         },
1356
1357         /* Thunderbolt 3 */
1358         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) },
1359         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) },
1360         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
1361         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
1362         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
1363         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
1364         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
1365         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
1366         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) },
1367         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) },
1368         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0),
1369           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1370         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1),
1371           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1372         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0),
1373           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1374         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1),
1375           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1376         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI0),
1377           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1378         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI1),
1379           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1380
1381         /* Any USB4 compliant host */
1382         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) },
1383
1384         { 0,}
1385 };
1386
1387 MODULE_DEVICE_TABLE(pci, nhi_ids);
1388 MODULE_LICENSE("GPL");
1389
1390 static struct pci_driver nhi_driver = {
1391         .name = "thunderbolt",
1392         .id_table = nhi_ids,
1393         .probe = nhi_probe,
1394         .remove = nhi_remove,
1395         .shutdown = nhi_remove,
1396         .driver.pm = &nhi_pm_ops,
1397 };
1398
1399 static int __init nhi_init(void)
1400 {
1401         int ret;
1402
1403         ret = tb_domain_init();
1404         if (ret)
1405                 return ret;
1406         ret = pci_register_driver(&nhi_driver);
1407         if (ret)
1408                 tb_domain_exit();
1409         return ret;
1410 }
1411
1412 static void __exit nhi_unload(void)
1413 {
1414         pci_unregister_driver(&nhi_driver);
1415         tb_domain_exit();
1416 }
1417
1418 rootfs_initcall(nhi_init);
1419 module_exit(nhi_unload);