drivers/scsi/pm8001/pm8001_sas.h

   1 /*
   2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #ifndef _PM8001_SAS_H_
  42 #define _PM8001_SAS_H_
  43
  44 #include <linux/kernel.h>
  45 #include <linux/module.h>
  46 #include <linux/spinlock.h>
  47 #include <linux/delay.h>
  48 #include <linux/types.h>
  49 #include <linux/ctype.h>
  50 #include <linux/dma-mapping.h>
  51 #include <linux/pci.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/workqueue.h>
  54 #include <scsi/libsas.h>
  55 #include <scsi/scsi_tcq.h>
  56 #include <scsi/sas_ata.h>
  57 #include <linux/atomic.h>
  58 #include "pm8001_defs.h"
  59
  60 #define DRV_NAME                "pm80xx"
  61 #define DRV_VERSION             "0.1.40"
  62 #define PM8001_FAIL_LOGGING     0x01 /* Error message logging */
  63 #define PM8001_INIT_LOGGING     0x02 /* driver init logging */
  64 #define PM8001_DISC_LOGGING     0x04 /* discovery layer logging */
  65 #define PM8001_IO_LOGGING       0x08 /* I/O path logging */
  66 #define PM8001_EH_LOGGING       0x10 /* libsas EH function logging*/
  67 #define PM8001_IOCTL_LOGGING    0x20 /* IOCTL message logging */
  68 #define PM8001_MSG_LOGGING      0x40 /* misc message logging */
  69 #define PM8001_DEV_LOGGING      0x80 /* development message logging */
  70 #define PM8001_DEVIO_LOGGING    0x100 /* development io message logging */
  71 #define PM8001_IOERR_LOGGING    0x200 /* development io err message logging */
  72
  73 #define pm8001_info(HBA, fmt, ...)                                      \
  74         pr_info("%s:: %s  %d:" fmt,                                     \
  75                 (HBA)->name, __func__, __LINE__, ##__VA_ARGS__)
  76
  77 #define pm8001_dbg(HBA, level, fmt, ...)                                \
  78 do {                                                                    \
  79         if (unlikely((HBA)->logging_level & PM8001_##level##_LOGGING))  \
  80                 pm8001_info(HBA, fmt, ##__VA_ARGS__);                   \
  81 } while (0)
  82
  83 #define PM8001_USE_TASKLET
  84 #define PM8001_USE_MSIX
  85 #define PM8001_READ_VPD
  86
  87
  88 #define IS_SPCV_12G(dev)        ((dev->device == 0X8074)                \
  89                                 || (dev->device == 0X8076)              \
  90                                 || (dev->device == 0X8077)              \
  91                                 || (dev->device == 0X8070)              \
  92                                 || (dev->device == 0X8072))
  93
  94 #define PM8001_NAME_LENGTH              32/* generic length of strings */
  95 extern struct list_head hba_list;
  96 extern const struct pm8001_dispatch pm8001_8001_dispatch;
  97 extern const struct pm8001_dispatch pm8001_80xx_dispatch;
  98
  99 struct pm8001_hba_info;
 100 struct pm8001_ccb_info;
 101 struct pm8001_device;
 102 /* define task management IU */
 103 struct pm8001_tmf_task {
 104         u8      tmf;
 105         u32     tag_of_task_to_be_managed;
 106 };
 107 struct pm8001_ioctl_payload {
 108         u32     signature;
 109         u16     major_function;
 110         u16     minor_function;
 111         u16     status;
 112         u16     offset;
 113         u16     id;
 114         u32     wr_length;
 115         u32     rd_length;
 116         u8      *func_specific;
 117 };
 118
 119 #define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF
 120 #define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24)
 121 #define MPI_FATAL_EDUMP_TABLE_LO_OFFSET            0x00     /* HNFBUFL */
 122 #define MPI_FATAL_EDUMP_TABLE_HI_OFFSET            0x04     /* HNFBUFH */
 123 #define MPI_FATAL_EDUMP_TABLE_LENGTH               0x08     /* HNFBLEN */
 124 #define MPI_FATAL_EDUMP_TABLE_HANDSHAKE            0x0C     /* FDDHSHK */
 125 #define MPI_FATAL_EDUMP_TABLE_STATUS               0x10     /* FDDTSTAT */
 126 #define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN            0x14     /* ACCDDLEN */
 127 #define MPI_FATAL_EDUMP_TABLE_TOTAL_LEN            0x18     /* TOTALLEN */
 128 #define MPI_FATAL_EDUMP_TABLE_SIGNATURE            0x1C     /* SIGNITURE */
 129 #define MPI_FATAL_EDUMP_HANDSHAKE_RDY              0x1
 130 #define MPI_FATAL_EDUMP_HANDSHAKE_BUSY             0x0
 131 #define MPI_FATAL_EDUMP_TABLE_STAT_RSVD                 0x0
 132 #define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED           0x1
 133 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2
 134 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE      0x3
 135 #define TYPE_GSM_SPACE        1
 136 #define TYPE_QUEUE            2
 137 #define TYPE_FATAL            3
 138 #define TYPE_NON_FATAL        4
 139 #define TYPE_INBOUND          1
 140 #define TYPE_OUTBOUND         2
 141 struct forensic_data {
 142         u32  data_type;
 143         union {
 144                 struct {
 145                         u32  direct_len;
 146                         u32  direct_offset;
 147                         void  *direct_data;
 148                 } gsm_buf;
 149                 struct {
 150                         u16  queue_type;
 151                         u16  queue_index;
 152                         u32  direct_len;
 153                         void  *direct_data;
 154                 } queue_buf;
 155                 struct {
 156                         u32  direct_len;
 157                         u32  direct_offset;
 158                         u32  read_len;
 159                         void  *direct_data;
 160                 } data_buf;
 161         };
 162 };
 163
 164 /* bit31-26 - mask bar */
 165 #define SCRATCH_PAD0_BAR_MASK                    0xFC000000
 166 /* bit25-0  - offset mask */
 167 #define SCRATCH_PAD0_OFFSET_MASK                 0x03FFFFFF
 168 /* if AAP error state */
 169 #define SCRATCH_PAD0_AAPERR_MASK                 0xFFFFFFFF
 170 /* Inbound doorbell bit7 */
 171 #define SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP        0x80
 172 /* Inbound doorbell bit7 SPCV */
 173 #define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO  0x80
 174 #define MAIN_MERRDCTO_MERRDCES                   0xA0/* DWORD 0x28) */
 175
 176 struct pm8001_dispatch {
 177         char *name;
 178         int (*chip_init)(struct pm8001_hba_info *pm8001_ha);
 179         int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha);
 180         void (*chip_rst)(struct pm8001_hba_info *pm8001_ha);
 181         int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha);
 182         void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha);
 183         irqreturn_t (*isr)(struct pm8001_hba_info *pm8001_ha, u8 vec);
 184         u32 (*is_our_interrupt)(struct pm8001_hba_info *pm8001_ha);
 185         int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha, u8 vec);
 186         void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
 187         void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
 188         void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
 189         int (*smp_req)(struct pm8001_hba_info *pm8001_ha,
 190                 struct pm8001_ccb_info *ccb);
 191         int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha,
 192                 struct pm8001_ccb_info *ccb);
 193         int (*sata_req)(struct pm8001_hba_info *pm8001_ha,
 194                 struct pm8001_ccb_info *ccb);
 195         int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
 196         int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
 197         int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha,
 198                 struct pm8001_device *pm8001_dev, u32 flag);
 199         int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id);
 200         int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha,
 201                 u32 phy_id, u32 phy_op);
 202         int (*task_abort)(struct pm8001_hba_info *pm8001_ha,
 203                 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag,
 204                 u32 cmd_tag);
 205         int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha,
 206                 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf);
 207         int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
 208         int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
 209         int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha,
 210                 void *payload);
 211         int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha,
 212                 struct pm8001_device *pm8001_dev, u32 state);
 213         int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha,
 214                 u32 state);
 215         int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha,
 216                 u32 state);
 217         int (*sas_re_init_req)(struct pm8001_hba_info *pm8001_ha);
 218 };
 219
 220 struct pm8001_chip_info {
 221         u32     encrypt;
 222         u32     n_phy;
 223         const struct pm8001_dispatch    *dispatch;
 224 };
 225 #define PM8001_CHIP_DISP        (pm8001_ha->chip->dispatch)
 226
 227 struct pm8001_port {
 228         struct asd_sas_port     sas_port;
 229         u8                      port_attached;
 230         u16                     wide_port_phymap;
 231         u8                      port_state;
 232         struct list_head        list;
 233 };
 234
 235 struct pm8001_phy {
 236         struct pm8001_hba_info  *pm8001_ha;
 237         struct pm8001_port      *port;
 238         struct asd_sas_phy      sas_phy;
 239         struct sas_identify     identify;
 240         struct scsi_device      *sdev;
 241         u64                     dev_sas_addr;
 242         u32                     phy_type;
 243         struct completion       *enable_completion;
 244         u32                     frame_rcvd_size;
 245         u8                      frame_rcvd[32];
 246         u8                      phy_attached;
 247         u8                      phy_state;
 248         enum sas_linkrate       minimum_linkrate;
 249         enum sas_linkrate       maximum_linkrate;
 250         struct completion       *reset_completion;
 251         bool                    port_reset_status;
 252         bool                    reset_success;
 253 };
 254
 255 /* port reset status */
 256 #define PORT_RESET_SUCCESS      0x00
 257 #define PORT_RESET_TMO          0x01
 258
 259 struct pm8001_device {
 260         enum sas_device_type    dev_type;
 261         struct domain_device    *sas_device;
 262         u32                     attached_phy;
 263         u32                     id;
 264         struct completion       *dcompletion;
 265         struct completion       *setds_completion;
 266         u32                     device_id;
 267         atomic_t                running_req;
 268 };
 269
 270 struct pm8001_prd_imt {
 271         __le32                  len;
 272         __le32                  e;
 273 };
 274
 275 struct pm8001_prd {
 276         __le64                  addr;           /* 64-bit buffer address */
 277         struct pm8001_prd_imt   im_len;         /* 64-bit length */
 278 } __attribute__ ((packed));
 279 /*
 280  * CCB(Command Control Block)
 281  */
 282 struct pm8001_ccb_info {
 283         struct list_head        entry;
 284         struct sas_task         *task;
 285         u32                     n_elem;
 286         u32                     ccb_tag;
 287         dma_addr_t              ccb_dma_handle;
 288         struct pm8001_device    *device;
 289         struct pm8001_prd       *buf_prd;
 290         struct fw_control_ex    *fw_control_context;
 291         u8                      open_retry;
 292 };
 293
 294 struct mpi_mem {
 295         void                    *virt_ptr;
 296         dma_addr_t              phys_addr;
 297         u32                     phys_addr_hi;
 298         u32                     phys_addr_lo;
 299         u32                     total_len;
 300         u32                     num_elements;
 301         u32                     element_size;
 302         u32                     alignment;
 303 };
 304
 305 struct mpi_mem_req {
 306         /* The number of element in the  mpiMemory array */
 307         u32                     count;
 308         /* The array of structures that define memroy regions*/
 309         struct mpi_mem          region[USI_MAX_MEMCNT];
 310 };
 311
 312 struct encrypt {
 313         u32     cipher_mode;
 314         u32     sec_mode;
 315         u32     status;
 316         u32     flag;
 317 };
 318
 319 struct sas_phy_attribute_table {
 320         u32     phystart1_16[16];
 321         u32     outbound_hw_event_pid1_16[16];
 322 };
 323
 324 union main_cfg_table {
 325         struct {
 326         u32                     signature;
 327         u32                     interface_rev;
 328         u32                     firmware_rev;
 329         u32                     max_out_io;
 330         u32                     max_sgl;
 331         u32                     ctrl_cap_flag;
 332         u32                     gst_offset;
 333         u32                     inbound_queue_offset;
 334         u32                     outbound_queue_offset;
 335         u32                     inbound_q_nppd_hppd;
 336         u32                     outbound_hw_event_pid0_3;
 337         u32                     outbound_hw_event_pid4_7;
 338         u32                     outbound_ncq_event_pid0_3;
 339         u32                     outbound_ncq_event_pid4_7;
 340         u32                     outbound_tgt_ITNexus_event_pid0_3;
 341         u32                     outbound_tgt_ITNexus_event_pid4_7;
 342         u32                     outbound_tgt_ssp_event_pid0_3;
 343         u32                     outbound_tgt_ssp_event_pid4_7;
 344         u32                     outbound_tgt_smp_event_pid0_3;
 345         u32                     outbound_tgt_smp_event_pid4_7;
 346         u32                     upper_event_log_addr;
 347         u32                     lower_event_log_addr;
 348         u32                     event_log_size;
 349         u32                     event_log_option;
 350         u32                     upper_iop_event_log_addr;
 351         u32                     lower_iop_event_log_addr;
 352         u32                     iop_event_log_size;
 353         u32                     iop_event_log_option;
 354         u32                     fatal_err_interrupt;
 355         u32                     fatal_err_dump_offset0;
 356         u32                     fatal_err_dump_length0;
 357         u32                     fatal_err_dump_offset1;
 358         u32                     fatal_err_dump_length1;
 359         u32                     hda_mode_flag;
 360         u32                     anolog_setup_table_offset;
 361         u32                     rsvd[4];
 362         } pm8001_tbl;
 363
 364         struct {
 365         u32                     signature;
 366         u32                     interface_rev;
 367         u32                     firmware_rev;
 368         u32                     max_out_io;
 369         u32                     max_sgl;
 370         u32                     ctrl_cap_flag;
 371         u32                     gst_offset;
 372         u32                     inbound_queue_offset;
 373         u32                     outbound_queue_offset;
 374         u32                     inbound_q_nppd_hppd;
 375         u32                     rsvd[8];
 376         u32                     crc_core_dump;
 377         u32                     rsvd1;
 378         u32                     upper_event_log_addr;
 379         u32                     lower_event_log_addr;
 380         u32                     event_log_size;
 381         u32                     event_log_severity;
 382         u32                     upper_pcs_event_log_addr;
 383         u32                     lower_pcs_event_log_addr;
 384         u32                     pcs_event_log_size;
 385         u32                     pcs_event_log_severity;
 386         u32                     fatal_err_interrupt;
 387         u32                     fatal_err_dump_offset0;
 388         u32                     fatal_err_dump_length0;
 389         u32                     fatal_err_dump_offset1;
 390         u32                     fatal_err_dump_length1;
 391         u32                     gpio_led_mapping;
 392         u32                     analog_setup_table_offset;
 393         u32                     int_vec_table_offset;
 394         u32                     phy_attr_table_offset;
 395         u32                     port_recovery_timer;
 396         u32                     interrupt_reassertion_delay;
 397         u32                     fatal_n_non_fatal_dump;         /* 0x28 */
 398         u32                     ila_version;
 399         u32                     inc_fw_version;
 400         } pm80xx_tbl;
 401 };
 402
 403 union general_status_table {
 404         struct {
 405         u32                     gst_len_mpistate;
 406         u32                     iq_freeze_state0;
 407         u32                     iq_freeze_state1;
 408         u32                     msgu_tcnt;
 409         u32                     iop_tcnt;
 410         u32                     rsvd;
 411         u32                     phy_state[8];
 412         u32                     gpio_input_val;
 413         u32                     rsvd1[2];
 414         u32                     recover_err_info[8];
 415         } pm8001_tbl;
 416         struct {
 417         u32                     gst_len_mpistate;
 418         u32                     iq_freeze_state0;
 419         u32                     iq_freeze_state1;
 420         u32                     msgu_tcnt;
 421         u32                     iop_tcnt;
 422         u32                     rsvd[9];
 423         u32                     gpio_input_val;
 424         u32                     rsvd1[2];
 425         u32                     recover_err_info[8];
 426         } pm80xx_tbl;
 427 };
 428 struct inbound_queue_table {
 429         u32                     element_pri_size_cnt;
 430         u32                     upper_base_addr;
 431         u32                     lower_base_addr;
 432         u32                     ci_upper_base_addr;
 433         u32                     ci_lower_base_addr;
 434         u32                     pi_pci_bar;
 435         u32                     pi_offset;
 436         u32                     total_length;
 437         void                    *base_virt;
 438         void                    *ci_virt;
 439         u32                     reserved;
 440         __le32                  consumer_index;
 441         u32                     producer_idx;
 442         spinlock_t              iq_lock;
 443 };
 444 struct outbound_queue_table {
 445         u32                     element_size_cnt;
 446         u32                     upper_base_addr;
 447         u32                     lower_base_addr;
 448         void                    *base_virt;
 449         u32                     pi_upper_base_addr;
 450         u32                     pi_lower_base_addr;
 451         u32                     ci_pci_bar;
 452         u32                     ci_offset;
 453         u32                     total_length;
 454         void                    *pi_virt;
 455         u32                     interrup_vec_cnt_delay;
 456         u32                     dinterrup_to_pci_offset;
 457         __le32                  producer_index;
 458         u32                     consumer_idx;
 459 };
 460 struct pm8001_hba_memspace {
 461         void __iomem            *memvirtaddr;
 462         u64                     membase;
 463         u32                     memsize;
 464 };
 465 struct isr_param {
 466         struct pm8001_hba_info *drv_inst;
 467         u32 irq_id;
 468 };
 469 struct pm8001_hba_info {
 470         char                    name[PM8001_NAME_LENGTH];
 471         struct list_head        list;
 472         unsigned long           flags;
 473         spinlock_t              lock;/* host-wide lock */
 474         spinlock_t              bitmap_lock;
 475         struct pci_dev          *pdev;/* our device */
 476         struct device           *dev;
 477         struct pm8001_hba_memspace io_mem[6];
 478         struct mpi_mem_req      memoryMap;
 479         struct encrypt          encrypt_info; /* support encryption */
 480         struct forensic_data    forensic_info;
 481         u32                     fatal_bar_loc;
 482         u32                     forensic_last_offset;
 483         u32                     fatal_forensic_shift_offset;
 484         u32                     forensic_fatal_step;
 485         u32                     forensic_preserved_accumulated_transfer;
 486         u32                     evtlog_ib_offset;
 487         u32                     evtlog_ob_offset;
 488         void __iomem    *msg_unit_tbl_addr;/*Message Unit Table Addr*/
 489         void __iomem    *main_cfg_tbl_addr;/*Main Config Table Addr*/
 490         void __iomem    *general_stat_tbl_addr;/*General Status Table Addr*/
 491         void __iomem    *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/
 492         void __iomem    *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/
 493         void __iomem    *pspa_q_tbl_addr;
 494                         /*MPI SAS PHY attributes Queue Config Table Addr*/
 495         void __iomem    *ivt_tbl_addr; /*MPI IVT Table Addr */
 496         void __iomem    *fatal_tbl_addr; /*MPI IVT Table Addr */
 497         union main_cfg_table    main_cfg_tbl;
 498         union general_status_table      gs_tbl;
 499         struct inbound_queue_table      inbnd_q_tbl[PM8001_MAX_INB_NUM];
 500         struct outbound_queue_table     outbnd_q_tbl[PM8001_MAX_OUTB_NUM];
 501         struct sas_phy_attribute_table  phy_attr_table;
 502                                         /* MPI SAS PHY attributes */
 503         u8                      sas_addr[SAS_ADDR_SIZE];
 504         struct sas_ha_struct    *sas;/* SCSI/SAS glue */
 505         struct Scsi_Host        *shost;
 506         u32                     chip_id;
 507         const struct pm8001_chip_info   *chip;
 508         struct completion       *nvmd_completion;
 509         int                     tags_num;
 510         unsigned long           *tags;
 511         struct pm8001_phy       phy[PM8001_MAX_PHYS];
 512         struct pm8001_port      port[PM8001_MAX_PHYS];
 513         u32                     id;
 514         u32                     irq;
 515         u32                     iomb_size; /* SPC and SPCV IOMB size */
 516         struct pm8001_device    *devices;
 517         struct pm8001_ccb_info  *ccb_info;
 518 #ifdef PM8001_USE_MSIX
 519         int                     number_of_intr;/*will be used in remove()*/
 520         char                    intr_drvname[PM8001_MAX_MSIX_VEC]
 521                                 [PM8001_NAME_LENGTH+1+3+1];
 522 #endif
 523 #ifdef PM8001_USE_TASKLET
 524         struct tasklet_struct   tasklet[PM8001_MAX_MSIX_VEC];
 525 #endif
 526         u32                     logging_level;
 527         u32                     link_rate;
 528         u32                     fw_status;
 529         u32                     smp_exp_mode;
 530         bool                    controller_fatal_error;
 531         const struct firmware   *fw_image;
 532         struct isr_param irq_vector[PM8001_MAX_MSIX_VEC];
 533         u32                     reset_in_progress;
 534         u32                     non_fatal_count;
 535         u32                     non_fatal_read_length;
 536         u32 max_q_num;
 537         u32 ib_offset;
 538         u32 ob_offset;
 539         u32 ci_offset;
 540         u32 pi_offset;
 541         u32 max_memcnt;
 542 };
 543
 544 struct pm8001_work {
 545         struct work_struct work;
 546         struct pm8001_hba_info *pm8001_ha;
 547         void *data;
 548         int handler;
 549 };
 550
 551 struct pm8001_fw_image_header {
 552         u8 vender_id[8];
 553         u8 product_id;
 554         u8 hardware_rev;
 555         u8 dest_partition;
 556         u8 reserved;
 557         u8 fw_rev[4];
 558         __be32  image_length;
 559         __be32 image_crc;
 560         __be32 startup_entry;
 561 } __attribute__((packed, aligned(4)));
 562
 563
 564 /**
 565  * FW Flash Update status values
 566  */
 567 #define FLASH_UPDATE_COMPLETE_PENDING_REBOOT    0x00
 568 #define FLASH_UPDATE_IN_PROGRESS                0x01
 569 #define FLASH_UPDATE_HDR_ERR                    0x02
 570 #define FLASH_UPDATE_OFFSET_ERR                 0x03
 571 #define FLASH_UPDATE_CRC_ERR                    0x04
 572 #define FLASH_UPDATE_LENGTH_ERR                 0x05
 573 #define FLASH_UPDATE_HW_ERR                     0x06
 574 #define FLASH_UPDATE_DNLD_NOT_SUPPORTED         0x10
 575 #define FLASH_UPDATE_DISABLED                   0x11
 576
 577 #define NCQ_READ_LOG_FLAG                       0x80000000
 578 #define NCQ_ABORT_ALL_FLAG                      0x40000000
 579 #define NCQ_2ND_RLE_FLAG                        0x20000000
 580
 581 /* Device states */
 582 #define DS_OPERATIONAL                          0x01
 583 #define DS_PORT_IN_RESET                        0x02
 584 #define DS_IN_RECOVERY                          0x03
 585 #define DS_IN_ERROR                             0x04
 586 #define DS_NON_OPERATIONAL                      0x07
 587
 588 /**
 589  * brief param structure for firmware flash update.
 590  */
 591 struct fw_flash_updata_info {
 592         u32                     cur_image_offset;
 593         u32                     cur_image_len;
 594         u32                     total_image_len;
 595         struct pm8001_prd       sgl;
 596 };
 597
 598 struct fw_control_info {
 599         u32                     retcode;/*ret code (status)*/
 600         u32                     phase;/*ret code phase*/
 601         u32                     phaseCmplt;/*percent complete for the current
 602         update phase */
 603         u32                     version;/*Hex encoded firmware version number*/
 604         u32                     offset;/*Used for downloading firmware  */
 605         u32                     len; /*len of buffer*/
 606         u32                     size;/* Used in OS VPD and Trace get size
 607         operations.*/
 608         u32                     reserved;/* padding required for 64 bit
 609         alignment */
 610         u8                      buffer[1];/* Start of buffer */
 611 };
 612 struct fw_control_ex {
 613         struct fw_control_info *fw_control;
 614         void                    *buffer;/* keep buffer pointer to be
 615         freed when the response comes*/
 616         void                    *virtAddr;/* keep virtual address of the data */
 617         void                    *usrAddr;/* keep virtual address of the
 618         user data */
 619         dma_addr_t              phys_addr;
 620         u32                     len; /* len of buffer  */
 621         void                    *payload; /* pointer to IOCTL Payload */
 622         u8                      inProgress;/*if 1 - the IOCTL request is in
 623         progress */
 624         void                    *param1;
 625         void                    *param2;
 626         void                    *param3;
 627 };
 628
 629 /* pm8001 workqueue */
 630 extern struct workqueue_struct *pm8001_wq;
 631
 632 /******************** function prototype *********************/
 633 int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out);
 634 void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha);
 635 u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag);
 636 void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
 637         struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx);
 638 int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
 639         void *funcdata);
 640 void pm8001_scan_start(struct Scsi_Host *shost);
 641 int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time);
 642 int pm8001_queue_command(struct sas_task *task, gfp_t gfp_flags);
 643 int pm8001_abort_task(struct sas_task *task);
 644 int pm8001_abort_task_set(struct domain_device *dev, u8 *lun);
 645 int pm8001_clear_aca(struct domain_device *dev, u8 *lun);
 646 int pm8001_clear_task_set(struct domain_device *dev, u8 *lun);
 647 int pm8001_dev_found(struct domain_device *dev);
 648 void pm8001_dev_gone(struct domain_device *dev);
 649 int pm8001_lu_reset(struct domain_device *dev, u8 *lun);
 650 int pm8001_I_T_nexus_reset(struct domain_device *dev);
 651 int pm8001_I_T_nexus_event_handler(struct domain_device *dev);
 652 int pm8001_query_task(struct sas_task *task);
 653 void pm8001_open_reject_retry(
 654         struct pm8001_hba_info *pm8001_ha,
 655         struct sas_task *task_to_close,
 656         struct pm8001_device *device_to_close);
 657 int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
 658         dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
 659         u32 mem_size, u32 align);
 660
 661 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha);
 662 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
 663                         struct inbound_queue_table *circularQ,
 664                         u32 opCode, void *payload, size_t nb,
 665                         u32 responseQueue);
 666 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
 667                                 u16 messageSize, void **messagePtr);
 668 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
 669                         struct outbound_queue_table *circularQ, u8 bc);
 670 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
 671                         struct outbound_queue_table *circularQ,
 672                         void **messagePtr1, u8 *pBC);
 673 int pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
 674                         struct pm8001_device *pm8001_dev, u32 state);
 675 int pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
 676                                         void *payload);
 677 int pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
 678                                         void *fw_flash_updata_info, u32 tag);
 679 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
 680 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
 681 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
 682                                 struct pm8001_ccb_info *ccb,
 683                                 struct pm8001_tmf_task *tmf);
 684 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
 685                                 struct pm8001_device *pm8001_dev,
 686                                 u8 flag, u32 task_tag, u32 cmd_tag);
 687 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id);
 688 void pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd);
 689 void pm8001_work_fn(struct work_struct *work);
 690 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha,
 691                                         void *data, int handler);
 692 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
 693                                                         void *piomb);
 694 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
 695                                                         void *piomb);
 696 void pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
 697                                                         void *piomb);
 698 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha,
 699                                                         void *piomb);
 700 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate);
 701 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, u8 *sas_addr);
 702 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i);
 703 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
 704 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
 705 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
 706                                                         void *piomb);
 707 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb);
 708 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
 709 struct sas_task *pm8001_alloc_task(void);
 710 void pm8001_task_done(struct sas_task *task);
 711 void pm8001_free_task(struct sas_task *task);
 712 void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag);
 713 struct pm8001_device *pm8001_find_dev(struct pm8001_hba_info *pm8001_ha,
 714                                         u32 device_id);
 715 int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha);
 716
 717 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
 718 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
 719         u32 length, u8 *buf);
 720 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
 721                 u32 phy, u32 length, u32 *buf);
 722 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
 723 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
 724                 struct device_attribute *attr, char *buf);
 725 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
 726                 struct device_attribute *attr, char *buf);
 727 ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf);
 728 /* ctl shared API */
 729 extern struct device_attribute *pm8001_host_attrs[];
 730
 731 static inline void
 732 pm8001_ccb_task_free_done(struct pm8001_hba_info *pm8001_ha,
 733                         struct sas_task *task, struct pm8001_ccb_info *ccb,
 734                         u32 ccb_idx)
 735 {
 736         pm8001_ccb_task_free(pm8001_ha, task, ccb, ccb_idx);
 737         smp_mb(); /*in order to force CPU ordering*/
 738         spin_unlock(&pm8001_ha->lock);
 739         task->task_done(task);
 740         spin_lock(&pm8001_ha->lock);
 741 }
 742
 743 #endif
 744