drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <[email protected]>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/display/drm_hdmi_audio_helper.h>
  35 #include <drm/display/drm_hdmi_helper.h>
  36 #include <drm/display/drm_hdmi_state_helper.h>
  37 #include <drm/display/drm_scdc_helper.h>
  38 #include <drm/drm_atomic_helper.h>
  39 #include <drm/drm_drv.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_probe_helper.h>
  42 #include <drm/drm_simple_kms_helper.h>
  43 #include <linux/clk.h>
  44 #include <linux/component.h>
  45 #include <linux/gpio/consumer.h>
  46 #include <linux/i2c.h>
  47 #include <linux/of.h>
  48 #include <linux/of_address.h>
  49 #include <linux/pm_runtime.h>
  50 #include <linux/rational.h>
  51 #include <linux/reset.h>
  52 #include <sound/dmaengine_pcm.h>
  53 #include <sound/hdmi-codec.h>
  54 #include <sound/pcm_drm_eld.h>
  55 #include <sound/pcm_params.h>
  56 #include <sound/soc.h>
  57 #include "media/cec.h"
  58 #include "vc4_drv.h"
  59 #include "vc4_hdmi.h"
  60 #include "vc4_hdmi_regs.h"
  61 #include "vc4_regs.h"
  62
  63 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  64 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  65 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  66 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  67 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  68 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  69
  70 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  71 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  72 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  73 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  74
  75 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  76 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  77 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  78 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  79 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  80 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  81
  82 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  83 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  84
  85 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  86 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  87 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  88 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  89
  90 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  91
  92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  94
  95 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  96 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  97
  98 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  99
 100 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
 101 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
 102
 103 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK   VC4_MASK(7, 0)
 104 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE     BIT(0)
 105 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE   BIT(4)
 106
 107 # define VC4_HD_M_SW_RST                        BIT(2)
 108 # define VC4_HD_M_ENABLE                        BIT(0)
 109
 110 #define HSM_MIN_CLOCK_FREQ      120000000
 111 #define CEC_CLOCK_FREQ 40000
 112
 113 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 114
 115 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
 116 {
 117         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 118
 119         lockdep_assert_held(&vc4_hdmi->mutex);
 120
 121         if (!display->is_hdmi)
 122                 return false;
 123
 124         if (!display->hdmi.scdc.supported ||
 125             !display->hdmi.scdc.scrambling.supported)
 126                 return false;
 127
 128         return true;
 129 }
 130
 131 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
 132                                            unsigned int bpc,
 133                                            enum hdmi_colorspace fmt)
 134 {
 135         unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt);
 136
 137         return clock > HDMI_14_MAX_TMDS_CLK;
 138 }
 139
 140 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 141 {
 142         struct drm_debugfs_entry *entry = m->private;
 143         struct vc4_hdmi *vc4_hdmi = entry->file.data;
 144         struct drm_device *drm = vc4_hdmi->connector.dev;
 145         struct drm_printer p = drm_seq_file_printer(m);
 146         int idx;
 147
 148         if (!drm_dev_enter(drm, &idx))
 149                 return -ENODEV;
 150
 151         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 152
 153         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 154         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 155         drm_print_regset32(&p, &vc4_hdmi->cec_regset);
 156         drm_print_regset32(&p, &vc4_hdmi->csc_regset);
 157         drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
 158         drm_print_regset32(&p, &vc4_hdmi->phy_regset);
 159         drm_print_regset32(&p, &vc4_hdmi->ram_regset);
 160         drm_print_regset32(&p, &vc4_hdmi->rm_regset);
 161
 162         pm_runtime_put(&vc4_hdmi->pdev->dev);
 163
 164         drm_dev_exit(idx);
 165
 166         return 0;
 167 }
 168
 169 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 170 {
 171         struct drm_device *drm = vc4_hdmi->connector.dev;
 172         unsigned long flags;
 173         int idx;
 174
 175         /*
 176          * We can be called by our bind callback, when the
 177          * connector->dev pointer might not be initialised yet.
 178          */
 179         if (drm && !drm_dev_enter(drm, &idx))
 180                 return;
 181
 182         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 183
 184         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 185         udelay(1);
 186         HDMI_WRITE(HDMI_M_CTL, 0);
 187
 188         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 189
 190         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 191                    VC4_HDMI_SW_RESET_HDMI |
 192                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 193
 194         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 195
 196         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 197
 198         if (drm)
 199                 drm_dev_exit(idx);
 200 }
 201
 202 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 203 {
 204         struct drm_device *drm = vc4_hdmi->connector.dev;
 205         unsigned long flags;
 206         int idx;
 207
 208         /*
 209          * We can be called by our bind callback, when the
 210          * connector->dev pointer might not be initialised yet.
 211          */
 212         if (drm && !drm_dev_enter(drm, &idx))
 213                 return;
 214
 215         reset_control_reset(vc4_hdmi->reset);
 216
 217         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 218
 219         HDMI_WRITE(HDMI_DVP_CTL, 0);
 220
 221         HDMI_WRITE(HDMI_CLOCK_STOP,
 222                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 223
 224         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 225
 226         if (drm)
 227                 drm_dev_exit(idx);
 228 }
 229
 230 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 231 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 232 {
 233         struct drm_device *drm = vc4_hdmi->connector.dev;
 234         unsigned long cec_rate;
 235         unsigned long flags;
 236         u16 clk_cnt;
 237         u32 value;
 238         int idx;
 239
 240         /*
 241          * This function is called by our runtime_resume implementation
 242          * and thus at bind time, when we haven't registered our
 243          * connector yet and thus don't have a pointer to the DRM
 244          * device.
 245          */
 246         if (drm && !drm_dev_enter(drm, &idx))
 247                 return;
 248
 249         cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 250
 251         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 252
 253         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 254         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 255
 256         /*
 257          * Set the clock divider: the hsm_clock rate and this divider
 258          * setting will give a 40 kHz CEC clock.
 259          */
 260         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 261         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 262         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 263
 264         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 265
 266         if (drm)
 267                 drm_dev_exit(idx);
 268 }
 269 #else
 270 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 271 #endif
 272
 273 static int reset_pipe(struct drm_crtc *crtc,
 274                         struct drm_modeset_acquire_ctx *ctx)
 275 {
 276         struct drm_atomic_state *state;
 277         struct drm_crtc_state *crtc_state;
 278         int ret;
 279
 280         state = drm_atomic_state_alloc(crtc->dev);
 281         if (!state)
 282                 return -ENOMEM;
 283
 284         state->acquire_ctx = ctx;
 285
 286         crtc_state = drm_atomic_get_crtc_state(state, crtc);
 287         if (IS_ERR(crtc_state)) {
 288                 ret = PTR_ERR(crtc_state);
 289                 goto out;
 290         }
 291
 292         crtc_state->connectors_changed = true;
 293
 294         ret = drm_atomic_commit(state);
 295 out:
 296         drm_atomic_state_put(state);
 297
 298         return ret;
 299 }
 300
 301 static int vc4_hdmi_reset_link(struct drm_connector *connector,
 302                                struct drm_modeset_acquire_ctx *ctx)
 303 {
 304         struct drm_device *drm;
 305         struct vc4_hdmi *vc4_hdmi;
 306         struct drm_connector_state *conn_state;
 307         struct drm_crtc_state *crtc_state;
 308         struct drm_crtc *crtc;
 309         bool scrambling_needed;
 310         u8 config;
 311         int ret;
 312
 313         if (!connector)
 314                 return 0;
 315
 316         drm = connector->dev;
 317         ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
 318         if (ret)
 319                 return ret;
 320
 321         conn_state = connector->state;
 322         crtc = conn_state->crtc;
 323         if (!crtc)
 324                 return 0;
 325
 326         ret = drm_modeset_lock(&crtc->mutex, ctx);
 327         if (ret)
 328                 return ret;
 329
 330         crtc_state = crtc->state;
 331         if (!crtc_state->active)
 332                 return 0;
 333
 334         vc4_hdmi = connector_to_vc4_hdmi(connector);
 335         mutex_lock(&vc4_hdmi->mutex);
 336
 337         if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
 338                 mutex_unlock(&vc4_hdmi->mutex);
 339                 return 0;
 340         }
 341
 342         scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
 343                                                            vc4_hdmi->output_bpc,
 344                                                            vc4_hdmi->output_format);
 345         if (!scrambling_needed) {
 346                 mutex_unlock(&vc4_hdmi->mutex);
 347                 return 0;
 348         }
 349
 350         if (conn_state->commit &&
 351             !try_wait_for_completion(&conn_state->commit->hw_done)) {
 352                 mutex_unlock(&vc4_hdmi->mutex);
 353                 return 0;
 354         }
 355
 356         ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
 357         if (ret < 0) {
 358                 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
 359                 mutex_unlock(&vc4_hdmi->mutex);
 360                 return 0;
 361         }
 362
 363         if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
 364                 mutex_unlock(&vc4_hdmi->mutex);
 365                 return 0;
 366         }
 367
 368         mutex_unlock(&vc4_hdmi->mutex);
 369
 370         /*
 371          * HDMI 2.0 says that one should not send scrambled data
 372          * prior to configuring the sink scrambling, and that
 373          * TMDS clock/data transmission should be suspended when
 374          * changing the TMDS clock rate in the sink. So let's
 375          * just do a full modeset here, even though some sinks
 376          * would be perfectly happy if were to just reconfigure
 377          * the SCDC settings on the fly.
 378          */
 379         return reset_pipe(crtc, ctx);
 380 }
 381
 382 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
 383                                     struct drm_modeset_acquire_ctx *ctx,
 384                                     enum drm_connector_status status)
 385 {
 386         struct drm_connector *connector = &vc4_hdmi->connector;
 387         int ret;
 388
 389         /*
 390          * NOTE: This function should really be called with vc4_hdmi->mutex
 391          * held, but doing so results in reentrancy issues since
 392          * cec_s_phys_addr() might call .adap_enable, which leads to that
 393          * funtion being called with our mutex held.
 394          *
 395          * A similar situation occurs with vc4_hdmi_reset_link() that
 396          * will call into our KMS hooks if the scrambling was enabled.
 397          *
 398          * Concurrency isn't an issue at the moment since we don't share
 399          * any state with any of the other frameworks so we can ignore
 400          * the lock for now.
 401          */
 402
 403         if (status == connector_status_disconnected) {
 404                 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 405                 return;
 406         }
 407
 408         drm_atomic_helper_connector_hdmi_hotplug(connector, status);
 409
 410         cec_s_phys_addr(vc4_hdmi->cec_adap,
 411                         connector->display_info.source_physical_address, false);
 412
 413         if (status != connector_status_connected)
 414                 return;
 415
 416         for (;;) {
 417                 ret = vc4_hdmi_reset_link(connector, ctx);
 418                 if (ret == -EDEADLK) {
 419                         drm_modeset_backoff(ctx);
 420                         continue;
 421                 }
 422
 423                 break;
 424         }
 425 }
 426
 427 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
 428                                          struct drm_modeset_acquire_ctx *ctx,
 429                                          bool force)
 430 {
 431         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 432         enum drm_connector_status status = connector_status_disconnected;
 433         int ret;
 434
 435         /*
 436          * NOTE: This function should really take vc4_hdmi->mutex, but
 437          * doing so results in reentrancy issues since
 438          * vc4_hdmi_handle_hotplug() can call into other functions that
 439          * would take the mutex while it's held here.
 440          *
 441          * Concurrency isn't an issue at the moment since we don't share
 442          * any state with any of the other frameworks so we can ignore
 443          * the lock for now.
 444          */
 445
 446         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
 447         if (ret) {
 448                 drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n",
 449                              ret);
 450                 return connector_status_unknown;
 451         }
 452
 453         if (vc4_hdmi->hpd_gpio) {
 454                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 455                         status = connector_status_connected;
 456         } else {
 457                 if (vc4_hdmi->variant->hp_detect &&
 458                     vc4_hdmi->variant->hp_detect(vc4_hdmi))
 459                         status = connector_status_connected;
 460         }
 461
 462         vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
 463         pm_runtime_put(&vc4_hdmi->pdev->dev);
 464
 465         return status;
 466 }
 467
 468 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 469 {
 470         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
 471         int ret = 0;
 472
 473         ret = drm_edid_connector_add_modes(connector);
 474
 475         if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
 476                 struct drm_device *drm = connector->dev;
 477                 const struct drm_display_mode *mode;
 478
 479                 list_for_each_entry(mode, &connector->probed_modes, head) {
 480                         if (vc4_hdmi_mode_needs_scrambling(mode, 8, HDMI_COLORSPACE_RGB)) {
 481                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 482                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 483                         }
 484                 }
 485         }
 486
 487         return ret;
 488 }
 489
 490 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 491                                            struct drm_atomic_state *state)
 492 {
 493         struct drm_connector_state *old_state =
 494                 drm_atomic_get_old_connector_state(state, connector);
 495         struct drm_connector_state *new_state =
 496                 drm_atomic_get_new_connector_state(state, connector);
 497         struct drm_crtc *crtc = new_state->crtc;
 498
 499         if (!crtc)
 500                 return 0;
 501
 502         if (old_state->tv.margins.left != new_state->tv.margins.left ||
 503             old_state->tv.margins.right != new_state->tv.margins.right ||
 504             old_state->tv.margins.top != new_state->tv.margins.top ||
 505             old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
 506                 struct drm_crtc_state *crtc_state;
 507                 int ret;
 508
 509                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 510                 if (IS_ERR(crtc_state))
 511                         return PTR_ERR(crtc_state);
 512
 513                 /*
 514                  * Strictly speaking, we should be calling
 515                  * drm_atomic_helper_check_planes() after our call to
 516                  * drm_atomic_add_affected_planes(). However, the
 517                  * connector atomic_check is called as part of
 518                  * drm_atomic_helper_check_modeset() that already
 519                  * happens before a call to
 520                  * drm_atomic_helper_check_planes() in
 521                  * drm_atomic_helper_check().
 522                  */
 523                 ret = drm_atomic_add_affected_planes(state, crtc);
 524                 if (ret)
 525                         return ret;
 526         }
 527
 528         if (old_state->colorspace != new_state->colorspace) {
 529                 struct drm_crtc_state *crtc_state;
 530
 531                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 532                 if (IS_ERR(crtc_state))
 533                         return PTR_ERR(crtc_state);
 534
 535                 crtc_state->mode_changed = true;
 536         }
 537
 538         return drm_atomic_helper_connector_hdmi_check(connector, state);
 539 }
 540
 541 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 542 {
 543         drm_atomic_helper_connector_reset(connector);
 544         __drm_atomic_helper_connector_hdmi_reset(connector, connector->state);
 545         drm_atomic_helper_connector_tv_margins_reset(connector);
 546 }
 547
 548 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 549         .force = drm_atomic_helper_connector_hdmi_force,
 550         .fill_modes = drm_helper_probe_single_connector_modes,
 551         .reset = vc4_hdmi_connector_reset,
 552         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 553         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 554 };
 555
 556 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 557         .detect_ctx = vc4_hdmi_connector_detect_ctx,
 558         .get_modes = vc4_hdmi_connector_get_modes,
 559         .atomic_check = vc4_hdmi_connector_atomic_check,
 560         .mode_valid = drm_hdmi_connector_mode_valid,
 561 };
 562
 563 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs;
 564 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs;
 565
 566 static int vc4_hdmi_connector_init(struct drm_device *dev,
 567                                    struct vc4_hdmi *vc4_hdmi)
 568 {
 569         struct drm_connector *connector = &vc4_hdmi->connector;
 570         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
 571         unsigned int max_bpc = 8;
 572         int ret;
 573
 574         if (vc4_hdmi->variant->supports_hdr)
 575                 max_bpc = 12;
 576
 577         ret = drmm_connector_hdmi_init(dev, connector,
 578                                        "Broadcom", "Videocore",
 579                                        &vc4_hdmi_connector_funcs,
 580                                        &vc4_hdmi_hdmi_connector_funcs,
 581                                        DRM_MODE_CONNECTOR_HDMIA,
 582                                        vc4_hdmi->ddc,
 583                                        BIT(HDMI_COLORSPACE_RGB) |
 584                                        BIT(HDMI_COLORSPACE_YUV422) |
 585                                        BIT(HDMI_COLORSPACE_YUV444),
 586                                        max_bpc);
 587         if (ret)
 588                 return ret;
 589
 590         ret = drm_connector_hdmi_audio_init(connector, dev->dev,
 591                                             &vc4_hdmi_audio_funcs,
 592                                             8, false, -1);
 593         if (ret)
 594                 return ret;
 595
 596         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 597
 598         /*
 599          * Some of the properties below require access to state, like bpc.
 600          * Allocate some default initial connector state with our reset helper.
 601          */
 602         if (connector->funcs->reset)
 603                 connector->funcs->reset(connector);
 604
 605         /* Create and attach TV margin props to this connector. */
 606         ret = drm_mode_create_tv_margin_properties(dev);
 607         if (ret)
 608                 return ret;
 609
 610         ret = drm_mode_create_hdmi_colorspace_property(connector, 0);
 611         if (ret)
 612                 return ret;
 613
 614         drm_connector_attach_colorspace_property(connector);
 615         drm_connector_attach_tv_margin_properties(connector);
 616
 617         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 618                              DRM_CONNECTOR_POLL_DISCONNECT);
 619
 620         connector->interlace_allowed = 1;
 621         connector->doublescan_allowed = 0;
 622         connector->stereo_allowed = 1;
 623
 624         ret = drm_connector_attach_broadcast_rgb_property(connector);
 625         if (ret)
 626                 return ret;
 627
 628         drm_connector_attach_encoder(connector, encoder);
 629
 630         return 0;
 631 }
 632
 633 static int vc4_hdmi_stop_packet(struct vc4_hdmi *vc4_hdmi,
 634                                 enum hdmi_infoframe_type type,
 635                                 bool poll)
 636 {
 637         struct drm_device *drm = vc4_hdmi->connector.dev;
 638         u32 packet_id = type - 0x80;
 639         unsigned long flags;
 640         int ret = 0;
 641         int idx;
 642
 643         if (!drm_dev_enter(drm, &idx))
 644                 return -ENODEV;
 645
 646         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 647         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 648                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 649         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 650
 651         if (poll) {
 652                 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 653                                  BIT(packet_id)), 100);
 654         }
 655
 656         drm_dev_exit(idx);
 657         return ret;
 658 }
 659
 660 static int vc4_hdmi_write_infoframe(struct drm_connector *connector,
 661                                     enum hdmi_infoframe_type type,
 662                                     const u8 *infoframe, size_t len)
 663 {
 664         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 665         struct drm_device *drm = connector->dev;
 666         u32 packet_id = type - 0x80;
 667         const struct vc4_hdmi_register *ram_packet_start =
 668                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 669         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 670         u32 packet_reg_next = ram_packet_start->offset +
 671                 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
 672         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 673                                                        ram_packet_start->reg);
 674         uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
 675         unsigned long flags;
 676         ssize_t i;
 677         int ret;
 678         int idx;
 679
 680         if (!drm_dev_enter(drm, &idx))
 681                 return 0;
 682
 683         if (len > sizeof(buffer)) {
 684                 ret = -ENOMEM;
 685                 goto out;
 686         }
 687
 688         memcpy(buffer, infoframe, len);
 689
 690         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 691                     VC4_HDMI_RAM_PACKET_ENABLE),
 692                   "Packet RAM has to be on to store the packet.");
 693
 694         ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true);
 695         if (ret) {
 696                 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret);
 697                 goto out;
 698         }
 699
 700         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 701
 702         for (i = 0; i < len; i += 7) {
 703                 writel(buffer[i + 0] << 0 |
 704                        buffer[i + 1] << 8 |
 705                        buffer[i + 2] << 16,
 706                        base + packet_reg);
 707                 packet_reg += 4;
 708
 709                 writel(buffer[i + 3] << 0 |
 710                        buffer[i + 4] << 8 |
 711                        buffer[i + 5] << 16 |
 712                        buffer[i + 6] << 24,
 713                        base + packet_reg);
 714                 packet_reg += 4;
 715         }
 716
 717         /*
 718          * clear remainder of packet ram as it's included in the
 719          * infoframe and triggers a checksum error on hdmi analyser
 720          */
 721         for (; packet_reg < packet_reg_next; packet_reg += 4)
 722                 writel(0, base + packet_reg);
 723
 724         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 725                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 726
 727         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 728
 729         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 730                         BIT(packet_id)), 100);
 731         if (ret)
 732                 drm_err(drm, "Failed to wait for infoframe to start: %d\n", ret);
 733
 734 out:
 735         drm_dev_exit(idx);
 736         return ret;
 737 }
 738
 739 #define SCRAMBLING_POLLING_DELAY_MS     1000
 740
 741 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 742 {
 743         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 744         struct drm_connector *connector = &vc4_hdmi->connector;
 745         struct drm_device *drm = connector->dev;
 746         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 747         unsigned long flags;
 748         int idx;
 749
 750         lockdep_assert_held(&vc4_hdmi->mutex);
 751
 752         if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
 753                 return;
 754
 755         if (!vc4_hdmi_mode_needs_scrambling(mode,
 756                                             vc4_hdmi->output_bpc,
 757                                             vc4_hdmi->output_format))
 758                 return;
 759
 760         if (!drm_dev_enter(drm, &idx))
 761                 return;
 762
 763         drm_scdc_set_high_tmds_clock_ratio(connector, true);
 764         drm_scdc_set_scrambling(connector, true);
 765
 766         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 767         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 768                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 769         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 770
 771         drm_dev_exit(idx);
 772
 773         vc4_hdmi->scdc_enabled = true;
 774
 775         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 776                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 777 }
 778
 779 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 780 {
 781         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 782         struct drm_connector *connector = &vc4_hdmi->connector;
 783         struct drm_device *drm = connector->dev;
 784         unsigned long flags;
 785         int idx;
 786
 787         lockdep_assert_held(&vc4_hdmi->mutex);
 788
 789         if (!vc4_hdmi->scdc_enabled)
 790                 return;
 791
 792         vc4_hdmi->scdc_enabled = false;
 793
 794         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 795                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 796
 797         if (!drm_dev_enter(drm, &idx))
 798                 return;
 799
 800         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 801         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 802                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 803         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 804
 805         drm_scdc_set_scrambling(connector, false);
 806         drm_scdc_set_high_tmds_clock_ratio(connector, false);
 807
 808         drm_dev_exit(idx);
 809 }
 810
 811 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 812 {
 813         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 814                                                  struct vc4_hdmi,
 815                                                  scrambling_work);
 816         struct drm_connector *connector = &vc4_hdmi->connector;
 817
 818         if (drm_scdc_get_scrambling_status(connector))
 819                 return;
 820
 821         drm_scdc_set_high_tmds_clock_ratio(connector, true);
 822         drm_scdc_set_scrambling(connector, true);
 823
 824         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 825                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 826 }
 827
 828 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 829                                                struct drm_atomic_state *state)
 830 {
 831         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 832         struct drm_device *drm = vc4_hdmi->connector.dev;
 833         struct vc4_dev *vc4 = to_vc4_dev(drm);
 834         unsigned long flags;
 835         int idx;
 836
 837         mutex_lock(&vc4_hdmi->mutex);
 838
 839         vc4_hdmi->packet_ram_enabled = false;
 840
 841         if (!drm_dev_enter(drm, &idx))
 842                 goto out;
 843
 844         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 845
 846         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 847
 848         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 849
 850         if (vc4->gen >= VC4_GEN_6_C)
 851                 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
 852                            VC4_HD_VID_CTL_BLANKPIX);
 853
 854         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 855
 856         mdelay(1);
 857
 858         /*
 859          * TODO: This should work on BCM2712, but doesn't for some
 860          * reason and result in a system lockup.
 861          */
 862         if (vc4->gen < VC4_GEN_6_C) {
 863                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 864                 HDMI_WRITE(HDMI_VID_CTL,
 865                            HDMI_READ(HDMI_VID_CTL) &
 866                            ~VC4_HD_VID_CTL_ENABLE);
 867                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 868         }
 869
 870         vc4_hdmi_disable_scrambling(encoder);
 871
 872         drm_dev_exit(idx);
 873
 874 out:
 875         mutex_unlock(&vc4_hdmi->mutex);
 876 }
 877
 878 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 879                                                  struct drm_atomic_state *state)
 880 {
 881         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 882         struct drm_device *drm = vc4_hdmi->connector.dev;
 883         unsigned long flags;
 884         int ret;
 885         int idx;
 886
 887         mutex_lock(&vc4_hdmi->mutex);
 888
 889         if (!drm_dev_enter(drm, &idx))
 890                 goto out;
 891
 892         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 893         HDMI_WRITE(HDMI_VID_CTL,
 894                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 895         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 896
 897         if (vc4_hdmi->variant->phy_disable)
 898                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 899
 900         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 901         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 902
 903         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 904         if (ret < 0)
 905                 drm_err(drm, "Failed to release power domain: %d\n", ret);
 906
 907         drm_dev_exit(idx);
 908
 909 out:
 910         mutex_unlock(&vc4_hdmi->mutex);
 911 }
 912
 913 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
 914                                struct drm_connector_state *state,
 915                                const struct drm_display_mode *mode)
 916 {
 917         struct drm_device *drm = vc4_hdmi->connector.dev;
 918         unsigned long flags;
 919         u32 csc_ctl;
 920         int idx;
 921
 922         if (!drm_dev_enter(drm, &idx))
 923                 return;
 924
 925         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 926
 927         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 928                                 VC4_HD_CSC_CTL_ORDER);
 929
 930         if (state->hdmi.is_limited_range) {
 931                 /* CEA VICs other than #1 requre limited range RGB
 932                  * output unless overridden by an AVI infoframe.
 933                  * Apply a colorspace conversion to squash 0-255 down
 934                  * to 16-235.  The matrix here is:
 935                  *
 936                  * [ 0      0      0.8594 16]
 937                  * [ 0      0.8594 0      16]
 938                  * [ 0.8594 0      0      16]
 939                  * [ 0      0      0       1]
 940                  */
 941                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 942                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 943                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 944                                          VC4_HD_CSC_CTL_MODE);
 945
 946                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 947                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 948                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 949                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 950                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 951                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 952         }
 953
 954         /* The RGB order applies even when CSC is disabled. */
 955         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 956
 957         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 958
 959         drm_dev_exit(idx);
 960 }
 961
 962 /*
 963  * Matrices for (internal) RGB to RGB output.
 964  *
 965  * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
 966  */
 967 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = {
 968         {
 969                 /*
 970                  * Full range - unity
 971                  *
 972                  * [ 1      0      0      0]
 973                  * [ 0      1      0      0]
 974                  * [ 0      0      1      0]
 975                  */
 976                 { 0x2000, 0x0000, 0x0000, 0x0000 },
 977                 { 0x0000, 0x2000, 0x0000, 0x0000 },
 978                 { 0x0000, 0x0000, 0x2000, 0x0000 },
 979         },
 980         {
 981                 /*
 982                  * Limited range
 983                  *
 984                  * CEA VICs other than #1 require limited range RGB
 985                  * output unless overridden by an AVI infoframe. Apply a
 986                  * colorspace conversion to squash 0-255 down to 16-235.
 987                  * The matrix here is:
 988                  *
 989                  * [ 0.8594 0      0      16]
 990                  * [ 0      0.8594 0      16]
 991                  * [ 0      0      0.8594 16]
 992                  */
 993                 { 0x1b80, 0x0000, 0x0000, 0x0400 },
 994                 { 0x0000, 0x1b80, 0x0000, 0x0400 },
 995                 { 0x0000, 0x0000, 0x1b80, 0x0400 },
 996         },
 997 };
 998
 999 /*
1000  * Conversion between Full Range RGB and YUV using the BT.601 Colorspace
1001  *
1002  * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1003  */
1004 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = {
1005         {
1006                 /*
1007                  * Full Range
1008                  *
1009                  * [  0.299000  0.587000  0.114000  0   ]
1010                  * [ -0.168736 -0.331264  0.500000  128 ]
1011                  * [  0.500000 -0.418688 -0.081312  128 ]
1012                  */
1013                 { 0x0991, 0x12c9, 0x03a6, 0x0000 },
1014                 { 0xfa9b, 0xf567, 0x1000, 0x2000 },
1015                 { 0x1000, 0xf29b, 0xfd67, 0x2000 },
1016         },
1017         {
1018                 /* Limited Range
1019                  *
1020                  * [  0.255785  0.502160  0.097523  16  ]
1021                  * [ -0.147644 -0.289856  0.437500  128 ]
1022                  * [  0.437500 -0.366352 -0.071148  128 ]
1023                  */
1024                 { 0x082f, 0x1012, 0x031f, 0x0400 },
1025                 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1026                 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1027         },
1028 };
1029
1030 /*
1031  * Conversion between Full Range RGB and YUV using the BT.709 Colorspace
1032  *
1033  * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1034  */
1035 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = {
1036         {
1037                 /*
1038                  * Full Range
1039                  *
1040                  * [  0.212600  0.715200  0.072200  0   ]
1041                  * [ -0.114572 -0.385428  0.500000  128 ]
1042                  * [  0.500000 -0.454153 -0.045847  128 ]
1043                  */
1044                 { 0x06ce, 0x16e3, 0x024f, 0x0000 },
1045                 { 0xfc56, 0xf3ac, 0x1000, 0x2000 },
1046                 { 0x1000, 0xf179, 0xfe89, 0x2000 },
1047         },
1048         {
1049                 /*
1050                  * Limited Range
1051                  *
1052                  * [  0.181906  0.611804  0.061758  16  ]
1053                  * [ -0.100268 -0.337232  0.437500  128 ]
1054                  * [  0.437500 -0.397386 -0.040114  128 ]
1055                  */
1056                 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1057                 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1058                 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1059         },
1060 };
1061
1062 /*
1063  * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace
1064  *
1065  * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1066  */
1067 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = {
1068         {
1069                 /*
1070                  * Full Range
1071                  *
1072                  * [  0.262700  0.678000  0.059300  0   ]
1073                  * [ -0.139630 -0.360370  0.500000  128 ]
1074                  * [  0.500000 -0.459786 -0.040214  128 ]
1075                  */
1076                 { 0x0868, 0x15b2, 0x01e6, 0x0000 },
1077                 { 0xfb89, 0xf479, 0x1000, 0x2000 },
1078                 { 0x1000, 0xf14a, 0xfeb8, 0x2000 },
1079         },
1080         {
1081                 /* Limited Range
1082                  *
1083                  * [  0.224732  0.580008  0.050729  16  ]
1084                  * [ -0.122176 -0.315324  0.437500  128 ]
1085                  * [  0.437500 -0.402312 -0.035188  128 ]
1086                  */
1087                 { 0x082f, 0x1012, 0x031f, 0x0400 },
1088                 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1089                 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1090         },
1091 };
1092
1093 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1094                                     const u16 coeffs[3][4])
1095 {
1096         lockdep_assert_held(&vc4_hdmi->hw_lock);
1097
1098         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1099         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1100         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1101         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1102         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1103         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1104 }
1105
1106 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi,
1107                                          const u16 coeffs[3][4])
1108 {
1109         lockdep_assert_held(&vc4_hdmi->hw_lock);
1110
1111         /* YUV444 needs the CSC matrices using the channels in a different order */
1112         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]);
1113         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]);
1114         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]);
1115         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]);
1116         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]);
1117         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]);
1118 }
1119
1120 static const u16
1121 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4]
1122 {
1123         switch (colorspace) {
1124         case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
1125         case DRM_MODE_COLORIMETRY_XVYCC_601:
1126         case DRM_MODE_COLORIMETRY_SYCC_601:
1127         case DRM_MODE_COLORIMETRY_OPYCC_601:
1128         case DRM_MODE_COLORIMETRY_BT601_YCC:
1129                 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited];
1130
1131         default:
1132         case DRM_MODE_COLORIMETRY_NO_DATA:
1133         case DRM_MODE_COLORIMETRY_BT709_YCC:
1134         case DRM_MODE_COLORIMETRY_XVYCC_709:
1135         case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
1136         case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
1137                 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited];
1138
1139         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1140         case DRM_MODE_COLORIMETRY_BT2020_YCC:
1141         case DRM_MODE_COLORIMETRY_BT2020_RGB:
1142         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1143         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1144                 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited];
1145         }
1146 }
1147
1148 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1149                                struct drm_connector_state *state,
1150                                const struct drm_display_mode *mode)
1151 {
1152         struct drm_device *drm = vc4_hdmi->connector.dev;
1153         unsigned int lim_range = state->hdmi.is_limited_range ? 1 : 0;
1154         unsigned long flags;
1155         const u16 (*csc)[4];
1156         u32 if_cfg = 0;
1157         u32 if_xbar = 0x543210;
1158         u32 csc_chan_ctl = 0;
1159         u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1160                                                                VC5_MT_CP_CSC_CTL_MODE);
1161         int idx;
1162
1163         if (!drm_dev_enter(drm, &idx))
1164                 return;
1165
1166         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1167
1168         switch (state->hdmi.output_format) {
1169         case HDMI_COLORSPACE_YUV444:
1170                 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1171
1172                 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc);
1173                 break;
1174
1175         case HDMI_COLORSPACE_YUV422:
1176                 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1177
1178                 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1179                                          VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1180                         VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1181                         VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1182
1183                 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1184                                               VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1185
1186                 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1187                                         VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1188
1189                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc);
1190                 break;
1191
1192         case HDMI_COLORSPACE_RGB:
1193                 if_xbar = 0x354021;
1194
1195                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]);
1196                 break;
1197
1198         default:
1199                 break;
1200         }
1201
1202         HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1203         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1204         HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1205         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1206
1207         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1208
1209         drm_dev_exit(idx);
1210 }
1211
1212 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1213                                  struct drm_connector_state *state,
1214                                  const struct drm_display_mode *mode)
1215 {
1216         struct drm_device *drm = vc4_hdmi->connector.dev;
1217         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1218         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1219         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1220         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1221         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1222                                    VC4_HDMI_VERTA_VSP) |
1223                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1224                                    VC4_HDMI_VERTA_VFP) |
1225                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1226         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1227                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1228                                    interlaced,
1229                                    VC4_HDMI_VERTB_VBP));
1230         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1231                           VC4_SET_FIELD(mode->crtc_vtotal -
1232                                         mode->crtc_vsync_end,
1233                                         VC4_HDMI_VERTB_VBP));
1234         unsigned long flags;
1235         u32 reg;
1236         int idx;
1237
1238         if (!drm_dev_enter(drm, &idx))
1239                 return;
1240
1241         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1242
1243         HDMI_WRITE(HDMI_HORZA,
1244                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1245                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1246                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1247                                  VC4_HDMI_HORZA_HAP));
1248
1249         HDMI_WRITE(HDMI_HORZB,
1250                    VC4_SET_FIELD((mode->htotal -
1251                                   mode->hsync_end) * pixel_rep,
1252                                  VC4_HDMI_HORZB_HBP) |
1253                    VC4_SET_FIELD((mode->hsync_end -
1254                                   mode->hsync_start) * pixel_rep,
1255                                  VC4_HDMI_HORZB_HSP) |
1256                    VC4_SET_FIELD((mode->hsync_start -
1257                                   mode->hdisplay) * pixel_rep,
1258                                  VC4_HDMI_HORZB_HFP));
1259
1260         HDMI_WRITE(HDMI_VERTA0, verta);
1261         HDMI_WRITE(HDMI_VERTA1, verta);
1262
1263         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1264         HDMI_WRITE(HDMI_VERTB1, vertb);
1265
1266         reg = HDMI_READ(HDMI_MISC_CONTROL);
1267         reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1268         reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1269         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1270
1271         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1272
1273         drm_dev_exit(idx);
1274 }
1275
1276 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1277                                  struct drm_connector_state *state,
1278                                  const struct drm_display_mode *mode)
1279 {
1280         struct drm_device *drm = vc4_hdmi->connector.dev;
1281         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1282         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1283         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1284         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1285         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1286                                    VC5_HDMI_VERTA_VSP) |
1287                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1288                                    VC5_HDMI_VERTA_VFP) |
1289                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1290         u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1291                                    VC5_HDMI_VERTB_VSPO) |
1292                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1293                                    interlaced,
1294                                    VC4_HDMI_VERTB_VBP));
1295         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1296                           VC4_SET_FIELD(mode->crtc_vtotal -
1297                                         mode->crtc_vsync_end,
1298                                         VC4_HDMI_VERTB_VBP));
1299         unsigned long flags;
1300         unsigned char gcp;
1301         u32 reg;
1302         int idx;
1303
1304         if (!drm_dev_enter(drm, &idx))
1305                 return;
1306
1307         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1308
1309         HDMI_WRITE(HDMI_HORZA,
1310                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1311                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1312                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1313                                  VC5_HDMI_HORZA_HAP) |
1314                    VC4_SET_FIELD((mode->hsync_start -
1315                                   mode->hdisplay) * pixel_rep,
1316                                  VC5_HDMI_HORZA_HFP));
1317
1318         HDMI_WRITE(HDMI_HORZB,
1319                    VC4_SET_FIELD((mode->htotal -
1320                                   mode->hsync_end) * pixel_rep,
1321                                  VC5_HDMI_HORZB_HBP) |
1322                    VC4_SET_FIELD((mode->hsync_end -
1323                                   mode->hsync_start) * pixel_rep,
1324                                  VC5_HDMI_HORZB_HSP));
1325
1326         HDMI_WRITE(HDMI_VERTA0, verta);
1327         HDMI_WRITE(HDMI_VERTA1, verta);
1328
1329         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1330         HDMI_WRITE(HDMI_VERTB1, vertb);
1331
1332         switch (state->hdmi.output_bpc) {
1333         case 12:
1334                 gcp = 6;
1335                 break;
1336         case 10:
1337                 gcp = 5;
1338                 break;
1339         case 8:
1340         default:
1341                 gcp = 0;
1342                 break;
1343         }
1344
1345         /*
1346          * YCC422 is always 36-bit and not considered deep colour so
1347          * doesn't signal in GCP.
1348          */
1349         if (state->hdmi.output_format == HDMI_COLORSPACE_YUV422) {
1350                 gcp = 0;
1351         }
1352
1353         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1354         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1355                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1356         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1357                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1358         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1359
1360         reg = HDMI_READ(HDMI_GCP_WORD_1);
1361         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1362         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1363         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
1364         reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
1365         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1366
1367         reg = HDMI_READ(HDMI_GCP_CONFIG);
1368         reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1369         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1370
1371         reg = HDMI_READ(HDMI_MISC_CONTROL);
1372         reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1373         reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1374         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1375
1376         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1377
1378         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1379
1380         drm_dev_exit(idx);
1381 }
1382
1383 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1384 {
1385         struct drm_device *drm = vc4_hdmi->connector.dev;
1386         unsigned long flags;
1387         u32 drift;
1388         int ret;
1389         int idx;
1390
1391         if (!drm_dev_enter(drm, &idx))
1392                 return;
1393
1394         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1395
1396         drift = HDMI_READ(HDMI_FIFO_CTL);
1397         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1398
1399         HDMI_WRITE(HDMI_FIFO_CTL,
1400                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1401         HDMI_WRITE(HDMI_FIFO_CTL,
1402                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1403
1404         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1405
1406         usleep_range(1000, 1100);
1407
1408         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1409
1410         HDMI_WRITE(HDMI_FIFO_CTL,
1411                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1412         HDMI_WRITE(HDMI_FIFO_CTL,
1413                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1414
1415         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1416
1417         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1418                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1419         WARN_ONCE(ret, "Timeout waiting for "
1420                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1421
1422         drm_dev_exit(idx);
1423 }
1424
1425 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1426                                                 struct drm_atomic_state *state)
1427 {
1428         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1429         struct drm_device *drm = vc4_hdmi->connector.dev;
1430         struct drm_connector *connector = &vc4_hdmi->connector;
1431         struct drm_connector_state *conn_state =
1432                 drm_atomic_get_new_connector_state(state, connector);
1433         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1434         unsigned long long tmds_char_rate = conn_state->hdmi.tmds_char_rate;
1435         unsigned long bvb_rate, hsm_rate;
1436         unsigned long flags;
1437         int ret;
1438         int idx;
1439
1440         mutex_lock(&vc4_hdmi->mutex);
1441
1442         if (!drm_dev_enter(drm, &idx))
1443                 goto out;
1444
1445         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1446         if (ret < 0) {
1447                 drm_err(drm, "Failed to retain power domain: %d\n", ret);
1448                 goto err_dev_exit;
1449         }
1450
1451         /*
1452          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1453          * be faster than pixel clock, infinitesimally faster, tested in
1454          * simulation. Otherwise, exact value is unimportant for HDMI
1455          * operation." This conflicts with bcm2835's vc4 documentation, which
1456          * states HSM's clock has to be at least 108% of the pixel clock.
1457          *
1458          * Real life tests reveal that vc4's firmware statement holds up, and
1459          * users are able to use pixel clocks closer to HSM's, namely for
1460          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1461          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1462          * 162MHz.
1463          *
1464          * Additionally, the AXI clock needs to be at least 25% of
1465          * pixel clock, but HSM ends up being the limiting factor.
1466          */
1467         hsm_rate = max_t(unsigned long,
1468                          HSM_MIN_CLOCK_FREQ,
1469                          div_u64(tmds_char_rate, 100) * 101);
1470         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1471         if (ret) {
1472                 drm_err(drm, "Failed to set HSM clock rate: %d\n", ret);
1473                 goto err_put_runtime_pm;
1474         }
1475
1476         ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1477         if (ret) {
1478                 drm_err(drm, "Failed to set pixel clock rate: %d\n", ret);
1479                 goto err_put_runtime_pm;
1480         }
1481
1482         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1483         if (ret) {
1484                 drm_err(drm, "Failed to turn on pixel clock: %d\n", ret);
1485                 goto err_put_runtime_pm;
1486         }
1487
1488         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1489
1490         if (tmds_char_rate > 297000000)
1491                 bvb_rate = 300000000;
1492         else if (tmds_char_rate > 148500000)
1493                 bvb_rate = 150000000;
1494         else
1495                 bvb_rate = 75000000;
1496
1497         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1498         if (ret) {
1499                 drm_err(drm, "Failed to set pixel bvb clock rate: %d\n", ret);
1500                 goto err_disable_pixel_clock;
1501         }
1502
1503         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1504         if (ret) {
1505                 drm_err(drm, "Failed to turn on pixel bvb clock: %d\n", ret);
1506                 goto err_disable_pixel_clock;
1507         }
1508
1509         if (vc4_hdmi->variant->phy_init)
1510                 vc4_hdmi->variant->phy_init(vc4_hdmi, conn_state);
1511
1512         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1513
1514         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1515                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1516                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1517                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1518
1519         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1520
1521         if (vc4_hdmi->variant->set_timings)
1522                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1523
1524         drm_dev_exit(idx);
1525
1526         mutex_unlock(&vc4_hdmi->mutex);
1527
1528         return;
1529
1530 err_disable_pixel_clock:
1531         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1532 err_put_runtime_pm:
1533         pm_runtime_put(&vc4_hdmi->pdev->dev);
1534 err_dev_exit:
1535         drm_dev_exit(idx);
1536 out:
1537         mutex_unlock(&vc4_hdmi->mutex);
1538         return;
1539 }
1540
1541 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1542                                              struct drm_atomic_state *state)
1543 {
1544         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1545         struct drm_device *drm = vc4_hdmi->connector.dev;
1546         struct drm_connector *connector = &vc4_hdmi->connector;
1547         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1548         struct drm_connector_state *conn_state =
1549                 drm_atomic_get_new_connector_state(state, connector);
1550         unsigned long flags;
1551         int idx;
1552
1553         mutex_lock(&vc4_hdmi->mutex);
1554
1555         if (!drm_dev_enter(drm, &idx))
1556                 goto out;
1557
1558         if (vc4_hdmi->variant->csc_setup)
1559                 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1560
1561         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1562         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1563         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1564
1565         drm_dev_exit(idx);
1566
1567 out:
1568         mutex_unlock(&vc4_hdmi->mutex);
1569 }
1570
1571 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1572                                               struct drm_atomic_state *state)
1573 {
1574         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1575         struct drm_connector *connector = &vc4_hdmi->connector;
1576         struct drm_device *drm = connector->dev;
1577         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1578         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1579         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1580         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1581         unsigned long flags;
1582         int ret;
1583         int idx;
1584
1585         mutex_lock(&vc4_hdmi->mutex);
1586
1587         if (!drm_dev_enter(drm, &idx))
1588                 goto out;
1589
1590         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1591
1592         HDMI_WRITE(HDMI_VID_CTL,
1593                    (HDMI_READ(HDMI_VID_CTL) &
1594                         ~(VC4_HD_VID_CTL_VSYNC_LOW | VC4_HD_VID_CTL_HSYNC_LOW)) |
1595                    VC4_HD_VID_CTL_ENABLE |
1596                    VC4_HD_VID_CTL_CLRRGB |
1597                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1598                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1599                    VC4_HD_VID_CTL_BLANK_INSERT_EN |
1600                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1601                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1602
1603         HDMI_WRITE(HDMI_VID_CTL,
1604                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1605
1606         if (display->is_hdmi) {
1607                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1608                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1609                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1610
1611                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1612
1613                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1614                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1615                 WARN_ONCE(ret, "Timeout waiting for "
1616                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1617         } else {
1618                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1619                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1620                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1621                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1622                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1623                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1624
1625                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1626
1627                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1628                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1629                 WARN_ONCE(ret, "Timeout waiting for "
1630                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1631         }
1632
1633         if (display->is_hdmi) {
1634                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1635
1636                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1637                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1638
1639                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1640                            VC4_HDMI_RAM_PACKET_ENABLE);
1641
1642                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1643                 vc4_hdmi->packet_ram_enabled = true;
1644
1645                 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
1646         }
1647
1648         vc4_hdmi_recenter_fifo(vc4_hdmi);
1649         vc4_hdmi_enable_scrambling(encoder);
1650
1651         drm_dev_exit(idx);
1652
1653 out:
1654         mutex_unlock(&vc4_hdmi->mutex);
1655 }
1656
1657 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1658                                              struct drm_crtc_state *crtc_state,
1659                                              struct drm_connector_state *conn_state)
1660 {
1661         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1662
1663         mutex_lock(&vc4_hdmi->mutex);
1664         drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1665                       &crtc_state->adjusted_mode);
1666         vc4_hdmi->output_bpc = conn_state->hdmi.output_bpc;
1667         vc4_hdmi->output_format = conn_state->hdmi.output_format;
1668         mutex_unlock(&vc4_hdmi->mutex);
1669 }
1670
1671 static enum drm_mode_status
1672 vc4_hdmi_connector_clock_valid(const struct drm_connector *connector,
1673                                const struct drm_display_mode *mode,
1674                                unsigned long long clock)
1675 {
1676         const struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
1677         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1678
1679         if (clock > vc4_hdmi->variant->max_pixel_clock)
1680                 return MODE_CLOCK_HIGH;
1681
1682         if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
1683                 return MODE_CLOCK_HIGH;
1684
1685         /* 4096x2160@60 is not reliable without overclocking core */
1686         if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
1687             mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
1688             drm_mode_vrefresh(mode) >= 50)
1689                 return MODE_CLOCK_HIGH;
1690
1691         return MODE_OK;
1692 }
1693
1694 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs = {
1695         .tmds_char_rate_valid   = vc4_hdmi_connector_clock_valid,
1696         .write_infoframe        = vc4_hdmi_write_infoframe,
1697 };
1698
1699 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1700 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1701
1702 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1703                                          struct drm_crtc_state *crtc_state,
1704                                          struct drm_connector_state *conn_state)
1705 {
1706         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1707         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1708         unsigned long long tmds_char_rate = mode->clock * 1000;
1709         unsigned long long tmds_bit_rate;
1710
1711         if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1712                 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1713                         /* Only try to fixup DBLCLK modes to get 480i and 576i
1714                          * working.
1715                          * A generic solution for all modes with odd horizontal
1716                          * timing values seems impossible based on trying to
1717                          * solve it for 1366x768 monitors.
1718                          */
1719                         if ((mode->hsync_start - mode->hdisplay) & 1)
1720                                 mode->hsync_start--;
1721                         if ((mode->hsync_end - mode->hsync_start) & 1)
1722                                 mode->hsync_end--;
1723                 }
1724
1725                 /* Now check whether we still have odd values remaining */
1726                 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1727                     (mode->hsync_end % 2) || (mode->htotal % 2))
1728                         return -EINVAL;
1729         }
1730
1731         /*
1732          * The 1440p@60 pixel rate is in the same range than the first
1733          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1734          * bandwidth). Slightly lower the frequency to bring it out of
1735          * the WiFi range.
1736          */
1737         tmds_bit_rate = tmds_char_rate * 10;
1738         if (vc4_hdmi->disable_wifi_frequencies &&
1739             (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1740              tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1741                 mode->clock = 238560;
1742                 tmds_char_rate = mode->clock * 1000;
1743         }
1744
1745         return 0;
1746 }
1747
1748 static enum drm_mode_status
1749 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1750                             const struct drm_display_mode *mode)
1751 {
1752         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1753
1754         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1755             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1756             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1757              (mode->hsync_end % 2) || (mode->htotal % 2)))
1758                 return MODE_H_ILLEGAL;
1759
1760         return MODE_OK;
1761 }
1762
1763 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1764         .atomic_check = vc4_hdmi_encoder_atomic_check,
1765         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1766         .mode_valid = vc4_hdmi_encoder_mode_valid,
1767 };
1768
1769 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
1770 {
1771         struct drm_device *drm = encoder->dev;
1772         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1773         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1774
1775         drm_debugfs_add_file(drm, variant->debugfs_name,
1776                              vc4_hdmi_debugfs_regs, vc4_hdmi);
1777
1778         return 0;
1779 }
1780
1781 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
1782         .late_register = vc4_hdmi_late_register,
1783 };
1784
1785 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1786 {
1787         int i;
1788         u32 channel_map = 0;
1789
1790         for (i = 0; i < 8; i++) {
1791                 if (channel_mask & BIT(i))
1792                         channel_map |= i << (3 * i);
1793         }
1794         return channel_map;
1795 }
1796
1797 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1798 {
1799         int i;
1800         u32 channel_map = 0;
1801
1802         for (i = 0; i < 8; i++) {
1803                 if (channel_mask & BIT(i))
1804                         channel_map |= i << (4 * i);
1805         }
1806         return channel_map;
1807 }
1808
1809 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1810 {
1811         struct drm_device *drm = vc4_hdmi->connector.dev;
1812         unsigned long flags;
1813         u32 hotplug;
1814         int idx;
1815
1816         if (!drm_dev_enter(drm, &idx))
1817                 return false;
1818
1819         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1820         hotplug = HDMI_READ(HDMI_HOTPLUG);
1821         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1822
1823         drm_dev_exit(idx);
1824
1825         return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1826 }
1827
1828 /* HDMI audio codec callbacks */
1829 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1830                                          unsigned int samplerate)
1831 {
1832         struct drm_device *drm = vc4_hdmi->connector.dev;
1833         u32 hsm_clock;
1834         unsigned long flags;
1835         unsigned long n, m;
1836         int idx;
1837
1838         if (!drm_dev_enter(drm, &idx))
1839                 return;
1840
1841         hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1842         rational_best_approximation(hsm_clock, samplerate,
1843                                     VC4_HD_MAI_SMP_N_MASK >>
1844                                     VC4_HD_MAI_SMP_N_SHIFT,
1845                                     (VC4_HD_MAI_SMP_M_MASK >>
1846                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1847                                     &n, &m);
1848
1849         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1850         HDMI_WRITE(HDMI_MAI_SMP,
1851                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1852                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1853         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1854
1855         drm_dev_exit(idx);
1856 }
1857
1858 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1859 {
1860         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1861         u32 n, cts;
1862         u64 tmp;
1863
1864         lockdep_assert_held(&vc4_hdmi->mutex);
1865         lockdep_assert_held(&vc4_hdmi->hw_lock);
1866
1867         n = 128 * samplerate / 1000;
1868         tmp = (u64)(mode->clock * 1000) * n;
1869         do_div(tmp, 128 * samplerate);
1870         cts = tmp;
1871
1872         HDMI_WRITE(HDMI_CRP_CFG,
1873                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1874                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1875
1876         /*
1877          * We could get slightly more accurate clocks in some cases by
1878          * providing a CTS_1 value.  The two CTS values are alternated
1879          * between based on the period fields
1880          */
1881         HDMI_WRITE(HDMI_CTS_0, cts);
1882         HDMI_WRITE(HDMI_CTS_1, cts);
1883 }
1884
1885 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1886 {
1887         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1888
1889         return snd_soc_card_get_drvdata(card);
1890 }
1891
1892 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1893 {
1894         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1895
1896         lockdep_assert_held(&vc4_hdmi->mutex);
1897
1898         /*
1899          * If the encoder is currently in DVI mode, treat the codec DAI
1900          * as missing.
1901          */
1902         if (!display->is_hdmi)
1903                 return false;
1904
1905         return true;
1906 }
1907
1908 static int vc4_hdmi_audio_startup(struct drm_connector *connector)
1909 {
1910         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
1911         struct drm_device *drm = vc4_hdmi->connector.dev;
1912         unsigned long flags;
1913         int ret = 0;
1914         int idx;
1915
1916         mutex_lock(&vc4_hdmi->mutex);
1917
1918         if (!drm_dev_enter(drm, &idx)) {
1919                 ret = -ENODEV;
1920                 goto out;
1921         }
1922
1923         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1924                 ret = -ENOTSUPP;
1925                 goto out_dev_exit;
1926         }
1927
1928         vc4_hdmi->audio.streaming = true;
1929
1930         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1931         HDMI_WRITE(HDMI_MAI_CTL,
1932                    VC4_HD_MAI_CTL_RESET |
1933                    VC4_HD_MAI_CTL_FLUSH |
1934                    VC4_HD_MAI_CTL_DLATE |
1935                    VC4_HD_MAI_CTL_ERRORE |
1936                    VC4_HD_MAI_CTL_ERRORF);
1937         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1938
1939         if (vc4_hdmi->variant->phy_rng_enable)
1940                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1941
1942 out_dev_exit:
1943         drm_dev_exit(idx);
1944 out:
1945         mutex_unlock(&vc4_hdmi->mutex);
1946
1947         return ret;
1948 }
1949
1950 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1951 {
1952         struct device *dev = &vc4_hdmi->pdev->dev;
1953         unsigned long flags;
1954         int ret;
1955
1956         lockdep_assert_held(&vc4_hdmi->mutex);
1957
1958         vc4_hdmi->audio.streaming = false;
1959         ret = vc4_hdmi_stop_packet(vc4_hdmi, HDMI_INFOFRAME_TYPE_AUDIO, false);
1960         if (ret)
1961                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1962
1963         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1964
1965         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1966         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1967         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1968
1969         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1970 }
1971
1972 static void vc4_hdmi_audio_shutdown(struct drm_connector *connector)
1973 {
1974         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
1975         struct drm_device *drm = vc4_hdmi->connector.dev;
1976         unsigned long flags;
1977         int idx;
1978
1979         mutex_lock(&vc4_hdmi->mutex);
1980
1981         if (!drm_dev_enter(drm, &idx))
1982                 goto out;
1983
1984         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1985
1986         HDMI_WRITE(HDMI_MAI_CTL,
1987                    VC4_HD_MAI_CTL_DLATE |
1988                    VC4_HD_MAI_CTL_ERRORE |
1989                    VC4_HD_MAI_CTL_ERRORF);
1990
1991         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1992
1993         if (vc4_hdmi->variant->phy_rng_disable)
1994                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1995
1996         vc4_hdmi->audio.streaming = false;
1997         vc4_hdmi_audio_reset(vc4_hdmi);
1998
1999         drm_dev_exit(idx);
2000
2001 out:
2002         mutex_unlock(&vc4_hdmi->mutex);
2003 }
2004
2005 static int sample_rate_to_mai_fmt(int samplerate)
2006 {
2007         switch (samplerate) {
2008         case 8000:
2009                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2010         case 11025:
2011                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2012         case 12000:
2013                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2014         case 16000:
2015                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2016         case 22050:
2017                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2018         case 24000:
2019                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2020         case 32000:
2021                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2022         case 44100:
2023                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2024         case 48000:
2025                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2026         case 64000:
2027                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2028         case 88200:
2029                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2030         case 96000:
2031                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2032         case 128000:
2033                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2034         case 176400:
2035                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2036         case 192000:
2037                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2038         default:
2039                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2040         }
2041 }
2042
2043 /* HDMI audio codec callbacks */
2044 static int vc4_hdmi_audio_prepare(struct drm_connector *connector,
2045                                   struct hdmi_codec_daifmt *daifmt,
2046                                   struct hdmi_codec_params *params)
2047 {
2048         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
2049         struct drm_device *drm = vc4_hdmi->connector.dev;
2050         struct vc4_dev *vc4 = to_vc4_dev(drm);
2051         unsigned int sample_rate = params->sample_rate;
2052         unsigned int channels = params->channels;
2053         unsigned long flags;
2054         u32 audio_packet_config, channel_mask;
2055         u32 channel_map;
2056         u32 mai_audio_format;
2057         u32 mai_sample_rate;
2058         int ret = 0;
2059         int idx;
2060
2061         dev_dbg(&vc4_hdmi->pdev->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2062                 sample_rate, params->sample_width, channels);
2063
2064         mutex_lock(&vc4_hdmi->mutex);
2065
2066         if (!drm_dev_enter(drm, &idx)) {
2067                 ret = -ENODEV;
2068                 goto out;
2069         }
2070
2071         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2072                 ret = -EINVAL;
2073                 goto out_dev_exit;
2074         }
2075
2076         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2077
2078         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2079         HDMI_WRITE(HDMI_MAI_CTL,
2080                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2081                    VC4_HD_MAI_CTL_WHOLSMP |
2082                    VC4_HD_MAI_CTL_CHALIGN |
2083                    VC4_HD_MAI_CTL_ENABLE);
2084
2085         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2086         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2087             params->channels == 8)
2088                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2089         else
2090                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2091         HDMI_WRITE(HDMI_MAI_FMT,
2092                    VC4_SET_FIELD(mai_sample_rate,
2093                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2094                    VC4_SET_FIELD(mai_audio_format,
2095                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2096
2097         /* The B frame identifier should match the value used by alsa-lib (8) */
2098         audio_packet_config =
2099                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2100                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2101                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2102
2103         channel_mask = GENMASK(channels - 1, 0);
2104         audio_packet_config |= VC4_SET_FIELD(channel_mask,
2105                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2106
2107         /* Set the MAI threshold */
2108         switch (vc4->gen) {
2109         case VC4_GEN_6_D:
2110                 HDMI_WRITE(HDMI_MAI_THR,
2111                            VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICHIGH) |
2112                            VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICLOW) |
2113                            VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQHIGH) |
2114                            VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQLOW));
2115                 break;
2116         case VC4_GEN_6_C:
2117         case VC4_GEN_5:
2118                 HDMI_WRITE(HDMI_MAI_THR,
2119                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
2120                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
2121                            VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) |
2122                            VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW));
2123                 break;
2124         case VC4_GEN_4:
2125                 HDMI_WRITE(HDMI_MAI_THR,
2126                            VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) |
2127                            VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) |
2128                            VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) |
2129                            VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW));
2130                 break;
2131         default:
2132                 drm_err(drm, "Unknown VC4 generation: %d", vc4->gen);
2133                 break;
2134         }
2135
2136         HDMI_WRITE(HDMI_MAI_CONFIG,
2137                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2138                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2139                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2140
2141         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2142         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2143         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2144
2145         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2146
2147         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2148
2149         ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector,
2150                                                                       &params->cea);
2151         if (ret)
2152                 goto out_dev_exit;
2153
2154 out_dev_exit:
2155         drm_dev_exit(idx);
2156 out:
2157         mutex_unlock(&vc4_hdmi->mutex);
2158
2159         return ret;
2160 }
2161
2162 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2163         .name = "vc4-hdmi-cpu-dai-component",
2164         .legacy_dai_naming = 1,
2165 };
2166
2167 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2168 {
2169         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2170
2171         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2172
2173         return 0;
2174 }
2175
2176 static const struct snd_soc_dai_ops vc4_snd_dai_ops = {
2177         .probe  = vc4_hdmi_audio_cpu_dai_probe,
2178 };
2179
2180 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2181         .name = "vc4-hdmi-cpu-dai",
2182         .ops = &vc4_snd_dai_ops,
2183         .playback = {
2184                 .stream_name = "Playback",
2185                 .channels_min = 1,
2186                 .channels_max = 8,
2187                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2188                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2189                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2190                          SNDRV_PCM_RATE_192000,
2191                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2192         },
2193 };
2194
2195 static const struct snd_dmaengine_pcm_config pcm_conf = {
2196         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2197         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2198 };
2199
2200 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs = {
2201         .startup = vc4_hdmi_audio_startup,
2202         .prepare = vc4_hdmi_audio_prepare,
2203         .shutdown = vc4_hdmi_audio_shutdown,
2204 };
2205
2206 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2207 {
2208         const struct vc4_hdmi_register *mai_data =
2209                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2210         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2211         struct snd_soc_card *card = &vc4_hdmi->audio.card;
2212         struct device *dev = &vc4_hdmi->pdev->dev;
2213         const __be32 *addr;
2214         int index, len;
2215         int ret;
2216
2217         /*
2218          * ASoC makes it a bit hard to retrieve a pointer to the
2219          * vc4_hdmi structure. Registering the card will overwrite our
2220          * device drvdata with a pointer to the snd_soc_card structure,
2221          * which can then be used to retrieve whatever drvdata we want
2222          * to associate.
2223          *
2224          * However, that doesn't fly in the case where we wouldn't
2225          * register an ASoC card (because of an old DT that is missing
2226          * the dmas properties for example), then the card isn't
2227          * registered and the device drvdata wouldn't be set.
2228          *
2229          * We can deal with both cases by making sure a snd_soc_card
2230          * pointer and a vc4_hdmi structure are pointing to the same
2231          * memory address, so we can treat them indistinctly without any
2232          * issue.
2233          */
2234         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2235         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2236
2237         if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2238                 dev_warn(dev,
2239                          "'dmas' DT property is missing or empty, no HDMI audio\n");
2240                 return 0;
2241         }
2242
2243         if (mai_data->reg != VC4_HD) {
2244                 WARN_ONCE(true, "MAI isn't in the HD block\n");
2245                 return -EINVAL;
2246         }
2247
2248         /*
2249          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2250          * the bus address specified in the DT, because the physical address
2251          * (the one returned by platform_get_resource()) is not appropriate
2252          * for DMA transfers.
2253          * This VC/MMU should probably be exposed to avoid this kind of hacks.
2254          */
2255         index = of_property_match_string(dev->of_node, "reg-names", "hd");
2256         /* Before BCM2711, we don't have a named register range */
2257         if (index < 0)
2258                 index = 1;
2259
2260         addr = of_get_address(dev->of_node, index, NULL, NULL);
2261         if (!addr)
2262                 return -EINVAL;
2263
2264         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2265         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2266         vc4_hdmi->audio.dma_data.maxburst = 2;
2267
2268         /*
2269          * NOTE: Strictly speaking, we should probably use a DRM-managed
2270          * registration there to avoid removing all the audio components
2271          * by the time the driver doesn't have any user anymore.
2272          *
2273          * However, the ASoC core uses a number of devm_kzalloc calls
2274          * when registering, even when using non-device-managed
2275          * functions (such as in snd_soc_register_component()).
2276          *
2277          * If we call snd_soc_unregister_component() in a DRM-managed
2278          * action, the device-managed actions have already been executed
2279          * and thus we would access memory that has been freed.
2280          *
2281          * Using device-managed hooks here probably leaves us open to a
2282          * bunch of issues if userspace still has a handle on the ALSA
2283          * device when the device is removed. However, this is mitigated
2284          * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2285          * path to prevent the access to the device resources if it
2286          * isn't there anymore.
2287          *
2288          * Then, the vc4_hdmi structure is DRM-managed and thus only
2289          * freed whenever the last user has closed the DRM device file.
2290          * It should thus outlive ALSA in most situations.
2291          */
2292         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2293         if (ret) {
2294                 dev_err(dev, "Could not register PCM component: %d\n", ret);
2295                 return ret;
2296         }
2297
2298         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2299                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
2300         if (ret) {
2301                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2302                 return ret;
2303         }
2304
2305         dai_link->cpus          = &vc4_hdmi->audio.cpu;
2306         dai_link->codecs        = &vc4_hdmi->audio.codec;
2307         dai_link->platforms     = &vc4_hdmi->audio.platform;
2308
2309         dai_link->num_cpus      = 1;
2310         dai_link->num_codecs    = 1;
2311         dai_link->num_platforms = 1;
2312
2313         dai_link->name = "MAI";
2314         dai_link->stream_name = "MAI PCM";
2315         dai_link->codecs->dai_name = "i2s-hifi";
2316         dai_link->cpus->dai_name = dev_name(dev);
2317         dai_link->codecs->name = dev_name(&vc4_hdmi->connector.hdmi_audio.codec_pdev->dev);
2318         dai_link->platforms->name = dev_name(dev);
2319
2320         card->dai_link = dai_link;
2321         card->num_links = 1;
2322         card->name = vc4_hdmi->variant->card_name;
2323         card->driver_name = "vc4-hdmi";
2324         card->dev = dev;
2325         card->owner = THIS_MODULE;
2326
2327         /*
2328          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2329          * stores a pointer to the snd card object in dev->driver_data. This
2330          * means we cannot use it for something else. The hdmi back-pointer is
2331          * now stored in card->drvdata and should be retrieved with
2332          * snd_soc_card_get_drvdata() if needed.
2333          */
2334         snd_soc_card_set_drvdata(card, vc4_hdmi);
2335         ret = devm_snd_soc_register_card(dev, card);
2336         if (ret)
2337                 dev_err_probe(dev, ret, "Could not register sound card\n");
2338
2339         return ret;
2340
2341 }
2342
2343 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2344 {
2345         struct vc4_hdmi *vc4_hdmi = priv;
2346         struct drm_connector *connector = &vc4_hdmi->connector;
2347         struct drm_device *dev = connector->dev;
2348
2349         if (dev && dev->registered)
2350                 drm_connector_helper_hpd_irq_event(connector);
2351
2352         return IRQ_HANDLED;
2353 }
2354
2355 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2356 {
2357         struct drm_connector *connector = &vc4_hdmi->connector;
2358         struct platform_device *pdev = vc4_hdmi->pdev;
2359         int ret;
2360
2361         if (vc4_hdmi->variant->external_irq_controller) {
2362                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2363                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2364
2365                 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2366                                                 NULL,
2367                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2368                                                 "vc4 hdmi hpd connected", vc4_hdmi);
2369                 if (ret)
2370                         return ret;
2371
2372                 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2373                                                 NULL,
2374                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2375                                                 "vc4 hdmi hpd disconnected", vc4_hdmi);
2376                 if (ret)
2377                         return ret;
2378
2379                 connector->polled = DRM_CONNECTOR_POLL_HPD;
2380         }
2381
2382         return 0;
2383 }
2384
2385 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2386 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2387 {
2388         struct vc4_hdmi *vc4_hdmi = priv;
2389
2390         if (vc4_hdmi->cec_rx_msg.len)
2391                 cec_received_msg(vc4_hdmi->cec_adap,
2392                                  &vc4_hdmi->cec_rx_msg);
2393
2394         return IRQ_HANDLED;
2395 }
2396
2397 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2398 {
2399         struct vc4_hdmi *vc4_hdmi = priv;
2400
2401         if (vc4_hdmi->cec_tx_ok) {
2402                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2403                                   0, 0, 0, 0);
2404         } else {
2405                 /*
2406                  * This CEC implementation makes 1 retry, so if we
2407                  * get a NACK, then that means it made 2 attempts.
2408                  */
2409                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2410                                   0, 2, 0, 0);
2411         }
2412         return IRQ_HANDLED;
2413 }
2414
2415 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2416 {
2417         struct vc4_hdmi *vc4_hdmi = priv;
2418         irqreturn_t ret;
2419
2420         if (vc4_hdmi->cec_irq_was_rx)
2421                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2422         else
2423                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2424
2425         return ret;
2426 }
2427
2428 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2429 {
2430         struct drm_device *dev = vc4_hdmi->connector.dev;
2431         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2432         unsigned int i;
2433
2434         lockdep_assert_held(&vc4_hdmi->hw_lock);
2435
2436         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2437                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2438
2439         if (msg->len > 16) {
2440                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2441                 return;
2442         }
2443
2444         for (i = 0; i < msg->len; i += 4) {
2445                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2446
2447                 msg->msg[i] = val & 0xff;
2448                 msg->msg[i + 1] = (val >> 8) & 0xff;
2449                 msg->msg[i + 2] = (val >> 16) & 0xff;
2450                 msg->msg[i + 3] = (val >> 24) & 0xff;
2451         }
2452 }
2453
2454 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2455 {
2456         u32 cntrl1;
2457
2458         /*
2459          * We don't need to protect the register access using
2460          * drm_dev_enter() there because the interrupt handler lifetime
2461          * is tied to the device itself, and not to the DRM device.
2462          *
2463          * So when the device will be gone, one of the first thing we
2464          * will be doing will be to unregister the interrupt handler,
2465          * and then unregister the DRM device. drm_dev_enter() would
2466          * thus always succeed if we are here.
2467          */
2468
2469         lockdep_assert_held(&vc4_hdmi->hw_lock);
2470
2471         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2472         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2473         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2474         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2475
2476         return IRQ_WAKE_THREAD;
2477 }
2478
2479 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2480 {
2481         struct vc4_hdmi *vc4_hdmi = priv;
2482         irqreturn_t ret;
2483
2484         spin_lock(&vc4_hdmi->hw_lock);
2485         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2486         spin_unlock(&vc4_hdmi->hw_lock);
2487
2488         return ret;
2489 }
2490
2491 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2492 {
2493         u32 cntrl1;
2494
2495         lockdep_assert_held(&vc4_hdmi->hw_lock);
2496
2497         /*
2498          * We don't need to protect the register access using
2499          * drm_dev_enter() there because the interrupt handler lifetime
2500          * is tied to the device itself, and not to the DRM device.
2501          *
2502          * So when the device will be gone, one of the first thing we
2503          * will be doing will be to unregister the interrupt handler,
2504          * and then unregister the DRM device. drm_dev_enter() would
2505          * thus always succeed if we are here.
2506          */
2507
2508         vc4_hdmi->cec_rx_msg.len = 0;
2509         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2510         vc4_cec_read_msg(vc4_hdmi, cntrl1);
2511         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2512         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2513         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2514
2515         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2516
2517         return IRQ_WAKE_THREAD;
2518 }
2519
2520 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2521 {
2522         struct vc4_hdmi *vc4_hdmi = priv;
2523         irqreturn_t ret;
2524
2525         spin_lock(&vc4_hdmi->hw_lock);
2526         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2527         spin_unlock(&vc4_hdmi->hw_lock);
2528
2529         return ret;
2530 }
2531
2532 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2533 {
2534         struct vc4_hdmi *vc4_hdmi = priv;
2535         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2536         irqreturn_t ret;
2537         u32 cntrl5;
2538
2539         /*
2540          * We don't need to protect the register access using
2541          * drm_dev_enter() there because the interrupt handler lifetime
2542          * is tied to the device itself, and not to the DRM device.
2543          *
2544          * So when the device will be gone, one of the first thing we
2545          * will be doing will be to unregister the interrupt handler,
2546          * and then unregister the DRM device. drm_dev_enter() would
2547          * thus always succeed if we are here.
2548          */
2549
2550         if (!(stat & VC4_HDMI_CPU_CEC))
2551                 return IRQ_NONE;
2552
2553         spin_lock(&vc4_hdmi->hw_lock);
2554         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2555         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2556         if (vc4_hdmi->cec_irq_was_rx)
2557                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2558         else
2559                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2560
2561         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2562         spin_unlock(&vc4_hdmi->hw_lock);
2563
2564         return ret;
2565 }
2566
2567 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2568 {
2569         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2570         struct drm_device *drm = vc4_hdmi->connector.dev;
2571         /* clock period in microseconds */
2572         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2573         unsigned long flags;
2574         u32 val;
2575         int ret;
2576         int idx;
2577
2578         if (!drm_dev_enter(drm, &idx))
2579                 /*
2580                  * We can't return an error code, because the CEC
2581                  * framework will emit WARN_ON messages at unbind
2582                  * otherwise.
2583                  */
2584                 return 0;
2585
2586         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2587         if (ret) {
2588                 drm_dev_exit(idx);
2589                 return ret;
2590         }
2591
2592         mutex_lock(&vc4_hdmi->mutex);
2593
2594         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2595
2596         val = HDMI_READ(HDMI_CEC_CNTRL_5);
2597         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2598                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2599                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2600         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2601                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2602
2603         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2604                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2605         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2606         HDMI_WRITE(HDMI_CEC_CNTRL_2,
2607                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2608                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2609                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2610                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2611                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2612         HDMI_WRITE(HDMI_CEC_CNTRL_3,
2613                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2614                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2615                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2616                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2617         HDMI_WRITE(HDMI_CEC_CNTRL_4,
2618                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2619                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2620                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2621                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2622
2623         if (!vc4_hdmi->variant->external_irq_controller)
2624                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2625
2626         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2627
2628         mutex_unlock(&vc4_hdmi->mutex);
2629         drm_dev_exit(idx);
2630
2631         return 0;
2632 }
2633
2634 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2635 {
2636         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2637         struct drm_device *drm = vc4_hdmi->connector.dev;
2638         unsigned long flags;
2639         int idx;
2640
2641         if (!drm_dev_enter(drm, &idx))
2642                 /*
2643                  * We can't return an error code, because the CEC
2644                  * framework will emit WARN_ON messages at unbind
2645                  * otherwise.
2646                  */
2647                 return 0;
2648
2649         mutex_lock(&vc4_hdmi->mutex);
2650
2651         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2652
2653         if (!vc4_hdmi->variant->external_irq_controller)
2654                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2655
2656         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2657                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2658
2659         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2660
2661         mutex_unlock(&vc4_hdmi->mutex);
2662
2663         pm_runtime_put(&vc4_hdmi->pdev->dev);
2664
2665         drm_dev_exit(idx);
2666
2667         return 0;
2668 }
2669
2670 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2671 {
2672         if (enable)
2673                 return vc4_hdmi_cec_enable(adap);
2674         else
2675                 return vc4_hdmi_cec_disable(adap);
2676 }
2677
2678 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2679 {
2680         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2681         struct drm_device *drm = vc4_hdmi->connector.dev;
2682         unsigned long flags;
2683         int idx;
2684
2685         if (!drm_dev_enter(drm, &idx))
2686                 /*
2687                  * We can't return an error code, because the CEC
2688                  * framework will emit WARN_ON messages at unbind
2689                  * otherwise.
2690                  */
2691                 return 0;
2692
2693         mutex_lock(&vc4_hdmi->mutex);
2694         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2695         HDMI_WRITE(HDMI_CEC_CNTRL_1,
2696                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2697                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2698         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2699         mutex_unlock(&vc4_hdmi->mutex);
2700
2701         drm_dev_exit(idx);
2702
2703         return 0;
2704 }
2705
2706 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2707                                       u32 signal_free_time, struct cec_msg *msg)
2708 {
2709         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2710         struct drm_device *dev = vc4_hdmi->connector.dev;
2711         unsigned long flags;
2712         u32 val;
2713         unsigned int i;
2714         int idx;
2715
2716         if (!drm_dev_enter(dev, &idx))
2717                 return -ENODEV;
2718
2719         if (msg->len > 16) {
2720                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2721                 drm_dev_exit(idx);
2722                 return -ENOMEM;
2723         }
2724
2725         mutex_lock(&vc4_hdmi->mutex);
2726
2727         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2728
2729         for (i = 0; i < msg->len; i += 4)
2730                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2731                            (msg->msg[i]) |
2732                            (msg->msg[i + 1] << 8) |
2733                            (msg->msg[i + 2] << 16) |
2734                            (msg->msg[i + 3] << 24));
2735
2736         val = HDMI_READ(HDMI_CEC_CNTRL_1);
2737         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2738         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2739         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2740         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2741         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2742
2743         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2744
2745         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2746         mutex_unlock(&vc4_hdmi->mutex);
2747         drm_dev_exit(idx);
2748
2749         return 0;
2750 }
2751
2752 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2753         .adap_enable = vc4_hdmi_cec_adap_enable,
2754         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2755         .adap_transmit = vc4_hdmi_cec_adap_transmit,
2756 };
2757
2758 static void vc4_hdmi_cec_release(void *ptr)
2759 {
2760         struct vc4_hdmi *vc4_hdmi = ptr;
2761
2762         cec_unregister_adapter(vc4_hdmi->cec_adap);
2763         vc4_hdmi->cec_adap = NULL;
2764 }
2765
2766 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2767 {
2768         struct cec_connector_info conn_info;
2769         struct platform_device *pdev = vc4_hdmi->pdev;
2770         struct device *dev = &pdev->dev;
2771         int ret;
2772
2773         if (!of_property_present(dev->of_node, "interrupts")) {
2774                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2775                 return 0;
2776         }
2777
2778         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2779                                                   vc4_hdmi,
2780                                                   vc4_hdmi->variant->card_name,
2781                                                   CEC_CAP_DEFAULTS |
2782                                                   CEC_CAP_CONNECTOR_INFO, 1);
2783         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2784         if (ret < 0)
2785                 return ret;
2786
2787         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2788         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2789
2790         if (vc4_hdmi->variant->external_irq_controller) {
2791                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
2792                                                 vc4_cec_irq_handler_rx_bare,
2793                                                 vc4_cec_irq_handler_rx_thread, 0,
2794                                                 "vc4 hdmi cec rx", vc4_hdmi);
2795                 if (ret)
2796                         goto err_delete_cec_adap;
2797
2798                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
2799                                                 vc4_cec_irq_handler_tx_bare,
2800                                                 vc4_cec_irq_handler_tx_thread, 0,
2801                                                 "vc4 hdmi cec tx", vc4_hdmi);
2802                 if (ret)
2803                         goto err_delete_cec_adap;
2804         } else {
2805                 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
2806                                                 vc4_cec_irq_handler,
2807                                                 vc4_cec_irq_handler_thread, 0,
2808                                                 "vc4 hdmi cec", vc4_hdmi);
2809                 if (ret)
2810                         goto err_delete_cec_adap;
2811         }
2812
2813         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2814         if (ret < 0)
2815                 goto err_delete_cec_adap;
2816
2817         /*
2818          * NOTE: Strictly speaking, we should probably use a DRM-managed
2819          * registration there to avoid removing the CEC adapter by the
2820          * time the DRM driver doesn't have any user anymore.
2821          *
2822          * However, the CEC framework already cleans up the CEC adapter
2823          * only when the last user has closed its file descriptor, so we
2824          * don't need to handle it in DRM.
2825          *
2826          * By the time the device-managed hook is executed, we will give
2827          * up our reference to the CEC adapter and therefore don't
2828          * really care when it's actually freed.
2829          *
2830          * There's still a problematic sequence: if we unregister our
2831          * CEC adapter, but the userspace keeps a handle on the CEC
2832          * adapter but not the DRM device for some reason. In such a
2833          * case, our vc4_hdmi structure will be freed, but the
2834          * cec_adapter structure will have a dangling pointer to what
2835          * used to be our HDMI controller. If we get a CEC call at that
2836          * moment, we could end up with a use-after-free. Fortunately,
2837          * the CEC framework already handles this too, by calling
2838          * cec_is_registered() in cec_ioctl() and cec_poll().
2839          */
2840         ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
2841         if (ret)
2842                 return ret;
2843
2844         return 0;
2845
2846 err_delete_cec_adap:
2847         cec_delete_adapter(vc4_hdmi->cec_adap);
2848
2849         return ret;
2850 }
2851 #else
2852 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2853 {
2854         return 0;
2855 }
2856 #endif
2857
2858 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
2859 {
2860         struct debugfs_reg32 *regs = ptr;
2861
2862         kfree(regs);
2863 }
2864
2865 static int vc4_hdmi_build_regset(struct drm_device *drm,
2866                                  struct vc4_hdmi *vc4_hdmi,
2867                                  struct debugfs_regset32 *regset,
2868                                  enum vc4_hdmi_regs reg)
2869 {
2870         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2871         struct debugfs_reg32 *regs, *new_regs;
2872         unsigned int count = 0;
2873         unsigned int i;
2874         int ret;
2875
2876         regs = kcalloc(variant->num_registers, sizeof(*regs),
2877                        GFP_KERNEL);
2878         if (!regs)
2879                 return -ENOMEM;
2880
2881         for (i = 0; i < variant->num_registers; i++) {
2882                 const struct vc4_hdmi_register *field = &variant->registers[i];
2883
2884                 if (field->reg != reg)
2885                         continue;
2886
2887                 regs[count].name = field->name;
2888                 regs[count].offset = field->offset;
2889                 count++;
2890         }
2891
2892         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2893         if (!new_regs)
2894                 return -ENOMEM;
2895
2896         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2897         regset->regs = new_regs;
2898         regset->nregs = count;
2899
2900         ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
2901         if (ret)
2902                 return ret;
2903
2904         return 0;
2905 }
2906
2907 static int vc4_hdmi_init_resources(struct drm_device *drm,
2908                                    struct vc4_hdmi *vc4_hdmi)
2909 {
2910         struct platform_device *pdev = vc4_hdmi->pdev;
2911         struct device *dev = &pdev->dev;
2912         int ret;
2913
2914         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2915         if (IS_ERR(vc4_hdmi->hdmicore_regs))
2916                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2917
2918         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2919         if (IS_ERR(vc4_hdmi->hd_regs))
2920                 return PTR_ERR(vc4_hdmi->hd_regs);
2921
2922         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2923         if (ret)
2924                 return ret;
2925
2926         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2927         if (ret)
2928                 return ret;
2929
2930         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2931         if (IS_ERR(vc4_hdmi->pixel_clock)) {
2932                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2933                 if (ret != -EPROBE_DEFER)
2934                         drm_err(drm, "Failed to get pixel clock\n");
2935                 return ret;
2936         }
2937
2938         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2939         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2940                 drm_err(drm, "Failed to get HDMI state machine clock\n");
2941                 return PTR_ERR(vc4_hdmi->hsm_clock);
2942         }
2943         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2944         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2945
2946         return 0;
2947 }
2948
2949 static int vc5_hdmi_init_resources(struct drm_device *drm,
2950                                    struct vc4_hdmi *vc4_hdmi)
2951 {
2952         struct platform_device *pdev = vc4_hdmi->pdev;
2953         struct device *dev = &pdev->dev;
2954         struct resource *res;
2955         int ret;
2956
2957         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2958         if (!res)
2959                 return -ENODEV;
2960
2961         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2962                                                resource_size(res));
2963         if (!vc4_hdmi->hdmicore_regs)
2964                 return -ENOMEM;
2965
2966         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2967         if (!res)
2968                 return -ENODEV;
2969
2970         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2971         if (!vc4_hdmi->hd_regs)
2972                 return -ENOMEM;
2973
2974         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2975         if (!res)
2976                 return -ENODEV;
2977
2978         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2979         if (!vc4_hdmi->cec_regs)
2980                 return -ENOMEM;
2981
2982         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2983         if (!res)
2984                 return -ENODEV;
2985
2986         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2987         if (!vc4_hdmi->csc_regs)
2988                 return -ENOMEM;
2989
2990         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2991         if (!res)
2992                 return -ENODEV;
2993
2994         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2995         if (!vc4_hdmi->dvp_regs)
2996                 return -ENOMEM;
2997
2998         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2999         if (!res)
3000                 return -ENODEV;
3001
3002         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3003         if (!vc4_hdmi->phy_regs)
3004                 return -ENOMEM;
3005
3006         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3007         if (!res)
3008                 return -ENODEV;
3009
3010         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3011         if (!vc4_hdmi->ram_regs)
3012                 return -ENOMEM;
3013
3014         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3015         if (!res)
3016                 return -ENODEV;
3017
3018         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3019         if (!vc4_hdmi->rm_regs)
3020                 return -ENOMEM;
3021
3022         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3023         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3024                 drm_err(drm, "Failed to get HDMI state machine clock\n");
3025                 return PTR_ERR(vc4_hdmi->hsm_clock);
3026         }
3027
3028         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3029         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3030                 drm_err(drm, "Failed to get pixel bvb clock\n");
3031                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3032         }
3033
3034         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3035         if (IS_ERR(vc4_hdmi->audio_clock)) {
3036                 drm_err(drm, "Failed to get audio clock\n");
3037                 return PTR_ERR(vc4_hdmi->audio_clock);
3038         }
3039
3040         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3041         if (IS_ERR(vc4_hdmi->cec_clock)) {
3042                 drm_err(drm, "Failed to get CEC clock\n");
3043                 return PTR_ERR(vc4_hdmi->cec_clock);
3044         }
3045
3046         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3047         if (IS_ERR(vc4_hdmi->reset)) {
3048                 drm_err(drm, "Failed to get HDMI reset line\n");
3049                 return PTR_ERR(vc4_hdmi->reset);
3050         }
3051
3052         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3053         if (ret)
3054                 return ret;
3055
3056         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3057         if (ret)
3058                 return ret;
3059
3060         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3061         if (ret)
3062                 return ret;
3063
3064         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3065         if (ret)
3066                 return ret;
3067
3068         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3069         if (ret)
3070                 return ret;
3071
3072         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3073         if (ret)
3074                 return ret;
3075
3076         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3077         if (ret)
3078                 return ret;
3079
3080         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3081         if (ret)
3082                 return ret;
3083
3084         return 0;
3085 }
3086
3087 static int vc4_hdmi_runtime_suspend(struct device *dev)
3088 {
3089         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3090
3091         clk_disable_unprepare(vc4_hdmi->audio_clock);
3092         clk_disable_unprepare(vc4_hdmi->hsm_clock);
3093
3094         return 0;
3095 }
3096
3097 static int vc4_hdmi_runtime_resume(struct device *dev)
3098 {
3099         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3100         unsigned long __maybe_unused flags;
3101         u32 __maybe_unused value;
3102         unsigned long rate;
3103         int ret;
3104
3105         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3106         if (ret)
3107                 return ret;
3108
3109         /*
3110          * Whenever the RaspberryPi boots without an HDMI monitor
3111          * plugged in, the firmware won't have initialized the HSM clock
3112          * rate and it will be reported as 0.
3113          *
3114          * If we try to access a register of the controller in such a
3115          * case, it will lead to a silent CPU stall. Let's make sure we
3116          * prevent such a case.
3117          */
3118         rate = clk_get_rate(vc4_hdmi->hsm_clock);
3119         if (!rate) {
3120                 ret = -EINVAL;
3121                 goto err_disable_clk;
3122         }
3123
3124         ret = clk_prepare_enable(vc4_hdmi->audio_clock);
3125         if (ret)
3126                 goto err_disable_clk;
3127
3128         if (vc4_hdmi->variant->reset)
3129                 vc4_hdmi->variant->reset(vc4_hdmi);
3130
3131 #ifdef CONFIG_DRM_VC4_HDMI_CEC
3132         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3133         value = HDMI_READ(HDMI_CEC_CNTRL_1);
3134         /* Set the logical address to Unregistered */
3135         value |= VC4_HDMI_CEC_ADDR_MASK;
3136         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3137         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3138
3139         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3140
3141         if (!vc4_hdmi->variant->external_irq_controller) {
3142                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3143                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3144                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3145         }
3146 #endif
3147
3148         return 0;
3149
3150 err_disable_clk:
3151         clk_disable_unprepare(vc4_hdmi->hsm_clock);
3152         return ret;
3153 }
3154
3155 static void vc4_hdmi_put_ddc_device(void *ptr)
3156 {
3157         struct vc4_hdmi *vc4_hdmi = ptr;
3158
3159         put_device(&vc4_hdmi->ddc->dev);
3160 }
3161
3162 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3163 {
3164         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3165         struct platform_device *pdev = to_platform_device(dev);
3166         struct drm_device *drm = dev_get_drvdata(master);
3167         struct vc4_hdmi *vc4_hdmi;
3168         struct drm_encoder *encoder;
3169         struct device_node *ddc_node;
3170         int ret;
3171
3172         vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3173         if (!vc4_hdmi)
3174                 return -ENOMEM;
3175
3176         ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3177         if (ret)
3178                 return ret;
3179
3180         spin_lock_init(&vc4_hdmi->hw_lock);
3181         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3182
3183         dev_set_drvdata(dev, vc4_hdmi);
3184         encoder = &vc4_hdmi->encoder.base;
3185         vc4_hdmi->encoder.type = variant->encoder_type;
3186         vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3187         vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3188         vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3189         vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3190         vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3191         vc4_hdmi->pdev = pdev;
3192         vc4_hdmi->variant = variant;
3193
3194         /*
3195          * Since we don't know the state of the controller and its
3196          * display (if any), let's assume it's always enabled.
3197          * vc4_hdmi_disable_scrambling() will thus run at boot, make
3198          * sure it's disabled, and avoid any inconsistency.
3199          */
3200         if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3201                 vc4_hdmi->scdc_enabled = true;
3202
3203         ret = variant->init_resources(drm, vc4_hdmi);
3204         if (ret)
3205                 return ret;
3206
3207         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3208         if (!ddc_node) {
3209                 drm_err(drm, "Failed to find ddc node in device tree\n");
3210                 return -ENODEV;
3211         }
3212
3213         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3214         of_node_put(ddc_node);
3215         if (!vc4_hdmi->ddc) {
3216                 drm_err(drm, "Failed to get ddc i2c adapter by node\n");
3217                 return -EPROBE_DEFER;
3218         }
3219
3220         ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3221         if (ret)
3222                 return ret;
3223
3224         /* Only use the GPIO HPD pin if present in the DT, otherwise
3225          * we'll use the HDMI core's register.
3226          */
3227         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3228         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3229                 return PTR_ERR(vc4_hdmi->hpd_gpio);
3230         }
3231
3232         vc4_hdmi->disable_wifi_frequencies =
3233                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3234
3235         ret = devm_pm_runtime_enable(dev);
3236         if (ret)
3237                 return ret;
3238
3239         /*
3240          *  We need to have the device powered up at this point to call
3241          *  our reset hook and for the CEC init.
3242          */
3243         ret = pm_runtime_resume_and_get(dev);
3244         if (ret)
3245                 return ret;
3246
3247         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3248              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1") ||
3249              of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi0") ||
3250              of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi1")) &&
3251             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3252                 clk_prepare_enable(vc4_hdmi->pixel_clock);
3253                 clk_prepare_enable(vc4_hdmi->hsm_clock);
3254                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3255         }
3256
3257         ret = drmm_encoder_init(drm, encoder,
3258                                 &vc4_hdmi_encoder_funcs,
3259                                 DRM_MODE_ENCODER_TMDS,
3260                                 NULL);
3261         if (ret)
3262                 goto err_put_runtime_pm;
3263
3264         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3265
3266         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3267         if (ret)
3268                 goto err_put_runtime_pm;
3269
3270         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3271         if (ret)
3272                 goto err_put_runtime_pm;
3273
3274         ret = vc4_hdmi_cec_init(vc4_hdmi);
3275         if (ret)
3276                 goto err_put_runtime_pm;
3277
3278         ret = vc4_hdmi_audio_init(vc4_hdmi);
3279         if (ret)
3280                 goto err_put_runtime_pm;
3281
3282         pm_runtime_put_sync(dev);
3283
3284         return 0;
3285
3286 err_put_runtime_pm:
3287         pm_runtime_put_sync(dev);
3288
3289         return ret;
3290 }
3291
3292 static const struct component_ops vc4_hdmi_ops = {
3293         .bind   = vc4_hdmi_bind,
3294 };
3295
3296 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3297 {
3298         return component_add(&pdev->dev, &vc4_hdmi_ops);
3299 }
3300
3301 static void vc4_hdmi_dev_remove(struct platform_device *pdev)
3302 {
3303         component_del(&pdev->dev, &vc4_hdmi_ops);
3304 }
3305
3306 static const struct vc4_hdmi_variant bcm2835_variant = {
3307         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3308         .debugfs_name           = "hdmi_regs",
3309         .card_name              = "vc4-hdmi",
3310         .max_pixel_clock        = 162000000,
3311         .registers              = vc4_hdmi_fields,
3312         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
3313
3314         .init_resources         = vc4_hdmi_init_resources,
3315         .csc_setup              = vc4_hdmi_csc_setup,
3316         .reset                  = vc4_hdmi_reset,
3317         .set_timings            = vc4_hdmi_set_timings,
3318         .phy_init               = vc4_hdmi_phy_init,
3319         .phy_disable            = vc4_hdmi_phy_disable,
3320         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
3321         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
3322         .channel_map            = vc4_hdmi_channel_map,
3323         .supports_hdr           = false,
3324 };
3325
3326 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3327         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3328         .debugfs_name           = "hdmi0_regs",
3329         .card_name              = "vc4-hdmi-0",
3330         .max_pixel_clock        = 600000000,
3331         .registers              = vc5_hdmi_hdmi0_fields,
3332         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3333         .phy_lane_mapping       = {
3334                 PHY_LANE_0,
3335                 PHY_LANE_1,
3336                 PHY_LANE_2,
3337                 PHY_LANE_CK,
3338         },
3339         .unsupported_odd_h_timings      = true,
3340         .external_irq_controller        = true,
3341
3342         .init_resources         = vc5_hdmi_init_resources,
3343         .csc_setup              = vc5_hdmi_csc_setup,
3344         .reset                  = vc5_hdmi_reset,
3345         .set_timings            = vc5_hdmi_set_timings,
3346         .phy_init               = vc5_hdmi_phy_init,
3347         .phy_disable            = vc5_hdmi_phy_disable,
3348         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3349         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3350         .channel_map            = vc5_hdmi_channel_map,
3351         .supports_hdr           = true,
3352         .hp_detect              = vc5_hdmi_hp_detect,
3353 };
3354
3355 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3356         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
3357         .debugfs_name           = "hdmi1_regs",
3358         .card_name              = "vc4-hdmi-1",
3359         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
3360         .registers              = vc5_hdmi_hdmi1_fields,
3361         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3362         .phy_lane_mapping       = {
3363                 PHY_LANE_1,
3364                 PHY_LANE_0,
3365                 PHY_LANE_CK,
3366                 PHY_LANE_2,
3367         },
3368         .unsupported_odd_h_timings      = true,
3369         .external_irq_controller        = true,
3370
3371         .init_resources         = vc5_hdmi_init_resources,
3372         .csc_setup              = vc5_hdmi_csc_setup,
3373         .reset                  = vc5_hdmi_reset,
3374         .set_timings            = vc5_hdmi_set_timings,
3375         .phy_init               = vc5_hdmi_phy_init,
3376         .phy_disable            = vc5_hdmi_phy_disable,
3377         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3378         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3379         .channel_map            = vc5_hdmi_channel_map,
3380         .supports_hdr           = true,
3381         .hp_detect              = vc5_hdmi_hp_detect,
3382 };
3383
3384 static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = {
3385         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3386         .debugfs_name           = "hdmi0_regs",
3387         .card_name              = "vc4-hdmi-0",
3388         .max_pixel_clock        = 600000000,
3389         .registers              = vc6_hdmi_hdmi0_fields,
3390         .num_registers          = ARRAY_SIZE(vc6_hdmi_hdmi0_fields),
3391         .phy_lane_mapping       = {
3392                 PHY_LANE_0,
3393                 PHY_LANE_1,
3394                 PHY_LANE_2,
3395                 PHY_LANE_CK,
3396         },
3397         .unsupported_odd_h_timings      = false,
3398         .external_irq_controller        = true,
3399
3400         .init_resources         = vc5_hdmi_init_resources,
3401         .csc_setup              = vc5_hdmi_csc_setup,
3402         .reset                  = vc5_hdmi_reset,
3403         .set_timings            = vc5_hdmi_set_timings,
3404         .phy_init               = vc6_hdmi_phy_init,
3405         .phy_disable            = vc6_hdmi_phy_disable,
3406         .channel_map            = vc5_hdmi_channel_map,
3407         .supports_hdr           = true,
3408         .hp_detect              = vc5_hdmi_hp_detect,
3409 };
3410
3411 static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = {
3412         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
3413         .debugfs_name           = "hdmi1_regs",
3414         .card_name              = "vc4-hdmi-1",
3415         .max_pixel_clock        = 600000000,
3416         .registers              = vc6_hdmi_hdmi1_fields,
3417         .num_registers          = ARRAY_SIZE(vc6_hdmi_hdmi1_fields),
3418         .phy_lane_mapping       = {
3419                 PHY_LANE_0,
3420                 PHY_LANE_1,
3421                 PHY_LANE_2,
3422                 PHY_LANE_CK,
3423         },
3424         .unsupported_odd_h_timings      = false,
3425         .external_irq_controller        = true,
3426
3427         .init_resources         = vc5_hdmi_init_resources,
3428         .csc_setup              = vc5_hdmi_csc_setup,
3429         .reset                  = vc5_hdmi_reset,
3430         .set_timings            = vc5_hdmi_set_timings,
3431         .phy_init               = vc6_hdmi_phy_init,
3432         .phy_disable            = vc6_hdmi_phy_disable,
3433         .channel_map            = vc5_hdmi_channel_map,
3434         .supports_hdr           = true,
3435         .hp_detect              = vc5_hdmi_hp_detect,
3436 };
3437
3438 static const struct of_device_id vc4_hdmi_dt_match[] = {
3439         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3440         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3441         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3442         { .compatible = "brcm,bcm2712-hdmi0", .data = &bcm2712_hdmi0_variant },
3443         { .compatible = "brcm,bcm2712-hdmi1", .data = &bcm2712_hdmi1_variant },
3444         {}
3445 };
3446
3447 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3448         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3449                            vc4_hdmi_runtime_resume,
3450                            NULL)
3451 };
3452
3453 struct platform_driver vc4_hdmi_driver = {
3454         .probe = vc4_hdmi_dev_probe,
3455         .remove = vc4_hdmi_dev_remove,
3456         .driver = {
3457                 .name = "vc4_hdmi",
3458                 .of_match_table = vc4_hdmi_dt_match,
3459                 .pm = &vc4_hdmi_pm_ops,
3460         },
3461 };