drivers/gpu/drm/tegra/hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Avionic Design GmbH
   4  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/delay.h>
  10 #include <linux/hdmi.h>
  11 #include <linux/math64.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_opp.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/reset.h>
  19
  20 #include <soc/tegra/common.h>
  21 #include <sound/hdmi-codec.h>
  22
  23 #include <drm/drm_bridge_connector.h>
  24 #include <drm/drm_atomic_helper.h>
  25 #include <drm/drm_crtc.h>
  26 #include <drm/drm_debugfs.h>
  27 #include <drm/drm_edid.h>
  28 #include <drm/drm_eld.h>
  29 #include <drm/drm_file.h>
  30 #include <drm/drm_fourcc.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/drm_simple_kms_helper.h>
  33
  34 #include "hda.h"
  35 #include "hdmi.h"
  36 #include "drm.h"
  37 #include "dc.h"
  38 #include "trace.h"
  39
  40 #define HDMI_ELD_BUFFER_SIZE 96
  41
  42 struct tmds_config {
  43         unsigned int pclk;
  44         u32 pll0;
  45         u32 pll1;
  46         u32 pe_current;
  47         u32 drive_current;
  48         u32 peak_current;
  49 };
  50
  51 struct tegra_hdmi_config {
  52         const struct tmds_config *tmds;
  53         unsigned int num_tmds;
  54
  55         unsigned long fuse_override_offset;
  56         u32 fuse_override_value;
  57
  58         bool has_sor_io_peak_current;
  59         bool has_hda;
  60         bool has_hbr;
  61 };
  62
  63 struct tegra_hdmi {
  64         struct host1x_client client;
  65         struct tegra_output output;
  66         struct device *dev;
  67
  68         struct regulator *hdmi;
  69         struct regulator *pll;
  70         struct regulator *vdd;
  71
  72         void __iomem *regs;
  73         unsigned int irq;
  74
  75         struct clk *clk_parent;
  76         struct clk *clk;
  77         struct reset_control *rst;
  78
  79         const struct tegra_hdmi_config *config;
  80
  81         unsigned int audio_source;
  82         struct tegra_hda_format format;
  83
  84         unsigned int pixel_clock;
  85         bool stereo;
  86         bool dvi;
  87
  88         struct drm_info_list *debugfs_files;
  89
  90         struct platform_device *audio_pdev;
  91         struct mutex audio_lock;
  92 };
  93
  94 static inline struct tegra_hdmi *
  95 host1x_client_to_hdmi(struct host1x_client *client)
  96 {
  97         return container_of(client, struct tegra_hdmi, client);
  98 }
  99
 100 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
 101 {
 102         return container_of(output, struct tegra_hdmi, output);
 103 }
 104
 105 #define HDMI_AUDIOCLK_FREQ 216000000
 106 #define HDMI_REKEY_DEFAULT 56
 107
 108 enum {
 109         AUTO = 0,
 110         SPDIF,
 111         HDA,
 112 };
 113
 114 static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
 115                                    unsigned int offset)
 116 {
 117         u32 value = readl(hdmi->regs + (offset << 2));
 118
 119         trace_hdmi_readl(hdmi->dev, offset, value);
 120
 121         return value;
 122 }
 123
 124 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
 125                                      unsigned int offset)
 126 {
 127         trace_hdmi_writel(hdmi->dev, offset, value);
 128         writel(value, hdmi->regs + (offset << 2));
 129 }
 130
 131 struct tegra_hdmi_audio_config {
 132         unsigned int n;
 133         unsigned int cts;
 134         unsigned int aval;
 135 };
 136
 137 static const struct tmds_config tegra20_tmds_config[] = {
 138         { /* slow pixel clock modes */
 139                 .pclk = 27000000,
 140                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 141                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
 142                         SOR_PLL_TX_REG_LOAD(3),
 143                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
 144                 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
 145                         PE_CURRENT1(PE_CURRENT_0_0_mA) |
 146                         PE_CURRENT2(PE_CURRENT_0_0_mA) |
 147                         PE_CURRENT3(PE_CURRENT_0_0_mA),
 148                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
 149                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
 150                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
 151                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
 152         },
 153         { /* high pixel clock modes */
 154                 .pclk = UINT_MAX,
 155                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 156                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
 157                         SOR_PLL_TX_REG_LOAD(3),
 158                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 159                 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
 160                         PE_CURRENT1(PE_CURRENT_6_0_mA) |
 161                         PE_CURRENT2(PE_CURRENT_6_0_mA) |
 162                         PE_CURRENT3(PE_CURRENT_6_0_mA),
 163                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
 164                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
 165                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
 166                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
 167         },
 168 };
 169
 170 static const struct tmds_config tegra30_tmds_config[] = {
 171         { /* 480p modes */
 172                 .pclk = 27000000,
 173                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 174                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
 175                         SOR_PLL_TX_REG_LOAD(0),
 176                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
 177                 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
 178                         PE_CURRENT1(PE_CURRENT_0_0_mA) |
 179                         PE_CURRENT2(PE_CURRENT_0_0_mA) |
 180                         PE_CURRENT3(PE_CURRENT_0_0_mA),
 181                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 182                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 183                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 184                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 185         }, { /* 720p modes */
 186                 .pclk = 74250000,
 187                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 188                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
 189                         SOR_PLL_TX_REG_LOAD(0),
 190                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 191                 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
 192                         PE_CURRENT1(PE_CURRENT_5_0_mA) |
 193                         PE_CURRENT2(PE_CURRENT_5_0_mA) |
 194                         PE_CURRENT3(PE_CURRENT_5_0_mA),
 195                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 196                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 197                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 198                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 199         }, { /* 1080p modes */
 200                 .pclk = UINT_MAX,
 201                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 202                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
 203                         SOR_PLL_TX_REG_LOAD(0),
 204                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 205                 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
 206                         PE_CURRENT1(PE_CURRENT_5_0_mA) |
 207                         PE_CURRENT2(PE_CURRENT_5_0_mA) |
 208                         PE_CURRENT3(PE_CURRENT_5_0_mA),
 209                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 210                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 211                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 212                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 213         },
 214 };
 215
 216 static const struct tmds_config tegra114_tmds_config[] = {
 217         { /* 480p/576p / 25.2MHz/27MHz modes */
 218                 .pclk = 27000000,
 219                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 220                         SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
 221                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 222                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 223                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 224                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 225                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 226                 .drive_current =
 227                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 228                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 229                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 230                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 231                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 232                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 233                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 234                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 235         }, { /* 720p / 74.25MHz modes */
 236                 .pclk = 74250000,
 237                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 238                         SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
 239                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 240                         SOR_PLL_TMDS_TERMADJ(0),
 241                 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
 242                         PE_CURRENT1(PE_CURRENT_15_mA_T114) |
 243                         PE_CURRENT2(PE_CURRENT_15_mA_T114) |
 244                         PE_CURRENT3(PE_CURRENT_15_mA_T114),
 245                 .drive_current =
 246                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 247                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 248                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 249                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 250                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 251                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 252                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 253                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 254         }, { /* 1080p / 148.5MHz modes */
 255                 .pclk = 148500000,
 256                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 257                         SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
 258                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 259                         SOR_PLL_TMDS_TERMADJ(0),
 260                 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
 261                         PE_CURRENT1(PE_CURRENT_10_mA_T114) |
 262                         PE_CURRENT2(PE_CURRENT_10_mA_T114) |
 263                         PE_CURRENT3(PE_CURRENT_10_mA_T114),
 264                 .drive_current =
 265                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
 266                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
 267                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
 268                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
 269                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 270                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 271                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 272                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 273         }, { /* 225/297MHz modes */
 274                 .pclk = UINT_MAX,
 275                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 276                         SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
 277                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
 278                         | SOR_PLL_TMDS_TERM_ENABLE,
 279                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 280                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 281                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 282                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 283                 .drive_current =
 284                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
 285                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
 286                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
 287                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
 288                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
 289                         PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
 290                         PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
 291                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
 292         },
 293 };
 294
 295 static const struct tmds_config tegra124_tmds_config[] = {
 296         { /* 480p/576p / 25.2MHz/27MHz modes */
 297                 .pclk = 27000000,
 298                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 299                         SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
 300                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 301                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 302                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 303                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 304                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 305                 .drive_current =
 306                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 307                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 308                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 309                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 310                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 311                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 312                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 313                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 314         }, { /* 720p / 74.25MHz modes */
 315                 .pclk = 74250000,
 316                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 317                         SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
 318                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 319                         SOR_PLL_TMDS_TERMADJ(0),
 320                 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
 321                         PE_CURRENT1(PE_CURRENT_15_mA_T114) |
 322                         PE_CURRENT2(PE_CURRENT_15_mA_T114) |
 323                         PE_CURRENT3(PE_CURRENT_15_mA_T114),
 324                 .drive_current =
 325                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 326                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 327                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 328                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 329                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 330                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 331                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 332                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 333         }, { /* 1080p / 148.5MHz modes */
 334                 .pclk = 148500000,
 335                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 336                         SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
 337                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 338                         SOR_PLL_TMDS_TERMADJ(0),
 339                 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
 340                         PE_CURRENT1(PE_CURRENT_10_mA_T114) |
 341                         PE_CURRENT2(PE_CURRENT_10_mA_T114) |
 342                         PE_CURRENT3(PE_CURRENT_10_mA_T114),
 343                 .drive_current =
 344                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
 345                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
 346                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
 347                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
 348                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 349                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 350                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 351                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 352         }, { /* 225/297MHz modes */
 353                 .pclk = UINT_MAX,
 354                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 355                         SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
 356                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
 357                         | SOR_PLL_TMDS_TERM_ENABLE,
 358                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 359                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 360                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 361                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 362                 .drive_current =
 363                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
 364                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
 365                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
 366                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
 367                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
 368                         PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
 369                         PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
 370                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
 371         },
 372 };
 373
 374 static void tegra_hdmi_audio_lock(struct tegra_hdmi *hdmi)
 375 {
 376         mutex_lock(&hdmi->audio_lock);
 377         disable_irq(hdmi->irq);
 378 }
 379
 380 static void tegra_hdmi_audio_unlock(struct tegra_hdmi *hdmi)
 381 {
 382         enable_irq(hdmi->irq);
 383         mutex_unlock(&hdmi->audio_lock);
 384 }
 385
 386 static int
 387 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pix_clock,
 388                             struct tegra_hdmi_audio_config *config)
 389 {
 390         const unsigned int afreq = 128 * audio_freq;
 391         const unsigned int min_n = afreq / 1500;
 392         const unsigned int max_n = afreq / 300;
 393         const unsigned int ideal_n = afreq / 1000;
 394         int64_t min_err = (uint64_t)-1 >> 1;
 395         unsigned int min_delta = -1;
 396         int n;
 397
 398         memset(config, 0, sizeof(*config));
 399         config->n = -1;
 400
 401         for (n = min_n; n <= max_n; n++) {
 402                 uint64_t cts_f, aval_f;
 403                 unsigned int delta;
 404                 int64_t cts, err;
 405
 406                 /* compute aval in 48.16 fixed point */
 407                 aval_f = ((int64_t)24000000 << 16) * n;
 408                 do_div(aval_f, afreq);
 409                 /* It should round without any rest */
 410                 if (aval_f & 0xFFFF)
 411                         continue;
 412
 413                 /* Compute cts in 48.16 fixed point */
 414                 cts_f = ((int64_t)pix_clock << 16) * n;
 415                 do_div(cts_f, afreq);
 416                 /* Round it to the nearest integer */
 417                 cts = (cts_f & ~0xFFFF) + ((cts_f & BIT(15)) << 1);
 418
 419                 delta = abs(n - ideal_n);
 420
 421                 /* Compute the absolute error */
 422                 err = abs((int64_t)cts_f - cts);
 423                 if (err < min_err || (err == min_err && delta < min_delta)) {
 424                         config->n = n;
 425                         config->cts = cts >> 16;
 426                         config->aval = aval_f >> 16;
 427                         min_delta = delta;
 428                         min_err = err;
 429                 }
 430         }
 431
 432         return config->n != -1 ? 0 : -EINVAL;
 433 }
 434
 435 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
 436 {
 437         static const unsigned int freqs[] = {
 438                 32000, 44100, 48000, 88200, 96000, 176400, 192000
 439         };
 440         unsigned int i;
 441
 442         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
 443                 unsigned int f = freqs[i];
 444                 unsigned int eight_half;
 445                 unsigned int delta;
 446                 u32 value;
 447
 448                 if (f > 96000)
 449                         delta = 2;
 450                 else if (f > 48000)
 451                         delta = 6;
 452                 else
 453                         delta = 9;
 454
 455                 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
 456                 value = AUDIO_FS_LOW(eight_half - delta) |
 457                         AUDIO_FS_HIGH(eight_half + delta);
 458                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
 459         }
 460 }
 461
 462 static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
 463 {
 464         static const struct {
 465                 unsigned int sample_rate;
 466                 unsigned int offset;
 467         } regs[] = {
 468                 {  32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
 469                 {  44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
 470                 {  48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
 471                 {  88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
 472                 {  96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
 473                 { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
 474                 { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
 475         };
 476         unsigned int i;
 477
 478         for (i = 0; i < ARRAY_SIZE(regs); i++) {
 479                 if (regs[i].sample_rate == hdmi->format.sample_rate) {
 480                         tegra_hdmi_writel(hdmi, value, regs[i].offset);
 481                         break;
 482                 }
 483         }
 484 }
 485
 486 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
 487 {
 488         struct tegra_hdmi_audio_config config;
 489         u32 source, value;
 490         int err;
 491
 492         switch (hdmi->audio_source) {
 493         case HDA:
 494                 if (hdmi->config->has_hda)
 495                         source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
 496                 else
 497                         return -EINVAL;
 498
 499                 break;
 500
 501         case SPDIF:
 502                 if (hdmi->config->has_hda)
 503                         source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
 504                 else
 505                         source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
 506                 break;
 507
 508         default:
 509                 if (hdmi->config->has_hda)
 510                         source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
 511                 else
 512                         source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
 513                 break;
 514         }
 515
 516         /*
 517          * Tegra30 and later use a slightly modified version of the register
 518          * layout to accomodate for changes related to supporting HDA as the
 519          * audio input source for HDMI. The source select field has moved to
 520          * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames
 521          * per block fields remain in the AUDIO_CNTRL0 register.
 522          */
 523         if (hdmi->config->has_hda) {
 524                 /*
 525                  * Inject null samples into the audio FIFO for every frame in
 526                  * which the codec did not receive any samples. This applies
 527                  * to stereo LPCM only.
 528                  *
 529                  * XXX: This seems to be a remnant of MCP days when this was
 530                  * used to work around issues with monitors not being able to
 531                  * play back system startup sounds early. It is possibly not
 532                  * needed on Linux at all.
 533                  */
 534                 if (hdmi->format.channels == 2)
 535                         value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
 536                 else
 537                         value = 0;
 538
 539                 value |= source;
 540
 541                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
 542         }
 543
 544         /*
 545          * On Tegra20, HDA is not a supported audio source and the source
 546          * select field is part of the AUDIO_CNTRL0 register.
 547          */
 548         value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
 549                 AUDIO_CNTRL0_ERROR_TOLERANCE(6);
 550
 551         if (!hdmi->config->has_hda)
 552                 value |= source;
 553
 554         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
 555
 556         /*
 557          * Advertise support for High Bit-Rate on Tegra114 and later.
 558          */
 559         if (hdmi->config->has_hbr) {
 560                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
 561                 value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
 562                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
 563         }
 564
 565         err = tegra_hdmi_get_audio_config(hdmi->format.sample_rate,
 566                                           hdmi->pixel_clock, &config);
 567         if (err < 0) {
 568                 dev_err(hdmi->dev,
 569                         "cannot set audio to %u Hz at %u Hz pixel clock\n",
 570                         hdmi->format.sample_rate, hdmi->pixel_clock);
 571                 return err;
 572         }
 573
 574         dev_dbg(hdmi->dev, "audio: pixclk=%u, n=%u, cts=%u, aval=%u\n",
 575                 hdmi->pixel_clock, config.n, config.cts, config.aval);
 576
 577         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
 578
 579         value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
 580                 AUDIO_N_VALUE(config.n - 1);
 581         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
 582
 583         tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config.n) | ACR_ENABLE,
 584                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 585
 586         tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config.cts),
 587                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 588
 589         value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
 590         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
 591
 592         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
 593         value &= ~AUDIO_N_RESETF;
 594         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
 595
 596         if (hdmi->config->has_hda)
 597                 tegra_hdmi_write_aval(hdmi, config.aval);
 598
 599         tegra_hdmi_setup_audio_fs_tables(hdmi);
 600
 601         return 0;
 602 }
 603
 604 static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
 605 {
 606         u32 value;
 607
 608         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 609         value &= ~GENERIC_CTRL_AUDIO;
 610         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 611 }
 612
 613 static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
 614 {
 615         u32 value;
 616
 617         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 618         value |= GENERIC_CTRL_AUDIO;
 619         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 620 }
 621
 622 static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
 623 {
 624         size_t length = drm_eld_size(hdmi->output.connector.eld), i;
 625         u32 value;
 626
 627         for (i = 0; i < length; i++)
 628                 tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
 629                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
 630
 631         /*
 632          * The HDA codec will always report an ELD buffer size of 96 bytes and
 633          * the HDA codec driver will check that each byte read from the buffer
 634          * is valid. Therefore every byte must be written, even if no 96 bytes
 635          * were parsed from EDID.
 636          */
 637         for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
 638                 tegra_hdmi_writel(hdmi, i << 8 | 0,
 639                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
 640
 641         value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
 642         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
 643 }
 644
 645 static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
 646 {
 647         u32 value = 0;
 648         size_t i;
 649
 650         for (i = size; i > 0; i--)
 651                 value = (value << 8) | ptr[i - 1];
 652
 653         return value;
 654 }
 655
 656 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
 657                                       size_t size)
 658 {
 659         const u8 *ptr = data;
 660         unsigned long offset;
 661         size_t i, j;
 662         u32 value;
 663
 664         switch (ptr[0]) {
 665         case HDMI_INFOFRAME_TYPE_AVI:
 666                 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
 667                 break;
 668
 669         case HDMI_INFOFRAME_TYPE_AUDIO:
 670                 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
 671                 break;
 672
 673         case HDMI_INFOFRAME_TYPE_VENDOR:
 674                 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
 675                 break;
 676
 677         default:
 678                 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
 679                         ptr[0]);
 680                 return;
 681         }
 682
 683         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
 684                 INFOFRAME_HEADER_VERSION(ptr[1]) |
 685                 INFOFRAME_HEADER_LEN(ptr[2]);
 686         tegra_hdmi_writel(hdmi, value, offset);
 687         offset++;
 688
 689         /*
 690          * Each subpack contains 7 bytes, divided into:
 691          * - subpack_low: bytes 0 - 3
 692          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
 693          */
 694         for (i = 3, j = 0; i < size; i += 7, j += 8) {
 695                 size_t rem = size - i, num = min_t(size_t, rem, 4);
 696
 697                 value = tegra_hdmi_subpack(&ptr[i], num);
 698                 tegra_hdmi_writel(hdmi, value, offset++);
 699
 700                 num = min_t(size_t, rem - num, 3);
 701
 702                 value = tegra_hdmi_subpack(&ptr[i + 4], num);
 703                 tegra_hdmi_writel(hdmi, value, offset++);
 704         }
 705 }
 706
 707 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
 708                                            struct drm_display_mode *mode)
 709 {
 710         struct hdmi_avi_infoframe frame;
 711         u8 buffer[17];
 712         ssize_t err;
 713
 714         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
 715                                                        &hdmi->output.connector, mode);
 716         if (err < 0) {
 717                 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
 718                 return;
 719         }
 720
 721         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 722         if (err < 0) {
 723                 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
 724                 return;
 725         }
 726
 727         tegra_hdmi_write_infopack(hdmi, buffer, err);
 728 }
 729
 730 static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
 731 {
 732         u32 value;
 733
 734         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 735         value &= ~INFOFRAME_CTRL_ENABLE;
 736         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 737 }
 738
 739 static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
 740 {
 741         u32 value;
 742
 743         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 744         value |= INFOFRAME_CTRL_ENABLE;
 745         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 746 }
 747
 748 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
 749 {
 750         struct hdmi_audio_infoframe frame;
 751         u8 buffer[14];
 752         ssize_t err;
 753
 754         err = hdmi_audio_infoframe_init(&frame);
 755         if (err < 0) {
 756                 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
 757                         err);
 758                 return;
 759         }
 760
 761         frame.channels = hdmi->format.channels;
 762
 763         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
 764         if (err < 0) {
 765                 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
 766                         err);
 767                 return;
 768         }
 769
 770         /*
 771          * The audio infoframe has only one set of subpack registers, so the
 772          * infoframe needs to be truncated. One set of subpack registers can
 773          * contain 7 bytes. Including the 3 byte header only the first 10
 774          * bytes can be programmed.
 775          */
 776         tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
 777 }
 778
 779 static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
 780 {
 781         u32 value;
 782
 783         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 784         value &= ~INFOFRAME_CTRL_ENABLE;
 785         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 786 }
 787
 788 static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
 789 {
 790         u32 value;
 791
 792         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 793         value |= INFOFRAME_CTRL_ENABLE;
 794         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 795 }
 796
 797 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
 798 {
 799         struct hdmi_vendor_infoframe frame;
 800         u8 buffer[10];
 801         ssize_t err;
 802
 803         hdmi_vendor_infoframe_init(&frame);
 804         frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
 805
 806         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
 807         if (err < 0) {
 808                 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
 809                         err);
 810                 return;
 811         }
 812
 813         tegra_hdmi_write_infopack(hdmi, buffer, err);
 814 }
 815
 816 static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
 817 {
 818         u32 value;
 819
 820         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 821         value &= ~GENERIC_CTRL_ENABLE;
 822         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 823 }
 824
 825 static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
 826 {
 827         u32 value;
 828
 829         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 830         value |= GENERIC_CTRL_ENABLE;
 831         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 832 }
 833
 834 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
 835                                   const struct tmds_config *tmds)
 836 {
 837         u32 value;
 838
 839         tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
 840         tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
 841         tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
 842
 843         tegra_hdmi_writel(hdmi, tmds->drive_current,
 844                           HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
 845
 846         value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
 847         value |= hdmi->config->fuse_override_value;
 848         tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
 849
 850         if (hdmi->config->has_sor_io_peak_current)
 851                 tegra_hdmi_writel(hdmi, tmds->peak_current,
 852                                   HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
 853 }
 854
 855 static int tegra_hdmi_reconfigure_audio(struct tegra_hdmi *hdmi)
 856 {
 857         int err;
 858
 859         err = tegra_hdmi_setup_audio(hdmi);
 860         if (err < 0) {
 861                 tegra_hdmi_disable_audio_infoframe(hdmi);
 862                 tegra_hdmi_disable_audio(hdmi);
 863         } else {
 864                 tegra_hdmi_setup_audio_infoframe(hdmi);
 865                 tegra_hdmi_enable_audio_infoframe(hdmi);
 866                 tegra_hdmi_enable_audio(hdmi);
 867         }
 868
 869         return err;
 870 }
 871
 872 static bool tegra_output_is_hdmi(struct tegra_output *output)
 873 {
 874         return output->connector.display_info.is_hdmi;
 875 }
 876
 877 static enum drm_connector_status
 878 tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
 879 {
 880         struct tegra_output *output = connector_to_output(connector);
 881         struct tegra_hdmi *hdmi = to_hdmi(output);
 882         enum drm_connector_status status;
 883
 884         status = tegra_output_connector_detect(connector, force);
 885         if (status == connector_status_connected)
 886                 return status;
 887
 888         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
 889         return status;
 890 }
 891
 892 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
 893
 894 static const struct debugfs_reg32 tegra_hdmi_regs[] = {
 895         DEBUGFS_REG32(HDMI_CTXSW),
 896         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0),
 897         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1),
 898         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2),
 899         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB),
 900         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB),
 901         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB),
 902         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB),
 903         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB),
 904         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB),
 905         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB),
 906         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB),
 907         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB),
 908         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB),
 909         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB),
 910         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB),
 911         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL),
 912         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE),
 913         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB),
 914         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB),
 915         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB),
 916         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2),
 917         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1),
 918         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI),
 919         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB),
 920         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB),
 921         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0),
 922         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0),
 923         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1),
 924         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2),
 925         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL),
 926         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS),
 927         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER),
 928         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW),
 929         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH),
 930         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL),
 931         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS),
 932         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER),
 933         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW),
 934         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH),
 935         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW),
 936         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH),
 937         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL),
 938         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS),
 939         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER),
 940         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW),
 941         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH),
 942         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW),
 943         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH),
 944         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW),
 945         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH),
 946         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW),
 947         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH),
 948         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL),
 949         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW),
 950         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH),
 951         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW),
 952         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH),
 953         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW),
 954         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH),
 955         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW),
 956         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH),
 957         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW),
 958         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH),
 959         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW),
 960         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH),
 961         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW),
 962         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH),
 963         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL),
 964         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT),
 965         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW),
 966         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL),
 967         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS),
 968         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK),
 969         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1),
 970         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2),
 971         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0),
 972         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1),
 973         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA),
 974         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE),
 975         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1),
 976         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2),
 977         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL),
 978         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP),
 979         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR),
 980         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST),
 981         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0),
 982         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1),
 983         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2),
 984         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM),
 985         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS),
 986         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA),
 987         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB),
 988         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK),
 989         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL),
 990         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)),
 991         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)),
 992         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)),
 993         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)),
 994         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)),
 995         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)),
 996         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)),
 997         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)),
 998         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)),
 999         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)),
1000         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)),
1001         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)),
1002         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)),
1003         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)),
1004         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)),
1005         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)),
1006         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0),
1007         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1),
1008         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0),
1009         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1),
1010         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0),
1011         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1),
1012         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0),
1013         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1),
1014         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0),
1015         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1),
1016         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG),
1017         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK),
1018         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT),
1019         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0),
1020         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1),
1021         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2),
1022         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)),
1023         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)),
1024         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)),
1025         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)),
1026         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)),
1027         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)),
1028         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)),
1029         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH),
1030         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD),
1031         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0),
1032         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N),
1033         DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING),
1034         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK),
1035         DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL),
1036         DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL),
1037         DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH),
1038         DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT),
1039         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL),
1040         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0),
1041         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1),
1042         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2),
1043         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0),
1044         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1),
1045         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2),
1046         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3),
1047         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG),
1048         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX),
1049         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0),
1050         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0),
1051         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0),
1052         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1),
1053         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR),
1054         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE),
1055         DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS),
1056         DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK),
1057         DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE),
1058         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT),
1059 };
1060
1061 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1062 {
1063         struct drm_info_node *node = s->private;
1064         struct tegra_hdmi *hdmi = node->info_ent->data;
1065         struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1066         struct drm_device *drm = node->minor->dev;
1067         unsigned int i;
1068         int err = 0;
1069
1070         drm_modeset_lock_all(drm);
1071
1072         if (!crtc || !crtc->state->active) {
1073                 err = -EBUSY;
1074                 goto unlock;
1075         }
1076
1077         for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) {
1078                 unsigned int offset = tegra_hdmi_regs[i].offset;
1079
1080                 seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name,
1081                            offset, tegra_hdmi_readl(hdmi, offset));
1082         }
1083
1084 unlock:
1085         drm_modeset_unlock_all(drm);
1086         return err;
1087 }
1088
1089 static struct drm_info_list debugfs_files[] = {
1090         { "regs", tegra_hdmi_show_regs, 0, NULL },
1091 };
1092
1093 static int tegra_hdmi_late_register(struct drm_connector *connector)
1094 {
1095         struct tegra_output *output = connector_to_output(connector);
1096         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1097         struct drm_minor *minor = connector->dev->primary;
1098         struct dentry *root = connector->debugfs_entry;
1099         struct tegra_hdmi *hdmi = to_hdmi(output);
1100
1101         hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1102                                       GFP_KERNEL);
1103         if (!hdmi->debugfs_files)
1104                 return -ENOMEM;
1105
1106         for (i = 0; i < count; i++)
1107                 hdmi->debugfs_files[i].data = hdmi;
1108
1109         drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor);
1110
1111         return 0;
1112 }
1113
1114 static void tegra_hdmi_early_unregister(struct drm_connector *connector)
1115 {
1116         struct tegra_output *output = connector_to_output(connector);
1117         struct drm_minor *minor = connector->dev->primary;
1118         unsigned int count = ARRAY_SIZE(debugfs_files);
1119         struct tegra_hdmi *hdmi = to_hdmi(output);
1120
1121         drm_debugfs_remove_files(hdmi->debugfs_files, count,
1122                                  connector->debugfs_entry, minor);
1123         kfree(hdmi->debugfs_files);
1124         hdmi->debugfs_files = NULL;
1125 }
1126
1127 static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
1128         .reset = drm_atomic_helper_connector_reset,
1129         .detect = tegra_hdmi_connector_detect,
1130         .fill_modes = drm_helper_probe_single_connector_modes,
1131         .destroy = tegra_output_connector_destroy,
1132         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1133         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1134         .late_register = tegra_hdmi_late_register,
1135         .early_unregister = tegra_hdmi_early_unregister,
1136 };
1137
1138 static enum drm_mode_status
1139 tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
1140                                 struct drm_display_mode *mode)
1141 {
1142         struct tegra_output *output = connector_to_output(connector);
1143         struct tegra_hdmi *hdmi = to_hdmi(output);
1144         unsigned long pclk = mode->clock * 1000;
1145         enum drm_mode_status status = MODE_OK;
1146         struct clk *parent;
1147         long err;
1148
1149         parent = clk_get_parent(hdmi->clk_parent);
1150
1151         err = clk_round_rate(parent, pclk * 4);
1152         if (err <= 0)
1153                 status = MODE_NOCLOCK;
1154
1155         return status;
1156 }
1157
1158 static const struct drm_connector_helper_funcs
1159 tegra_hdmi_connector_helper_funcs = {
1160         .get_modes = tegra_output_connector_get_modes,
1161         .mode_valid = tegra_hdmi_connector_mode_valid,
1162 };
1163
1164 static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
1165 {
1166         struct tegra_output *output = encoder_to_output(encoder);
1167         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1168         struct tegra_hdmi *hdmi = to_hdmi(output);
1169         u32 value;
1170         int err;
1171
1172         tegra_hdmi_audio_lock(hdmi);
1173
1174         /*
1175          * The following accesses registers of the display controller, so make
1176          * sure it's only executed when the output is attached to one.
1177          */
1178         if (dc) {
1179                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1180                 value &= ~HDMI_ENABLE;
1181                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1182
1183                 tegra_dc_commit(dc);
1184         }
1185
1186         if (!hdmi->dvi) {
1187                 if (hdmi->stereo)
1188                         tegra_hdmi_disable_stereo_infoframe(hdmi);
1189
1190                 tegra_hdmi_disable_audio_infoframe(hdmi);
1191                 tegra_hdmi_disable_avi_infoframe(hdmi);
1192                 tegra_hdmi_disable_audio(hdmi);
1193         }
1194
1195         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
1196         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
1197
1198         hdmi->pixel_clock = 0;
1199
1200         tegra_hdmi_audio_unlock(hdmi);
1201
1202         err = host1x_client_suspend(&hdmi->client);
1203         if (err < 0)
1204                 dev_err(hdmi->dev, "failed to suspend: %d\n", err);
1205 }
1206
1207 static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
1208 {
1209         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1210         unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
1211         struct tegra_output *output = encoder_to_output(encoder);
1212         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1213         struct tegra_hdmi *hdmi = to_hdmi(output);
1214         unsigned int pulse_start, div82;
1215         int retries = 1000;
1216         u32 value;
1217         int err;
1218
1219         err = host1x_client_resume(&hdmi->client);
1220         if (err < 0) {
1221                 dev_err(hdmi->dev, "failed to resume: %d\n", err);
1222                 return;
1223         }
1224
1225         tegra_hdmi_audio_lock(hdmi);
1226
1227         /*
1228          * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1229          * is used for interoperability between the HDA codec driver and the
1230          * HDMI driver.
1231          */
1232         tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
1233         tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
1234
1235         hdmi->pixel_clock = mode->clock * 1000;
1236         h_sync_width = mode->hsync_end - mode->hsync_start;
1237         h_back_porch = mode->htotal - mode->hsync_end;
1238         h_front_porch = mode->hsync_start - mode->hdisplay;
1239
1240         err = dev_pm_opp_set_rate(hdmi->dev, hdmi->pixel_clock);
1241         if (err < 0) {
1242                 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
1243                         err);
1244         }
1245
1246         DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
1247
1248         /* power up sequence */
1249         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1250         value &= ~SOR_PLL_PDBG;
1251         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1252
1253         usleep_range(10, 20);
1254
1255         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1256         value &= ~SOR_PLL_PWR;
1257         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1258
1259         tegra_dc_writel(dc, VSYNC_H_POSITION(1),
1260                         DC_DISP_DISP_TIMING_OPTIONS);
1261         tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
1262                         DC_DISP_DISP_COLOR_CONTROL);
1263
1264         /* video_preamble uses h_pulse2 */
1265         pulse_start = 1 + h_sync_width + h_back_porch - 10;
1266
1267         tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1268
1269         value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
1270                 PULSE_LAST_END_A;
1271         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1272
1273         value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
1274         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1275
1276         value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
1277                 VSYNC_WINDOW_ENABLE;
1278         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1279
1280         if (dc->pipe)
1281                 value = HDMI_SRC_DISPLAYB;
1282         else
1283                 value = HDMI_SRC_DISPLAYA;
1284
1285         if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
1286                                         (mode->vdisplay == 576)))
1287                 tegra_hdmi_writel(hdmi,
1288                                   value | ARM_VIDEO_RANGE_FULL,
1289                                   HDMI_NV_PDISP_INPUT_CONTROL);
1290         else
1291                 tegra_hdmi_writel(hdmi,
1292                                   value | ARM_VIDEO_RANGE_LIMITED,
1293                                   HDMI_NV_PDISP_INPUT_CONTROL);
1294
1295         div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
1296         value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
1297         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
1298
1299         hdmi->dvi = !tegra_output_is_hdmi(output);
1300         if (!hdmi->dvi) {
1301                 /*
1302                  * Make sure that the audio format has been configured before
1303                  * enabling audio, otherwise we may try to divide by zero.
1304                 */
1305                 if (hdmi->format.sample_rate > 0) {
1306                         err = tegra_hdmi_setup_audio(hdmi);
1307                         if (err < 0)
1308                                 hdmi->dvi = true;
1309                 }
1310         }
1311
1312         if (hdmi->config->has_hda)
1313                 tegra_hdmi_write_eld(hdmi);
1314
1315         rekey = HDMI_REKEY_DEFAULT;
1316         value = HDMI_CTRL_REKEY(rekey);
1317         value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
1318                                           h_front_porch - rekey - 18) / 32);
1319
1320         if (!hdmi->dvi)
1321                 value |= HDMI_CTRL_ENABLE;
1322
1323         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
1324
1325         if (!hdmi->dvi) {
1326                 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
1327                 tegra_hdmi_setup_audio_infoframe(hdmi);
1328
1329                 if (hdmi->stereo)
1330                         tegra_hdmi_setup_stereo_infoframe(hdmi);
1331         }
1332
1333         /* TMDS CONFIG */
1334         for (i = 0; i < hdmi->config->num_tmds; i++) {
1335                 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
1336                         tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
1337                         break;
1338                 }
1339         }
1340
1341         tegra_hdmi_writel(hdmi,
1342                           SOR_SEQ_PU_PC(0) |
1343                           SOR_SEQ_PU_PC_ALT(0) |
1344                           SOR_SEQ_PD_PC(8) |
1345                           SOR_SEQ_PD_PC_ALT(8),
1346                           HDMI_NV_PDISP_SOR_SEQ_CTL);
1347
1348         value = SOR_SEQ_INST_WAIT_TIME(1) |
1349                 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1350                 SOR_SEQ_INST_HALT |
1351                 SOR_SEQ_INST_PIN_A_LOW |
1352                 SOR_SEQ_INST_PIN_B_LOW |
1353                 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1354
1355         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
1356         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
1357
1358         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
1359         value &= ~SOR_CSTM_ROTCLK(~0);
1360         value |= SOR_CSTM_ROTCLK(2);
1361         value |= SOR_CSTM_PLLDIV;
1362         value &= ~SOR_CSTM_LVDS_ENABLE;
1363         value &= ~SOR_CSTM_MODE_MASK;
1364         value |= SOR_CSTM_MODE_TMDS;
1365         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
1366
1367         /* start SOR */
1368         tegra_hdmi_writel(hdmi,
1369                           SOR_PWR_NORMAL_STATE_PU |
1370                           SOR_PWR_NORMAL_START_NORMAL |
1371                           SOR_PWR_SAFE_STATE_PD |
1372                           SOR_PWR_SETTING_NEW_TRIGGER,
1373                           HDMI_NV_PDISP_SOR_PWR);
1374         tegra_hdmi_writel(hdmi,
1375                           SOR_PWR_NORMAL_STATE_PU |
1376                           SOR_PWR_NORMAL_START_NORMAL |
1377                           SOR_PWR_SAFE_STATE_PD |
1378                           SOR_PWR_SETTING_NEW_DONE,
1379                           HDMI_NV_PDISP_SOR_PWR);
1380
1381         do {
1382                 BUG_ON(--retries < 0);
1383                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1384         } while (value & SOR_PWR_SETTING_NEW_PENDING);
1385
1386         value = SOR_STATE_ASY_CRCMODE_COMPLETE |
1387                 SOR_STATE_ASY_OWNER_HEAD0 |
1388                 SOR_STATE_ASY_SUBOWNER_BOTH |
1389                 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1390                 SOR_STATE_ASY_DEPOL_POS;
1391
1392         /* setup sync polarities */
1393         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1394                 value |= SOR_STATE_ASY_HSYNCPOL_POS;
1395
1396         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1397                 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1398
1399         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1400                 value |= SOR_STATE_ASY_VSYNCPOL_POS;
1401
1402         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1403                 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1404
1405         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1406
1407         value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1408         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1409
1410         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1411         tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1412         tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1413                           HDMI_NV_PDISP_SOR_STATE1);
1414         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1415
1416         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1417         value |= HDMI_ENABLE;
1418         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1419
1420         tegra_dc_commit(dc);
1421
1422         if (!hdmi->dvi) {
1423                 tegra_hdmi_enable_avi_infoframe(hdmi);
1424                 tegra_hdmi_enable_audio_infoframe(hdmi);
1425                 tegra_hdmi_enable_audio(hdmi);
1426
1427                 if (hdmi->stereo)
1428                         tegra_hdmi_enable_stereo_infoframe(hdmi);
1429         }
1430
1431         /* TODO: add HDCP support */
1432
1433         tegra_hdmi_audio_unlock(hdmi);
1434 }
1435
1436 static int
1437 tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1438                                 struct drm_crtc_state *crtc_state,
1439                                 struct drm_connector_state *conn_state)
1440 {
1441         struct tegra_output *output = encoder_to_output(encoder);
1442         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1443         unsigned long pclk = crtc_state->mode.clock * 1000;
1444         struct tegra_hdmi *hdmi = to_hdmi(output);
1445         int err;
1446
1447         err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
1448                                          pclk, 0);
1449         if (err < 0) {
1450                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1451                 return err;
1452         }
1453
1454         return err;
1455 }
1456
1457 static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1458         .disable = tegra_hdmi_encoder_disable,
1459         .enable = tegra_hdmi_encoder_enable,
1460         .atomic_check = tegra_hdmi_encoder_atomic_check,
1461 };
1462
1463 static int tegra_hdmi_hw_params(struct device *dev, void *data,
1464                                 struct hdmi_codec_daifmt *fmt,
1465                                 struct hdmi_codec_params *hparms)
1466 {
1467         struct tegra_hdmi *hdmi = data;
1468         int ret = 0;
1469
1470         tegra_hdmi_audio_lock(hdmi);
1471
1472         hdmi->format.sample_rate = hparms->sample_rate;
1473         hdmi->format.channels = hparms->channels;
1474
1475         if (hdmi->pixel_clock && !hdmi->dvi)
1476                 ret = tegra_hdmi_reconfigure_audio(hdmi);
1477
1478         tegra_hdmi_audio_unlock(hdmi);
1479
1480         return ret;
1481 }
1482
1483 static int tegra_hdmi_audio_startup(struct device *dev, void *data)
1484 {
1485         struct tegra_hdmi *hdmi = data;
1486         int ret;
1487
1488         ret = host1x_client_resume(&hdmi->client);
1489         if (ret < 0)
1490                 dev_err(hdmi->dev, "failed to resume: %d\n", ret);
1491
1492         return ret;
1493 }
1494
1495 static void tegra_hdmi_audio_shutdown(struct device *dev, void *data)
1496 {
1497         struct tegra_hdmi *hdmi = data;
1498         int ret;
1499
1500         tegra_hdmi_audio_lock(hdmi);
1501
1502         hdmi->format.sample_rate = 0;
1503         hdmi->format.channels = 0;
1504
1505         tegra_hdmi_audio_unlock(hdmi);
1506
1507         ret = host1x_client_suspend(&hdmi->client);
1508         if (ret < 0)
1509                 dev_err(hdmi->dev, "failed to suspend: %d\n", ret);
1510 }
1511
1512 static const struct hdmi_codec_ops tegra_hdmi_codec_ops = {
1513         .hw_params = tegra_hdmi_hw_params,
1514         .audio_startup = tegra_hdmi_audio_startup,
1515         .audio_shutdown = tegra_hdmi_audio_shutdown,
1516 };
1517
1518 static int tegra_hdmi_codec_register(struct tegra_hdmi *hdmi)
1519 {
1520         struct hdmi_codec_pdata codec_data = {};
1521
1522         if (hdmi->config->has_hda)
1523                 return 0;
1524
1525         codec_data.ops = &tegra_hdmi_codec_ops;
1526         codec_data.data = hdmi;
1527         codec_data.spdif = 1;
1528
1529         hdmi->audio_pdev = platform_device_register_data(hdmi->dev,
1530                                                          HDMI_CODEC_DRV_NAME,
1531                                                          PLATFORM_DEVID_AUTO,
1532                                                          &codec_data,
1533                                                          sizeof(codec_data));
1534         if (IS_ERR(hdmi->audio_pdev))
1535                 return PTR_ERR(hdmi->audio_pdev);
1536
1537         hdmi->format.channels = 2;
1538
1539         return 0;
1540 }
1541
1542 static void tegra_hdmi_codec_unregister(struct tegra_hdmi *hdmi)
1543 {
1544         if (hdmi->audio_pdev)
1545                 platform_device_unregister(hdmi->audio_pdev);
1546 }
1547
1548 static int tegra_hdmi_init(struct host1x_client *client)
1549 {
1550         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1551         struct drm_device *drm = dev_get_drvdata(client->host);
1552         struct drm_connector *connector;
1553         int err;
1554
1555         hdmi->output.dev = client->dev;
1556
1557         drm_simple_encoder_init(drm, &hdmi->output.encoder,
1558                                 DRM_MODE_ENCODER_TMDS);
1559         drm_encoder_helper_add(&hdmi->output.encoder,
1560                                &tegra_hdmi_encoder_helper_funcs);
1561
1562         if (hdmi->output.bridge) {
1563                 err = drm_bridge_attach(&hdmi->output.encoder, hdmi->output.bridge,
1564                                         NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1565                 if (err) {
1566                         dev_err(client->dev, "failed to attach bridge: %d\n",
1567                                 err);
1568                         return err;
1569                 }
1570
1571                 connector = drm_bridge_connector_init(drm, &hdmi->output.encoder);
1572                 if (IS_ERR(connector)) {
1573                         dev_err(client->dev,
1574                                 "failed to initialize bridge connector: %pe\n",
1575                                 connector);
1576                         return PTR_ERR(connector);
1577                 }
1578
1579                 drm_connector_attach_encoder(connector, &hdmi->output.encoder);
1580         } else {
1581                 drm_connector_init_with_ddc(drm, &hdmi->output.connector,
1582                                             &tegra_hdmi_connector_funcs,
1583                                             DRM_MODE_CONNECTOR_HDMIA,
1584                                             hdmi->output.ddc);
1585                 drm_connector_helper_add(&hdmi->output.connector,
1586                                          &tegra_hdmi_connector_helper_funcs);
1587                 hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1588
1589                 drm_connector_attach_encoder(&hdmi->output.connector,
1590                                              &hdmi->output.encoder);
1591                 drm_connector_register(&hdmi->output.connector);
1592         }
1593
1594         err = tegra_output_init(drm, &hdmi->output);
1595         if (err < 0) {
1596                 dev_err(client->dev, "failed to initialize output: %d\n", err);
1597                 return err;
1598         }
1599
1600         hdmi->output.encoder.possible_crtcs = 0x3;
1601
1602         err = regulator_enable(hdmi->hdmi);
1603         if (err < 0) {
1604                 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1605                         err);
1606                 goto output_exit;
1607         }
1608
1609         err = regulator_enable(hdmi->pll);
1610         if (err < 0) {
1611                 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
1612                 goto disable_hdmi;
1613         }
1614
1615         err = regulator_enable(hdmi->vdd);
1616         if (err < 0) {
1617                 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
1618                 goto disable_pll;
1619         }
1620
1621         err = tegra_hdmi_codec_register(hdmi);
1622         if (err < 0) {
1623                 dev_err(hdmi->dev, "failed to register audio codec: %d\n", err);
1624                 goto disable_vdd;
1625         }
1626
1627         return 0;
1628
1629 disable_vdd:
1630         regulator_disable(hdmi->vdd);
1631 disable_pll:
1632         regulator_disable(hdmi->pll);
1633 disable_hdmi:
1634         regulator_disable(hdmi->hdmi);
1635 output_exit:
1636         tegra_output_exit(&hdmi->output);
1637
1638         return err;
1639 }
1640
1641 static int tegra_hdmi_exit(struct host1x_client *client)
1642 {
1643         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1644
1645         tegra_hdmi_codec_unregister(hdmi);
1646
1647         tegra_output_exit(&hdmi->output);
1648
1649         regulator_disable(hdmi->vdd);
1650         regulator_disable(hdmi->pll);
1651         regulator_disable(hdmi->hdmi);
1652
1653         return 0;
1654 }
1655
1656 static int tegra_hdmi_runtime_suspend(struct host1x_client *client)
1657 {
1658         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1659         struct device *dev = client->dev;
1660         int err;
1661
1662         err = reset_control_assert(hdmi->rst);
1663         if (err < 0) {
1664                 dev_err(dev, "failed to assert reset: %d\n", err);
1665                 return err;
1666         }
1667
1668         usleep_range(1000, 2000);
1669
1670         clk_disable_unprepare(hdmi->clk);
1671         pm_runtime_put_sync(dev);
1672
1673         return 0;
1674 }
1675
1676 static int tegra_hdmi_runtime_resume(struct host1x_client *client)
1677 {
1678         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1679         struct device *dev = client->dev;
1680         int err;
1681
1682         err = pm_runtime_resume_and_get(dev);
1683         if (err < 0) {
1684                 dev_err(dev, "failed to get runtime PM: %d\n", err);
1685                 return err;
1686         }
1687
1688         err = clk_prepare_enable(hdmi->clk);
1689         if (err < 0) {
1690                 dev_err(dev, "failed to enable clock: %d\n", err);
1691                 goto put_rpm;
1692         }
1693
1694         usleep_range(1000, 2000);
1695
1696         err = reset_control_deassert(hdmi->rst);
1697         if (err < 0) {
1698                 dev_err(dev, "failed to deassert reset: %d\n", err);
1699                 goto disable_clk;
1700         }
1701
1702         return 0;
1703
1704 disable_clk:
1705         clk_disable_unprepare(hdmi->clk);
1706 put_rpm:
1707         pm_runtime_put_sync(dev);
1708         return err;
1709 }
1710
1711 static const struct host1x_client_ops hdmi_client_ops = {
1712         .init = tegra_hdmi_init,
1713         .exit = tegra_hdmi_exit,
1714         .suspend = tegra_hdmi_runtime_suspend,
1715         .resume = tegra_hdmi_runtime_resume,
1716 };
1717
1718 static const struct tegra_hdmi_config tegra20_hdmi_config = {
1719         .tmds = tegra20_tmds_config,
1720         .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1721         .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1722         .fuse_override_value = 1 << 31,
1723         .has_sor_io_peak_current = false,
1724         .has_hda = false,
1725         .has_hbr = false,
1726 };
1727
1728 static const struct tegra_hdmi_config tegra30_hdmi_config = {
1729         .tmds = tegra30_tmds_config,
1730         .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1731         .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1732         .fuse_override_value = 1 << 31,
1733         .has_sor_io_peak_current = false,
1734         .has_hda = true,
1735         .has_hbr = false,
1736 };
1737
1738 static const struct tegra_hdmi_config tegra114_hdmi_config = {
1739         .tmds = tegra114_tmds_config,
1740         .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1741         .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1742         .fuse_override_value = 1 << 31,
1743         .has_sor_io_peak_current = true,
1744         .has_hda = true,
1745         .has_hbr = true,
1746 };
1747
1748 static const struct tegra_hdmi_config tegra124_hdmi_config = {
1749         .tmds = tegra124_tmds_config,
1750         .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1751         .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1752         .fuse_override_value = 1 << 31,
1753         .has_sor_io_peak_current = true,
1754         .has_hda = true,
1755         .has_hbr = true,
1756 };
1757
1758 static const struct of_device_id tegra_hdmi_of_match[] = {
1759         { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1760         { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1761         { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1762         { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1763         { },
1764 };
1765 MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
1766
1767 static irqreturn_t tegra_hdmi_irq(int irq, void *data)
1768 {
1769         struct tegra_hdmi *hdmi = data;
1770         u32 value;
1771
1772         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
1773         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
1774
1775         if (value & INT_CODEC_SCRATCH0) {
1776                 unsigned int format;
1777                 u32 value;
1778
1779                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1780
1781                 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
1782                         format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
1783
1784                         tegra_hda_parse_format(format, &hdmi->format);
1785                         tegra_hdmi_reconfigure_audio(hdmi);
1786                 } else {
1787                         tegra_hdmi_disable_audio_infoframe(hdmi);
1788                         tegra_hdmi_disable_audio(hdmi);
1789                 }
1790         }
1791
1792         return IRQ_HANDLED;
1793 }
1794
1795 static int tegra_hdmi_probe(struct platform_device *pdev)
1796 {
1797         struct tegra_hdmi *hdmi;
1798         int err;
1799
1800         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1801         if (!hdmi)
1802                 return -ENOMEM;
1803
1804         hdmi->config = of_device_get_match_data(&pdev->dev);
1805         hdmi->dev = &pdev->dev;
1806
1807         hdmi->audio_source = AUTO;
1808         hdmi->stereo = false;
1809         hdmi->dvi = false;
1810
1811         mutex_init(&hdmi->audio_lock);
1812
1813         hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1814         if (IS_ERR(hdmi->clk)) {
1815                 dev_err(&pdev->dev, "failed to get clock\n");
1816                 return PTR_ERR(hdmi->clk);
1817         }
1818
1819         hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1820         if (IS_ERR(hdmi->rst)) {
1821                 dev_err(&pdev->dev, "failed to get reset\n");
1822                 return PTR_ERR(hdmi->rst);
1823         }
1824
1825         hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1826         if (IS_ERR(hdmi->clk_parent))
1827                 return PTR_ERR(hdmi->clk_parent);
1828
1829         err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1830         if (err < 0) {
1831                 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1832                 return err;
1833         }
1834
1835         hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1836         err = PTR_ERR_OR_ZERO(hdmi->hdmi);
1837         if (err)
1838                 return dev_err_probe(&pdev->dev, err,
1839                                      "failed to get HDMI regulator\n");
1840
1841         hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1842         err = PTR_ERR_OR_ZERO(hdmi->pll);
1843         if (err)
1844                 return dev_err_probe(&pdev->dev, err,
1845                                      "failed to get PLL regulator\n");
1846
1847         hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1848         err = PTR_ERR_OR_ZERO(hdmi->vdd);
1849         if (err)
1850                 return dev_err_probe(&pdev->dev, err,
1851                                      "failed to get VDD regulator\n");
1852
1853         hdmi->output.dev = &pdev->dev;
1854
1855         err = tegra_output_probe(&hdmi->output);
1856         if (err < 0)
1857                 return err;
1858
1859         hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
1860         if (IS_ERR(hdmi->regs)) {
1861                 err = PTR_ERR(hdmi->regs);
1862                 goto remove;
1863         }
1864
1865         err = platform_get_irq(pdev, 0);
1866         if (err < 0)
1867                 goto remove;
1868
1869         hdmi->irq = err;
1870
1871         err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
1872                                dev_name(hdmi->dev), hdmi);
1873         if (err < 0) {
1874                 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
1875                         hdmi->irq, err);
1876                 goto remove;
1877         }
1878
1879         platform_set_drvdata(pdev, hdmi);
1880
1881         err = devm_pm_runtime_enable(&pdev->dev);
1882         if (err)
1883                 goto remove;
1884
1885         err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
1886         if (err)
1887                 goto remove;
1888
1889         INIT_LIST_HEAD(&hdmi->client.list);
1890         hdmi->client.ops = &hdmi_client_ops;
1891         hdmi->client.dev = &pdev->dev;
1892
1893         err = host1x_client_register(&hdmi->client);
1894         if (err < 0) {
1895                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1896                         err);
1897                 goto remove;
1898         }
1899
1900         return 0;
1901
1902 remove:
1903         tegra_output_remove(&hdmi->output);
1904         return err;
1905 }
1906
1907 static void tegra_hdmi_remove(struct platform_device *pdev)
1908 {
1909         struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1910
1911         host1x_client_unregister(&hdmi->client);
1912
1913         tegra_output_remove(&hdmi->output);
1914 }
1915
1916 struct platform_driver tegra_hdmi_driver = {
1917         .driver = {
1918                 .name = "tegra-hdmi",
1919                 .of_match_table = tegra_hdmi_of_match,
1920         },
1921         .probe = tegra_hdmi_probe,
1922         .remove = tegra_hdmi_remove,
1923 };