2 * Copyright 2022 Advanced Micro Devices, Inc.
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26 #ifndef __DC_LINK_DP_PHY_H__
27 #define __DC_LINK_DP_PHY_H__
30 void dp_enable_link_phy(
32 const struct link_resource *link_res,
33 enum signal_type signal,
34 enum clock_source_id clock_source,
35 const struct dc_link_settings *link_settings);
37 void dp_disable_link_phy(struct dc_link *link,
38 const struct link_resource *link_res,
39 enum signal_type signal);
41 void dp_set_hw_lane_settings(
43 const struct link_resource *link_res,
44 const struct link_training_settings *link_settings,
47 void dp_set_drive_settings(
49 const struct link_resource *link_res,
50 struct link_training_settings *lt_settings);
52 enum dc_status dp_set_fec_ready(struct dc_link *link,
53 const struct link_resource *link_res, bool ready);
55 void dp_set_fec_enable(struct dc_link *link, bool enable);
57 void dpcd_write_rx_power_ctrl(struct dc_link *link, bool on);
59 #endif /* __DC_LINK_DP_PHY_H__ */