drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dc.h"
  27 #include "dc_dmub_srv.h"
  28 #include "../dmub/dmub_srv.h"
  29 #include "dm_helpers.h"
  30 #include "dc_hw_types.h"
  31 #include "core_types.h"
  32 #include "../basics/conversion.h"
  33 #include "cursor_reg_cache.h"
  34 #include "resource.h"
  35 #include "clk_mgr.h"
  36 #include "dc_state_priv.h"
  37
  38 #define CTX dc_dmub_srv->ctx
  39 #define DC_LOGGER CTX->logger
  40
  41 static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc,
  42                                   struct dmub_srv *dmub)
  43 {
  44         dc_srv->dmub = dmub;
  45         dc_srv->ctx = dc->ctx;
  46 }
  47
  48 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)
  49 {
  50         struct dc_dmub_srv *dc_srv =
  51                 kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL);
  52
  53         if (dc_srv == NULL) {
  54                 BREAK_TO_DEBUGGER();
  55                 return NULL;
  56         }
  57
  58         dc_dmub_srv_construct(dc_srv, dc, dmub);
  59
  60         return dc_srv;
  61 }
  62
  63 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)
  64 {
  65         if (*dmub_srv) {
  66                 kfree(*dmub_srv);
  67                 *dmub_srv = NULL;
  68         }
  69 }
  70
  71 void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
  72 {
  73         struct dmub_srv *dmub = dc_dmub_srv->dmub;
  74         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
  75         enum dmub_status status;
  76
  77         status = dmub_srv_wait_for_idle(dmub, 100000);
  78         if (status != DMUB_STATUS_OK) {
  79                 DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
  80                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
  81         }
  82 }
  83
  84 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv)
  85 {
  86         struct dmub_srv *dmub = dc_dmub_srv->dmub;
  87         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
  88         enum dmub_status status = DMUB_STATUS_OK;
  89
  90         status = dmub_srv_clear_inbox0_ack(dmub);
  91         if (status != DMUB_STATUS_OK) {
  92                 DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status);
  93                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
  94         }
  95 }
  96
  97 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv)
  98 {
  99         struct dmub_srv *dmub = dc_dmub_srv->dmub;
 100         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
 101         enum dmub_status status = DMUB_STATUS_OK;
 102
 103         status = dmub_srv_wait_for_inbox0_ack(dmub, 100000);
 104         if (status != DMUB_STATUS_OK) {
 105                 DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n");
 106                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 107         }
 108 }
 109
 110 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dc_dmub_srv,
 111                                  union dmub_inbox0_data_register data)
 112 {
 113         struct dmub_srv *dmub = dc_dmub_srv->dmub;
 114         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
 115         enum dmub_status status = DMUB_STATUS_OK;
 116
 117         status = dmub_srv_send_inbox0_cmd(dmub, data);
 118         if (status != DMUB_STATUS_OK) {
 119                 DC_ERROR("Error sending INBOX0 cmd\n");
 120                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 121         }
 122 }
 123
 124 bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,
 125                 unsigned int count,
 126                 union dmub_rb_cmd *cmd_list)
 127 {
 128         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
 129         struct dmub_srv *dmub;
 130         enum dmub_status status;
 131         int i;
 132
 133         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 134                 return false;
 135
 136         dmub = dc_dmub_srv->dmub;
 137
 138         for (i = 0 ; i < count; i++) {
 139                 // Queue command
 140                 status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 141
 142                 if (status == DMUB_STATUS_QUEUE_FULL) {
 143                         /* Execute and wait for queue to become empty again. */
 144                         status = dmub_srv_cmd_execute(dmub);
 145                         if (status == DMUB_STATUS_POWER_STATE_D3)
 146                                 return false;
 147
 148                         dmub_srv_wait_for_idle(dmub, 100000);
 149
 150                         /* Requeue the command. */
 151                         status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 152                 }
 153
 154                 if (status != DMUB_STATUS_OK) {
 155                         if (status != DMUB_STATUS_POWER_STATE_D3) {
 156                                 DC_ERROR("Error queueing DMUB command: status=%d\n", status);
 157                                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 158                         }
 159                         return false;
 160                 }
 161         }
 162
 163         status = dmub_srv_cmd_execute(dmub);
 164         if (status != DMUB_STATUS_OK) {
 165                 if (status != DMUB_STATUS_POWER_STATE_D3) {
 166                         DC_ERROR("Error starting DMUB execution: status=%d\n", status);
 167                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 168                 }
 169                 return false;
 170         }
 171
 172         return true;
 173 }
 174
 175 bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv,
 176                 enum dm_dmub_wait_type wait_type,
 177                 union dmub_rb_cmd *cmd_list)
 178 {
 179         struct dmub_srv *dmub;
 180         enum dmub_status status;
 181
 182         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 183                 return false;
 184
 185         dmub = dc_dmub_srv->dmub;
 186
 187         // Wait for DMUB to process command
 188         if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) {
 189                 status = dmub_srv_wait_for_idle(dmub, 100000);
 190
 191                 if (status != DMUB_STATUS_OK) {
 192                         DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);
 193                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 194                         return false;
 195                 }
 196
 197                 // Copy data back from ring buffer into command
 198                 if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)
 199                         dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list);
 200         }
 201
 202         return true;
 203 }
 204
 205 bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
 206 {
 207         return dc_dmub_srv_cmd_run_list(dc_dmub_srv, 1, cmd, wait_type);
 208 }
 209
 210 bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type)
 211 {
 212         struct dc_context *dc_ctx;
 213         struct dmub_srv *dmub;
 214         enum dmub_status status;
 215         int i;
 216
 217         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 218                 return false;
 219
 220         dc_ctx = dc_dmub_srv->ctx;
 221         dmub = dc_dmub_srv->dmub;
 222
 223         for (i = 0 ; i < count; i++) {
 224                 // Queue command
 225                 status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 226
 227                 if (status == DMUB_STATUS_QUEUE_FULL) {
 228                         /* Execute and wait for queue to become empty again. */
 229                         status = dmub_srv_cmd_execute(dmub);
 230                         if (status == DMUB_STATUS_POWER_STATE_D3)
 231                                 return false;
 232
 233                         dmub_srv_wait_for_idle(dmub, 100000);
 234
 235                         /* Requeue the command. */
 236                         status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 237                 }
 238
 239                 if (status != DMUB_STATUS_OK) {
 240                         if (status != DMUB_STATUS_POWER_STATE_D3) {
 241                                 DC_ERROR("Error queueing DMUB command: status=%d\n", status);
 242                                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 243                         }
 244                         return false;
 245                 }
 246         }
 247
 248         status = dmub_srv_cmd_execute(dmub);
 249         if (status != DMUB_STATUS_OK) {
 250                 if (status != DMUB_STATUS_POWER_STATE_D3) {
 251                         DC_ERROR("Error starting DMUB execution: status=%d\n", status);
 252                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 253                 }
 254                 return false;
 255         }
 256
 257         // Wait for DMUB to process command
 258         if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) {
 259                 if (dc_dmub_srv->ctx->dc->debug.disable_timeout) {
 260                         do {
 261                                 status = dmub_srv_wait_for_idle(dmub, 100000);
 262                         } while (status != DMUB_STATUS_OK);
 263                 } else
 264                         status = dmub_srv_wait_for_idle(dmub, 100000);
 265
 266                 if (status != DMUB_STATUS_OK) {
 267                         DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);
 268                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 269                         return false;
 270                 }
 271
 272                 // Copy data back from ring buffer into command
 273                 if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)
 274                         dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list);
 275         }
 276
 277         return true;
 278 }
 279
 280 bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)
 281 {
 282         struct dmub_srv *dmub;
 283         struct dc_context *dc_ctx;
 284         union dmub_fw_boot_status boot_status;
 285         enum dmub_status status;
 286
 287         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 288                 return false;
 289
 290         dmub = dc_dmub_srv->dmub;
 291         dc_ctx = dc_dmub_srv->ctx;
 292
 293         status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
 294         if (status != DMUB_STATUS_OK) {
 295                 DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
 296                 return false;
 297         }
 298
 299         return boot_status.bits.optimized_init_done;
 300 }
 301
 302 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
 303                                     unsigned int stream_mask)
 304 {
 305         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 306                 return false;
 307
 308         return dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,
 309                                          stream_mask, NULL, DM_DMUB_WAIT_TYPE_WAIT);
 310 }
 311
 312 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
 313 {
 314         struct dmub_srv *dmub;
 315         struct dc_context *dc_ctx;
 316         union dmub_fw_boot_status boot_status;
 317         enum dmub_status status;
 318
 319         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 320                 return false;
 321
 322         dmub = dc_dmub_srv->dmub;
 323         dc_ctx = dc_dmub_srv->ctx;
 324
 325         status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
 326         if (status != DMUB_STATUS_OK) {
 327                 DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
 328                 return false;
 329         }
 330
 331         return boot_status.bits.restore_required;
 332 }
 333
 334 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)
 335 {
 336         struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;
 337         return dmub_srv_get_outbox0_msg(dmub, entry);
 338 }
 339
 340 void dc_dmub_trace_event_control(struct dc *dc, bool enable)
 341 {
 342         dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);
 343 }
 344
 345 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max)
 346 {
 347         union dmub_rb_cmd cmd = { 0 };
 348
 349         cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 350         cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE;
 351         cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max;
 352         cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min;
 353         cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
 354
 355         cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
 356
 357         // Send the command to the DMCUB.
 358         dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 359 }
 360
 361 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)
 362 {
 363         union dmub_rb_cmd cmd = { 0 };
 364
 365         cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 366         cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER;
 367         cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
 368
 369         cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
 370
 371         // Send the command to the DMCUB.
 372         dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 373 }
 374
 375 static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)
 376 {
 377         uint8_t pipes = 0;
 378         int i = 0;
 379
 380         for (i = 0; i < MAX_PIPES; i++) {
 381                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 382
 383                 if (pipe->stream == stream && pipe->stream_res.tg)
 384                         pipes = i;
 385         }
 386         return pipes;
 387 }
 388
 389 static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context,
 390                 struct pipe_ctx *head_pipe,
 391                 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data)
 392 {
 393         int j;
 394         int pipe_idx = 0;
 395
 396         fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst;
 397         for (j = 0; j < dc->res_pool->pipe_count; j++) {
 398                 struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];
 399
 400                 if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) {
 401                         fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst;
 402                 }
 403         }
 404         fams_pipe_data->pipe_count = pipe_idx;
 405 }
 406
 407 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)
 408 {
 409         union dmub_rb_cmd cmd = { 0 };
 410         struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data;
 411         int i = 0, k = 0;
 412         int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it.
 413         uint8_t visual_confirm_enabled;
 414         int pipe_idx = 0;
 415
 416         if (dc == NULL)
 417                 return false;
 418
 419         visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS;
 420
 421         // Format command.
 422         cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 423         cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL;
 424         cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate;
 425         cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled;
 426
 427         if (should_manage_pstate) {
 428                 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 429                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 430
 431                         if (!pipe->stream)
 432                                 continue;
 433
 434                         /* If FAMS is being used to support P-State and there is a stream
 435                          * that does not use FAMS, we are in an FPO + VActive scenario.
 436                          * Assign vactive stretch margin in this case.
 437                          */
 438                         if (!pipe->stream->fpo_in_use) {
 439                                 cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us;
 440                                 break;
 441                         }
 442                         pipe_idx++;
 443                 }
 444         }
 445
 446         for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {
 447                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 448
 449                 if (resource_is_pipe_type(pipe, OTG_MASTER) && pipe->stream->fpo_in_use) {
 450                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 451                         uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000;
 452
 453                         config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;
 454                         config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz;
 455                         config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps;
 456                         config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);
 457                         dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);
 458                         k++;
 459                 }
 460         }
 461         cmd.fw_assisted_mclk_switch.header.payload_bytes =
 462                 sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header);
 463
 464         // Send the command to the DMCUB.
 465         dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 466
 467         return true;
 468 }
 469
 470 void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv)
 471 {
 472         union dmub_rb_cmd cmd = { 0 };
 473
 474         if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)
 475                 return;
 476
 477         memset(&cmd, 0, sizeof(cmd));
 478
 479         /* Prepare fw command */
 480         cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS;
 481         cmd.query_feature_caps.header.sub_type = 0;
 482         cmd.query_feature_caps.header.ret_status = 1;
 483         cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data);
 484
 485         /* If command was processed, copy feature caps to dmub srv */
 486         if (dc_wake_and_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
 487             cmd.query_feature_caps.header.ret_status == 0) {
 488                 memcpy(&dc_dmub_srv->dmub->feature_caps,
 489                        &cmd.query_feature_caps.query_feature_caps_data,
 490                        sizeof(struct dmub_feature_caps));
 491         }
 492 }
 493
 494 void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)
 495 {
 496         union dmub_rb_cmd cmd = { 0 };
 497         unsigned int panel_inst = 0;
 498
 499         dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst);
 500
 501         memset(&cmd, 0, sizeof(cmd));
 502
 503         // Prepare fw command
 504         cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR;
 505         cmd.visual_confirm_color.header.sub_type = 0;
 506         cmd.visual_confirm_color.header.ret_status = 1;
 507         cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data);
 508         cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst;
 509
 510         // If command was processed, copy feature caps to dmub srv
 511         if (dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
 512                 cmd.visual_confirm_color.header.ret_status == 0) {
 513                 memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,
 514                         &cmd.visual_confirm_color.visual_confirm_color_data,
 515                         sizeof(struct dmub_visual_confirm_color));
 516         }
 517 }
 518
 519 /**
 520  * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command
 521  *
 522  * @dc: [in] pointer to dc object
 523  * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
 524  * @vblank_pipe: [in] pipe_ctx for the DRR pipe
 525  * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info
 526  * @context: [in] DC state for access to phantom stream
 527  *
 528  * Populate the DMCUB SubVP command with DRR pipe info. All the information
 529  * required for calculating the SubVP + DRR microschedule is populated here.
 530  *
 531  * High level algorithm:
 532  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
 533  * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule
 534  * 3. Populate the drr_info with the min and max supported vtotal values
 535  */
 536 static void populate_subvp_cmd_drr_info(struct dc *dc,
 537                 struct dc_state *context,
 538                 struct pipe_ctx *subvp_pipe,
 539                 struct pipe_ctx *vblank_pipe,
 540                 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data)
 541 {
 542         struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe->stream);
 543         struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
 544         struct dc_crtc_timing *phantom_timing = &phantom_stream->timing;
 545         struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing;
 546         uint16_t drr_frame_us = 0;
 547         uint16_t min_drr_supported_us = 0;
 548         uint16_t max_drr_supported_us = 0;
 549         uint16_t max_drr_vblank_us = 0;
 550         uint16_t max_drr_mallregion_us = 0;
 551         uint16_t mall_region_us = 0;
 552         uint16_t prefetch_us = 0;
 553         uint16_t subvp_active_us = 0;
 554         uint16_t drr_active_us = 0;
 555         uint16_t min_vtotal_supported = 0;
 556         uint16_t max_vtotal_supported = 0;
 557
 558         pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true;
 559         pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping
 560         pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now
 561
 562         drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000),
 563                         (((uint64_t)drr_timing->pix_clk_100hz * 100)));
 564         // P-State allow width and FW delays already included phantom_timing->v_addressable
 565         mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000),
 566                         (((uint64_t)phantom_timing->pix_clk_100hz * 100)));
 567         min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
 568         min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us),
 569                         (((uint64_t)drr_timing->h_total * 1000000)));
 570
 571         prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000),
 572                         (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
 573         subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000),
 574                         (((uint64_t)main_timing->pix_clk_100hz * 100)));
 575         drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000),
 576                         (((uint64_t)drr_timing->pix_clk_100hz * 100)));
 577         max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us -
 578                         dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us;
 579         max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us;
 580         max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us;
 581         max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us),
 582                         (((uint64_t)drr_timing->h_total * 1000000)));
 583
 584         /* When calculating the max vtotal supported for SubVP + DRR cases, add
 585          * margin due to possible rounding errors (being off by 1 line in the
 586          * FW calculation can incorrectly push the P-State switch to wait 1 frame
 587          * longer).
 588          */
 589         max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us;
 590
 591         pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
 592         pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
 593         pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us;
 594 }
 595
 596 /**
 597  * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command
 598  *
 599  * @dc: [in] current dc state
 600  * @context: [in] new dc state
 601  * @cmd: [in] DMUB cmd to be populated with SubVP info
 602  * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe
 603  * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
 604  *
 605  * Populate the DMCUB SubVP command with VBLANK pipe info. All the information
 606  * required to calculate the microschedule for SubVP + VBLANK case is stored in
 607  * the pipe_data (subvp_data and vblank_data).  Also check if the VBLANK pipe
 608  * is a DRR display -- if it is make a call to populate drr_info.
 609  */
 610 static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc,
 611                 struct dc_state *context,
 612                 union dmub_rb_cmd *cmd,
 613                 struct pipe_ctx *vblank_pipe,
 614                 uint8_t cmd_pipe_index)
 615 {
 616         uint32_t i;
 617         struct pipe_ctx *pipe = NULL;
 618         struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
 619                         &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
 620
 621         // Find the SubVP pipe
 622         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 623                 pipe = &context->res_ctx.pipe_ctx[i];
 624
 625                 // We check for master pipe, but it shouldn't matter since we only need
 626                 // the pipe for timing info (stream should be same for any pipe splits)
 627                 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
 628                                 !resource_is_pipe_type(pipe, DPP_PIPE))
 629                         continue;
 630
 631                 // Find the SubVP pipe
 632                 if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)
 633                         break;
 634         }
 635
 636         pipe_data->mode = VBLANK;
 637         pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz;
 638         pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total -
 639                                                         vblank_pipe->stream->timing.v_front_porch;
 640         pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total;
 641         pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total;
 642         pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx;
 643         pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start;
 644         pipe_data->pipe_config.vblank_data.vblank_end =
 645                         vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable;
 646
 647         if (vblank_pipe->stream->ignore_msa_timing_param &&
 648                 (vblank_pipe->stream->allow_freesync || vblank_pipe->stream->vrr_active_variable || vblank_pipe->stream->vrr_active_fixed))
 649                 populate_subvp_cmd_drr_info(dc, context, pipe, vblank_pipe, pipe_data);
 650 }
 651
 652 /**
 653  * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case
 654  *
 655  * @dc: [in] current dc state
 656  * @context: [in] new dc state
 657  * @cmd: [in] DMUB cmd to be populated with SubVP info
 658  * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2)
 659  *
 660  * For SubVP + SubVP, we use a single vertical interrupt to start the
 661  * microschedule for both SubVP pipes. In order for this to work correctly, the
 662  * MALL REGION of both SubVP pipes must start at the same time. This function
 663  * lengthens the prefetch end to mall start delay of the SubVP pipe that has
 664  * the shorter prefetch so that both MALL REGION's will start at the same time.
 665  */
 666 static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
 667                 struct dc_state *context,
 668                 union dmub_rb_cmd *cmd,
 669                 struct pipe_ctx *subvp_pipes[])
 670 {
 671         uint32_t subvp0_prefetch_us = 0;
 672         uint32_t subvp1_prefetch_us = 0;
 673         uint32_t prefetch_delta_us = 0;
 674         struct dc_stream_state *phantom_stream0 = NULL;
 675         struct dc_stream_state *phantom_stream1 = NULL;
 676         struct dc_crtc_timing *phantom_timing0 = NULL;
 677         struct dc_crtc_timing *phantom_timing1 = NULL;
 678         struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL;
 679
 680         phantom_stream0 = dc_state_get_paired_subvp_stream(context, subvp_pipes[0]->stream);
 681         phantom_stream1 = dc_state_get_paired_subvp_stream(context, subvp_pipes[1]->stream);
 682         phantom_timing0 = &phantom_stream0->timing;
 683         phantom_timing1 = &phantom_stream1->timing;
 684
 685         subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) *
 686                         (uint64_t)phantom_timing0->h_total * 1000000),
 687                         (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
 688         subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) *
 689                         (uint64_t)phantom_timing1->h_total * 1000000),
 690                         (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
 691
 692         // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time)
 693         // should increase it's prefetch time to match the other
 694         if (subvp0_prefetch_us > subvp1_prefetch_us) {
 695                 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1];
 696                 prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us;
 697                 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
 698                                 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
 699                                         ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)),
 700                                         ((uint64_t)phantom_timing1->h_total * 1000000));
 701
 702         } else if (subvp1_prefetch_us >  subvp0_prefetch_us) {
 703                 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0];
 704                 prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us;
 705                 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
 706                                 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
 707                                         ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)),
 708                                         ((uint64_t)phantom_timing0->h_total * 1000000));
 709         }
 710 }
 711
 712 /**
 713  * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command
 714  *
 715  * @dc: [in] current dc state
 716  * @context: [in] new dc state
 717  * @cmd: [in] DMUB cmd to be populated with SubVP info
 718  * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
 719  * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
 720  *
 721  * Populate the DMCUB SubVP command with SubVP pipe info. All the information
 722  * required to calculate the microschedule for the SubVP pipe is stored in the
 723  * pipe_data of the DMCUB SubVP command.
 724  */
 725 static void populate_subvp_cmd_pipe_info(struct dc *dc,
 726                 struct dc_state *context,
 727                 union dmub_rb_cmd *cmd,
 728                 struct pipe_ctx *subvp_pipe,
 729                 uint8_t cmd_pipe_index)
 730 {
 731         uint32_t j;
 732         struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
 733                         &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
 734         struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe->stream);
 735         struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
 736         struct dc_crtc_timing *phantom_timing = &phantom_stream->timing;
 737         uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den;
 738
 739         pipe_data->mode = SUBVP;
 740         pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz;
 741         pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total;
 742         pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total;
 743         pipe_data->pipe_config.subvp_data.main_vblank_start =
 744                         main_timing->v_total - main_timing->v_front_porch;
 745         pipe_data->pipe_config.subvp_data.main_vblank_end =
 746                         main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable;
 747         pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;
 748         pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst;
 749         pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param &&
 750                 (subvp_pipe->stream->allow_freesync || subvp_pipe->stream->vrr_active_variable || subvp_pipe->stream->vrr_active_fixed);
 751
 752         /* Calculate the scaling factor from the src and dst height.
 753          * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2.
 754          * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor"
 755          *
 756          * Make sure to combine stream and plane scaling together.
 757          */
 758         reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height,
 759                         &out_num_stream, &out_den_stream);
 760         reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height,
 761                         &out_num_plane, &out_den_plane);
 762         reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den);
 763         pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num;
 764         pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den;
 765
 766         // Prefetch lines is equal to VACTIVE + BP + VSYNC
 767         pipe_data->pipe_config.subvp_data.prefetch_lines =
 768                         phantom_timing->v_total - phantom_timing->v_front_porch;
 769
 770         // Round up
 771         pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
 772                         div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
 773                                         ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
 774         pipe_data->pipe_config.subvp_data.processing_delay_lines =
 775                         div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
 776                                         ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
 777
 778         if (subvp_pipe->bottom_pipe) {
 779                 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx;
 780         } else if (subvp_pipe->next_odm_pipe) {
 781                 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx;
 782         } else {
 783                 pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0;
 784         }
 785
 786         // Find phantom pipe index based on phantom stream
 787         for (j = 0; j < dc->res_pool->pipe_count; j++) {
 788                 struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];
 789
 790                 if (phantom_pipe->stream == dc_state_get_paired_subvp_stream(context, subvp_pipe->stream)) {
 791                         pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst;
 792                         if (phantom_pipe->bottom_pipe) {
 793                                 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst;
 794                         } else if (phantom_pipe->next_odm_pipe) {
 795                                 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst;
 796                         } else {
 797                                 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0;
 798                         }
 799                         break;
 800                 }
 801         }
 802 }
 803
 804 /**
 805  * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command
 806  *
 807  * @dc: [in] current dc state
 808  * @context: [in] new dc state
 809  * @enable: [in] if true enables the pipes population
 810  *
 811  * This function loops through each pipe and populates the DMUB SubVP CMD info
 812  * based on the pipe (e.g. SubVP, VBLANK).
 813  */
 814 void dc_dmub_setup_subvp_dmub_command(struct dc *dc,
 815                 struct dc_state *context,
 816                 bool enable)
 817 {
 818         uint8_t cmd_pipe_index = 0;
 819         uint32_t i, pipe_idx;
 820         uint8_t subvp_count = 0;
 821         union dmub_rb_cmd cmd;
 822         struct pipe_ctx *subvp_pipes[2];
 823         uint32_t wm_val_refclk = 0;
 824         enum mall_stream_type pipe_mall_type;
 825
 826         memset(&cmd, 0, sizeof(cmd));
 827         // FW command for SUBVP
 828         cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 829         cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD;
 830         cmd.fw_assisted_mclk_switch_v2.header.payload_bytes =
 831                         sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header);
 832
 833         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 834                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 835
 836                 /* For SubVP pipe count, only count the top most (ODM / MPC) pipe
 837                  */
 838                 if (resource_is_pipe_type(pipe, OTG_MASTER) &&
 839                                 resource_is_pipe_type(pipe, DPP_PIPE) &&
 840                                 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)
 841                         subvp_pipes[subvp_count++] = pipe;
 842         }
 843
 844         if (enable) {
 845                 // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd
 846                 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 847                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 848                         pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);
 849
 850                         if (!pipe->stream)
 851                                 continue;
 852
 853                         /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe.
 854                          * Any ODM or MPC splits being used in SubVP will be handled internally in
 855                          * populate_subvp_cmd_pipe_info
 856                          */
 857                         if (resource_is_pipe_type(pipe, OTG_MASTER) &&
 858                                         resource_is_pipe_type(pipe, DPP_PIPE) &&
 859                                         pipe_mall_type == SUBVP_MAIN) {
 860                                 populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
 861                         } else if (resource_is_pipe_type(pipe, OTG_MASTER) &&
 862                                         resource_is_pipe_type(pipe, DPP_PIPE) &&
 863                                         pipe_mall_type == SUBVP_NONE) {
 864                                 // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where
 865                                 // we run through DML without calculating "natural" P-state support
 866                                 populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
 867
 868                         }
 869                         pipe_idx++;
 870                 }
 871                 if (subvp_count == 2) {
 872                         update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes);
 873                 }
 874                 cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
 875                 cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us;
 876
 877                 // Store the original watermark value for this SubVP config so we can lower it when the
 878                 // MCLK switch starts
 879                 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns *
 880                                 (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000;
 881
 882                 cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF;
 883         }
 884
 885         dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 886 }
 887
 888 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)
 889 {
 890         if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data)
 891                 return false;
 892         return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data);
 893 }
 894
 895 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)
 896 {
 897         struct dmub_diagnostic_data diag_data = {0};
 898
 899         if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
 900                 DC_LOG_ERROR("%s: invalid parameters.", __func__);
 901                 return;
 902         }
 903
 904         if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) {
 905                 DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__);
 906                 return;
 907         }
 908
 909         DC_LOG_DEBUG("DMCUB STATE:");
 910         DC_LOG_DEBUG("    dmcub_version      : %08x", diag_data.dmcub_version);
 911         DC_LOG_DEBUG("    scratch  [0]       : %08x", diag_data.scratch[0]);
 912         DC_LOG_DEBUG("    scratch  [1]       : %08x", diag_data.scratch[1]);
 913         DC_LOG_DEBUG("    scratch  [2]       : %08x", diag_data.scratch[2]);
 914         DC_LOG_DEBUG("    scratch  [3]       : %08x", diag_data.scratch[3]);
 915         DC_LOG_DEBUG("    scratch  [4]       : %08x", diag_data.scratch[4]);
 916         DC_LOG_DEBUG("    scratch  [5]       : %08x", diag_data.scratch[5]);
 917         DC_LOG_DEBUG("    scratch  [6]       : %08x", diag_data.scratch[6]);
 918         DC_LOG_DEBUG("    scratch  [7]       : %08x", diag_data.scratch[7]);
 919         DC_LOG_DEBUG("    scratch  [8]       : %08x", diag_data.scratch[8]);
 920         DC_LOG_DEBUG("    scratch  [9]       : %08x", diag_data.scratch[9]);
 921         DC_LOG_DEBUG("    scratch [10]       : %08x", diag_data.scratch[10]);
 922         DC_LOG_DEBUG("    scratch [11]       : %08x", diag_data.scratch[11]);
 923         DC_LOG_DEBUG("    scratch [12]       : %08x", diag_data.scratch[12]);
 924         DC_LOG_DEBUG("    scratch [13]       : %08x", diag_data.scratch[13]);
 925         DC_LOG_DEBUG("    scratch [14]       : %08x", diag_data.scratch[14]);
 926         DC_LOG_DEBUG("    scratch [15]       : %08x", diag_data.scratch[15]);
 927         DC_LOG_DEBUG("    pc                 : %08x", diag_data.pc);
 928         DC_LOG_DEBUG("    unk_fault_addr     : %08x", diag_data.undefined_address_fault_addr);
 929         DC_LOG_DEBUG("    inst_fault_addr    : %08x", diag_data.inst_fetch_fault_addr);
 930         DC_LOG_DEBUG("    data_fault_addr    : %08x", diag_data.data_write_fault_addr);
 931         DC_LOG_DEBUG("    inbox1_rptr        : %08x", diag_data.inbox1_rptr);
 932         DC_LOG_DEBUG("    inbox1_wptr        : %08x", diag_data.inbox1_wptr);
 933         DC_LOG_DEBUG("    inbox1_size        : %08x", diag_data.inbox1_size);
 934         DC_LOG_DEBUG("    inbox0_rptr        : %08x", diag_data.inbox0_rptr);
 935         DC_LOG_DEBUG("    inbox0_wptr        : %08x", diag_data.inbox0_wptr);
 936         DC_LOG_DEBUG("    inbox0_size        : %08x", diag_data.inbox0_size);
 937         DC_LOG_DEBUG("    is_enabled         : %d", diag_data.is_dmcub_enabled);
 938         DC_LOG_DEBUG("    is_soft_reset      : %d", diag_data.is_dmcub_soft_reset);
 939         DC_LOG_DEBUG("    is_secure_reset    : %d", diag_data.is_dmcub_secure_reset);
 940         DC_LOG_DEBUG("    is_traceport_en    : %d", diag_data.is_traceport_en);
 941         DC_LOG_DEBUG("    is_cw0_en          : %d", diag_data.is_cw0_enabled);
 942         DC_LOG_DEBUG("    is_cw6_en          : %d", diag_data.is_cw6_enabled);
 943 }
 944
 945 static bool dc_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
 946 {
 947         struct pipe_ctx *test_pipe, *split_pipe;
 948         const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data;
 949         struct rect r1 = scl_data->recout, r2, r2_half;
 950         int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b;
 951         int cur_layer = pipe_ctx->plane_state->layer_index;
 952
 953         /**
 954          * Disable the cursor if there's another pipe above this with a
 955          * plane that contains this pipe's viewport to prevent double cursor
 956          * and incorrect scaling artifacts.
 957          */
 958         for (test_pipe = pipe_ctx->top_pipe; test_pipe;
 959              test_pipe = test_pipe->top_pipe) {
 960                 // Skip invisible layer and pipe-split plane on same layer
 961                 if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer)
 962                         continue;
 963
 964                 r2 = test_pipe->plane_res.scl_data.recout;
 965                 r2_r = r2.x + r2.width;
 966                 r2_b = r2.y + r2.height;
 967                 split_pipe = test_pipe;
 968
 969                 /**
 970                  * There is another half plane on same layer because of
 971                  * pipe-split, merge together per same height.
 972                  */
 973                 for (split_pipe = pipe_ctx->top_pipe; split_pipe;
 974                      split_pipe = split_pipe->top_pipe)
 975                         if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) {
 976                                 r2_half = split_pipe->plane_res.scl_data.recout;
 977                                 r2.x = (r2_half.x < r2.x) ? r2_half.x : r2.x;
 978                                 r2.width = r2.width + r2_half.width;
 979                                 r2_r = r2.x + r2.width;
 980                                 break;
 981                         }
 982
 983                 if (r1.x >= r2.x && r1.y >= r2.y && r1_r <= r2_r && r1_b <= r2_b)
 984                         return true;
 985         }
 986
 987         return false;
 988 }
 989
 990 static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx)
 991 {
 992         if (pipe_ctx->plane_state != NULL) {
 993                 if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
 994                         return false;
 995
 996                 if (dc_can_pipe_disable_cursor(pipe_ctx))
 997                         return false;
 998         }
 999
1000         if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||
1001                 pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) &&
1002                 pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1)
1003                 return true;
1004
1005         if (pipe_ctx->stream->link->replay_settings.config.replay_supported)
1006                 return true;
1007
1008         return false;
1009 }
1010
1011 static void dc_build_cursor_update_payload0(
1012                 struct pipe_ctx *pipe_ctx, uint8_t p_idx,
1013                 struct dmub_cmd_update_cursor_payload0 *payload)
1014 {
1015         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1016         unsigned int panel_inst = 0;
1017
1018         if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,
1019                 pipe_ctx->stream->link, &panel_inst))
1020                 return;
1021
1022         /* Payload: Cursor Rect is built from position & attribute
1023          * x & y are obtained from postion
1024          */
1025         payload->cursor_rect.x = hubp->cur_rect.x;
1026         payload->cursor_rect.y = hubp->cur_rect.y;
1027         /* w & h are obtained from attribute */
1028         payload->cursor_rect.width  = hubp->cur_rect.w;
1029         payload->cursor_rect.height = hubp->cur_rect.h;
1030
1031         payload->enable      = hubp->pos.cur_ctl.bits.cur_enable;
1032         payload->pipe_idx    = p_idx;
1033         payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
1034         payload->panel_inst  = panel_inst;
1035 }
1036
1037 static void dc_build_cursor_position_update_payload0(
1038                 struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx,
1039                 const struct hubp *hubp, const struct dpp *dpp)
1040 {
1041         /* Hubp */
1042         pl->position_cfg.pHubp.cur_ctl.raw  = hubp->pos.cur_ctl.raw;
1043         pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw;
1044         pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw;
1045         pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw;
1046
1047         /* dpp */
1048         pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw;
1049         pl->position_cfg.pipe_idx = p_idx;
1050 }
1051
1052 static void dc_build_cursor_attribute_update_payload1(
1053                 struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx,
1054                 const struct hubp *hubp, const struct dpp *dpp)
1055 {
1056         /* Hubp */
1057         pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH;
1058         pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR;
1059         pl_A->aHubp.cur_ctl.raw  = hubp->att.cur_ctl.raw;
1060         pl_A->aHubp.size.raw     = hubp->att.size.raw;
1061         pl_A->aHubp.settings.raw = hubp->att.settings.raw;
1062
1063         /* dpp */
1064         pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw;
1065 }
1066
1067 /**
1068  * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command
1069  *
1070  * @pCtx: [in] pipe context
1071  * @pipe_idx: [in] pipe index
1072  *
1073  * This function would store the cursor related information and pass it into
1074  * dmub
1075  */
1076 void dc_send_update_cursor_info_to_dmu(
1077                 struct pipe_ctx *pCtx, uint8_t pipe_idx)
1078 {
1079         union dmub_rb_cmd cmd[2];
1080         union dmub_cmd_update_cursor_info_data *update_cursor_info_0 =
1081                                         &cmd[0].update_cursor_info.update_cursor_info_data;
1082
1083         memset(cmd, 0, sizeof(cmd));
1084
1085         if (!dc_dmub_should_update_cursor_data(pCtx))
1086                 return;
1087         /*
1088          * Since we use multi_cmd_pending for dmub command, the 2nd command is
1089          * only assigned to store cursor attributes info.
1090          * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other
1091          * is to store cursor position info.
1092          *
1093          * Command heaer type must be the same type if using  multi_cmd_pending.
1094          * Besides, while process 2nd command in DMU, the sub type is useless.
1095          * So it's meanless to pass the sub type header with different type.
1096          */
1097
1098         {
1099                 /* Build Payload#0 Header */
1100                 cmd[0].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1101                 cmd[0].update_cursor_info.header.payload_bytes =
1102                                 sizeof(cmd[0].update_cursor_info.update_cursor_info_data);
1103                 cmd[0].update_cursor_info.header.multi_cmd_pending = 1; //To combine multi dmu cmd, 1st cmd
1104
1105                 /* Prepare Payload */
1106                 dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info_0->payload0);
1107
1108                 dc_build_cursor_position_update_payload0(&update_cursor_info_0->payload0, pipe_idx,
1109                                 pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1110                 }
1111         {
1112                 /* Build Payload#1 Header */
1113                 cmd[1].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1114                 cmd[1].update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg);
1115                 cmd[1].update_cursor_info.header.multi_cmd_pending = 0; //Indicate it's the last command.
1116
1117                 dc_build_cursor_attribute_update_payload1(
1118                                 &cmd[1].update_cursor_info.update_cursor_info_data.payload1.attribute_cfg,
1119                                 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1120
1121                 /* Combine 2nd cmds update_curosr_info to DMU */
1122                 dc_wake_and_execute_dmub_cmd_list(pCtx->stream->ctx, 2, cmd, DM_DMUB_WAIT_TYPE_WAIT);
1123         }
1124 }
1125
1126 bool dc_dmub_check_min_version(struct dmub_srv *srv)
1127 {
1128         if (!srv->hw_funcs.is_psrsu_supported)
1129                 return true;
1130         return srv->hw_funcs.is_psrsu_supported(srv);
1131 }
1132
1133 void dc_dmub_srv_enable_dpia_trace(const struct dc *dc)
1134 {
1135         struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;
1136
1137         if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
1138                 DC_LOG_ERROR("%s: invalid parameters.", __func__);
1139                 return;
1140         }
1141
1142         if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1,
1143                                        0x0010, NULL, DM_DMUB_WAIT_TYPE_WAIT)) {
1144                 DC_LOG_ERROR("timeout updating trace buffer mask word\n");
1145                 return;
1146         }
1147
1148         if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK,
1149                                        0x0000, NULL, DM_DMUB_WAIT_TYPE_WAIT)) {
1150                 DC_LOG_ERROR("timeout updating trace buffer mask word\n");
1151                 return;
1152         }
1153
1154         DC_LOG_DEBUG("Enabled DPIA trace\n");
1155 }
1156
1157 void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index)
1158 {
1159         dmub_srv_subvp_save_surf_addr(dc_dmub_srv->dmub, addr, subvp_index);
1160 }
1161
1162 bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait)
1163 {
1164         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
1165         enum dmub_status status;
1166
1167         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
1168                 return true;
1169
1170         if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)
1171                 return true;
1172
1173         if (wait) {
1174                 if (dc_dmub_srv->ctx->dc->debug.disable_timeout) {
1175                         do {
1176                                 status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv->dmub, 500000);
1177                         } while (status != DMUB_STATUS_OK);
1178                 } else {
1179                         status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv->dmub, 500000);
1180                         if (status != DMUB_STATUS_OK) {
1181                                 DC_ERROR("Error querying DMUB hw power up status: error=%d\n", status);
1182                                 return false;
1183                         }
1184                 }
1185         } else
1186                 return dmub_srv_is_hw_pwr_up(dc_dmub_srv->dmub);
1187
1188         return true;
1189 }
1190
1191 static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)
1192 {
1193         union dmub_rb_cmd cmd = {0};
1194
1195         if (dc->debug.dmcub_emulation)
1196                 return;
1197
1198         memset(&cmd, 0, sizeof(cmd));
1199         cmd.idle_opt_notify_idle.header.type = DMUB_CMD__IDLE_OPT;
1200         cmd.idle_opt_notify_idle.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE;
1201         cmd.idle_opt_notify_idle.header.payload_bytes =
1202                 sizeof(cmd.idle_opt_notify_idle) -
1203                 sizeof(cmd.idle_opt_notify_idle.header);
1204
1205         cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle;
1206
1207         if (allow_idle) {
1208                 if (dc->hwss.set_idle_state)
1209                         dc->hwss.set_idle_state(dc, true);
1210         }
1211
1212         /* NOTE: This does not use the "wake" interface since this is part of the wake path. */
1213         /* We also do not perform a wait since DMCUB could enter idle after the notification. */
1214         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
1215 }
1216
1217 static void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
1218 {
1219         uint32_t allow_state = 0;
1220         uint32_t commit_state = 0;
1221
1222         if (dc->debug.dmcub_emulation)
1223                 return;
1224
1225         if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)
1226                 return;
1227
1228         if (dc->hwss.get_idle_state &&
1229                 dc->hwss.set_idle_state &&
1230                 dc->clk_mgr->funcs->exit_low_power_state) {
1231
1232                 allow_state = dc->hwss.get_idle_state(dc);
1233                 dc->hwss.set_idle_state(dc, false);
1234
1235                 if (!(allow_state & DMUB_IPS2_ALLOW_MASK)) {
1236                         // Wait for evaluation time
1237                         for (;;) {
1238                                 udelay(dc->debug.ips2_eval_delay_us);
1239                                 commit_state = dc->hwss.get_idle_state(dc);
1240                                 if (commit_state & DMUB_IPS2_ALLOW_MASK)
1241                                         break;
1242
1243                                 /* allow was still set, retry eval delay */
1244                                 dc->hwss.set_idle_state(dc, false);
1245                         }
1246
1247                         if (!(commit_state & DMUB_IPS2_COMMIT_MASK)) {
1248                                 // Tell PMFW to exit low power state
1249                                 dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
1250
1251                                 // Wait for IPS2 entry upper bound
1252                                 udelay(dc->debug.ips2_entry_delay_us);
1253                                 dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
1254
1255                                 for (;;) {
1256                                         commit_state = dc->hwss.get_idle_state(dc);
1257                                         if (commit_state & DMUB_IPS2_COMMIT_MASK)
1258                                                 break;
1259
1260                                         udelay(1);
1261                                 }
1262
1263                                 if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))
1264                                         ASSERT(0);
1265
1266                                 /* TODO: See if we can return early here - IPS2 should go
1267                                  * back directly to IPS0 and clear the flags, but it will
1268                                  * be safer to directly notify DMCUB of this.
1269                                  */
1270                                 allow_state = dc->hwss.get_idle_state(dc);
1271                         }
1272                 }
1273
1274                 dc_dmub_srv_notify_idle(dc, false);
1275                 if (!(allow_state & DMUB_IPS1_ALLOW_MASK)) {
1276                         for (;;) {
1277                                 commit_state = dc->hwss.get_idle_state(dc);
1278                                 if (commit_state & DMUB_IPS1_COMMIT_MASK)
1279                                         break;
1280
1281                                 udelay(1);
1282                         }
1283                 }
1284         }
1285
1286         if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))
1287                 ASSERT(0);
1288 }
1289
1290 void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state powerState)
1291 {
1292         struct dmub_srv *dmub;
1293
1294         if (!dc_dmub_srv)
1295                 return;
1296
1297         dmub = dc_dmub_srv->dmub;
1298
1299         if (powerState == DC_ACPI_CM_POWER_STATE_D0)
1300                 dmub_srv_set_power_state(dmub, DMUB_POWER_STATE_D0);
1301         else
1302                 dmub_srv_set_power_state(dmub, DMUB_POWER_STATE_D3);
1303 }
1304
1305 void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle)
1306 {
1307         struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;
1308
1309         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
1310                 return;
1311
1312         if (dc_dmub_srv->idle_allowed == allow_idle)
1313                 return;
1314
1315         /*
1316          * Entering a low power state requires a driver notification.
1317          * Powering up the hardware requires notifying PMFW and DMCUB.
1318          * Clearing the driver idle allow requires a DMCUB command.
1319          * DMCUB commands requires the DMCUB to be powered up and restored.
1320          *
1321          * Exit out early to prevent an infinite loop of DMCUB commands
1322          * triggering exit low power - use software state to track this.
1323          */
1324         dc_dmub_srv->idle_allowed = allow_idle;
1325
1326         if (!allow_idle)
1327                 dc_dmub_srv_exit_low_power_state(dc);
1328         else
1329                 dc_dmub_srv_notify_idle(dc, allow_idle);
1330 }
1331
1332 bool dc_wake_and_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd,
1333                                   enum dm_dmub_wait_type wait_type)
1334 {
1335         return dc_wake_and_execute_dmub_cmd_list(ctx, 1, cmd, wait_type);
1336 }
1337
1338 bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count,
1339                                        union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
1340 {
1341         struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;
1342         bool result = false, reallow_idle = false;
1343
1344         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
1345                 return false;
1346
1347         if (count == 0)
1348                 return true;
1349
1350         if (dc_dmub_srv->idle_allowed) {
1351                 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, false);
1352                 reallow_idle = true;
1353         }
1354
1355         /*
1356          * These may have different implementations in DM, so ensure
1357          * that we guide it to the expected helper.
1358          */
1359         if (count > 1)
1360                 result = dm_execute_dmub_cmd_list(ctx, count, cmd, wait_type);
1361         else
1362                 result = dm_execute_dmub_cmd(ctx, cmd, wait_type);
1363
1364         if (result && reallow_idle)
1365                 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true);
1366
1367         return result;
1368 }
1369
1370 static bool dc_dmub_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code,
1371                                   uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type)
1372 {
1373         struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;
1374         const uint32_t wait_us = wait_type == DM_DMUB_WAIT_TYPE_NO_WAIT ? 0 : 30;
1375         enum dmub_status status;
1376
1377         if (response)
1378                 *response = 0;
1379
1380         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
1381                 return false;
1382
1383         status = dmub_srv_send_gpint_command(dc_dmub_srv->dmub, command_code, param, wait_us);
1384         if (status != DMUB_STATUS_OK) {
1385                 if (status == DMUB_STATUS_TIMEOUT && wait_type == DM_DMUB_WAIT_TYPE_NO_WAIT)
1386                         return true;
1387
1388                 return false;
1389         }
1390
1391         if (response && wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)
1392                 dmub_srv_get_gpint_response(dc_dmub_srv->dmub, response);
1393
1394         return true;
1395 }
1396
1397 bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code,
1398                                uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type)
1399 {
1400         struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;
1401         bool result = false, reallow_idle = false;
1402
1403         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
1404                 return false;
1405
1406         if (dc_dmub_srv->idle_allowed) {
1407                 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, false);
1408                 reallow_idle = true;
1409         }
1410
1411         result = dc_dmub_execute_gpint(ctx, command_code, param, response, wait_type);
1412
1413         if (result && reallow_idle)
1414                 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true);
1415
1416         return result;
1417 }