drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c

   1 /*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "link_encoder.h"
  29 #include "stream_encoder.h"
  30
  31 #include "resource.h"
  32 #include "include/irq_service_interface.h"
  33 #include "dce110/dce110_resource.h"
  34 #include "dce110/dce110_timing_generator.h"
  35
  36 #include "irq/dce110/irq_service_dce110.h"
  37
  38 #include "dce/dce_mem_input.h"
  39 #include "dce/dce_transform.h"
  40 #include "dce/dce_link_encoder.h"
  41 #include "dce/dce_stream_encoder.h"
  42 #include "dce/dce_audio.h"
  43 #include "dce/dce_opp.h"
  44 #include "dce/dce_ipp.h"
  45 #include "dce/dce_clocks.h"
  46 #include "dce/dce_clock_source.h"
  47
  48 #include "dce/dce_hwseq.h"
  49 #include "dce112/dce112_hw_sequencer.h"
  50 #include "dce/dce_abm.h"
  51 #include "dce/dce_dmcu.h"
  52 #include "dce/dce_aux.h"
  53
  54 #include "reg_helper.h"
  55
  56 #include "dce/dce_11_2_d.h"
  57 #include "dce/dce_11_2_sh_mask.h"
  58
  59 #include "dce100/dce100_resource.h"
  60 #define DC_LOGGER \
  61                 dc->ctx->logger
  62
  63 #ifndef mmDP_DPHY_INTERNAL_CTRL
  64         #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
  65         #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
  66         #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
  67         #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
  68         #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
  69         #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
  70         #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
  71         #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
  72         #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
  73         #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
  74 #endif
  75
  76 #ifndef mmBIOS_SCRATCH_2
  77         #define mmBIOS_SCRATCH_2 0x05CB
  78         #define mmBIOS_SCRATCH_6 0x05CF
  79 #endif
  80
  81 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
  82         #define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
  83         #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
  84         #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
  85         #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
  86         #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
  87         #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
  88         #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
  89         #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
  90 #endif
  91
  92 #ifndef mmDP_DPHY_FAST_TRAINING
  93         #define mmDP_DPHY_FAST_TRAINING                         0x4ABC
  94         #define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
  95         #define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
  96         #define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
  97         #define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
  98         #define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
  99         #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
 100         #define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
 101 #endif
 102
 103 enum dce112_clk_src_array_id {
 104         DCE112_CLK_SRC_PLL0,
 105         DCE112_CLK_SRC_PLL1,
 106         DCE112_CLK_SRC_PLL2,
 107         DCE112_CLK_SRC_PLL3,
 108         DCE112_CLK_SRC_PLL4,
 109         DCE112_CLK_SRC_PLL5,
 110
 111         DCE112_CLK_SRC_TOTAL
 112 };
 113
 114 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
 115         {
 116                 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
 117                 .dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
 118         },
 119         {
 120                 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
 121                 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
 122         },
 123         {
 124                 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
 125                 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
 126         },
 127         {
 128                 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
 129                 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
 130         },
 131         {
 132                 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
 133                 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
 134         },
 135         {
 136                 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
 137                 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
 138         }
 139 };
 140
 141 /* set register offset */
 142 #define SR(reg_name)\
 143         .reg_name = mm ## reg_name
 144
 145 /* set register offset with instance */
 146 #define SRI(reg_name, block, id)\
 147         .reg_name = mm ## block ## id ## _ ## reg_name
 148
 149
 150 static const struct dccg_registers disp_clk_regs = {
 151                 CLK_COMMON_REG_LIST_DCE_BASE()
 152 };
 153
 154 static const struct dccg_shift disp_clk_shift = {
 155                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 156 };
 157
 158 static const struct dccg_mask disp_clk_mask = {
 159                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 160 };
 161
 162 static const struct dce_dmcu_registers dmcu_regs = {
 163                 DMCU_DCE110_COMMON_REG_LIST()
 164 };
 165
 166 static const struct dce_dmcu_shift dmcu_shift = {
 167                 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
 168 };
 169
 170 static const struct dce_dmcu_mask dmcu_mask = {
 171                 DMCU_MASK_SH_LIST_DCE110(_MASK)
 172 };
 173
 174 static const struct dce_abm_registers abm_regs = {
 175                 ABM_DCE110_COMMON_REG_LIST()
 176 };
 177
 178 static const struct dce_abm_shift abm_shift = {
 179                 ABM_MASK_SH_LIST_DCE110(__SHIFT)
 180 };
 181
 182 static const struct dce_abm_mask abm_mask = {
 183                 ABM_MASK_SH_LIST_DCE110(_MASK)
 184 };
 185
 186 #define ipp_regs(id)\
 187 [id] = {\
 188                 IPP_DCE110_REG_LIST_DCE_BASE(id)\
 189 }
 190
 191 static const struct dce_ipp_registers ipp_regs[] = {
 192                 ipp_regs(0),
 193                 ipp_regs(1),
 194                 ipp_regs(2),
 195                 ipp_regs(3),
 196                 ipp_regs(4),
 197                 ipp_regs(5)
 198 };
 199
 200 static const struct dce_ipp_shift ipp_shift = {
 201                 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 202 };
 203
 204 static const struct dce_ipp_mask ipp_mask = {
 205                 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 206 };
 207
 208 #define transform_regs(id)\
 209 [id] = {\
 210                 XFM_COMMON_REG_LIST_DCE110(id)\
 211 }
 212
 213 static const struct dce_transform_registers xfm_regs[] = {
 214                 transform_regs(0),
 215                 transform_regs(1),
 216                 transform_regs(2),
 217                 transform_regs(3),
 218                 transform_regs(4),
 219                 transform_regs(5)
 220 };
 221
 222 static const struct dce_transform_shift xfm_shift = {
 223                 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 224 };
 225
 226 static const struct dce_transform_mask xfm_mask = {
 227                 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
 228 };
 229
 230 #define aux_regs(id)\
 231 [id] = {\
 232         AUX_REG_LIST(id)\
 233 }
 234
 235 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 236                 aux_regs(0),
 237                 aux_regs(1),
 238                 aux_regs(2),
 239                 aux_regs(3),
 240                 aux_regs(4),
 241                 aux_regs(5)
 242 };
 243
 244 #define hpd_regs(id)\
 245 [id] = {\
 246         HPD_REG_LIST(id)\
 247 }
 248
 249 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 250                 hpd_regs(0),
 251                 hpd_regs(1),
 252                 hpd_regs(2),
 253                 hpd_regs(3),
 254                 hpd_regs(4),
 255                 hpd_regs(5)
 256 };
 257
 258 #define link_regs(id)\
 259 [id] = {\
 260         LE_DCE110_REG_LIST(id)\
 261 }
 262
 263 static const struct dce110_link_enc_registers link_enc_regs[] = {
 264         link_regs(0),
 265         link_regs(1),
 266         link_regs(2),
 267         link_regs(3),
 268         link_regs(4),
 269         link_regs(5),
 270         link_regs(6),
 271 };
 272
 273 #define stream_enc_regs(id)\
 274 [id] = {\
 275         SE_COMMON_REG_LIST(id),\
 276         .TMDS_CNTL = 0,\
 277 }
 278
 279 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 280         stream_enc_regs(0),
 281         stream_enc_regs(1),
 282         stream_enc_regs(2),
 283         stream_enc_regs(3),
 284         stream_enc_regs(4),
 285         stream_enc_regs(5)
 286 };
 287
 288 static const struct dce_stream_encoder_shift se_shift = {
 289                 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT)
 290 };
 291
 292 static const struct dce_stream_encoder_mask se_mask = {
 293                 SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
 294 };
 295
 296 #define opp_regs(id)\
 297 [id] = {\
 298         OPP_DCE_112_REG_LIST(id),\
 299 }
 300
 301 static const struct dce_opp_registers opp_regs[] = {
 302         opp_regs(0),
 303         opp_regs(1),
 304         opp_regs(2),
 305         opp_regs(3),
 306         opp_regs(4),
 307         opp_regs(5)
 308 };
 309
 310 static const struct dce_opp_shift opp_shift = {
 311         OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
 312 };
 313
 314 static const struct dce_opp_mask opp_mask = {
 315         OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK)
 316 };
 317
 318 #define aux_engine_regs(id)\
 319 [id] = {\
 320         AUX_COMMON_REG_LIST(id), \
 321         .AUX_RESET_MASK = 0 \
 322 }
 323
 324 static const struct dce110_aux_registers aux_engine_regs[] = {
 325                 aux_engine_regs(0),
 326                 aux_engine_regs(1),
 327                 aux_engine_regs(2),
 328                 aux_engine_regs(3),
 329                 aux_engine_regs(4),
 330                 aux_engine_regs(5)
 331 };
 332
 333 #define audio_regs(id)\
 334 [id] = {\
 335         AUD_COMMON_REG_LIST(id)\
 336 }
 337
 338 static const struct dce_audio_registers audio_regs[] = {
 339         audio_regs(0),
 340         audio_regs(1),
 341         audio_regs(2),
 342         audio_regs(3),
 343         audio_regs(4),
 344         audio_regs(5)
 345 };
 346
 347 static const struct dce_audio_shift audio_shift = {
 348                 AUD_COMMON_MASK_SH_LIST(__SHIFT)
 349 };
 350
 351 static const struct dce_aduio_mask audio_mask = {
 352                 AUD_COMMON_MASK_SH_LIST(_MASK)
 353 };
 354
 355 #define clk_src_regs(index, id)\
 356 [index] = {\
 357         CS_COMMON_REG_LIST_DCE_112(id),\
 358 }
 359
 360 static const struct dce110_clk_src_regs clk_src_regs[] = {
 361         clk_src_regs(0, A),
 362         clk_src_regs(1, B),
 363         clk_src_regs(2, C),
 364         clk_src_regs(3, D),
 365         clk_src_regs(4, E),
 366         clk_src_regs(5, F)
 367 };
 368
 369 static const struct dce110_clk_src_shift cs_shift = {
 370                 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
 371 };
 372
 373 static const struct dce110_clk_src_mask cs_mask = {
 374                 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
 375 };
 376
 377 static const struct bios_registers bios_regs = {
 378         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 379 };
 380
 381 static const struct resource_caps polaris_10_resource_cap = {
 382                 .num_timing_generator = 6,
 383                 .num_audio = 6,
 384                 .num_stream_encoder = 6,
 385                 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
 386 };
 387
 388 static const struct resource_caps polaris_11_resource_cap = {
 389                 .num_timing_generator = 5,
 390                 .num_audio = 5,
 391                 .num_stream_encoder = 5,
 392                 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
 393 };
 394
 395 #define CTX  ctx
 396 #define REG(reg) mm ## reg
 397
 398 #ifndef mmCC_DC_HDMI_STRAPS
 399 #define mmCC_DC_HDMI_STRAPS 0x4819
 400 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
 401 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
 402 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
 403 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 404 #endif
 405
 406 static void read_dce_straps(
 407         struct dc_context *ctx,
 408         struct resource_straps *straps)
 409 {
 410         REG_GET_2(CC_DC_HDMI_STRAPS,
 411                         HDMI_DISABLE, &straps->hdmi_disable,
 412                         AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
 413
 414         REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
 415 }
 416
 417 static struct audio *create_audio(
 418                 struct dc_context *ctx, unsigned int inst)
 419 {
 420         return dce_audio_create(ctx, inst,
 421                         &audio_regs[inst], &audio_shift, &audio_mask);
 422 }
 423
 424
 425 static struct timing_generator *dce112_timing_generator_create(
 426                 struct dc_context *ctx,
 427                 uint32_t instance,
 428                 const struct dce110_timing_generator_offsets *offsets)
 429 {
 430         struct dce110_timing_generator *tg110 =
 431                 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
 432
 433         if (!tg110)
 434                 return NULL;
 435
 436         dce110_timing_generator_construct(tg110, ctx, instance, offsets);
 437         return &tg110->base;
 438 }
 439
 440 static struct stream_encoder *dce112_stream_encoder_create(
 441         enum engine_id eng_id,
 442         struct dc_context *ctx)
 443 {
 444         struct dce110_stream_encoder *enc110 =
 445                 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 446
 447         if (!enc110)
 448                 return NULL;
 449
 450         dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 451                                         &stream_enc_regs[eng_id],
 452                                         &se_shift, &se_mask);
 453         return &enc110->base;
 454 }
 455
 456 #define SRII(reg_name, block, id)\
 457         .reg_name[id] = mm ## block ## id ## _ ## reg_name
 458
 459 static const struct dce_hwseq_registers hwseq_reg = {
 460                 HWSEQ_DCE112_REG_LIST()
 461 };
 462
 463 static const struct dce_hwseq_shift hwseq_shift = {
 464                 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT)
 465 };
 466
 467 static const struct dce_hwseq_mask hwseq_mask = {
 468                 HWSEQ_DCE112_MASK_SH_LIST(_MASK)
 469 };
 470
 471 static struct dce_hwseq *dce112_hwseq_create(
 472         struct dc_context *ctx)
 473 {
 474         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 475
 476         if (hws) {
 477                 hws->ctx = ctx;
 478                 hws->regs = &hwseq_reg;
 479                 hws->shifts = &hwseq_shift;
 480                 hws->masks = &hwseq_mask;
 481         }
 482         return hws;
 483 }
 484
 485 static const struct resource_create_funcs res_create_funcs = {
 486         .read_dce_straps = read_dce_straps,
 487         .create_audio = create_audio,
 488         .create_stream_encoder = dce112_stream_encoder_create,
 489         .create_hwseq = dce112_hwseq_create,
 490 };
 491
 492 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
 493 static const struct dce_mem_input_registers mi_regs[] = {
 494                 mi_inst_regs(0),
 495                 mi_inst_regs(1),
 496                 mi_inst_regs(2),
 497                 mi_inst_regs(3),
 498                 mi_inst_regs(4),
 499                 mi_inst_regs(5),
 500 };
 501
 502 static const struct dce_mem_input_shift mi_shifts = {
 503                 MI_DCE11_2_MASK_SH_LIST(__SHIFT)
 504 };
 505
 506 static const struct dce_mem_input_mask mi_masks = {
 507                 MI_DCE11_2_MASK_SH_LIST(_MASK)
 508 };
 509
 510 static struct mem_input *dce112_mem_input_create(
 511         struct dc_context *ctx,
 512         uint32_t inst)
 513 {
 514         struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
 515                                                GFP_KERNEL);
 516
 517         if (!dce_mi) {
 518                 BREAK_TO_DEBUGGER();
 519                 return NULL;
 520         }
 521
 522         dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 523         return &dce_mi->base;
 524 }
 525
 526 static void dce112_transform_destroy(struct transform **xfm)
 527 {
 528         kfree(TO_DCE_TRANSFORM(*xfm));
 529         *xfm = NULL;
 530 }
 531
 532 static struct transform *dce112_transform_create(
 533         struct dc_context *ctx,
 534         uint32_t inst)
 535 {
 536         struct dce_transform *transform =
 537                 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
 538
 539         if (!transform)
 540                 return NULL;
 541
 542         dce_transform_construct(transform, ctx, inst,
 543                                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
 544         transform->lb_memory_size = 0x1404; /*5124*/
 545         return &transform->base;
 546 }
 547
 548 static const struct encoder_feature_support link_enc_feature = {
 549                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 550                 .max_hdmi_pixel_clock = 600000,
 551                 .ycbcr420_supported = true,
 552                 .flags.bits.IS_HBR2_CAPABLE = true,
 553                 .flags.bits.IS_HBR3_CAPABLE = true,
 554                 .flags.bits.IS_TPS3_CAPABLE = true,
 555                 .flags.bits.IS_TPS4_CAPABLE = true,
 556                 .flags.bits.IS_YCBCR_CAPABLE = true
 557 };
 558
 559 struct link_encoder *dce112_link_encoder_create(
 560         const struct encoder_init_data *enc_init_data)
 561 {
 562         struct dce110_link_encoder *enc110 =
 563                 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 564
 565         if (!enc110)
 566                 return NULL;
 567
 568         dce110_link_encoder_construct(enc110,
 569                                       enc_init_data,
 570                                       &link_enc_feature,
 571                                       &link_enc_regs[enc_init_data->transmitter],
 572                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 573                                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
 574         return &enc110->base;
 575 }
 576
 577 static struct input_pixel_processor *dce112_ipp_create(
 578         struct dc_context *ctx, uint32_t inst)
 579 {
 580         struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
 581
 582         if (!ipp) {
 583                 BREAK_TO_DEBUGGER();
 584                 return NULL;
 585         }
 586
 587         dce_ipp_construct(ipp, ctx, inst,
 588                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 589         return &ipp->base;
 590 }
 591
 592 struct output_pixel_processor *dce112_opp_create(
 593         struct dc_context *ctx,
 594         uint32_t inst)
 595 {
 596         struct dce110_opp *opp =
 597                 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
 598
 599         if (!opp)
 600                 return NULL;
 601
 602         dce110_opp_construct(opp,
 603                              ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 604         return &opp->base;
 605 }
 606
 607 struct engine *dce112_aux_engine_create(
 608         struct dc_context *ctx,
 609         uint32_t inst)
 610 {
 611         struct aux_engine_dce110 *aux_engine =
 612                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 613
 614         if (!aux_engine)
 615                 return NULL;
 616
 617         dce110_aux_engine_construct(aux_engine, ctx, inst,
 618                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 619                                     &aux_engine_regs[inst]);
 620
 621         return &aux_engine->base.base;
 622 }
 623
 624 struct clock_source *dce112_clock_source_create(
 625         struct dc_context *ctx,
 626         struct dc_bios *bios,
 627         enum clock_source_id id,
 628         const struct dce110_clk_src_regs *regs,
 629         bool dp_clk_src)
 630 {
 631         struct dce110_clk_src *clk_src =
 632                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 633
 634         if (!clk_src)
 635                 return NULL;
 636
 637         if (dce110_clk_src_construct(clk_src, ctx, bios, id,
 638                         regs, &cs_shift, &cs_mask)) {
 639                 clk_src->base.dp_clk_src = dp_clk_src;
 640                 return &clk_src->base;
 641         }
 642
 643         BREAK_TO_DEBUGGER();
 644         return NULL;
 645 }
 646
 647 void dce112_clock_source_destroy(struct clock_source **clk_src)
 648 {
 649         kfree(TO_DCE110_CLK_SRC(*clk_src));
 650         *clk_src = NULL;
 651 }
 652
 653 static void destruct(struct dce110_resource_pool *pool)
 654 {
 655         unsigned int i;
 656
 657         for (i = 0; i < pool->base.pipe_count; i++) {
 658                 if (pool->base.opps[i] != NULL)
 659                         dce110_opp_destroy(&pool->base.opps[i]);
 660
 661                 if (pool->base.engines[i] != NULL)
 662                         dce110_engine_destroy(&pool->base.engines[i]);
 663
 664                 if (pool->base.transforms[i] != NULL)
 665                         dce112_transform_destroy(&pool->base.transforms[i]);
 666
 667                 if (pool->base.ipps[i] != NULL)
 668                         dce_ipp_destroy(&pool->base.ipps[i]);
 669
 670                 if (pool->base.mis[i] != NULL) {
 671                         kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 672                         pool->base.mis[i] = NULL;
 673                 }
 674
 675                 if (pool->base.timing_generators[i] != NULL) {
 676                         kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 677                         pool->base.timing_generators[i] = NULL;
 678                 }
 679
 680                 if (pool->base.engines[i] != NULL)
 681                         dce110_engine_destroy(&pool->base.engines[i]);
 682
 683         }
 684
 685         for (i = 0; i < pool->base.stream_enc_count; i++) {
 686                 if (pool->base.stream_enc[i] != NULL)
 687                         kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 688         }
 689
 690         for (i = 0; i < pool->base.clk_src_count; i++) {
 691                 if (pool->base.clock_sources[i] != NULL) {
 692                         dce112_clock_source_destroy(&pool->base.clock_sources[i]);
 693                 }
 694         }
 695
 696         if (pool->base.dp_clock_source != NULL)
 697                 dce112_clock_source_destroy(&pool->base.dp_clock_source);
 698
 699         for (i = 0; i < pool->base.audio_count; i++)    {
 700                 if (pool->base.audios[i] != NULL) {
 701                         dce_aud_destroy(&pool->base.audios[i]);
 702                 }
 703         }
 704
 705         if (pool->base.abm != NULL)
 706                 dce_abm_destroy(&pool->base.abm);
 707
 708         if (pool->base.dmcu != NULL)
 709                 dce_dmcu_destroy(&pool->base.dmcu);
 710
 711         if (pool->base.dccg != NULL)
 712                 dce_dccg_destroy(&pool->base.dccg);
 713
 714         if (pool->base.irqs != NULL) {
 715                 dal_irq_service_destroy(&pool->base.irqs);
 716         }
 717 }
 718
 719 static struct clock_source *find_matching_pll(
 720                 struct resource_context *res_ctx,
 721                 const struct resource_pool *pool,
 722                 const struct dc_stream_state *const stream)
 723 {
 724         switch (stream->sink->link->link_enc->transmitter) {
 725         case TRANSMITTER_UNIPHY_A:
 726                 return pool->clock_sources[DCE112_CLK_SRC_PLL0];
 727         case TRANSMITTER_UNIPHY_B:
 728                 return pool->clock_sources[DCE112_CLK_SRC_PLL1];
 729         case TRANSMITTER_UNIPHY_C:
 730                 return pool->clock_sources[DCE112_CLK_SRC_PLL2];
 731         case TRANSMITTER_UNIPHY_D:
 732                 return pool->clock_sources[DCE112_CLK_SRC_PLL3];
 733         case TRANSMITTER_UNIPHY_E:
 734                 return pool->clock_sources[DCE112_CLK_SRC_PLL4];
 735         case TRANSMITTER_UNIPHY_F:
 736                 return pool->clock_sources[DCE112_CLK_SRC_PLL5];
 737         default:
 738                 return NULL;
 739         };
 740
 741         return 0;
 742 }
 743
 744 static enum dc_status build_mapped_resource(
 745                 const struct dc *dc,
 746                 struct dc_state *context,
 747                 struct dc_stream_state *stream)
 748 {
 749         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
 750
 751         if (!pipe_ctx)
 752                 return DC_ERROR_UNEXPECTED;
 753
 754         dce110_resource_build_pipe_hw_param(pipe_ctx);
 755
 756         resource_build_info_frame(pipe_ctx);
 757
 758         return DC_OK;
 759 }
 760
 761 bool dce112_validate_bandwidth(
 762         struct dc *dc,
 763         struct dc_state *context)
 764 {
 765         bool result = false;
 766
 767         DC_LOG_BANDWIDTH_CALCS(
 768                 "%s: start",
 769                 __func__);
 770
 771         if (bw_calcs(
 772                         dc->ctx,
 773                         dc->bw_dceip,
 774                         dc->bw_vbios,
 775                         context->res_ctx.pipe_ctx,
 776                         dc->res_pool->pipe_count,
 777                         &context->bw.dce))
 778                 result = true;
 779
 780         if (!result)
 781                 DC_LOG_BANDWIDTH_VALIDATION(
 782                         "%s: Bandwidth validation failed!",
 783                         __func__);
 784
 785         if (memcmp(&dc->current_state->bw.dce,
 786                         &context->bw.dce, sizeof(context->bw.dce))) {
 787
 788                 DC_LOG_BANDWIDTH_CALCS(
 789                         "%s: finish,\n"
 790                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 791                         "stutMark_b: %d stutMark_a: %d\n"
 792                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 793                         "stutMark_b: %d stutMark_a: %d\n"
 794                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 795                         "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
 796                         "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
 797                         "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
 798                         ,
 799                         __func__,
 800                         context->bw.dce.nbp_state_change_wm_ns[0].b_mark,
 801                         context->bw.dce.nbp_state_change_wm_ns[0].a_mark,
 802                         context->bw.dce.urgent_wm_ns[0].b_mark,
 803                         context->bw.dce.urgent_wm_ns[0].a_mark,
 804                         context->bw.dce.stutter_exit_wm_ns[0].b_mark,
 805                         context->bw.dce.stutter_exit_wm_ns[0].a_mark,
 806                         context->bw.dce.nbp_state_change_wm_ns[1].b_mark,
 807                         context->bw.dce.nbp_state_change_wm_ns[1].a_mark,
 808                         context->bw.dce.urgent_wm_ns[1].b_mark,
 809                         context->bw.dce.urgent_wm_ns[1].a_mark,
 810                         context->bw.dce.stutter_exit_wm_ns[1].b_mark,
 811                         context->bw.dce.stutter_exit_wm_ns[1].a_mark,
 812                         context->bw.dce.nbp_state_change_wm_ns[2].b_mark,
 813                         context->bw.dce.nbp_state_change_wm_ns[2].a_mark,
 814                         context->bw.dce.urgent_wm_ns[2].b_mark,
 815                         context->bw.dce.urgent_wm_ns[2].a_mark,
 816                         context->bw.dce.stutter_exit_wm_ns[2].b_mark,
 817                         context->bw.dce.stutter_exit_wm_ns[2].a_mark,
 818                         context->bw.dce.stutter_mode_enable,
 819                         context->bw.dce.cpuc_state_change_enable,
 820                         context->bw.dce.cpup_state_change_enable,
 821                         context->bw.dce.nbp_state_change_enable,
 822                         context->bw.dce.all_displays_in_sync,
 823                         context->bw.dce.dispclk_khz,
 824                         context->bw.dce.sclk_khz,
 825                         context->bw.dce.sclk_deep_sleep_khz,
 826                         context->bw.dce.yclk_khz,
 827                         context->bw.dce.blackout_recovery_time_us);
 828         }
 829         return result;
 830 }
 831
 832 enum dc_status resource_map_phy_clock_resources(
 833                 const struct dc *dc,
 834                 struct dc_state *context,
 835                 struct dc_stream_state *stream)
 836 {
 837
 838         /* acquire new resources */
 839         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
 840                         &context->res_ctx, stream);
 841
 842         if (!pipe_ctx)
 843                 return DC_ERROR_UNEXPECTED;
 844
 845         if (dc_is_dp_signal(pipe_ctx->stream->signal)
 846                 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
 847                 pipe_ctx->clock_source =
 848                                 dc->res_pool->dp_clock_source;
 849         else
 850                 pipe_ctx->clock_source = find_matching_pll(
 851                         &context->res_ctx, dc->res_pool,
 852                         stream);
 853
 854         if (pipe_ctx->clock_source == NULL)
 855                 return DC_NO_CLOCK_SOURCE_RESOURCE;
 856
 857         resource_reference_clock_source(
 858                 &context->res_ctx,
 859                 dc->res_pool,
 860                 pipe_ctx->clock_source);
 861
 862         return DC_OK;
 863 }
 864
 865 static bool dce112_validate_surface_sets(
 866                 struct dc_state *context)
 867 {
 868         int i;
 869
 870         for (i = 0; i < context->stream_count; i++) {
 871                 if (context->stream_status[i].plane_count == 0)
 872                         continue;
 873
 874                 if (context->stream_status[i].plane_count > 1)
 875                         return false;
 876
 877                 if (context->stream_status[i].plane_states[0]->format
 878                                 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 879                         return false;
 880         }
 881
 882         return true;
 883 }
 884
 885 enum dc_status dce112_add_stream_to_ctx(
 886                 struct dc *dc,
 887                 struct dc_state *new_ctx,
 888                 struct dc_stream_state *dc_stream)
 889 {
 890         enum dc_status result = DC_ERROR_UNEXPECTED;
 891
 892         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
 893
 894         if (result == DC_OK)
 895                 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
 896
 897
 898         if (result == DC_OK)
 899                 result = build_mapped_resource(dc, new_ctx, dc_stream);
 900
 901         return result;
 902 }
 903
 904 enum dc_status dce112_validate_global(
 905                 struct dc *dc,
 906                 struct dc_state *context)
 907 {
 908         if (!dce112_validate_surface_sets(context))
 909                 return DC_FAIL_SURFACE_VALIDATE;
 910
 911         return DC_OK;
 912 }
 913
 914 static void dce112_destroy_resource_pool(struct resource_pool **pool)
 915 {
 916         struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
 917
 918         destruct(dce110_pool);
 919         kfree(dce110_pool);
 920         *pool = NULL;
 921 }
 922
 923 static const struct resource_funcs dce112_res_pool_funcs = {
 924         .destroy = dce112_destroy_resource_pool,
 925         .link_enc_create = dce112_link_encoder_create,
 926         .validate_bandwidth = dce112_validate_bandwidth,
 927         .validate_plane = dce100_validate_plane,
 928         .add_stream_to_ctx = dce112_add_stream_to_ctx,
 929         .validate_global = dce112_validate_global
 930 };
 931
 932 static void bw_calcs_data_update_from_pplib(struct dc *dc)
 933 {
 934         struct dm_pp_clock_levels_with_latency eng_clks = {0};
 935         struct dm_pp_clock_levels_with_latency mem_clks = {0};
 936         struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
 937         struct dm_pp_clock_levels clks = {0};
 938
 939         /*do system clock  TODO PPLIB: after PPLIB implement,
 940          * then remove old way
 941          */
 942         if (!dm_pp_get_clock_levels_by_type_with_latency(
 943                         dc->ctx,
 944                         DM_PP_CLOCK_TYPE_ENGINE_CLK,
 945                         &eng_clks)) {
 946
 947                 /* This is only for temporary */
 948                 dm_pp_get_clock_levels_by_type(
 949                                 dc->ctx,
 950                                 DM_PP_CLOCK_TYPE_ENGINE_CLK,
 951                                 &clks);
 952                 /* convert all the clock fro kHz to fix point mHz */
 953                 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
 954                                 clks.clocks_in_khz[clks.num_levels-1], 1000);
 955                 dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
 956                                 clks.clocks_in_khz[clks.num_levels/8], 1000);
 957                 dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
 958                                 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
 959                 dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
 960                                 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
 961                 dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
 962                                 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
 963                 dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
 964                                 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
 965                 dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
 966                                 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
 967                 dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
 968                                 clks.clocks_in_khz[0], 1000);
 969
 970                 /*do memory clock*/
 971                 dm_pp_get_clock_levels_by_type(
 972                                 dc->ctx,
 973                                 DM_PP_CLOCK_TYPE_MEMORY_CLK,
 974                                 &clks);
 975
 976                 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
 977                         clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
 978                 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
 979                         clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
 980                         1000);
 981                 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
 982                         clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
 983                         1000);
 984
 985                 return;
 986         }
 987
 988         /* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
 989         dc->bw_vbios->high_sclk = bw_frc_to_fixed(
 990                 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
 991         dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
 992                 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
 993         dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
 994                 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
 995         dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
 996                 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
 997         dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
 998                 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
 999         dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1000                 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
1001         dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1002                 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
1003         dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1004                         eng_clks.data[0].clocks_in_khz, 1000);
1005
1006         /*do memory clock*/
1007         dm_pp_get_clock_levels_by_type_with_latency(
1008                         dc->ctx,
1009                         DM_PP_CLOCK_TYPE_MEMORY_CLK,
1010                         &mem_clks);
1011
1012         /* we don't need to call PPLIB for validation clock since they
1013          * also give us the highest sclk and highest mclk (UMA clock).
1014          * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
1015          * YCLK = UMACLK*m_memoryTypeMultiplier
1016          */
1017         dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1018                 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
1019         dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1020                 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
1021                 1000);
1022         dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1023                 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
1024                 1000);
1025
1026         /* Now notify PPLib/SMU about which Watermarks sets they should select
1027          * depending on DPM state they are in. And update BW MGR GFX Engine and
1028          * Memory clock member variables for Watermarks calculations for each
1029          * Watermark Set
1030          */
1031         clk_ranges.num_wm_sets = 4;
1032         clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1033         clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1034                         eng_clks.data[0].clocks_in_khz;
1035         clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1036                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1037         clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1038                         mem_clks.data[0].clocks_in_khz;
1039         clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1040                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1041
1042         clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1043         clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1044                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1045         /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1046         clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1047         clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1048                         mem_clks.data[0].clocks_in_khz;
1049         clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1050                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1051
1052         clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1053         clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1054                         eng_clks.data[0].clocks_in_khz;
1055         clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1056                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1057         clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1058                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1059         /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1060         clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1061
1062         clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1063         clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1064                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1065         /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1066         clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1067         clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1068                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1069         /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1070         clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1071
1072         /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1073         dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1074 }
1075
1076 const struct resource_caps *dce112_resource_cap(
1077         struct hw_asic_id *asic_id)
1078 {
1079         if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
1080             ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev))
1081                 return &polaris_11_resource_cap;
1082         else
1083                 return &polaris_10_resource_cap;
1084 }
1085
1086 static bool construct(
1087         uint8_t num_virtual_links,
1088         struct dc *dc,
1089         struct dce110_resource_pool *pool)
1090 {
1091         unsigned int i;
1092         struct dc_context *ctx = dc->ctx;
1093         struct dm_pp_static_clock_info static_clk_info = {0};
1094
1095         ctx->dc_bios->regs = &bios_regs;
1096
1097         pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
1098         pool->base.funcs = &dce112_res_pool_funcs;
1099
1100         /*************************************************
1101          *  Resource + asic cap harcoding                *
1102          *************************************************/
1103         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1104         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1105         pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1106         dc->caps.max_downscale_ratio = 200;
1107         dc->caps.i2c_speed_in_khz = 100;
1108         dc->caps.max_cursor_size = 128;
1109         dc->caps.dual_link_dvi = true;
1110
1111
1112         /*************************************************
1113          *  Create resources                             *
1114          *************************************************/
1115
1116         pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
1117                         dce112_clock_source_create(
1118                                 ctx, ctx->dc_bios,
1119                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1120                                 &clk_src_regs[0], false);
1121         pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =
1122                         dce112_clock_source_create(
1123                                 ctx, ctx->dc_bios,
1124                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1125                                 &clk_src_regs[1], false);
1126         pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =
1127                         dce112_clock_source_create(
1128                                 ctx, ctx->dc_bios,
1129                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1130                                 &clk_src_regs[2], false);
1131         pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =
1132                         dce112_clock_source_create(
1133                                 ctx, ctx->dc_bios,
1134                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1135                                 &clk_src_regs[3], false);
1136         pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =
1137                         dce112_clock_source_create(
1138                                 ctx, ctx->dc_bios,
1139                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1140                                 &clk_src_regs[4], false);
1141         pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =
1142                         dce112_clock_source_create(
1143                                 ctx, ctx->dc_bios,
1144                                 CLOCK_SOURCE_COMBO_PHY_PLL5,
1145                                 &clk_src_regs[5], false);
1146         pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
1147
1148         pool->base.dp_clock_source =  dce112_clock_source_create(
1149                 ctx, ctx->dc_bios,
1150                 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);
1151
1152
1153         for (i = 0; i < pool->base.clk_src_count; i++) {
1154                 if (pool->base.clock_sources[i] == NULL) {
1155                         dm_error("DC: failed to create clock sources!\n");
1156                         BREAK_TO_DEBUGGER();
1157                         goto res_create_fail;
1158                 }
1159         }
1160
1161         pool->base.dccg = dce112_dccg_create(ctx,
1162                         &disp_clk_regs,
1163                         &disp_clk_shift,
1164                         &disp_clk_mask);
1165         if (pool->base.dccg == NULL) {
1166                 dm_error("DC: failed to create display clock!\n");
1167                 BREAK_TO_DEBUGGER();
1168                 goto res_create_fail;
1169         }
1170
1171         pool->base.dmcu = dce_dmcu_create(ctx,
1172                         &dmcu_regs,
1173                         &dmcu_shift,
1174                         &dmcu_mask);
1175         if (pool->base.dmcu == NULL) {
1176                 dm_error("DC: failed to create dmcu!\n");
1177                 BREAK_TO_DEBUGGER();
1178                 goto res_create_fail;
1179         }
1180
1181         pool->base.abm = dce_abm_create(ctx,
1182                         &abm_regs,
1183                         &abm_shift,
1184                         &abm_mask);
1185         if (pool->base.abm == NULL) {
1186                 dm_error("DC: failed to create abm!\n");
1187                 BREAK_TO_DEBUGGER();
1188                 goto res_create_fail;
1189         }
1190
1191         /* get static clock information for PPLIB or firmware, save
1192          * max_clock_state
1193          */
1194         if (dm_pp_get_static_clocks(ctx, &static_clk_info))
1195                 pool->base.dccg->max_clks_state =
1196                                 static_clk_info.max_clocks_state;
1197
1198         {
1199                 struct irq_service_init_data init_data;
1200                 init_data.ctx = dc->ctx;
1201                 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1202                 if (!pool->base.irqs)
1203                         goto res_create_fail;
1204         }
1205
1206         for (i = 0; i < pool->base.pipe_count; i++) {
1207                 pool->base.timing_generators[i] =
1208                                 dce112_timing_generator_create(
1209                                         ctx,
1210                                         i,
1211                                         &dce112_tg_offsets[i]);
1212                 if (pool->base.timing_generators[i] == NULL) {
1213                         BREAK_TO_DEBUGGER();
1214                         dm_error("DC: failed to create tg!\n");
1215                         goto res_create_fail;
1216                 }
1217
1218                 pool->base.mis[i] = dce112_mem_input_create(ctx, i);
1219                 if (pool->base.mis[i] == NULL) {
1220                         BREAK_TO_DEBUGGER();
1221                         dm_error(
1222                                 "DC: failed to create memory input!\n");
1223                         goto res_create_fail;
1224                 }
1225
1226                 pool->base.ipps[i] = dce112_ipp_create(ctx, i);
1227                 if (pool->base.ipps[i] == NULL) {
1228                         BREAK_TO_DEBUGGER();
1229                         dm_error(
1230                                 "DC:failed to create input pixel processor!\n");
1231                         goto res_create_fail;
1232                 }
1233
1234                 pool->base.transforms[i] = dce112_transform_create(ctx, i);
1235                 if (pool->base.transforms[i] == NULL) {
1236                         BREAK_TO_DEBUGGER();
1237                         dm_error(
1238                                 "DC: failed to create transform!\n");
1239                         goto res_create_fail;
1240                 }
1241
1242                 pool->base.opps[i] = dce112_opp_create(
1243                         ctx,
1244                         i);
1245                 if (pool->base.opps[i] == NULL) {
1246                         BREAK_TO_DEBUGGER();
1247                         dm_error(
1248                                 "DC:failed to create output pixel processor!\n");
1249                         goto res_create_fail;
1250                 }
1251                 pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
1252                 if (pool->base.engines[i] == NULL) {
1253                         BREAK_TO_DEBUGGER();
1254                         dm_error(
1255                                 "DC:failed to create aux engine!!\n");
1256                         goto res_create_fail;
1257                 }
1258         }
1259
1260         if (!resource_construct(num_virtual_links, dc, &pool->base,
1261                           &res_create_funcs))
1262                 goto res_create_fail;
1263
1264         dc->caps.max_planes =  pool->base.pipe_count;
1265
1266         /* Create hardware sequencer */
1267         dce112_hw_sequencer_construct(dc);
1268
1269         bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1270
1271         bw_calcs_data_update_from_pplib(dc);
1272
1273         return true;
1274
1275 res_create_fail:
1276         destruct(pool);
1277         return false;
1278 }
1279
1280 struct resource_pool *dce112_create_resource_pool(
1281         uint8_t num_virtual_links,
1282         struct dc *dc)
1283 {
1284         struct dce110_resource_pool *pool =
1285                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1286
1287         if (!pool)
1288                 return NULL;
1289
1290         if (construct(num_virtual_links, dc, pool))
1291                 return &pool->base;
1292
1293         BREAK_TO_DEBUGGER();
1294         return NULL;
1295 }