2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/bitfield.h>
32 #include <linux/byteorder/generic.h>
33 #include <linux/cec.h>
34 #include <linux/hdmi.h>
35 #include <linux/i2c.h>
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/pci.h>
39 #include <linux/seq_buf.h>
40 #include <linux/slab.h>
41 #include <linux/vga_switcheroo.h>
43 #include <drm/drm_drv.h>
44 #include <drm/drm_edid.h>
45 #include <drm/drm_eld.h>
46 #include <drm/drm_encoder.h>
47 #include <drm/drm_print.h>
49 #include "drm_crtc_internal.h"
50 #include "drm_displayid_internal.h"
51 #include "drm_internal.h"
53 static int oui(u8 first, u8 second, u8 third)
55 return (first << 16) | (second << 8) | third;
58 #define EDID_EST_TIMINGS 16
59 #define EDID_STD_TIMINGS 8
60 #define EDID_DETAILED_TIMINGS 4
63 * EDID blocks out in the wild have a variety of bugs, try to collect
64 * them here (note that userspace may work around broken monitors first,
65 * but fixes should make their way here so that the kernel "just works"
66 * on as many displays as possible).
69 /* First detailed mode wrong, use largest 60Hz mode */
70 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
71 /* Reported 135MHz pixel clock is too high, needs adjustment */
72 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
73 /* Prefer the largest mode at 75 Hz */
74 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
75 /* Detail timing is in cm not mm */
76 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
77 /* Detailed timing descriptors have bogus size values, so just take the
78 * maximum size and use that.
80 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
81 /* use +hsync +vsync for detailed mode */
82 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
83 /* Force reduced-blanking timings for detailed modes */
84 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
86 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
88 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
90 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
92 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
93 /* Non desktop display (i.e. HMD) */
94 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
95 /* Cap the DSC target bitrate to 15bpp */
96 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
98 #define MICROSOFT_IEEE_OUI 0xca125c
100 struct detailed_mode_closure {
101 struct drm_connector *connector;
102 const struct drm_edid *drm_edid;
107 struct drm_edid_match_closure {
108 const struct drm_edid_ident *ident;
117 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
120 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, \
121 vend_chr_2, product_id), \
126 static const struct edid_quirk {
127 const struct drm_edid_ident ident;
129 } edid_quirk_list[] = {
131 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
133 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
135 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
136 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
139 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC),
141 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
142 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
144 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
145 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
147 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
148 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
150 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
151 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
153 /* Belinea 10 15 55 */
154 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
155 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
157 /* Envision Peripherals, Inc. EN-7100e */
158 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
159 /* Envision EN2028 */
160 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
162 /* Funai Electronics PM36B */
163 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
164 EDID_QUIRK_DETAILED_IN_CM),
167 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
170 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
172 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
173 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
175 /* LG Philips LCD LP154W01-A5 */
176 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
177 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
179 /* Samsung SyncMaster 205BW. Note: irony */
180 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
181 /* Samsung SyncMaster 22[5-6]BW */
182 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
183 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
185 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
186 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
188 /* ViewSonic VA2026w */
189 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
191 /* Medion MD 30217 PG */
192 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
195 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
197 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
198 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
200 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
201 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
203 /* Valve Index Headset */
204 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
209 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
210 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
217 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
218 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
222 /* HTC Vive and Vive Pro VR Headsets */
223 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
224 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
226 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
227 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
228 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
229 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
230 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
232 /* Windows Mixed Reality Headsets */
233 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
234 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
235 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
236 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
237 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
238 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
240 /* Sony PlayStation VR Headset */
241 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
243 /* Sensics VR Headsets */
244 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
246 /* OSVR HDK and HDK2 VR Headsets */
247 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
248 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
252 * Autogenerated from the DMT spec.
253 * This table is copied from xfree86/modes/xf86EdidModes.c.
255 static const struct drm_display_mode drm_dmt_modes[] = {
256 /* 0x01 - 640x350@85Hz */
257 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
258 736, 832, 0, 350, 382, 385, 445, 0,
259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
260 /* 0x02 - 640x400@85Hz */
261 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
262 736, 832, 0, 400, 401, 404, 445, 0,
263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
264 /* 0x03 - 720x400@85Hz */
265 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
266 828, 936, 0, 400, 401, 404, 446, 0,
267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
268 /* 0x04 - 640x480@60Hz */
269 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
270 752, 800, 0, 480, 490, 492, 525, 0,
271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
272 /* 0x05 - 640x480@72Hz */
273 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
274 704, 832, 0, 480, 489, 492, 520, 0,
275 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
276 /* 0x06 - 640x480@75Hz */
277 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
278 720, 840, 0, 480, 481, 484, 500, 0,
279 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
280 /* 0x07 - 640x480@85Hz */
281 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
282 752, 832, 0, 480, 481, 484, 509, 0,
283 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
284 /* 0x08 - 800x600@56Hz */
285 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
286 896, 1024, 0, 600, 601, 603, 625, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
288 /* 0x09 - 800x600@60Hz */
289 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
290 968, 1056, 0, 600, 601, 605, 628, 0,
291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
292 /* 0x0a - 800x600@72Hz */
293 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
294 976, 1040, 0, 600, 637, 643, 666, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
296 /* 0x0b - 800x600@75Hz */
297 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
298 896, 1056, 0, 600, 601, 604, 625, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
300 /* 0x0c - 800x600@85Hz */
301 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
302 896, 1048, 0, 600, 601, 604, 631, 0,
303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
304 /* 0x0d - 800x600@120Hz RB */
305 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
306 880, 960, 0, 600, 603, 607, 636, 0,
307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
308 /* 0x0e - 848x480@60Hz */
309 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
310 976, 1088, 0, 480, 486, 494, 517, 0,
311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
312 /* 0x0f - 1024x768@43Hz, interlace */
313 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
314 1208, 1264, 0, 768, 768, 776, 817, 0,
315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
316 DRM_MODE_FLAG_INTERLACE) },
317 /* 0x10 - 1024x768@60Hz */
318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
319 1184, 1344, 0, 768, 771, 777, 806, 0,
320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
321 /* 0x11 - 1024x768@70Hz */
322 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
323 1184, 1328, 0, 768, 771, 777, 806, 0,
324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
325 /* 0x12 - 1024x768@75Hz */
326 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
327 1136, 1312, 0, 768, 769, 772, 800, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
329 /* 0x13 - 1024x768@85Hz */
330 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
331 1168, 1376, 0, 768, 769, 772, 808, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
333 /* 0x14 - 1024x768@120Hz RB */
334 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
335 1104, 1184, 0, 768, 771, 775, 813, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
337 /* 0x15 - 1152x864@75Hz */
338 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
339 1344, 1600, 0, 864, 865, 868, 900, 0,
340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 0x55 - 1280x720@60Hz */
342 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
343 1430, 1650, 0, 720, 725, 730, 750, 0,
344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
345 /* 0x16 - 1280x768@60Hz RB */
346 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
347 1360, 1440, 0, 768, 771, 778, 790, 0,
348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
349 /* 0x17 - 1280x768@60Hz */
350 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
351 1472, 1664, 0, 768, 771, 778, 798, 0,
352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
353 /* 0x18 - 1280x768@75Hz */
354 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
355 1488, 1696, 0, 768, 771, 778, 805, 0,
356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
357 /* 0x19 - 1280x768@85Hz */
358 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
359 1496, 1712, 0, 768, 771, 778, 809, 0,
360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 0x1a - 1280x768@120Hz RB */
362 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
363 1360, 1440, 0, 768, 771, 778, 813, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
365 /* 0x1b - 1280x800@60Hz RB */
366 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
367 1360, 1440, 0, 800, 803, 809, 823, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
369 /* 0x1c - 1280x800@60Hz */
370 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
371 1480, 1680, 0, 800, 803, 809, 831, 0,
372 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
373 /* 0x1d - 1280x800@75Hz */
374 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
375 1488, 1696, 0, 800, 803, 809, 838, 0,
376 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
377 /* 0x1e - 1280x800@85Hz */
378 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
379 1496, 1712, 0, 800, 803, 809, 843, 0,
380 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
381 /* 0x1f - 1280x800@120Hz RB */
382 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
383 1360, 1440, 0, 800, 803, 809, 847, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
385 /* 0x20 - 1280x960@60Hz */
386 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
387 1488, 1800, 0, 960, 961, 964, 1000, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
389 /* 0x21 - 1280x960@85Hz */
390 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
391 1504, 1728, 0, 960, 961, 964, 1011, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
393 /* 0x22 - 1280x960@120Hz RB */
394 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
395 1360, 1440, 0, 960, 963, 967, 1017, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
397 /* 0x23 - 1280x1024@60Hz */
398 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
399 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
401 /* 0x24 - 1280x1024@75Hz */
402 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
403 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
405 /* 0x25 - 1280x1024@85Hz */
406 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
407 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 0x26 - 1280x1024@120Hz RB */
410 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
411 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
413 /* 0x27 - 1360x768@60Hz */
414 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
415 1536, 1792, 0, 768, 771, 777, 795, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
417 /* 0x28 - 1360x768@120Hz RB */
418 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
419 1440, 1520, 0, 768, 771, 776, 813, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
421 /* 0x51 - 1366x768@60Hz */
422 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
423 1579, 1792, 0, 768, 771, 774, 798, 0,
424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 0x56 - 1366x768@60Hz */
426 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
427 1436, 1500, 0, 768, 769, 772, 800, 0,
428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 0x29 - 1400x1050@60Hz RB */
430 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
431 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
433 /* 0x2a - 1400x1050@60Hz */
434 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
435 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
437 /* 0x2b - 1400x1050@75Hz */
438 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
439 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
441 /* 0x2c - 1400x1050@85Hz */
442 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
443 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
445 /* 0x2d - 1400x1050@120Hz RB */
446 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
447 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
449 /* 0x2e - 1440x900@60Hz RB */
450 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
451 1520, 1600, 0, 900, 903, 909, 926, 0,
452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
453 /* 0x2f - 1440x900@60Hz */
454 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
455 1672, 1904, 0, 900, 903, 909, 934, 0,
456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
457 /* 0x30 - 1440x900@75Hz */
458 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
459 1688, 1936, 0, 900, 903, 909, 942, 0,
460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
461 /* 0x31 - 1440x900@85Hz */
462 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
463 1696, 1952, 0, 900, 903, 909, 948, 0,
464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
465 /* 0x32 - 1440x900@120Hz RB */
466 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
467 1520, 1600, 0, 900, 903, 909, 953, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
469 /* 0x53 - 1600x900@60Hz */
470 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
471 1704, 1800, 0, 900, 901, 904, 1000, 0,
472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
473 /* 0x33 - 1600x1200@60Hz */
474 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
475 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 0x34 - 1600x1200@65Hz */
478 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
479 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
481 /* 0x35 - 1600x1200@70Hz */
482 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
483 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
485 /* 0x36 - 1600x1200@75Hz */
486 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
487 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
489 /* 0x37 - 1600x1200@85Hz */
490 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
491 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
493 /* 0x38 - 1600x1200@120Hz RB */
494 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
495 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
497 /* 0x39 - 1680x1050@60Hz RB */
498 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
499 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
501 /* 0x3a - 1680x1050@60Hz */
502 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
503 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
505 /* 0x3b - 1680x1050@75Hz */
506 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
507 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
509 /* 0x3c - 1680x1050@85Hz */
510 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
511 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
513 /* 0x3d - 1680x1050@120Hz RB */
514 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
515 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
517 /* 0x3e - 1792x1344@60Hz */
518 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
519 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
521 /* 0x3f - 1792x1344@75Hz */
522 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
523 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
525 /* 0x40 - 1792x1344@120Hz RB */
526 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
527 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
529 /* 0x41 - 1856x1392@60Hz */
530 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
531 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
533 /* 0x42 - 1856x1392@75Hz */
534 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
535 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
537 /* 0x43 - 1856x1392@120Hz RB */
538 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
539 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
541 /* 0x52 - 1920x1080@60Hz */
542 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
543 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
545 /* 0x44 - 1920x1200@60Hz RB */
546 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
547 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
549 /* 0x45 - 1920x1200@60Hz */
550 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
551 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
553 /* 0x46 - 1920x1200@75Hz */
554 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
555 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
557 /* 0x47 - 1920x1200@85Hz */
558 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
559 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
561 /* 0x48 - 1920x1200@120Hz RB */
562 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
563 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
565 /* 0x49 - 1920x1440@60Hz */
566 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
567 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
568 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
569 /* 0x4a - 1920x1440@75Hz */
570 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
571 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
573 /* 0x4b - 1920x1440@120Hz RB */
574 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
575 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
577 /* 0x54 - 2048x1152@60Hz */
578 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
579 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
580 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
581 /* 0x4c - 2560x1600@60Hz RB */
582 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
583 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
585 /* 0x4d - 2560x1600@60Hz */
586 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
587 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
588 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
589 /* 0x4e - 2560x1600@75Hz */
590 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
591 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
592 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
593 /* 0x4f - 2560x1600@85Hz */
594 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
595 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
596 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
597 /* 0x50 - 2560x1600@120Hz RB */
598 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
599 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
601 /* 0x57 - 4096x2160@60Hz RB */
602 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
603 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
606 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
607 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
612 * These more or less come from the DMT spec. The 720x400 modes are
613 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
614 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
615 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
618 * The DMT modes have been fact-checked; the rest are mild guesses.
620 static const struct drm_display_mode edid_est_modes[] = {
621 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
622 968, 1056, 0, 600, 601, 605, 628, 0,
623 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
624 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
625 896, 1024, 0, 600, 601, 603, 625, 0,
626 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
627 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
628 720, 840, 0, 480, 481, 484, 500, 0,
629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
630 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
631 704, 832, 0, 480, 489, 492, 520, 0,
632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
633 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
634 768, 864, 0, 480, 483, 486, 525, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
636 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
637 752, 800, 0, 480, 490, 492, 525, 0,
638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
639 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
640 846, 900, 0, 400, 421, 423, 449, 0,
641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
642 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
643 846, 900, 0, 400, 412, 414, 449, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
645 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
646 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
648 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
649 1136, 1312, 0, 768, 769, 772, 800, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
651 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
652 1184, 1328, 0, 768, 771, 777, 806, 0,
653 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
654 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
655 1184, 1344, 0, 768, 771, 777, 806, 0,
656 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
657 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
658 1208, 1264, 0, 768, 768, 776, 817, 0,
659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
660 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
661 928, 1152, 0, 624, 625, 628, 667, 0,
662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
663 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
664 896, 1056, 0, 600, 601, 604, 625, 0,
665 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
666 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
667 976, 1040, 0, 600, 637, 643, 666, 0,
668 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
669 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
670 1344, 1600, 0, 864, 865, 868, 900, 0,
671 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
681 static const struct minimode est3_modes[] = {
689 { 1024, 768, 85, 0 },
690 { 1152, 864, 75, 0 },
692 { 1280, 768, 60, 1 },
693 { 1280, 768, 60, 0 },
694 { 1280, 768, 75, 0 },
695 { 1280, 768, 85, 0 },
696 { 1280, 960, 60, 0 },
697 { 1280, 960, 85, 0 },
698 { 1280, 1024, 60, 0 },
699 { 1280, 1024, 85, 0 },
701 { 1360, 768, 60, 0 },
702 { 1440, 900, 60, 1 },
703 { 1440, 900, 60, 0 },
704 { 1440, 900, 75, 0 },
705 { 1440, 900, 85, 0 },
706 { 1400, 1050, 60, 1 },
707 { 1400, 1050, 60, 0 },
708 { 1400, 1050, 75, 0 },
710 { 1400, 1050, 85, 0 },
711 { 1680, 1050, 60, 1 },
712 { 1680, 1050, 60, 0 },
713 { 1680, 1050, 75, 0 },
714 { 1680, 1050, 85, 0 },
715 { 1600, 1200, 60, 0 },
716 { 1600, 1200, 65, 0 },
717 { 1600, 1200, 70, 0 },
719 { 1600, 1200, 75, 0 },
720 { 1600, 1200, 85, 0 },
721 { 1792, 1344, 60, 0 },
722 { 1792, 1344, 75, 0 },
723 { 1856, 1392, 60, 0 },
724 { 1856, 1392, 75, 0 },
725 { 1920, 1200, 60, 1 },
726 { 1920, 1200, 60, 0 },
728 { 1920, 1200, 75, 0 },
729 { 1920, 1200, 85, 0 },
730 { 1920, 1440, 60, 0 },
731 { 1920, 1440, 75, 0 },
734 static const struct minimode extra_modes[] = {
735 { 1024, 576, 60, 0 },
736 { 1366, 768, 60, 0 },
737 { 1600, 900, 60, 0 },
738 { 1680, 945, 60, 0 },
739 { 1920, 1080, 60, 0 },
740 { 2048, 1152, 60, 0 },
741 { 2048, 1536, 60, 0 },
745 * From CEA/CTA-861 spec.
747 * Do not access directly, instead always use cea_mode_for_vic().
749 static const struct drm_display_mode edid_cea_modes_1[] = {
750 /* 1 - 640x480@60Hz 4:3 */
751 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
752 752, 800, 0, 480, 490, 492, 525, 0,
753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
754 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
755 /* 2 - 720x480@60Hz 4:3 */
756 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
757 798, 858, 0, 480, 489, 495, 525, 0,
758 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
759 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
760 /* 3 - 720x480@60Hz 16:9 */
761 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
762 798, 858, 0, 480, 489, 495, 525, 0,
763 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
765 /* 4 - 1280x720@60Hz 16:9 */
766 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
767 1430, 1650, 0, 720, 725, 730, 750, 0,
768 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
770 /* 5 - 1920x1080i@60Hz 16:9 */
771 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
772 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
773 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
774 DRM_MODE_FLAG_INTERLACE),
775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
776 /* 6 - 720(1440)x480i@60Hz 4:3 */
777 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
778 801, 858, 0, 480, 488, 494, 525, 0,
779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
780 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
782 /* 7 - 720(1440)x480i@60Hz 16:9 */
783 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
784 801, 858, 0, 480, 488, 494, 525, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
786 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
788 /* 8 - 720(1440)x240@60Hz 4:3 */
789 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
790 801, 858, 0, 240, 244, 247, 262, 0,
791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
792 DRM_MODE_FLAG_DBLCLK),
793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
794 /* 9 - 720(1440)x240@60Hz 16:9 */
795 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
796 801, 858, 0, 240, 244, 247, 262, 0,
797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
798 DRM_MODE_FLAG_DBLCLK),
799 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
800 /* 10 - 2880x480i@60Hz 4:3 */
801 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
802 3204, 3432, 0, 480, 488, 494, 525, 0,
803 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
804 DRM_MODE_FLAG_INTERLACE),
805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
806 /* 11 - 2880x480i@60Hz 16:9 */
807 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
808 3204, 3432, 0, 480, 488, 494, 525, 0,
809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
810 DRM_MODE_FLAG_INTERLACE),
811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
812 /* 12 - 2880x240@60Hz 4:3 */
813 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
814 3204, 3432, 0, 240, 244, 247, 262, 0,
815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
817 /* 13 - 2880x240@60Hz 16:9 */
818 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
819 3204, 3432, 0, 240, 244, 247, 262, 0,
820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
822 /* 14 - 1440x480@60Hz 4:3 */
823 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
824 1596, 1716, 0, 480, 489, 495, 525, 0,
825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
827 /* 15 - 1440x480@60Hz 16:9 */
828 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
829 1596, 1716, 0, 480, 489, 495, 525, 0,
830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
831 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
832 /* 16 - 1920x1080@60Hz 16:9 */
833 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
834 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
836 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
837 /* 17 - 720x576@50Hz 4:3 */
838 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
839 796, 864, 0, 576, 581, 586, 625, 0,
840 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
841 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
842 /* 18 - 720x576@50Hz 16:9 */
843 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
844 796, 864, 0, 576, 581, 586, 625, 0,
845 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
847 /* 19 - 1280x720@50Hz 16:9 */
848 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
849 1760, 1980, 0, 720, 725, 730, 750, 0,
850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
852 /* 20 - 1920x1080i@50Hz 16:9 */
853 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
854 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
855 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
856 DRM_MODE_FLAG_INTERLACE),
857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
858 /* 21 - 720(1440)x576i@50Hz 4:3 */
859 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
860 795, 864, 0, 576, 580, 586, 625, 0,
861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
862 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
864 /* 22 - 720(1440)x576i@50Hz 16:9 */
865 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
866 795, 864, 0, 576, 580, 586, 625, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
868 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
870 /* 23 - 720(1440)x288@50Hz 4:3 */
871 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
872 795, 864, 0, 288, 290, 293, 312, 0,
873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
874 DRM_MODE_FLAG_DBLCLK),
875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
876 /* 24 - 720(1440)x288@50Hz 16:9 */
877 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
878 795, 864, 0, 288, 290, 293, 312, 0,
879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
880 DRM_MODE_FLAG_DBLCLK),
881 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
882 /* 25 - 2880x576i@50Hz 4:3 */
883 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
884 3180, 3456, 0, 576, 580, 586, 625, 0,
885 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
886 DRM_MODE_FLAG_INTERLACE),
887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
888 /* 26 - 2880x576i@50Hz 16:9 */
889 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
890 3180, 3456, 0, 576, 580, 586, 625, 0,
891 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
892 DRM_MODE_FLAG_INTERLACE),
893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
894 /* 27 - 2880x288@50Hz 4:3 */
895 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
896 3180, 3456, 0, 288, 290, 293, 312, 0,
897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
899 /* 28 - 2880x288@50Hz 16:9 */
900 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
901 3180, 3456, 0, 288, 290, 293, 312, 0,
902 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
904 /* 29 - 1440x576@50Hz 4:3 */
905 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
906 1592, 1728, 0, 576, 581, 586, 625, 0,
907 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
909 /* 30 - 1440x576@50Hz 16:9 */
910 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
911 1592, 1728, 0, 576, 581, 586, 625, 0,
912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
914 /* 31 - 1920x1080@50Hz 16:9 */
915 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
916 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
919 /* 32 - 1920x1080@24Hz 16:9 */
920 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
921 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
924 /* 33 - 1920x1080@25Hz 16:9 */
925 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
926 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
929 /* 34 - 1920x1080@30Hz 16:9 */
930 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
931 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
933 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
934 /* 35 - 2880x480@60Hz 4:3 */
935 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
936 3192, 3432, 0, 480, 489, 495, 525, 0,
937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
938 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
939 /* 36 - 2880x480@60Hz 16:9 */
940 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
941 3192, 3432, 0, 480, 489, 495, 525, 0,
942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
943 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
944 /* 37 - 2880x576@50Hz 4:3 */
945 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
946 3184, 3456, 0, 576, 581, 586, 625, 0,
947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
948 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
949 /* 38 - 2880x576@50Hz 16:9 */
950 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
951 3184, 3456, 0, 576, 581, 586, 625, 0,
952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
953 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
954 /* 39 - 1920x1080i@50Hz 16:9 */
955 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
956 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
957 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
958 DRM_MODE_FLAG_INTERLACE),
959 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
960 /* 40 - 1920x1080i@100Hz 16:9 */
961 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
962 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
963 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
964 DRM_MODE_FLAG_INTERLACE),
965 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
966 /* 41 - 1280x720@100Hz 16:9 */
967 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
968 1760, 1980, 0, 720, 725, 730, 750, 0,
969 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
970 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
971 /* 42 - 720x576@100Hz 4:3 */
972 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
973 796, 864, 0, 576, 581, 586, 625, 0,
974 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
976 /* 43 - 720x576@100Hz 16:9 */
977 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
978 796, 864, 0, 576, 581, 586, 625, 0,
979 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
981 /* 44 - 720(1440)x576i@100Hz 4:3 */
982 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
983 795, 864, 0, 576, 580, 586, 625, 0,
984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
985 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
986 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
987 /* 45 - 720(1440)x576i@100Hz 16:9 */
988 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
989 795, 864, 0, 576, 580, 586, 625, 0,
990 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
991 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
992 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
993 /* 46 - 1920x1080i@120Hz 16:9 */
994 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
995 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
996 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
997 DRM_MODE_FLAG_INTERLACE),
998 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
999 /* 47 - 1280x720@120Hz 16:9 */
1000 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1001 1430, 1650, 0, 720, 725, 730, 750, 0,
1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1003 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1004 /* 48 - 720x480@120Hz 4:3 */
1005 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1006 798, 858, 0, 480, 489, 495, 525, 0,
1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1008 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1009 /* 49 - 720x480@120Hz 16:9 */
1010 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1011 798, 858, 0, 480, 489, 495, 525, 0,
1012 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1013 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1014 /* 50 - 720(1440)x480i@120Hz 4:3 */
1015 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1016 801, 858, 0, 480, 488, 494, 525, 0,
1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1018 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1019 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1020 /* 51 - 720(1440)x480i@120Hz 16:9 */
1021 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1022 801, 858, 0, 480, 488, 494, 525, 0,
1023 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1024 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1025 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1026 /* 52 - 720x576@200Hz 4:3 */
1027 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1028 796, 864, 0, 576, 581, 586, 625, 0,
1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1030 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1031 /* 53 - 720x576@200Hz 16:9 */
1032 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1033 796, 864, 0, 576, 581, 586, 625, 0,
1034 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1035 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1036 /* 54 - 720(1440)x576i@200Hz 4:3 */
1037 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1038 795, 864, 0, 576, 580, 586, 625, 0,
1039 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1040 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1041 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1042 /* 55 - 720(1440)x576i@200Hz 16:9 */
1043 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1044 795, 864, 0, 576, 580, 586, 625, 0,
1045 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1046 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1047 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1048 /* 56 - 720x480@240Hz 4:3 */
1049 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1050 798, 858, 0, 480, 489, 495, 525, 0,
1051 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1052 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1053 /* 57 - 720x480@240Hz 16:9 */
1054 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1055 798, 858, 0, 480, 489, 495, 525, 0,
1056 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1057 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1058 /* 58 - 720(1440)x480i@240Hz 4:3 */
1059 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1060 801, 858, 0, 480, 488, 494, 525, 0,
1061 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1062 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1064 /* 59 - 720(1440)x480i@240Hz 16:9 */
1065 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1066 801, 858, 0, 480, 488, 494, 525, 0,
1067 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1068 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1070 /* 60 - 1280x720@24Hz 16:9 */
1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1072 3080, 3300, 0, 720, 725, 730, 750, 0,
1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1075 /* 61 - 1280x720@25Hz 16:9 */
1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1077 3740, 3960, 0, 720, 725, 730, 750, 0,
1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1080 /* 62 - 1280x720@30Hz 16:9 */
1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1082 3080, 3300, 0, 720, 725, 730, 750, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1085 /* 63 - 1920x1080@120Hz 16:9 */
1086 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1087 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1090 /* 64 - 1920x1080@100Hz 16:9 */
1091 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1092 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1095 /* 65 - 1280x720@24Hz 64:27 */
1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1097 3080, 3300, 0, 720, 725, 730, 750, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1100 /* 66 - 1280x720@25Hz 64:27 */
1101 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1102 3740, 3960, 0, 720, 725, 730, 750, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1105 /* 67 - 1280x720@30Hz 64:27 */
1106 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1107 3080, 3300, 0, 720, 725, 730, 750, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1110 /* 68 - 1280x720@50Hz 64:27 */
1111 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1112 1760, 1980, 0, 720, 725, 730, 750, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1115 /* 69 - 1280x720@60Hz 64:27 */
1116 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1117 1430, 1650, 0, 720, 725, 730, 750, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1120 /* 70 - 1280x720@100Hz 64:27 */
1121 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1122 1760, 1980, 0, 720, 725, 730, 750, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1125 /* 71 - 1280x720@120Hz 64:27 */
1126 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1127 1430, 1650, 0, 720, 725, 730, 750, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1130 /* 72 - 1920x1080@24Hz 64:27 */
1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1132 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1135 /* 73 - 1920x1080@25Hz 64:27 */
1136 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1137 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1140 /* 74 - 1920x1080@30Hz 64:27 */
1141 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1142 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1145 /* 75 - 1920x1080@50Hz 64:27 */
1146 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1147 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1150 /* 76 - 1920x1080@60Hz 64:27 */
1151 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1152 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1155 /* 77 - 1920x1080@100Hz 64:27 */
1156 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1157 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1160 /* 78 - 1920x1080@120Hz 64:27 */
1161 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1162 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1165 /* 79 - 1680x720@24Hz 64:27 */
1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1167 3080, 3300, 0, 720, 725, 730, 750, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1170 /* 80 - 1680x720@25Hz 64:27 */
1171 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1172 2948, 3168, 0, 720, 725, 730, 750, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1175 /* 81 - 1680x720@30Hz 64:27 */
1176 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1177 2420, 2640, 0, 720, 725, 730, 750, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1180 /* 82 - 1680x720@50Hz 64:27 */
1181 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1182 1980, 2200, 0, 720, 725, 730, 750, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1185 /* 83 - 1680x720@60Hz 64:27 */
1186 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1187 1980, 2200, 0, 720, 725, 730, 750, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1190 /* 84 - 1680x720@100Hz 64:27 */
1191 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1192 1780, 2000, 0, 720, 725, 730, 825, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1195 /* 85 - 1680x720@120Hz 64:27 */
1196 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1197 1780, 2000, 0, 720, 725, 730, 825, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1200 /* 86 - 2560x1080@24Hz 64:27 */
1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1202 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1205 /* 87 - 2560x1080@25Hz 64:27 */
1206 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1207 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1210 /* 88 - 2560x1080@30Hz 64:27 */
1211 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1212 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1215 /* 89 - 2560x1080@50Hz 64:27 */
1216 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1217 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1220 /* 90 - 2560x1080@60Hz 64:27 */
1221 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1222 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1225 /* 91 - 2560x1080@100Hz 64:27 */
1226 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1227 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1230 /* 92 - 2560x1080@120Hz 64:27 */
1231 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1232 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1235 /* 93 - 3840x2160@24Hz 16:9 */
1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1237 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1240 /* 94 - 3840x2160@25Hz 16:9 */
1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1242 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1245 /* 95 - 3840x2160@30Hz 16:9 */
1246 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1247 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1250 /* 96 - 3840x2160@50Hz 16:9 */
1251 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1252 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1255 /* 97 - 3840x2160@60Hz 16:9 */
1256 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1257 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1260 /* 98 - 4096x2160@24Hz 256:135 */
1261 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1262 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1265 /* 99 - 4096x2160@25Hz 256:135 */
1266 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1267 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1270 /* 100 - 4096x2160@30Hz 256:135 */
1271 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1272 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1275 /* 101 - 4096x2160@50Hz 256:135 */
1276 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1277 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1280 /* 102 - 4096x2160@60Hz 256:135 */
1281 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1282 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1285 /* 103 - 3840x2160@24Hz 64:27 */
1286 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1287 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1290 /* 104 - 3840x2160@25Hz 64:27 */
1291 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1292 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1295 /* 105 - 3840x2160@30Hz 64:27 */
1296 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1297 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1300 /* 106 - 3840x2160@50Hz 64:27 */
1301 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1302 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1305 /* 107 - 3840x2160@60Hz 64:27 */
1306 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1307 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1310 /* 108 - 1280x720@48Hz 16:9 */
1311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1312 2280, 2500, 0, 720, 725, 730, 750, 0,
1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1315 /* 109 - 1280x720@48Hz 64:27 */
1316 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1317 2280, 2500, 0, 720, 725, 730, 750, 0,
1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1320 /* 110 - 1680x720@48Hz 64:27 */
1321 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1322 2530, 2750, 0, 720, 725, 730, 750, 0,
1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1325 /* 111 - 1920x1080@48Hz 16:9 */
1326 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1327 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1330 /* 112 - 1920x1080@48Hz 64:27 */
1331 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1332 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1335 /* 113 - 2560x1080@48Hz 64:27 */
1336 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1337 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1340 /* 114 - 3840x2160@48Hz 16:9 */
1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1342 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1345 /* 115 - 4096x2160@48Hz 256:135 */
1346 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1347 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1350 /* 116 - 3840x2160@48Hz 64:27 */
1351 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1352 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1355 /* 117 - 3840x2160@100Hz 16:9 */
1356 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1357 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1360 /* 118 - 3840x2160@120Hz 16:9 */
1361 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1362 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1365 /* 119 - 3840x2160@100Hz 64:27 */
1366 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1367 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1370 /* 120 - 3840x2160@120Hz 64:27 */
1371 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1372 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1375 /* 121 - 5120x2160@24Hz 64:27 */
1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1377 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1380 /* 122 - 5120x2160@25Hz 64:27 */
1381 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1382 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1384 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1385 /* 123 - 5120x2160@30Hz 64:27 */
1386 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1387 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1389 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1390 /* 124 - 5120x2160@48Hz 64:27 */
1391 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1392 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1394 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1395 /* 125 - 5120x2160@50Hz 64:27 */
1396 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1397 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1399 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1400 /* 126 - 5120x2160@60Hz 64:27 */
1401 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1402 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1405 /* 127 - 5120x2160@100Hz 64:27 */
1406 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1407 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1413 * From CEA/CTA-861 spec.
1415 * Do not access directly, instead always use cea_mode_for_vic().
1417 static const struct drm_display_mode edid_cea_modes_193[] = {
1418 /* 193 - 5120x2160@120Hz 64:27 */
1419 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1420 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1423 /* 194 - 7680x4320@24Hz 16:9 */
1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1425 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1428 /* 195 - 7680x4320@25Hz 16:9 */
1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1430 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1433 /* 196 - 7680x4320@30Hz 16:9 */
1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1435 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1438 /* 197 - 7680x4320@48Hz 16:9 */
1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1440 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1443 /* 198 - 7680x4320@50Hz 16:9 */
1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1445 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1448 /* 199 - 7680x4320@60Hz 16:9 */
1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1450 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1453 /* 200 - 7680x4320@100Hz 16:9 */
1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1455 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1458 /* 201 - 7680x4320@120Hz 16:9 */
1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1460 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1463 /* 202 - 7680x4320@24Hz 64:27 */
1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1465 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1468 /* 203 - 7680x4320@25Hz 64:27 */
1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1470 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1473 /* 204 - 7680x4320@30Hz 64:27 */
1474 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1475 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1478 /* 205 - 7680x4320@48Hz 64:27 */
1479 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1480 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1483 /* 206 - 7680x4320@50Hz 64:27 */
1484 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1485 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1488 /* 207 - 7680x4320@60Hz 64:27 */
1489 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1490 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1493 /* 208 - 7680x4320@100Hz 64:27 */
1494 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1495 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1498 /* 209 - 7680x4320@120Hz 64:27 */
1499 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1500 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1503 /* 210 - 10240x4320@24Hz 64:27 */
1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1505 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1508 /* 211 - 10240x4320@25Hz 64:27 */
1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1510 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1513 /* 212 - 10240x4320@30Hz 64:27 */
1514 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1515 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1518 /* 213 - 10240x4320@48Hz 64:27 */
1519 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1520 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1523 /* 214 - 10240x4320@50Hz 64:27 */
1524 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1525 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1527 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1528 /* 215 - 10240x4320@60Hz 64:27 */
1529 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1530 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1532 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1533 /* 216 - 10240x4320@100Hz 64:27 */
1534 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1535 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1537 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1538 /* 217 - 10240x4320@120Hz 64:27 */
1539 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1540 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1542 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1543 /* 218 - 4096x2160@100Hz 256:135 */
1544 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1545 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1548 /* 219 - 4096x2160@120Hz 256:135 */
1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1550 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1552 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1556 * HDMI 1.4 4k modes. Index using the VIC.
1558 static const struct drm_display_mode edid_4k_modes[] = {
1559 /* 0 - dummy, VICs start at 1 */
1561 /* 1 - 3840x2160@30Hz */
1562 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1563 3840, 4016, 4104, 4400, 0,
1564 2160, 2168, 2178, 2250, 0,
1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1567 /* 2 - 3840x2160@25Hz */
1568 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1569 3840, 4896, 4984, 5280, 0,
1570 2160, 2168, 2178, 2250, 0,
1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1572 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1573 /* 3 - 3840x2160@24Hz */
1574 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1575 3840, 5116, 5204, 5500, 0,
1576 2160, 2168, 2178, 2250, 0,
1577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1578 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1579 /* 4 - 4096x2160@24Hz (SMPTE) */
1580 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1581 4096, 5116, 5204, 5500, 0,
1582 2160, 2168, 2178, 2250, 0,
1583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1584 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1587 /*** DDC fetch and block validation ***/
1590 * The opaque EDID type, internal to drm_edid.c.
1593 /* Size allocated for edid */
1595 const struct edid *edid;
1598 static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1600 static int edid_hfeeodb_block_count(const struct edid *edid)
1602 int eeodb = edid_hfeeodb_extension_block_count(edid);
1604 return eeodb ? eeodb + 1 : 0;
1607 static int edid_extension_block_count(const struct edid *edid)
1609 return edid->extensions;
1612 static int edid_block_count(const struct edid *edid)
1614 return edid_extension_block_count(edid) + 1;
1617 static int edid_size_by_blocks(int num_blocks)
1619 return num_blocks * EDID_LENGTH;
1622 static int edid_size(const struct edid *edid)
1624 return edid_size_by_blocks(edid_block_count(edid));
1627 static const void *edid_block_data(const struct edid *edid, int index)
1629 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1631 return edid + index;
1634 static const void *edid_extension_block_data(const struct edid *edid, int index)
1636 return edid_block_data(edid, index + 1);
1639 /* EDID block count indicated in EDID, may exceed allocated size */
1640 static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1644 /* Starting point */
1645 num_blocks = edid_block_count(drm_edid->edid);
1647 /* HF-EEODB override */
1648 if (drm_edid->size >= edid_size_by_blocks(2)) {
1652 * Note: HF-EEODB may specify a smaller extension count than the
1653 * regular one. Unlike in buffer allocation, here we can use it.
1655 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1663 /* EDID block count, limited by allocated size */
1664 static int drm_edid_block_count(const struct drm_edid *drm_edid)
1666 /* Limit by allocated size */
1667 return min(__drm_edid_block_count(drm_edid),
1668 (int)drm_edid->size / EDID_LENGTH);
1671 /* EDID extension block count, limited by allocated size */
1672 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1674 return drm_edid_block_count(drm_edid) - 1;
1677 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1679 return edid_block_data(drm_edid->edid, index);
1682 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1685 return edid_extension_block_data(drm_edid->edid, index);
1689 * Initializer helper for legacy interfaces, where we have no choice but to
1690 * trust edid size. Not for general purpose use.
1692 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1693 const struct edid *edid)
1698 memset(drm_edid, 0, sizeof(*drm_edid));
1700 drm_edid->edid = edid;
1701 drm_edid->size = edid_size(edid);
1707 * EDID base and extension block iterator.
1709 * struct drm_edid_iter iter;
1712 * drm_edid_iter_begin(drm_edid, &iter);
1713 * drm_edid_iter_for_each(block, &iter) {
1714 * // do stuff with block
1716 * drm_edid_iter_end(&iter);
1718 struct drm_edid_iter {
1719 const struct drm_edid *drm_edid;
1721 /* Current block index. */
1725 static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1726 struct drm_edid_iter *iter)
1728 memset(iter, 0, sizeof(*iter));
1730 iter->drm_edid = drm_edid;
1733 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1735 const void *block = NULL;
1737 if (!iter->drm_edid)
1740 if (iter->index < drm_edid_block_count(iter->drm_edid))
1741 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1746 #define drm_edid_iter_for_each(__block, __iter) \
1747 while (((__block) = __drm_edid_iter_next(__iter)))
1749 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1751 memset(iter, 0, sizeof(*iter));
1754 static const u8 edid_header[] = {
1755 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1758 static void edid_header_fix(void *edid)
1760 memcpy(edid, edid_header, sizeof(edid_header));
1764 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1765 * @_edid: pointer to raw base EDID block
1767 * Sanity check the header of the base EDID block.
1769 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1771 int drm_edid_header_is_valid(const void *_edid)
1773 const struct edid *edid = _edid;
1776 for (i = 0; i < sizeof(edid_header); i++) {
1777 if (edid->header[i] == edid_header[i])
1783 EXPORT_SYMBOL(drm_edid_header_is_valid);
1785 static int edid_fixup __read_mostly = 6;
1786 module_param_named(edid_fixup, edid_fixup, int, 0400);
1787 MODULE_PARM_DESC(edid_fixup,
1788 "Minimum number of valid EDID header bytes (0-8, default 6)");
1790 static int edid_block_compute_checksum(const void *_block)
1792 const u8 *block = _block;
1794 u8 csum = 0, crc = 0;
1796 for (i = 0; i < EDID_LENGTH - 1; i++)
1804 static int edid_block_get_checksum(const void *_block)
1806 const struct edid *block = _block;
1808 return block->checksum;
1811 static int edid_block_tag(const void *_block)
1813 const u8 *block = _block;
1818 static bool edid_block_is_zero(const void *edid)
1820 return !memchr_inv(edid, 0, EDID_LENGTH);
1823 static bool drm_edid_eq(const struct drm_edid *drm_edid,
1824 const void *raw_edid, size_t raw_edid_size)
1826 bool edid1_present = drm_edid && drm_edid->edid && drm_edid->size;
1827 bool edid2_present = raw_edid && raw_edid_size;
1829 if (edid1_present != edid2_present)
1832 if (edid1_present) {
1833 if (drm_edid->size != raw_edid_size)
1836 if (memcmp(drm_edid->edid, raw_edid, drm_edid->size))
1843 enum edid_block_status {
1845 EDID_BLOCK_READ_FAIL,
1848 EDID_BLOCK_HEADER_CORRUPT,
1849 EDID_BLOCK_HEADER_REPAIR,
1850 EDID_BLOCK_HEADER_FIXED,
1851 EDID_BLOCK_CHECKSUM,
1855 static enum edid_block_status edid_block_check(const void *_block,
1858 const struct edid *block = _block;
1861 return EDID_BLOCK_NULL;
1863 if (is_base_block) {
1864 int score = drm_edid_header_is_valid(block);
1866 if (score < clamp(edid_fixup, 0, 8)) {
1867 if (edid_block_is_zero(block))
1868 return EDID_BLOCK_ZERO;
1870 return EDID_BLOCK_HEADER_CORRUPT;
1874 return EDID_BLOCK_HEADER_REPAIR;
1877 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1878 if (edid_block_is_zero(block))
1879 return EDID_BLOCK_ZERO;
1881 return EDID_BLOCK_CHECKSUM;
1884 if (is_base_block) {
1885 if (block->version != 1)
1886 return EDID_BLOCK_VERSION;
1889 return EDID_BLOCK_OK;
1892 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1894 return status == EDID_BLOCK_OK ||
1895 status == EDID_BLOCK_HEADER_FIXED ||
1896 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1899 static bool edid_block_valid(const void *block, bool base)
1901 return edid_block_status_valid(edid_block_check(block, base),
1902 edid_block_tag(block));
1905 static void edid_block_status_print(enum edid_block_status status,
1906 const struct edid *block,
1912 case EDID_BLOCK_READ_FAIL:
1913 pr_debug("EDID block %d read failed\n", block_num);
1915 case EDID_BLOCK_NULL:
1916 pr_debug("EDID block %d pointer is NULL\n", block_num);
1918 case EDID_BLOCK_ZERO:
1919 pr_notice("EDID block %d is all zeroes\n", block_num);
1921 case EDID_BLOCK_HEADER_CORRUPT:
1922 pr_notice("EDID has corrupt header\n");
1924 case EDID_BLOCK_HEADER_REPAIR:
1925 pr_debug("EDID corrupt header needs repair\n");
1927 case EDID_BLOCK_HEADER_FIXED:
1928 pr_debug("EDID corrupt header fixed\n");
1930 case EDID_BLOCK_CHECKSUM:
1931 if (edid_block_status_valid(status, edid_block_tag(block))) {
1932 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1933 block_num, edid_block_tag(block),
1934 edid_block_compute_checksum(block));
1936 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1937 block_num, edid_block_tag(block),
1938 edid_block_compute_checksum(block));
1941 case EDID_BLOCK_VERSION:
1942 pr_notice("EDID has major version %d, instead of 1\n",
1946 WARN(1, "EDID block %d unknown edid block status code %d\n",
1952 static void edid_block_dump(const char *level, const void *block, int block_num)
1954 enum edid_block_status status;
1957 status = edid_block_check(block, block_num == 0);
1958 if (status == EDID_BLOCK_ZERO)
1959 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1960 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1961 sprintf(prefix, "\t[%02x] BAD ", block_num);
1963 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1965 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1966 block, EDID_LENGTH, false);
1970 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1971 * @_block: pointer to raw EDID block
1972 * @block_num: type of block to validate (0 for base, extension otherwise)
1973 * @print_bad_edid: if true, dump bad EDID blocks to the console
1974 * @edid_corrupt: if true, the header or checksum is invalid
1976 * Validate a base or extension EDID block and optionally dump bad blocks to
1979 * Return: True if the block is valid, false otherwise.
1981 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1984 struct edid *block = (struct edid *)_block;
1985 enum edid_block_status status;
1986 bool is_base_block = block_num == 0;
1989 if (WARN_ON(!block))
1992 status = edid_block_check(block, is_base_block);
1993 if (status == EDID_BLOCK_HEADER_REPAIR) {
1994 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1995 edid_header_fix(block);
1997 /* Retry with fixed header, update status if that worked. */
1998 status = edid_block_check(block, is_base_block);
1999 if (status == EDID_BLOCK_OK)
2000 status = EDID_BLOCK_HEADER_FIXED;
2005 * Unknown major version isn't corrupt but we can't use it. Only
2006 * the base block can reset edid_corrupt to false.
2008 if (is_base_block &&
2009 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2010 *edid_corrupt = false;
2011 else if (status != EDID_BLOCK_OK)
2012 *edid_corrupt = true;
2015 edid_block_status_print(status, block, block_num);
2017 /* Determine whether we can use this block with this status. */
2018 valid = edid_block_status_valid(status, edid_block_tag(block));
2020 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2021 pr_notice("Raw EDID:\n");
2022 edid_block_dump(KERN_NOTICE, block, block_num);
2027 EXPORT_SYMBOL(drm_edid_block_valid);
2030 * drm_edid_is_valid - sanity check EDID data
2033 * Sanity-check an entire EDID record (including extensions)
2035 * Return: True if the EDID data is valid, false otherwise.
2037 bool drm_edid_is_valid(struct edid *edid)
2044 for (i = 0; i < edid_block_count(edid); i++) {
2045 void *block = (void *)edid_block_data(edid, i);
2047 if (!drm_edid_block_valid(block, i, true, NULL))
2053 EXPORT_SYMBOL(drm_edid_is_valid);
2056 * drm_edid_valid - sanity check EDID data
2057 * @drm_edid: EDID data
2059 * Sanity check an EDID. Cross check block count against allocated size and
2060 * checksum the blocks.
2062 * Return: True if the EDID data is valid, false otherwise.
2064 bool drm_edid_valid(const struct drm_edid *drm_edid)
2071 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2074 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2075 const void *block = drm_edid_block_data(drm_edid, i);
2077 if (!edid_block_valid(block, i == 0))
2083 EXPORT_SYMBOL(drm_edid_valid);
2085 static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2089 int i, valid_blocks = 0;
2092 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2093 * back to regular extension count here. We don't want to start
2094 * modifying the HF-EEODB extension too.
2096 for (i = 0; i < edid_block_count(edid); i++) {
2097 const void *src_block = edid_block_data(edid, i);
2099 if (edid_block_valid(src_block, i == 0)) {
2100 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2102 memmove(dst_block, src_block, EDID_LENGTH);
2107 /* We already trusted the base block to be valid here... */
2108 if (WARN_ON(!valid_blocks)) {
2113 edid->extensions = valid_blocks - 1;
2114 edid->checksum = edid_block_compute_checksum(edid);
2116 *alloc_size = edid_size_by_blocks(valid_blocks);
2118 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2125 #define DDC_SEGMENT_ADDR 0x30
2127 * drm_do_probe_ddc_edid() - get EDID information via I2C
2128 * @data: I2C device adapter
2129 * @buf: EDID data buffer to be filled
2130 * @block: 128 byte EDID block to start fetching from
2131 * @len: EDID data buffer length to fetch
2133 * Try to fetch EDID information by calling I2C driver functions.
2135 * Return: 0 on success or -1 on failure.
2138 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2140 struct i2c_adapter *adapter = data;
2141 unsigned char start = block * EDID_LENGTH;
2142 unsigned char segment = block >> 1;
2143 unsigned char xfers = segment ? 3 : 2;
2144 int ret, retries = 5;
2147 * The core I2C driver will automatically retry the transfer if the
2148 * adapter reports EAGAIN. However, we find that bit-banging transfers
2149 * are susceptible to errors under a heavily loaded machine and
2150 * generate spurious NAKs and timeouts. Retrying the transfer
2151 * of the individual block a few times seems to overcome this.
2154 struct i2c_msg msgs[] = {
2156 .addr = DDC_SEGMENT_ADDR,
2174 * Avoid sending the segment addr to not upset non-compliant
2177 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2179 if (ret == -ENXIO) {
2180 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2184 } while (ret != xfers && --retries);
2186 return ret == xfers ? 0 : -1;
2189 static void connector_bad_edid(struct drm_connector *connector,
2190 const struct edid *edid, int num_blocks)
2196 * 0x7e in the EDID is the number of extension blocks. The EDID
2197 * is 1 (base block) + num_ext_blocks big. That means we can think
2198 * of 0x7e in the EDID of the _index_ of the last block in the
2199 * combined chunk of memory.
2201 last_block = edid->extensions;
2203 /* Calculate real checksum for the last edid extension block data */
2204 if (last_block < num_blocks)
2205 connector->real_edid_checksum =
2206 edid_block_compute_checksum(edid + last_block);
2208 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2211 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2212 connector->base.id, connector->name);
2213 for (i = 0; i < num_blocks; i++)
2214 edid_block_dump(KERN_DEBUG, edid + i, i);
2217 /* Get override or firmware EDID */
2218 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2220 const struct drm_edid *override = NULL;
2222 mutex_lock(&connector->edid_override_mutex);
2224 if (connector->edid_override)
2225 override = drm_edid_dup(connector->edid_override);
2227 mutex_unlock(&connector->edid_override_mutex);
2230 override = drm_edid_load_firmware(connector);
2232 return IS_ERR(override) ? NULL : override;
2235 /* For debugfs edid_override implementation */
2236 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2238 const struct drm_edid *drm_edid;
2240 mutex_lock(&connector->edid_override_mutex);
2242 drm_edid = connector->edid_override;
2244 seq_write(m, drm_edid->edid, drm_edid->size);
2246 mutex_unlock(&connector->edid_override_mutex);
2251 /* For debugfs edid_override implementation */
2252 int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2255 const struct drm_edid *drm_edid;
2257 drm_edid = drm_edid_alloc(edid, size);
2258 if (!drm_edid_valid(drm_edid)) {
2259 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2260 connector->base.id, connector->name);
2261 drm_edid_free(drm_edid);
2265 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2266 connector->base.id, connector->name);
2268 mutex_lock(&connector->edid_override_mutex);
2270 drm_edid_free(connector->edid_override);
2271 connector->edid_override = drm_edid;
2273 mutex_unlock(&connector->edid_override_mutex);
2278 /* For debugfs edid_override implementation */
2279 int drm_edid_override_reset(struct drm_connector *connector)
2281 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2282 connector->base.id, connector->name);
2284 mutex_lock(&connector->edid_override_mutex);
2286 drm_edid_free(connector->edid_override);
2287 connector->edid_override = NULL;
2289 mutex_unlock(&connector->edid_override_mutex);
2295 * drm_edid_override_connector_update - add modes from override/firmware EDID
2296 * @connector: connector we're probing
2298 * Add modes from the override/firmware EDID, if available. Only to be used from
2299 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2300 * failed during drm_get_edid() and caused the override/firmware EDID to be
2303 * Return: The number of modes added or 0 if we couldn't find any.
2305 int drm_edid_override_connector_update(struct drm_connector *connector)
2307 const struct drm_edid *override;
2310 override = drm_edid_override_get(connector);
2312 if (drm_edid_connector_update(connector, override) == 0)
2313 num_modes = drm_edid_connector_add_modes(connector);
2315 drm_edid_free(override);
2317 drm_dbg_kms(connector->dev,
2318 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2319 connector->base.id, connector->name, num_modes);
2324 EXPORT_SYMBOL(drm_edid_override_connector_update);
2326 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2328 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2329 read_block_fn read_block,
2332 enum edid_block_status status;
2333 bool is_base_block = block_num == 0;
2336 for (try = 0; try < 4; try++) {
2337 if (read_block(context, block, block_num, EDID_LENGTH))
2338 return EDID_BLOCK_READ_FAIL;
2340 status = edid_block_check(block, is_base_block);
2341 if (status == EDID_BLOCK_HEADER_REPAIR) {
2342 edid_header_fix(block);
2344 /* Retry with fixed header, update status if that worked. */
2345 status = edid_block_check(block, is_base_block);
2346 if (status == EDID_BLOCK_OK)
2347 status = EDID_BLOCK_HEADER_FIXED;
2350 if (edid_block_status_valid(status, edid_block_tag(block)))
2353 /* Fail early for unrepairable base block all zeros. */
2354 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2361 static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2362 read_block_fn read_block, void *context,
2365 enum edid_block_status status;
2366 int i, num_blocks, invalid_blocks = 0;
2367 const struct drm_edid *override;
2368 struct edid *edid, *new;
2369 size_t alloc_size = EDID_LENGTH;
2371 override = drm_edid_override_get(connector);
2373 alloc_size = override->size;
2374 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2375 drm_edid_free(override);
2381 edid = kmalloc(alloc_size, GFP_KERNEL);
2385 status = edid_block_read(edid, 0, read_block, context);
2387 edid_block_status_print(status, edid, 0);
2389 if (status == EDID_BLOCK_READ_FAIL)
2392 /* FIXME: Clarify what a corrupt EDID actually means. */
2393 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2394 connector->edid_corrupt = false;
2396 connector->edid_corrupt = true;
2398 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2399 if (status == EDID_BLOCK_ZERO)
2400 connector->null_edid_counter++;
2402 connector_bad_edid(connector, edid, 1);
2406 if (!edid_extension_block_count(edid))
2409 alloc_size = edid_size(edid);
2410 new = krealloc(edid, alloc_size, GFP_KERNEL);
2415 num_blocks = edid_block_count(edid);
2416 for (i = 1; i < num_blocks; i++) {
2417 void *block = (void *)edid_block_data(edid, i);
2419 status = edid_block_read(block, i, read_block, context);
2421 edid_block_status_print(status, block, i);
2423 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2424 if (status == EDID_BLOCK_READ_FAIL)
2427 } else if (i == 1) {
2429 * If the first EDID extension is a CTA extension, and
2430 * the first Data Block is HF-EEODB, override the
2431 * extension block count.
2433 * Note: HF-EEODB could specify a smaller extension
2434 * count too, but we can't risk allocating a smaller
2437 int eeodb = edid_hfeeodb_block_count(edid);
2439 if (eeodb > num_blocks) {
2441 alloc_size = edid_size_by_blocks(num_blocks);
2442 new = krealloc(edid, alloc_size, GFP_KERNEL);
2450 if (invalid_blocks) {
2451 connector_bad_edid(connector, edid, num_blocks);
2453 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2468 * drm_edid_raw - Get a pointer to the raw EDID data.
2469 * @drm_edid: drm_edid container
2471 * Get a pointer to the raw EDID data.
2473 * This is for transition only. Avoid using this like the plague.
2475 * Return: Pointer to raw EDID data.
2477 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2479 if (!drm_edid || !drm_edid->size)
2483 * Do not return pointers where relying on EDID extension count would
2484 * lead to buffer overflow.
2486 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2489 return drm_edid->edid;
2491 EXPORT_SYMBOL(drm_edid_raw);
2493 /* Allocate struct drm_edid container *without* duplicating the edid data */
2494 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2496 struct drm_edid *drm_edid;
2498 if (!edid || !size || size < EDID_LENGTH)
2501 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2503 drm_edid->edid = edid;
2504 drm_edid->size = size;
2511 * drm_edid_alloc - Allocate a new drm_edid container
2512 * @edid: Pointer to raw EDID data
2513 * @size: Size of memory allocated for EDID
2515 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2516 * the actual size that has been allocated for the data. There is no validation
2517 * of the raw EDID data against the size, but at least the EDID base block must
2518 * fit in the buffer.
2520 * The returned pointer must be freed using drm_edid_free().
2522 * Return: drm_edid container, or NULL on errors
2524 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2526 const struct drm_edid *drm_edid;
2528 if (!edid || !size || size < EDID_LENGTH)
2531 edid = kmemdup(edid, size, GFP_KERNEL);
2535 drm_edid = _drm_edid_alloc(edid, size);
2541 EXPORT_SYMBOL(drm_edid_alloc);
2544 * drm_edid_dup - Duplicate a drm_edid container
2545 * @drm_edid: EDID to duplicate
2547 * The returned pointer must be freed using drm_edid_free().
2549 * Returns: drm_edid container copy, or NULL on errors
2551 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2556 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2558 EXPORT_SYMBOL(drm_edid_dup);
2561 * drm_edid_free - Free the drm_edid container
2562 * @drm_edid: EDID to free
2564 void drm_edid_free(const struct drm_edid *drm_edid)
2569 kfree(drm_edid->edid);
2572 EXPORT_SYMBOL(drm_edid_free);
2575 * drm_probe_ddc() - probe DDC presence
2576 * @adapter: I2C adapter to probe
2578 * Return: True on success, false on failure.
2581 drm_probe_ddc(struct i2c_adapter *adapter)
2585 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2587 EXPORT_SYMBOL(drm_probe_ddc);
2590 * drm_get_edid - get EDID data, if available
2591 * @connector: connector we're probing
2592 * @adapter: I2C adapter to use for DDC
2594 * Poke the given I2C channel to grab EDID data if possible. If found,
2595 * attach it to the connector.
2597 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2599 struct edid *drm_get_edid(struct drm_connector *connector,
2600 struct i2c_adapter *adapter)
2604 if (connector->force == DRM_FORCE_OFF)
2607 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2610 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2611 drm_connector_update_edid_property(connector, edid);
2614 EXPORT_SYMBOL(drm_get_edid);
2617 * drm_edid_read_custom - Read EDID data using given EDID block read function
2618 * @connector: Connector to use
2619 * @read_block: EDID block read function
2620 * @context: Private data passed to the block read function
2622 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2623 * exposes a different interface to read EDID blocks this function can be used
2624 * to get EDID data using a custom block read function.
2626 * As in the general case the DDC bus is accessible by the kernel at the I2C
2627 * level, drivers must make all reasonable efforts to expose it as an I2C
2628 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2631 * The EDID may be overridden using debugfs override_edid or firmware EDID
2632 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2633 * order. Having either of them bypasses actual EDID reads.
2635 * The returned pointer must be freed using drm_edid_free().
2637 * Return: Pointer to EDID, or NULL if probe/read failed.
2639 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2640 read_block_fn read_block,
2643 const struct drm_edid *drm_edid;
2647 edid = _drm_do_get_edid(connector, read_block, context, &size);
2651 /* Sanity check for now */
2652 drm_WARN_ON(connector->dev, !size);
2654 drm_edid = _drm_edid_alloc(edid, size);
2660 EXPORT_SYMBOL(drm_edid_read_custom);
2663 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2664 * @connector: Connector to use
2665 * @adapter: I2C adapter to use for DDC
2667 * Read EDID using the given I2C adapter.
2669 * The EDID may be overridden using debugfs override_edid or firmware EDID
2670 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2671 * order. Having either of them bypasses actual EDID reads.
2673 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2674 * using drm_edid_read() instead of this function.
2676 * The returned pointer must be freed using drm_edid_free().
2678 * Return: Pointer to EDID, or NULL if probe/read failed.
2680 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2681 struct i2c_adapter *adapter)
2683 const struct drm_edid *drm_edid;
2685 if (connector->force == DRM_FORCE_OFF)
2688 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2691 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2693 /* Note: Do *not* call connector updates here. */
2697 EXPORT_SYMBOL(drm_edid_read_ddc);
2700 * drm_edid_read - Read EDID data using connector's I2C adapter
2701 * @connector: Connector to use
2703 * Read EDID using the connector's I2C adapter.
2705 * The EDID may be overridden using debugfs override_edid or firmware EDID
2706 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2707 * order. Having either of them bypasses actual EDID reads.
2709 * The returned pointer must be freed using drm_edid_free().
2711 * Return: Pointer to EDID, or NULL if probe/read failed.
2713 const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2715 if (drm_WARN_ON(connector->dev, !connector->ddc))
2718 return drm_edid_read_ddc(connector, connector->ddc);
2720 EXPORT_SYMBOL(drm_edid_read);
2723 * drm_edid_get_product_id - Get the vendor and product identification
2725 * @id: Where to place the product id
2727 void drm_edid_get_product_id(const struct drm_edid *drm_edid,
2728 struct drm_edid_product_id *id)
2730 if (drm_edid && drm_edid->edid && drm_edid->size >= EDID_LENGTH)
2731 memcpy(id, &drm_edid->edid->product_id, sizeof(*id));
2733 memset(id, 0, sizeof(*id));
2735 EXPORT_SYMBOL(drm_edid_get_product_id);
2737 static void decode_date(struct seq_buf *s, const struct drm_edid_product_id *id)
2739 int week = id->week_of_manufacture;
2740 int year = id->year_of_manufacture + 1990;
2743 seq_buf_printf(s, "model year: %d", year);
2745 seq_buf_printf(s, "year of manufacture: %d", year);
2747 seq_buf_printf(s, "week/year of manufacture: %d/%d", week, year);
2751 * drm_edid_print_product_id - Print decoded product id to printer
2753 * @id: EDID product id
2754 * @raw: If true, also print the raw hex
2756 * See VESA E-EDID 1.4 section 3.4.
2758 void drm_edid_print_product_id(struct drm_printer *p,
2759 const struct drm_edid_product_id *id, bool raw)
2761 DECLARE_SEQ_BUF(date, 40);
2764 drm_edid_decode_mfg_id(be16_to_cpu(id->manufacturer_name), vend);
2766 decode_date(&date, id);
2768 drm_printf(p, "manufacturer name: %s, product code: %u, serial number: %u, %s\n",
2769 vend, le16_to_cpu(id->product_code),
2770 le32_to_cpu(id->serial_number), seq_buf_str(&date));
2773 drm_printf(p, "raw product id: %*ph\n", (int)sizeof(*id), id);
2775 WARN_ON(seq_buf_has_overflowed(&date));
2777 EXPORT_SYMBOL(drm_edid_print_product_id);
2780 * drm_edid_get_panel_id - Get a panel's ID from EDID
2781 * @drm_edid: EDID that contains panel ID.
2783 * This function uses the first block of the EDID of a panel and (assuming
2784 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2785 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2786 * supposed to be different for each different modem of panel.
2788 * Return: A 32-bit ID that should be different for each make/model of panel.
2789 * See the functions drm_edid_encode_panel_id() and
2790 * drm_edid_decode_panel_id() for some details on the structure of this
2791 * ID. Return 0 if the EDID size is less than a base block.
2793 u32 drm_edid_get_panel_id(const struct drm_edid *drm_edid)
2795 const struct edid *edid = drm_edid->edid;
2797 if (drm_edid->size < EDID_LENGTH)
2801 * We represent the ID as a 32-bit number so it can easily be compared
2804 * NOTE that we deal with endianness differently for the top half
2805 * of this ID than for the bottom half. The bottom half (the product
2806 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2807 * that's how everyone seems to interpret it. The top half (the mfg_id)
2808 * gets stored as big endian because that makes
2809 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2810 * to write (it's easier to extract the ASCII). It doesn't really
2811 * matter, though, as long as the number here is unique.
2813 return (u32)edid->mfg_id[0] << 24 |
2814 (u32)edid->mfg_id[1] << 16 |
2815 (u32)EDID_PRODUCT_ID(edid);
2817 EXPORT_SYMBOL(drm_edid_get_panel_id);
2820 * drm_edid_read_base_block - Get a panel's EDID base block
2821 * @adapter: I2C adapter to use for DDC
2823 * This function returns the drm_edid containing the first block of the EDID of
2826 * This function is intended to be used during early probing on devices where
2827 * more than one panel might be present. Because of its intended use it must
2828 * assume that the EDID of the panel is correct, at least as far as the base
2829 * block is concerned (in other words, we don't process any overrides here).
2831 * Caller should call drm_edid_free() after use.
2833 * NOTE: it's expected that this function and drm_do_get_edid() will both
2834 * be read the EDID, but there is no caching between them. Since we're only
2835 * reading the first block, hopefully this extra overhead won't be too big.
2837 * WARNING: Only use this function when the connector is unknown. For example,
2838 * during the early probe of panel. The EDID read from the function is temporary
2839 * and should be replaced by the full EDID returned from other drm_edid_read.
2841 * Return: Pointer to allocated EDID base block, or NULL on any failure.
2843 const struct drm_edid *drm_edid_read_base_block(struct i2c_adapter *adapter)
2845 enum edid_block_status status;
2848 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2852 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2854 edid_block_status_print(status, base_block, 0);
2856 if (!edid_block_status_valid(status, edid_block_tag(base_block))) {
2857 edid_block_dump(KERN_NOTICE, base_block, 0);
2862 return _drm_edid_alloc(base_block, EDID_LENGTH);
2864 EXPORT_SYMBOL(drm_edid_read_base_block);
2867 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2868 * @connector: connector we're probing
2869 * @adapter: I2C adapter to use for DDC
2871 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2872 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2873 * switch DDC to the GPU which is retrieving EDID.
2875 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2877 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2878 struct i2c_adapter *adapter)
2880 struct drm_device *dev = connector->dev;
2881 struct pci_dev *pdev = to_pci_dev(dev->dev);
2884 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2887 vga_switcheroo_lock_ddc(pdev);
2888 edid = drm_get_edid(connector, adapter);
2889 vga_switcheroo_unlock_ddc(pdev);
2893 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2896 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2897 * @connector: connector we're probing
2898 * @adapter: I2C adapter to use for DDC
2900 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2901 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2902 * temporarily switch DDC to the GPU which is retrieving EDID.
2904 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2906 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2907 struct i2c_adapter *adapter)
2909 struct drm_device *dev = connector->dev;
2910 struct pci_dev *pdev = to_pci_dev(dev->dev);
2911 const struct drm_edid *drm_edid;
2913 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2916 vga_switcheroo_lock_ddc(pdev);
2917 drm_edid = drm_edid_read_ddc(connector, adapter);
2918 vga_switcheroo_unlock_ddc(pdev);
2922 EXPORT_SYMBOL(drm_edid_read_switcheroo);
2925 * drm_edid_duplicate - duplicate an EDID and the extensions
2926 * @edid: EDID to duplicate
2928 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2930 struct edid *drm_edid_duplicate(const struct edid *edid)
2935 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2937 EXPORT_SYMBOL(drm_edid_duplicate);
2939 /*** EDID parsing ***/
2942 * edid_get_quirks - return quirk flags for a given EDID
2943 * @drm_edid: EDID to process
2945 * This tells subsequent routines what fixes they need to apply.
2947 * Return: A u32 represents the quirks to apply.
2949 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2951 const struct edid_quirk *quirk;
2954 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2955 quirk = &edid_quirk_list[i];
2956 if (drm_edid_match(drm_edid, &quirk->ident))
2957 return quirk->quirks;
2963 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2964 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2967 * Walk the mode list for connector, clearing the preferred status on existing
2968 * modes and setting it anew for the right mode ala quirks.
2970 static void edid_fixup_preferred(struct drm_connector *connector)
2972 const struct drm_display_info *info = &connector->display_info;
2973 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2974 int target_refresh = 0;
2975 int cur_vrefresh, preferred_vrefresh;
2977 if (list_empty(&connector->probed_modes))
2980 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
2981 target_refresh = 60;
2982 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
2983 target_refresh = 75;
2985 preferred_mode = list_first_entry(&connector->probed_modes,
2986 struct drm_display_mode, head);
2988 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2989 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2991 if (cur_mode == preferred_mode)
2994 /* Largest mode is preferred */
2995 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2996 preferred_mode = cur_mode;
2998 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2999 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
3000 /* At a given size, try to get closest to target refresh */
3001 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
3002 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
3003 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
3004 preferred_mode = cur_mode;
3008 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
3012 mode_is_rb(const struct drm_display_mode *mode)
3014 return (mode->htotal - mode->hdisplay == 160) &&
3015 (mode->hsync_end - mode->hdisplay == 80) &&
3016 (mode->hsync_end - mode->hsync_start == 32) &&
3017 (mode->vsync_start - mode->vdisplay == 3);
3021 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
3022 * @dev: Device to duplicate against
3023 * @hsize: Mode width
3024 * @vsize: Mode height
3025 * @fresh: Mode refresh rate
3026 * @rb: Mode reduced-blanking-ness
3028 * Walk the DMT mode list looking for a match for the given parameters.
3030 * Return: A newly allocated copy of the mode, or NULL if not found.
3032 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
3033 int hsize, int vsize, int fresh,
3038 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3039 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
3041 if (hsize != ptr->hdisplay)
3043 if (vsize != ptr->vdisplay)
3045 if (fresh != drm_mode_vrefresh(ptr))
3047 if (rb != mode_is_rb(ptr))
3050 return drm_mode_duplicate(dev, ptr);
3055 EXPORT_SYMBOL(drm_mode_find_dmt);
3057 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
3059 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3060 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3061 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3063 return descriptor->pixel_clock == 0 &&
3064 descriptor->data.other_data.pad1 == 0 &&
3065 descriptor->data.other_data.type == type;
3068 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
3070 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3072 return descriptor->pixel_clock != 0;
3075 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
3078 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3082 const u8 *det_base = ext + d;
3084 if (d < 4 || d > 127)
3088 for (i = 0; i < n; i++)
3089 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3093 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3095 unsigned int i, n = min((int)ext[0x02], 6);
3096 const u8 *det_base = ext + 5;
3099 return; /* unknown version */
3101 for (i = 0; i < n; i++)
3102 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3105 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3106 detailed_cb *cb, void *closure)
3108 struct drm_edid_iter edid_iter;
3115 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3116 cb(&drm_edid->edid->detailed_timings[i], closure);
3118 drm_edid_iter_begin(drm_edid, &edid_iter);
3119 drm_edid_iter_for_each(ext, &edid_iter) {
3122 cea_for_each_detailed_block(ext, cb, closure);
3125 vtb_for_each_detailed_block(ext, cb, closure);
3131 drm_edid_iter_end(&edid_iter);
3135 is_rb(const struct detailed_timing *descriptor, void *data)
3139 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3142 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3143 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3145 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3146 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3150 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3152 drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3154 if (drm_edid->edid->revision >= 4) {
3157 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3161 return drm_edid_is_digital(drm_edid);
3165 find_gtf2(const struct detailed_timing *descriptor, void *data)
3167 const struct detailed_timing **res = data;
3169 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3172 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3174 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3178 /* Secondary GTF curve kicks in above some break frequency */
3180 drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3182 const struct detailed_timing *descriptor = NULL;
3184 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3186 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3188 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3192 drm_gtf2_2c(const struct drm_edid *drm_edid)
3194 const struct detailed_timing *descriptor = NULL;
3196 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3198 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3200 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3204 drm_gtf2_m(const struct drm_edid *drm_edid)
3206 const struct detailed_timing *descriptor = NULL;
3208 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3210 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3212 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3216 drm_gtf2_k(const struct drm_edid *drm_edid)
3218 const struct detailed_timing *descriptor = NULL;
3220 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3222 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3224 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3228 drm_gtf2_2j(const struct drm_edid *drm_edid)
3230 const struct detailed_timing *descriptor = NULL;
3232 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3234 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3236 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3240 get_timing_level(const struct detailed_timing *descriptor, void *data)
3244 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3247 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3249 switch (descriptor->data.other_data.data.range.flags) {
3250 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3253 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3256 case DRM_EDID_CVT_SUPPORT_FLAG:
3264 /* Get standard timing level (CVT/GTF/DMT). */
3265 static int standard_timing_level(const struct drm_edid *drm_edid)
3267 const struct edid *edid = drm_edid->edid;
3269 if (edid->revision >= 4) {
3271 * If the range descriptor doesn't
3272 * indicate otherwise default to CVT
3274 int ret = LEVEL_CVT;
3276 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3279 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3281 } else if (edid->revision >= 2) {
3289 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3290 * monitors fill with ascii space (0x20) instead.
3293 bad_std_timing(u8 a, u8 b)
3295 return (a == 0x00 && b == 0x00) ||
3296 (a == 0x01 && b == 0x01) ||
3297 (a == 0x20 && b == 0x20);
3300 static int drm_mode_hsync(const struct drm_display_mode *mode)
3302 if (mode->htotal <= 0)
3305 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3308 static struct drm_display_mode *
3309 drm_gtf2_mode(struct drm_device *dev,
3310 const struct drm_edid *drm_edid,
3311 int hsize, int vsize, int vrefresh_rate)
3313 struct drm_display_mode *mode;
3316 * This is potentially wrong if there's ever a monitor with
3317 * more than one ranges section, each claiming a different
3318 * secondary GTF curve. Please don't do that.
3320 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3324 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3325 drm_mode_destroy(dev, mode);
3326 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3327 vrefresh_rate, 0, 0,
3328 drm_gtf2_m(drm_edid),
3329 drm_gtf2_2c(drm_edid),
3330 drm_gtf2_k(drm_edid),
3331 drm_gtf2_2j(drm_edid));
3338 * Take the standard timing params (in this case width, aspect, and refresh)
3339 * and convert them into a real mode using CVT/GTF/DMT.
3341 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3342 const struct drm_edid *drm_edid,
3343 const struct std_timing *t)
3345 struct drm_device *dev = connector->dev;
3346 struct drm_display_mode *m, *mode = NULL;
3349 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3350 >> EDID_TIMING_ASPECT_SHIFT;
3351 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3352 >> EDID_TIMING_VFREQ_SHIFT;
3353 int timing_level = standard_timing_level(drm_edid);
3355 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3358 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3359 hsize = t->hsize * 8 + 248;
3360 /* vrefresh_rate = vfreq + 60 */
3361 vrefresh_rate = vfreq + 60;
3362 /* the vdisplay is calculated based on the aspect ratio */
3363 if (aspect_ratio == 0) {
3364 if (drm_edid->edid->revision < 3)
3367 vsize = (hsize * 10) / 16;
3368 } else if (aspect_ratio == 1)
3369 vsize = (hsize * 3) / 4;
3370 else if (aspect_ratio == 2)
3371 vsize = (hsize * 4) / 5;
3373 vsize = (hsize * 9) / 16;
3375 /* HDTV hack, part 1 */
3376 if (vrefresh_rate == 60 &&
3377 ((hsize == 1360 && vsize == 765) ||
3378 (hsize == 1368 && vsize == 769))) {
3384 * If this connector already has a mode for this size and refresh
3385 * rate (because it came from detailed or CVT info), use that
3386 * instead. This way we don't have to guess at interlace or
3389 list_for_each_entry(m, &connector->probed_modes, head)
3390 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3391 drm_mode_vrefresh(m) == vrefresh_rate)
3394 /* HDTV hack, part 2 */
3395 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3396 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3400 mode->hdisplay = 1366;
3401 mode->hsync_start = mode->hsync_start - 1;
3402 mode->hsync_end = mode->hsync_end - 1;
3406 /* check whether it can be found in default mode table */
3407 if (drm_monitor_supports_rb(drm_edid)) {
3408 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3413 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3417 /* okay, generate it */
3418 switch (timing_level) {
3422 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3425 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3428 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3436 * EDID is delightfully ambiguous about how interlaced modes are to be
3437 * encoded. Our internal representation is of frame height, but some
3438 * HDTV detailed timings are encoded as field height.
3440 * The format list here is from CEA, in frame size. Technically we
3441 * should be checking refresh rate too. Whatever.
3444 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3445 const struct detailed_pixel_timing *pt)
3448 static const struct {
3450 } cea_interlaced[] = {
3460 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3463 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3464 if ((mode->hdisplay == cea_interlaced[i].w) &&
3465 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3466 mode->vdisplay *= 2;
3467 mode->vsync_start *= 2;
3468 mode->vsync_end *= 2;
3474 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3478 * Create a new mode from an EDID detailed timing section. An EDID detailed
3479 * timing block contains enough info for us to create and return a new struct
3482 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3483 const struct drm_edid *drm_edid,
3484 const struct detailed_timing *timing)
3486 const struct drm_display_info *info = &connector->display_info;
3487 struct drm_device *dev = connector->dev;
3488 struct drm_display_mode *mode;
3489 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3490 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3491 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3492 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3493 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3494 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3495 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3496 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3497 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3499 /* ignore tiny modes */
3500 if (hactive < 64 || vactive < 64)
3503 if (pt->misc & DRM_EDID_PT_STEREO) {
3504 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3505 connector->base.id, connector->name);
3508 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3509 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3510 connector->base.id, connector->name);
3513 /* it is incorrect if hsync/vsync width is zero */
3514 if (!hsync_pulse_width || !vsync_pulse_width) {
3515 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3516 connector->base.id, connector->name);
3520 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3521 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3528 mode = drm_mode_create(dev);
3532 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3533 mode->clock = 1088 * 10;
3535 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3537 mode->hdisplay = hactive;
3538 mode->hsync_start = mode->hdisplay + hsync_offset;
3539 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3540 mode->htotal = mode->hdisplay + hblank;
3542 mode->vdisplay = vactive;
3543 mode->vsync_start = mode->vdisplay + vsync_offset;
3544 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3545 mode->vtotal = mode->vdisplay + vblank;
3547 /* Some EDIDs have bogus h/vsync_end values */
3548 if (mode->hsync_end > mode->htotal) {
3549 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n",
3550 connector->base.id, connector->name,
3551 mode->hsync_end, mode->htotal);
3552 mode->hsync_end = mode->htotal;
3554 if (mode->vsync_end > mode->vtotal) {
3555 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n",
3556 connector->base.id, connector->name,
3557 mode->vsync_end, mode->vtotal);
3558 mode->vsync_end = mode->vtotal;
3561 drm_mode_do_interlace_quirk(mode, pt);
3563 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3564 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3566 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3567 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3568 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3569 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3573 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3574 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3576 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
3577 mode->width_mm *= 10;
3578 mode->height_mm *= 10;
3581 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3582 mode->width_mm = drm_edid->edid->width_cm * 10;
3583 mode->height_mm = drm_edid->edid->height_cm * 10;
3586 mode->type = DRM_MODE_TYPE_DRIVER;
3587 drm_mode_set_name(mode);
3593 mode_in_hsync_range(const struct drm_display_mode *mode,
3594 const struct edid *edid, const u8 *t)
3596 int hsync, hmin, hmax;
3599 if (edid->revision >= 4)
3600 hmin += ((t[4] & 0x04) ? 255 : 0);
3602 if (edid->revision >= 4)
3603 hmax += ((t[4] & 0x08) ? 255 : 0);
3604 hsync = drm_mode_hsync(mode);
3606 return (hsync <= hmax && hsync >= hmin);
3610 mode_in_vsync_range(const struct drm_display_mode *mode,
3611 const struct edid *edid, const u8 *t)
3613 int vsync, vmin, vmax;
3616 if (edid->revision >= 4)
3617 vmin += ((t[4] & 0x01) ? 255 : 0);
3619 if (edid->revision >= 4)
3620 vmax += ((t[4] & 0x02) ? 255 : 0);
3621 vsync = drm_mode_vrefresh(mode);
3623 return (vsync <= vmax && vsync >= vmin);
3627 range_pixel_clock(const struct edid *edid, const u8 *t)
3630 if (t[9] == 0 || t[9] == 255)
3633 /* 1.4 with CVT support gives us real precision, yay */
3634 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3635 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3637 /* 1.3 is pathetic, so fuzz up a bit */
3638 return t[9] * 10000 + 5001;
3641 static bool mode_in_range(const struct drm_display_mode *mode,
3642 const struct drm_edid *drm_edid,
3643 const struct detailed_timing *timing)
3645 const struct edid *edid = drm_edid->edid;
3647 const u8 *t = (const u8 *)timing;
3649 if (!mode_in_hsync_range(mode, edid, t))
3652 if (!mode_in_vsync_range(mode, edid, t))
3655 max_clock = range_pixel_clock(edid, t);
3657 if (mode->clock > max_clock)
3660 /* 1.4 max horizontal check */
3661 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3662 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3665 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3671 static bool valid_inferred_mode(const struct drm_connector *connector,
3672 const struct drm_display_mode *mode)
3674 const struct drm_display_mode *m;
3677 list_for_each_entry(m, &connector->probed_modes, head) {
3678 if (mode->hdisplay == m->hdisplay &&
3679 mode->vdisplay == m->vdisplay &&
3680 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3681 return false; /* duplicated */
3682 if (mode->hdisplay <= m->hdisplay &&
3683 mode->vdisplay <= m->vdisplay)
3689 static int drm_dmt_modes_for_range(struct drm_connector *connector,
3690 const struct drm_edid *drm_edid,
3691 const struct detailed_timing *timing)
3694 struct drm_display_mode *newmode;
3695 struct drm_device *dev = connector->dev;
3697 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3698 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3699 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3700 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3702 drm_mode_probed_add(connector, newmode);
3711 /* fix up 1366x768 mode from 1368x768;
3712 * GFT/CVT can't express 1366 width which isn't dividable by 8
3714 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3716 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3717 mode->hdisplay = 1366;
3718 mode->hsync_start--;
3720 drm_mode_set_name(mode);
3724 static int drm_gtf_modes_for_range(struct drm_connector *connector,
3725 const struct drm_edid *drm_edid,
3726 const struct detailed_timing *timing)
3729 struct drm_display_mode *newmode;
3730 struct drm_device *dev = connector->dev;
3732 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3733 const struct minimode *m = &extra_modes[i];
3735 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3739 drm_mode_fixup_1366x768(newmode);
3740 if (!mode_in_range(newmode, drm_edid, timing) ||
3741 !valid_inferred_mode(connector, newmode)) {
3742 drm_mode_destroy(dev, newmode);
3746 drm_mode_probed_add(connector, newmode);
3753 static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3754 const struct drm_edid *drm_edid,
3755 const struct detailed_timing *timing)
3758 struct drm_display_mode *newmode;
3759 struct drm_device *dev = connector->dev;
3761 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3762 const struct minimode *m = &extra_modes[i];
3764 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3768 drm_mode_fixup_1366x768(newmode);
3769 if (!mode_in_range(newmode, drm_edid, timing) ||
3770 !valid_inferred_mode(connector, newmode)) {
3771 drm_mode_destroy(dev, newmode);
3775 drm_mode_probed_add(connector, newmode);
3782 static int drm_cvt_modes_for_range(struct drm_connector *connector,
3783 const struct drm_edid *drm_edid,
3784 const struct detailed_timing *timing)
3787 struct drm_display_mode *newmode;
3788 struct drm_device *dev = connector->dev;
3789 bool rb = drm_monitor_supports_rb(drm_edid);
3791 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3792 const struct minimode *m = &extra_modes[i];
3794 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3798 drm_mode_fixup_1366x768(newmode);
3799 if (!mode_in_range(newmode, drm_edid, timing) ||
3800 !valid_inferred_mode(connector, newmode)) {
3801 drm_mode_destroy(dev, newmode);
3805 drm_mode_probed_add(connector, newmode);
3813 do_inferred_modes(const struct detailed_timing *timing, void *c)
3815 struct detailed_mode_closure *closure = c;
3816 const struct detailed_non_pixel *data = &timing->data.other_data;
3817 const struct detailed_data_monitor_range *range = &data->data.range;
3819 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3822 closure->modes += drm_dmt_modes_for_range(closure->connector,
3826 if (closure->drm_edid->edid->revision < 2)
3827 return; /* GTF not defined yet */
3829 switch (range->flags) {
3830 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3831 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3835 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3836 closure->modes += drm_gtf_modes_for_range(closure->connector,
3840 case DRM_EDID_CVT_SUPPORT_FLAG:
3841 if (closure->drm_edid->edid->revision < 4)
3844 closure->modes += drm_cvt_modes_for_range(closure->connector,
3848 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3854 static int add_inferred_modes(struct drm_connector *connector,
3855 const struct drm_edid *drm_edid)
3857 struct detailed_mode_closure closure = {
3858 .connector = connector,
3859 .drm_edid = drm_edid,
3862 if (drm_edid->edid->revision >= 1)
3863 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3865 return closure.modes;
3869 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3871 int i, j, m, modes = 0;
3872 struct drm_display_mode *mode;
3873 const u8 *est = ((const u8 *)timing) + 6;
3875 for (i = 0; i < 6; i++) {
3876 for (j = 7; j >= 0; j--) {
3877 m = (i * 8) + (7 - j);
3878 if (m >= ARRAY_SIZE(est3_modes))
3880 if (est[i] & (1 << j)) {
3881 mode = drm_mode_find_dmt(connector->dev,
3887 drm_mode_probed_add(connector, mode);
3898 do_established_modes(const struct detailed_timing *timing, void *c)
3900 struct detailed_mode_closure *closure = c;
3902 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3905 closure->modes += drm_est3_modes(closure->connector, timing);
3909 * Get established modes from EDID and add them. Each EDID block contains a
3910 * bitmap of the supported "established modes" list (defined above). Tease them
3911 * out and add them to the global modes list.
3913 static int add_established_modes(struct drm_connector *connector,
3914 const struct drm_edid *drm_edid)
3916 struct drm_device *dev = connector->dev;
3917 const struct edid *edid = drm_edid->edid;
3918 unsigned long est_bits = edid->established_timings.t1 |
3919 (edid->established_timings.t2 << 8) |
3920 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3922 struct detailed_mode_closure closure = {
3923 .connector = connector,
3924 .drm_edid = drm_edid,
3927 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3928 if (est_bits & (1<<i)) {
3929 struct drm_display_mode *newmode;
3931 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3933 drm_mode_probed_add(connector, newmode);
3939 if (edid->revision >= 1)
3940 drm_for_each_detailed_block(drm_edid, do_established_modes,
3943 return modes + closure.modes;
3947 do_standard_modes(const struct detailed_timing *timing, void *c)
3949 struct detailed_mode_closure *closure = c;
3950 const struct detailed_non_pixel *data = &timing->data.other_data;
3951 struct drm_connector *connector = closure->connector;
3954 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3957 for (i = 0; i < 6; i++) {
3958 const struct std_timing *std = &data->data.timings[i];
3959 struct drm_display_mode *newmode;
3961 newmode = drm_mode_std(connector, closure->drm_edid, std);
3963 drm_mode_probed_add(connector, newmode);
3970 * Get standard modes from EDID and add them. Standard modes can be calculated
3971 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3972 * add them to the list.
3974 static int add_standard_modes(struct drm_connector *connector,
3975 const struct drm_edid *drm_edid)
3978 struct detailed_mode_closure closure = {
3979 .connector = connector,
3980 .drm_edid = drm_edid,
3983 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3984 struct drm_display_mode *newmode;
3986 newmode = drm_mode_std(connector, drm_edid,
3987 &drm_edid->edid->standard_timings[i]);
3989 drm_mode_probed_add(connector, newmode);
3994 if (drm_edid->edid->revision >= 1)
3995 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3998 /* XXX should also look for standard codes in VTB blocks */
4000 return modes + closure.modes;
4003 static int drm_cvt_modes(struct drm_connector *connector,
4004 const struct detailed_timing *timing)
4006 int i, j, modes = 0;
4007 struct drm_display_mode *newmode;
4008 struct drm_device *dev = connector->dev;
4009 const struct cvt_timing *cvt;
4010 static const int rates[] = { 60, 85, 75, 60, 50 };
4011 const u8 empty[3] = { 0, 0, 0 };
4013 for (i = 0; i < 4; i++) {
4016 cvt = &(timing->data.other_data.data.cvt[i]);
4018 if (!memcmp(cvt->code, empty, 3))
4021 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
4022 switch (cvt->code[1] & 0x0c) {
4023 /* default - because compiler doesn't see that we've enumerated all cases */
4026 width = height * 4 / 3;
4029 width = height * 16 / 9;
4032 width = height * 16 / 10;
4035 width = height * 15 / 9;
4039 for (j = 1; j < 5; j++) {
4040 if (cvt->code[2] & (1 << j)) {
4041 newmode = drm_cvt_mode(dev, width, height,
4045 drm_mode_probed_add(connector, newmode);
4056 do_cvt_mode(const struct detailed_timing *timing, void *c)
4058 struct detailed_mode_closure *closure = c;
4060 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
4063 closure->modes += drm_cvt_modes(closure->connector, timing);
4067 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4069 struct detailed_mode_closure closure = {
4070 .connector = connector,
4071 .drm_edid = drm_edid,
4074 if (drm_edid->edid->revision >= 3)
4075 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
4077 /* XXX should also look for CVT codes in VTB blocks */
4079 return closure.modes;
4082 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4083 struct drm_display_mode *mode);
4086 do_detailed_mode(const struct detailed_timing *timing, void *c)
4088 struct detailed_mode_closure *closure = c;
4089 struct drm_display_mode *newmode;
4091 if (!is_detailed_timing_descriptor(timing))
4094 newmode = drm_mode_detailed(closure->connector,
4095 closure->drm_edid, timing);
4099 if (closure->preferred)
4100 newmode->type |= DRM_MODE_TYPE_PREFERRED;
4103 * Detailed modes are limited to 10kHz pixel clock resolution,
4104 * so fix up anything that looks like CEA/HDMI mode, but the clock
4105 * is just slightly off.
4107 fixup_detailed_cea_mode_clock(closure->connector, newmode);
4109 drm_mode_probed_add(closure->connector, newmode);
4111 closure->preferred = false;
4115 * add_detailed_modes - Add modes from detailed timings
4116 * @connector: attached connector
4117 * @drm_edid: EDID block to scan
4119 static int add_detailed_modes(struct drm_connector *connector,
4120 const struct drm_edid *drm_edid)
4122 struct detailed_mode_closure closure = {
4123 .connector = connector,
4124 .drm_edid = drm_edid,
4127 if (drm_edid->edid->revision >= 4)
4128 closure.preferred = true; /* first detailed timing is always preferred */
4131 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4133 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4135 return closure.modes;
4138 /* CTA-861-H Table 60 - CTA Tag Codes */
4139 #define CTA_DB_AUDIO 1
4140 #define CTA_DB_VIDEO 2
4141 #define CTA_DB_VENDOR 3
4142 #define CTA_DB_SPEAKER 4
4143 #define CTA_DB_EXTENDED_TAG 7
4145 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
4146 #define CTA_EXT_DB_VIDEO_CAP 0
4147 #define CTA_EXT_DB_VENDOR 1
4148 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
4149 #define CTA_EXT_DB_420_VIDEO_DATA 14
4150 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
4151 #define CTA_EXT_DB_HF_EEODB 0x78
4152 #define CTA_EXT_DB_HF_SCDB 0x79
4154 #define EDID_BASIC_AUDIO (1 << 6)
4155 #define EDID_CEA_YCRCB444 (1 << 5)
4156 #define EDID_CEA_YCRCB422 (1 << 4)
4157 #define EDID_CEA_VCDB_QS (1 << 6)
4160 * Search EDID for CEA extension block.
4162 * FIXME: Prefer not returning pointers to raw EDID data.
4164 const u8 *drm_edid_find_extension(const struct drm_edid *drm_edid,
4165 int ext_id, int *ext_index)
4167 const u8 *edid_ext = NULL;
4170 /* No EDID or EDID extensions */
4171 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4174 /* Find CEA extension */
4175 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4176 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4177 if (edid_block_tag(edid_ext) == ext_id)
4181 if (i >= drm_edid_extension_block_count(drm_edid))
4189 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
4190 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4192 const struct displayid_block *block;
4193 struct displayid_iter iter;
4194 struct drm_edid_iter edid_iter;
4198 /* Look for a top level CEA extension block */
4199 drm_edid_iter_begin(drm_edid, &edid_iter);
4200 drm_edid_iter_for_each(ext, &edid_iter) {
4201 if (ext[0] == CEA_EXT) {
4206 drm_edid_iter_end(&edid_iter);
4211 /* CEA blocks can also be found embedded in a DisplayID block */
4212 displayid_iter_edid_begin(drm_edid, &iter);
4213 displayid_iter_for_each(block, &iter) {
4214 if (block->tag == DATA_BLOCK_CTA) {
4219 displayid_iter_end(&iter);
4224 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4226 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4227 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4229 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4230 return &edid_cea_modes_1[vic - 1];
4231 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4232 return &edid_cea_modes_193[vic - 193];
4236 static u8 cea_num_vics(void)
4238 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4241 static u8 cea_next_vic(u8 vic)
4243 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4249 * Calculate the alternate clock for the CEA mode
4250 * (60Hz vs. 59.94Hz etc.)
4253 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4255 unsigned int clock = cea_mode->clock;
4257 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4261 * edid_cea_modes contains the 59.94Hz
4262 * variant for 240 and 480 line modes,
4263 * and the 60Hz variant otherwise.
4265 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4266 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4268 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4274 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4277 * For certain VICs the spec allows the vertical
4278 * front porch to vary by one or two lines.
4280 * cea_modes[] stores the variant with the shortest
4281 * vertical front porch. We can adjust the mode to
4282 * get the other variants by simply increasing the
4283 * vertical front porch length.
4285 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4286 cea_mode_for_vic(9)->vtotal != 262 ||
4287 cea_mode_for_vic(12)->vtotal != 262 ||
4288 cea_mode_for_vic(13)->vtotal != 262 ||
4289 cea_mode_for_vic(23)->vtotal != 312 ||
4290 cea_mode_for_vic(24)->vtotal != 312 ||
4291 cea_mode_for_vic(27)->vtotal != 312 ||
4292 cea_mode_for_vic(28)->vtotal != 312);
4294 if (((vic == 8 || vic == 9 ||
4295 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4296 ((vic == 23 || vic == 24 ||
4297 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4298 mode->vsync_start++;
4308 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4309 unsigned int clock_tolerance)
4311 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4314 if (!to_match->clock)
4317 if (to_match->picture_aspect_ratio)
4318 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4320 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4321 struct drm_display_mode cea_mode;
4322 unsigned int clock1, clock2;
4324 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4326 /* Check both 60Hz and 59.94Hz */
4327 clock1 = cea_mode.clock;
4328 clock2 = cea_mode_alternate_clock(&cea_mode);
4330 if (abs(to_match->clock - clock1) > clock_tolerance &&
4331 abs(to_match->clock - clock2) > clock_tolerance)
4335 if (drm_mode_match(to_match, &cea_mode, match_flags))
4337 } while (cea_mode_alternate_timings(vic, &cea_mode));
4344 * drm_match_cea_mode - look for a CEA mode matching given mode
4345 * @to_match: display mode
4347 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4350 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4352 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4355 if (!to_match->clock)
4358 if (to_match->picture_aspect_ratio)
4359 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4361 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4362 struct drm_display_mode cea_mode;
4363 unsigned int clock1, clock2;
4365 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4367 /* Check both 60Hz and 59.94Hz */
4368 clock1 = cea_mode.clock;
4369 clock2 = cea_mode_alternate_clock(&cea_mode);
4371 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4372 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4376 if (drm_mode_match(to_match, &cea_mode, match_flags))
4378 } while (cea_mode_alternate_timings(vic, &cea_mode));
4383 EXPORT_SYMBOL(drm_match_cea_mode);
4385 static bool drm_valid_cea_vic(u8 vic)
4387 return cea_mode_for_vic(vic) != NULL;
4390 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4392 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4395 return mode->picture_aspect_ratio;
4397 return HDMI_PICTURE_ASPECT_NONE;
4400 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4402 return edid_4k_modes[video_code].picture_aspect_ratio;
4406 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4410 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4412 return cea_mode_alternate_clock(hdmi_mode);
4415 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4416 unsigned int clock_tolerance)
4418 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4421 if (!to_match->clock)
4424 if (to_match->picture_aspect_ratio)
4425 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4427 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4428 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4429 unsigned int clock1, clock2;
4431 /* Make sure to also match alternate clocks */
4432 clock1 = hdmi_mode->clock;
4433 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4435 if (abs(to_match->clock - clock1) > clock_tolerance &&
4436 abs(to_match->clock - clock2) > clock_tolerance)
4439 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4447 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4448 * @to_match: display mode
4450 * An HDMI mode is one defined in the HDMI vendor specific block.
4452 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4454 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4456 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4459 if (!to_match->clock)
4462 if (to_match->picture_aspect_ratio)
4463 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4465 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4466 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4467 unsigned int clock1, clock2;
4469 /* Make sure to also match alternate clocks */
4470 clock1 = hdmi_mode->clock;
4471 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4473 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4474 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4475 drm_mode_match(to_match, hdmi_mode, match_flags))
4481 static bool drm_valid_hdmi_vic(u8 vic)
4483 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4486 static int add_alternate_cea_modes(struct drm_connector *connector,
4487 const struct drm_edid *drm_edid)
4489 struct drm_device *dev = connector->dev;
4490 struct drm_display_mode *mode, *tmp;
4494 /* Don't add CTA modes if the CTA extension block is missing */
4495 if (!drm_edid_has_cta_extension(drm_edid))
4499 * Go through all probed modes and create a new mode
4500 * with the alternate clock for certain CEA modes.
4502 list_for_each_entry(mode, &connector->probed_modes, head) {
4503 const struct drm_display_mode *cea_mode = NULL;
4504 struct drm_display_mode *newmode;
4505 u8 vic = drm_match_cea_mode(mode);
4506 unsigned int clock1, clock2;
4508 if (drm_valid_cea_vic(vic)) {
4509 cea_mode = cea_mode_for_vic(vic);
4510 clock2 = cea_mode_alternate_clock(cea_mode);
4512 vic = drm_match_hdmi_mode(mode);
4513 if (drm_valid_hdmi_vic(vic)) {
4514 cea_mode = &edid_4k_modes[vic];
4515 clock2 = hdmi_mode_alternate_clock(cea_mode);
4522 clock1 = cea_mode->clock;
4524 if (clock1 == clock2)
4527 if (mode->clock != clock1 && mode->clock != clock2)
4530 newmode = drm_mode_duplicate(dev, cea_mode);
4534 /* Carry over the stereo flags */
4535 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4538 * The current mode could be either variant. Make
4539 * sure to pick the "other" clock for the new mode.
4541 if (mode->clock != clock1)
4542 newmode->clock = clock1;
4544 newmode->clock = clock2;
4546 list_add_tail(&newmode->head, &list);
4549 list_for_each_entry_safe(mode, tmp, &list, head) {
4550 list_del(&mode->head);
4551 drm_mode_probed_add(connector, mode);
4558 static u8 svd_to_vic(u8 svd)
4560 /* 0-6 bit vic, 7th bit native mode indicator */
4561 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4568 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4569 * the EDID, or NULL on errors.
4571 static struct drm_display_mode *
4572 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
4574 const struct drm_display_info *info = &connector->display_info;
4575 struct drm_device *dev = connector->dev;
4577 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
4580 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
4584 * do_y420vdb_modes - Parse YCBCR 420 only modes
4585 * @connector: connector corresponding to the HDMI sink
4586 * @svds: start of the data block of CEA YCBCR 420 VDB
4587 * @len: length of the CEA YCBCR 420 VDB
4589 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4590 * which contains modes which can be supported in YCBCR 420
4591 * output format only.
4593 static int do_y420vdb_modes(struct drm_connector *connector,
4594 const u8 *svds, u8 svds_len)
4596 struct drm_device *dev = connector->dev;
4599 for (i = 0; i < svds_len; i++) {
4600 u8 vic = svd_to_vic(svds[i]);
4601 struct drm_display_mode *newmode;
4603 if (!drm_valid_cea_vic(vic))
4606 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4609 drm_mode_probed_add(connector, newmode);
4617 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4619 * @video_code: CEA VIC of the mode
4621 * Creates a new mode matching the specified CEA VIC.
4623 * Returns: A new drm_display_mode on success or NULL on failure
4625 struct drm_display_mode *
4626 drm_display_mode_from_cea_vic(struct drm_device *dev,
4629 const struct drm_display_mode *cea_mode;
4630 struct drm_display_mode *newmode;
4632 cea_mode = cea_mode_for_vic(video_code);
4636 newmode = drm_mode_duplicate(dev, cea_mode);
4642 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4644 /* Add modes based on VICs parsed in parse_cta_vdb() */
4645 static int add_cta_vdb_modes(struct drm_connector *connector)
4647 const struct drm_display_info *info = &connector->display_info;
4653 for (i = 0; i < info->vics_len; i++) {
4654 struct drm_display_mode *mode;
4656 mode = drm_display_mode_from_vic_index(connector, i);
4658 drm_mode_probed_add(connector, mode);
4666 struct stereo_mandatory_mode {
4667 int width, height, vrefresh;
4671 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4672 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4673 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4675 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4677 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4678 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4679 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4680 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4681 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4685 stereo_match_mandatory(const struct drm_display_mode *mode,
4686 const struct stereo_mandatory_mode *stereo_mode)
4688 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4690 return mode->hdisplay == stereo_mode->width &&
4691 mode->vdisplay == stereo_mode->height &&
4692 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4693 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4696 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4698 struct drm_device *dev = connector->dev;
4699 const struct drm_display_mode *mode;
4700 struct list_head stereo_modes;
4703 INIT_LIST_HEAD(&stereo_modes);
4705 list_for_each_entry(mode, &connector->probed_modes, head) {
4706 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4707 const struct stereo_mandatory_mode *mandatory;
4708 struct drm_display_mode *new_mode;
4710 if (!stereo_match_mandatory(mode,
4711 &stereo_mandatory_modes[i]))
4714 mandatory = &stereo_mandatory_modes[i];
4715 new_mode = drm_mode_duplicate(dev, mode);
4719 new_mode->flags |= mandatory->flags;
4720 list_add_tail(&new_mode->head, &stereo_modes);
4725 list_splice_tail(&stereo_modes, &connector->probed_modes);
4730 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4732 struct drm_device *dev = connector->dev;
4733 struct drm_display_mode *newmode;
4735 if (!drm_valid_hdmi_vic(vic)) {
4736 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4737 connector->base.id, connector->name, vic);
4741 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4745 drm_mode_probed_add(connector, newmode);
4750 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4753 struct drm_display_mode *newmode;
4756 if (structure & (1 << 0)) {
4757 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4759 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4760 drm_mode_probed_add(connector, newmode);
4764 if (structure & (1 << 6)) {
4765 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4767 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4768 drm_mode_probed_add(connector, newmode);
4772 if (structure & (1 << 8)) {
4773 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4775 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4776 drm_mode_probed_add(connector, newmode);
4784 static bool hdmi_vsdb_latency_present(const u8 *db)
4786 return db[8] & BIT(7);
4789 static bool hdmi_vsdb_i_latency_present(const u8 *db)
4791 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4794 static int hdmi_vsdb_latency_length(const u8 *db)
4796 if (hdmi_vsdb_i_latency_present(db))
4798 else if (hdmi_vsdb_latency_present(db))
4805 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4806 * @connector: connector corresponding to the HDMI sink
4807 * @db: start of the CEA vendor specific block
4808 * @len: length of the CEA block payload, ie. one can access up to db[len]
4810 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4811 * also adds the stereo 3d modes when applicable.
4814 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
4816 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4817 u8 vic_len, hdmi_3d_len = 0;
4824 /* no HDMI_Video_Present */
4825 if (!(db[8] & (1 << 5)))
4828 offset += hdmi_vsdb_latency_length(db);
4830 /* the declared length is not long enough for the 2 first bytes
4831 * of additional video format capabilities */
4832 if (len < (8 + offset + 2))
4837 if (db[8 + offset] & (1 << 7)) {
4838 modes += add_hdmi_mandatory_stereo_modes(connector);
4840 /* 3D_Multi_present */
4841 multi_present = (db[8 + offset] & 0x60) >> 5;
4845 vic_len = db[8 + offset] >> 5;
4846 hdmi_3d_len = db[8 + offset] & 0x1f;
4848 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4851 vic = db[9 + offset + i];
4852 modes += add_hdmi_mode(connector, vic);
4854 offset += 1 + vic_len;
4856 if (multi_present == 1)
4858 else if (multi_present == 2)
4863 if (len < (8 + offset + hdmi_3d_len - 1))
4866 if (hdmi_3d_len < multi_len)
4869 if (multi_present == 1 || multi_present == 2) {
4870 /* 3D_Structure_ALL */
4871 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4873 /* check if 3D_MASK is present */
4874 if (multi_present == 2)
4875 mask = (db[10 + offset] << 8) | db[11 + offset];
4879 for (i = 0; i < 16; i++) {
4880 if (mask & (1 << i))
4881 modes += add_3d_struct_modes(connector,
4886 offset += multi_len;
4888 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4890 struct drm_display_mode *newmode = NULL;
4891 unsigned int newflag = 0;
4892 bool detail_present;
4894 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4896 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4899 /* 2D_VIC_order_X */
4900 vic_index = db[8 + offset + i] >> 4;
4902 /* 3D_Structure_X */
4903 switch (db[8 + offset + i] & 0x0f) {
4905 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4908 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4912 if ((db[9 + offset + i] >> 4) == 1)
4913 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4918 newmode = drm_display_mode_from_vic_index(connector,
4922 newmode->flags |= newflag;
4923 drm_mode_probed_add(connector, newmode);
4937 cea_revision(const u8 *cea)
4940 * FIXME is this correct for the DispID variant?
4941 * The DispID spec doesn't really specify whether
4942 * this is the revision of the CEA extension or
4943 * the DispID CEA data block. And the only value
4944 * given as an example is 0.
4950 * CTA Data Block iterator.
4952 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4955 * struct cea_db *db:
4956 * struct cea_db_iter iter;
4958 * cea_db_iter_edid_begin(edid, &iter);
4959 * cea_db_iter_for_each(db, &iter) {
4960 * // do stuff with db
4962 * cea_db_iter_end(&iter);
4964 struct cea_db_iter {
4965 struct drm_edid_iter edid_iter;
4966 struct displayid_iter displayid_iter;
4968 /* Current Data Block Collection. */
4969 const u8 *collection;
4971 /* Current Data Block index in current collection. */
4974 /* End index in current collection. */
4978 /* CTA-861-H section 7.4 CTA Data BLock Collection */
4984 static int cea_db_tag(const struct cea_db *db)
4986 return db->tag_length >> 5;
4989 static int cea_db_payload_len(const void *_db)
4991 /* FIXME: Transition to passing struct cea_db * everywhere. */
4992 const struct cea_db *db = _db;
4994 return db->tag_length & 0x1f;
4997 static const void *cea_db_data(const struct cea_db *db)
5002 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
5004 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
5005 cea_db_payload_len(db) >= 1 &&
5009 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
5011 const u8 *data = cea_db_data(db);
5013 return cea_db_tag(db) == CTA_DB_VENDOR &&
5014 cea_db_payload_len(db) >= 3 &&
5015 oui(data[2], data[1], data[0]) == vendor_oui;
5018 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
5019 struct cea_db_iter *iter)
5021 memset(iter, 0, sizeof(*iter));
5023 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
5024 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
5027 static const struct cea_db *
5028 __cea_db_iter_current_block(const struct cea_db_iter *iter)
5030 const struct cea_db *db;
5032 if (!iter->collection)
5035 db = (const struct cea_db *)&iter->collection[iter->index];
5037 if (iter->index + sizeof(*db) <= iter->end &&
5038 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
5046 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5048 static int cea_db_collection_size(const u8 *cta)
5052 if (d < 4 || d > 127)
5060 * - VESA E-EDID v1.4
5061 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5063 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5067 drm_edid_iter_for_each(ext, &iter->edid_iter) {
5070 /* Only support CTA Extension revision 3+ */
5071 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5074 size = cea_db_collection_size(ext);
5079 iter->end = iter->index + size;
5089 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5090 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5092 * Note that the above do not specify any connection between DisplayID Data
5093 * Block revision and CTA Extension versions.
5095 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5097 const struct displayid_block *block;
5099 displayid_iter_for_each(block, &iter->displayid_iter) {
5100 if (block->tag != DATA_BLOCK_CTA)
5104 * The displayid iterator has already verified the block bounds
5105 * in displayid_iter_block().
5107 iter->index = sizeof(*block);
5108 iter->end = iter->index + block->num_bytes;
5116 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5118 const struct cea_db *db;
5120 if (iter->collection) {
5121 /* Current collection should always be valid. */
5122 db = __cea_db_iter_current_block(iter);
5124 iter->collection = NULL;
5128 /* Next block in CTA Data Block Collection */
5129 iter->index += sizeof(*db) + cea_db_payload_len(db);
5131 db = __cea_db_iter_current_block(iter);
5138 * Find the next CTA Data Block Collection. First iterate all
5139 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5141 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5142 * Extension, it's recommended that DisplayID extensions are
5143 * exposed after all of the CTA Extensions.
5145 iter->collection = __cea_db_iter_edid_next(iter);
5146 if (!iter->collection)
5147 iter->collection = __cea_db_iter_displayid_next(iter);
5149 if (!iter->collection)
5152 db = __cea_db_iter_current_block(iter);
5158 #define cea_db_iter_for_each(__db, __iter) \
5159 while (((__db) = __cea_db_iter_next(__iter)))
5161 static void cea_db_iter_end(struct cea_db_iter *iter)
5163 displayid_iter_end(&iter->displayid_iter);
5164 drm_edid_iter_end(&iter->edid_iter);
5166 memset(iter, 0, sizeof(*iter));
5169 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5171 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5172 cea_db_payload_len(db) >= 5;
5175 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5177 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5178 cea_db_payload_len(db) >= 7;
5181 static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5183 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5184 cea_db_payload_len(db) >= 2;
5187 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5189 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5190 cea_db_payload_len(db) == 21;
5193 static bool cea_db_is_vcdb(const struct cea_db *db)
5195 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5196 cea_db_payload_len(db) == 2;
5199 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5201 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5202 cea_db_payload_len(db) >= 7;
5205 static bool cea_db_is_y420cmdb(const struct cea_db *db)
5207 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5210 static bool cea_db_is_y420vdb(const struct cea_db *db)
5212 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5215 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5217 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5218 cea_db_payload_len(db) >= 3;
5222 * Get the HF-EEODB override extension block count from EDID.
5224 * The passed in EDID may be partially read, as long as it has at least two
5225 * blocks (base block and one extension block) if EDID extension count is > 0.
5227 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5228 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5229 * iterators instead.
5232 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5234 static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5238 /* No extensions according to base block, no HF-EEODB. */
5239 if (!edid_extension_block_count(edid))
5242 /* HF-EEODB is always in the first EDID extension block only */
5243 cta = edid_extension_block_data(edid, 0);
5244 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5247 /* Need to have the data block collection, and at least 3 bytes. */
5248 if (cea_db_collection_size(cta) < 3)
5252 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5253 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5254 * through 6 of Block 1 of the E-EDID.
5256 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5263 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5265 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5266 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5267 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5268 * support YCBCR420 output too.
5270 static void parse_cta_y420cmdb(struct drm_connector *connector,
5271 const struct cea_db *db, u64 *y420cmdb_map)
5273 struct drm_display_info *info = &connector->display_info;
5274 int i, map_len = cea_db_payload_len(db) - 1;
5275 const u8 *data = cea_db_data(db) + 1;
5279 /* All CEA modes support ycbcr420 sampling also.*/
5285 * This map indicates which of the existing CEA block modes
5286 * from VDB can support YCBCR420 output too. So if bit=0 is
5287 * set, first mode from VDB can support YCBCR420 output too.
5288 * We will parse and keep this map, before parsing VDB itself
5289 * to avoid going through the same block again and again.
5291 * Spec is not clear about max possible size of this block.
5292 * Clamping max bitmap block size at 8 bytes. Every byte can
5293 * address 8 CEA modes, in this way this map can address
5294 * 8*8 = first 64 SVDs.
5296 if (WARN_ON_ONCE(map_len > 8))
5299 for (i = 0; i < map_len; i++)
5300 map |= (u64)data[i] << (8 * i);
5304 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5306 *y420cmdb_map = map;
5309 static int add_cea_modes(struct drm_connector *connector,
5310 const struct drm_edid *drm_edid)
5312 const struct cea_db *db;
5313 struct cea_db_iter iter;
5316 /* CTA VDB block VICs parsed earlier */
5317 modes = add_cta_vdb_modes(connector);
5319 cea_db_iter_edid_begin(drm_edid, &iter);
5320 cea_db_iter_for_each(db, &iter) {
5321 if (cea_db_is_hdmi_vsdb(db)) {
5322 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5323 cea_db_payload_len(db));
5324 } else if (cea_db_is_y420vdb(db)) {
5325 const u8 *vdb420 = cea_db_data(db) + 1;
5327 /* Add 4:2:0(only) modes present in EDID */
5328 modes += do_y420vdb_modes(connector, vdb420,
5329 cea_db_payload_len(db) - 1);
5332 cea_db_iter_end(&iter);
5337 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5338 struct drm_display_mode *mode)
5340 const struct drm_display_mode *cea_mode;
5341 int clock1, clock2, clock;
5346 * allow 5kHz clock difference either way to account for
5347 * the 10kHz clock resolution limit of detailed timings.
5349 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5350 if (drm_valid_cea_vic(vic)) {
5352 cea_mode = cea_mode_for_vic(vic);
5353 clock1 = cea_mode->clock;
5354 clock2 = cea_mode_alternate_clock(cea_mode);
5356 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5357 if (drm_valid_hdmi_vic(vic)) {
5359 cea_mode = &edid_4k_modes[vic];
5360 clock1 = cea_mode->clock;
5361 clock2 = hdmi_mode_alternate_clock(cea_mode);
5367 /* pick whichever is closest */
5368 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5373 if (mode->clock == clock)
5376 drm_dbg_kms(connector->dev,
5377 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5378 connector->base.id, connector->name,
5379 type, vic, mode->clock, clock);
5380 mode->clock = clock;
5383 static void drm_calculate_luminance_range(struct drm_connector *connector)
5385 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5386 struct drm_luminance_range_info *luminance_range =
5387 &connector->display_info.luminance_range;
5388 static const u8 pre_computed_values[] = {
5389 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5390 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5392 u32 max_avg, min_cll, max, min, q, r;
5394 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5397 max_avg = hdr_metadata->max_fall;
5398 min_cll = hdr_metadata->min_cll;
5401 * From the specification (CTA-861-G), for calculating the maximum
5402 * luminance we need to use:
5403 * Luminance = 50*2**(CV/32)
5404 * Where CV is a one-byte value.
5405 * For calculating this expression we may need float point precision;
5406 * to avoid this complexity level, we take advantage that CV is divided
5407 * by a constant. From the Euclids division algorithm, we know that CV
5408 * can be written as: CV = 32*q + r. Next, we replace CV in the
5409 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5410 * need to pre-compute the value of r/32. For pre-computing the values
5411 * We just used the following Ruby line:
5412 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5413 * The results of the above expressions can be verified at
5414 * pre_computed_values.
5418 max = (1 << q) * pre_computed_values[r];
5420 /* min luminance: maxLum * (CV/255)^2 / 100 */
5421 q = DIV_ROUND_CLOSEST(min_cll, 255);
5422 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5424 luminance_range->min_luminance = min;
5425 luminance_range->max_luminance = max;
5428 static uint8_t eotf_supported(const u8 *edid_ext)
5430 return edid_ext[2] &
5431 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5432 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5433 BIT(HDMI_EOTF_SMPTE_ST2084) |
5434 BIT(HDMI_EOTF_BT_2100_HLG));
5437 static uint8_t hdr_metadata_type(const u8 *edid_ext)
5439 return edid_ext[3] &
5440 BIT(HDMI_STATIC_METADATA_TYPE1);
5444 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5448 len = cea_db_payload_len(db);
5450 connector->hdr_sink_metadata.hdmi_type1.eotf =
5452 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5453 hdr_metadata_type(db);
5456 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5458 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5460 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5462 /* Calculate only when all values are available */
5463 drm_calculate_luminance_range(connector);
5467 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
5469 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5471 u8 len = cea_db_payload_len(db);
5473 if (len >= 6 && (db[6] & (1 << 7)))
5474 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5476 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5477 connector->latency_present[0] = true;
5478 connector->video_latency[0] = db[9];
5479 connector->audio_latency[0] = db[10];
5482 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5483 connector->latency_present[1] = true;
5484 connector->video_latency[1] = db[11];
5485 connector->audio_latency[1] = db[12];
5488 drm_dbg_kms(connector->dev,
5489 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5490 connector->base.id, connector->name,
5491 connector->latency_present[0], connector->latency_present[1],
5492 connector->video_latency[0], connector->video_latency[1],
5493 connector->audio_latency[0], connector->audio_latency[1]);
5497 match_identity(const struct detailed_timing *timing, void *data)
5499 struct drm_edid_match_closure *closure = data;
5501 const char *name = closure->ident->name;
5502 unsigned int name_len = strlen(name);
5503 const char *desc = timing->data.other_data.data.str.str;
5504 unsigned int desc_len = ARRAY_SIZE(timing->data.other_data.data.str.str);
5506 if (name_len > desc_len ||
5507 !(is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME) ||
5508 is_display_descriptor(timing, EDID_DETAIL_MONITOR_STRING)))
5511 if (strncmp(name, desc, name_len))
5514 for (i = name_len; i < desc_len; i++) {
5515 if (desc[i] == '\n')
5517 /* Allow white space before EDID string terminator. */
5518 if (!isspace(desc[i]))
5522 closure->matched = true;
5526 * drm_edid_match - match drm_edid with given identity
5528 * @ident: the EDID identity to match with
5530 * Check if the EDID matches with the given identity.
5532 * Return: True if the given identity matched with EDID, false otherwise.
5534 bool drm_edid_match(const struct drm_edid *drm_edid,
5535 const struct drm_edid_ident *ident)
5537 if (!drm_edid || drm_edid_get_panel_id(drm_edid) != ident->panel_id)
5540 /* Match with name only if it's not NULL. */
5542 struct drm_edid_match_closure closure = {
5547 drm_for_each_detailed_block(drm_edid, match_identity, &closure);
5549 return closure.matched;
5554 EXPORT_SYMBOL(drm_edid_match);
5557 monitor_name(const struct detailed_timing *timing, void *data)
5559 const char **res = data;
5561 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5564 *res = timing->data.other_data.data.str.str;
5567 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5569 const char *edid_name = NULL;
5572 if (!drm_edid || !name)
5575 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5576 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5577 if (edid_name[mnl] == 0x0a)
5580 name[mnl] = edid_name[mnl];
5587 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5588 * @edid: monitor EDID information
5589 * @name: pointer to a character array to hold the name of the monitor
5590 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5593 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5595 int name_length = 0;
5602 struct drm_edid drm_edid = {
5604 .size = edid_size(edid),
5607 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5608 memcpy(name, buf, name_length);
5611 name[name_length] = '\0';
5613 EXPORT_SYMBOL(drm_edid_get_monitor_name);
5615 static void clear_eld(struct drm_connector *connector)
5617 memset(connector->eld, 0, sizeof(connector->eld));
5619 connector->latency_present[0] = false;
5620 connector->latency_present[1] = false;
5621 connector->video_latency[0] = 0;
5622 connector->audio_latency[0] = 0;
5623 connector->video_latency[1] = 0;
5624 connector->audio_latency[1] = 0;
5628 * Get 3-byte SAD buffer from struct cea_sad.
5630 void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad)
5632 sad[0] = cta_sad->format << 3 | cta_sad->channels;
5633 sad[1] = cta_sad->freq;
5634 sad[2] = cta_sad->byte2;
5638 * Set struct cea_sad from 3-byte SAD buffer.
5640 void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad)
5642 cta_sad->format = (sad[0] & 0x78) >> 3;
5643 cta_sad->channels = sad[0] & 0x07;
5644 cta_sad->freq = sad[1] & 0x7f;
5645 cta_sad->byte2 = sad[2];
5649 * drm_edid_to_eld - build ELD from EDID
5650 * @connector: connector corresponding to the HDMI/DP sink
5651 * @drm_edid: EDID to parse
5653 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5654 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5656 static void drm_edid_to_eld(struct drm_connector *connector,
5657 const struct drm_edid *drm_edid)
5659 const struct drm_display_info *info = &connector->display_info;
5660 const struct cea_db *db;
5661 struct cea_db_iter iter;
5662 uint8_t *eld = connector->eld;
5663 int total_sad_count = 0;
5669 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5670 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5671 connector->base.id, connector->name,
5672 &eld[DRM_ELD_MONITOR_NAME_STRING]);
5674 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5675 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5677 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5679 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5680 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5681 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5682 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5684 cea_db_iter_edid_begin(drm_edid, &iter);
5685 cea_db_iter_for_each(db, &iter) {
5686 const u8 *data = cea_db_data(db);
5687 int len = cea_db_payload_len(db);
5690 switch (cea_db_tag(db)) {
5692 /* Audio Data Block, contains SADs */
5693 sad_count = min(len / 3, 15 - total_sad_count);
5695 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5696 data, sad_count * 3);
5697 total_sad_count += sad_count;
5699 case CTA_DB_SPEAKER:
5700 /* Speaker Allocation Data Block */
5702 eld[DRM_ELD_SPEAKER] = data[0];
5705 /* HDMI Vendor-Specific Data Block */
5706 if (cea_db_is_hdmi_vsdb(db))
5707 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5713 cea_db_iter_end(&iter);
5715 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5717 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5718 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5719 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5721 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5723 eld[DRM_ELD_BASELINE_ELD_LEN] =
5724 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5726 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5727 connector->base.id, connector->name,
5728 drm_eld_size(eld), total_sad_count);
5731 static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5732 struct cea_sad **psads)
5734 const struct cea_db *db;
5735 struct cea_db_iter iter;
5738 cea_db_iter_edid_begin(drm_edid, &iter);
5739 cea_db_iter_for_each(db, &iter) {
5740 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5741 struct cea_sad *sads;
5744 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5745 sads = kcalloc(count, sizeof(*sads), GFP_KERNEL);
5749 for (i = 0; i < count; i++)
5750 drm_edid_cta_sad_set(&sads[i], &db->data[i * 3]);
5754 cea_db_iter_end(&iter);
5756 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5762 * drm_edid_to_sad - extracts SADs from EDID
5763 * @edid: EDID to parse
5764 * @sads: pointer that will be set to the extracted SADs
5766 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5768 * Note: The returned pointer needs to be freed using kfree().
5770 * Return: The number of found SADs or negative number on error.
5772 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5774 struct drm_edid drm_edid;
5776 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5778 EXPORT_SYMBOL(drm_edid_to_sad);
5780 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5783 const struct cea_db *db;
5784 struct cea_db_iter iter;
5787 cea_db_iter_edid_begin(drm_edid, &iter);
5788 cea_db_iter_for_each(db, &iter) {
5789 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5790 cea_db_payload_len(db) == 3) {
5791 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5795 count = cea_db_payload_len(db);
5799 cea_db_iter_end(&iter);
5801 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5807 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5808 * @edid: EDID to parse
5809 * @sadb: pointer to the speaker block
5811 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5813 * Note: The returned pointer needs to be freed using kfree().
5815 * Return: The number of found Speaker Allocation Blocks or negative number on
5818 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5820 struct drm_edid drm_edid;
5822 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5825 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5828 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5829 * @connector: connector associated with the HDMI/DP sink
5830 * @mode: the display mode
5832 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5833 * the sink doesn't support audio or video.
5835 int drm_av_sync_delay(struct drm_connector *connector,
5836 const struct drm_display_mode *mode)
5838 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5841 if (!connector->latency_present[0])
5843 if (!connector->latency_present[1])
5846 a = connector->audio_latency[i];
5847 v = connector->video_latency[i];
5850 * HDMI/DP sink doesn't support audio or video?
5852 if (a == 255 || v == 255)
5856 * Convert raw EDID values to millisecond.
5857 * Treat unknown latency as 0ms.
5860 a = min(2 * (a - 1), 500);
5862 v = min(2 * (v - 1), 500);
5864 return max(v - a, 0);
5866 EXPORT_SYMBOL(drm_av_sync_delay);
5868 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5870 const struct cea_db *db;
5871 struct cea_db_iter iter;
5875 * Because HDMI identifier is in Vendor Specific Block,
5876 * search it from all data blocks of CEA extension.
5878 cea_db_iter_edid_begin(drm_edid, &iter);
5879 cea_db_iter_for_each(db, &iter) {
5880 if (cea_db_is_hdmi_vsdb(db)) {
5885 cea_db_iter_end(&iter);
5891 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5892 * @edid: monitor EDID information
5894 * Parse the CEA extension according to CEA-861-B.
5896 * Drivers that have added the modes parsed from EDID to drm_display_info
5897 * should use &drm_display_info.is_hdmi instead of calling this function.
5899 * Return: True if the monitor is HDMI, false if not or unknown.
5901 bool drm_detect_hdmi_monitor(const struct edid *edid)
5903 struct drm_edid drm_edid;
5905 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5907 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5909 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5911 struct drm_edid_iter edid_iter;
5912 const struct cea_db *db;
5913 struct cea_db_iter iter;
5915 bool has_audio = false;
5917 drm_edid_iter_begin(drm_edid, &edid_iter);
5918 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5919 if (edid_ext[0] == CEA_EXT) {
5920 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5925 drm_edid_iter_end(&edid_iter);
5928 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5932 cea_db_iter_edid_begin(drm_edid, &iter);
5933 cea_db_iter_for_each(db, &iter) {
5934 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5935 const u8 *data = cea_db_data(db);
5938 for (i = 0; i < cea_db_payload_len(db); i += 3)
5939 DRM_DEBUG_KMS("CEA audio format %d\n",
5940 (data[i] >> 3) & 0xf);
5945 cea_db_iter_end(&iter);
5952 * drm_detect_monitor_audio - check monitor audio capability
5953 * @edid: EDID block to scan
5955 * Monitor should have CEA extension block.
5956 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5957 * audio' only. If there is any audio extension block and supported
5958 * audio format, assume at least 'basic audio' support, even if 'basic
5959 * audio' is not defined in EDID.
5961 * Return: True if the monitor supports audio, false otherwise.
5963 bool drm_detect_monitor_audio(const struct edid *edid)
5965 struct drm_edid drm_edid;
5967 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5969 EXPORT_SYMBOL(drm_detect_monitor_audio);
5973 * drm_default_rgb_quant_range - default RGB quantization range
5974 * @mode: display mode
5976 * Determine the default RGB quantization range for the mode,
5977 * as specified in CEA-861.
5979 * Return: The default RGB quantization range for the mode
5981 enum hdmi_quantization_range
5982 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5984 /* All CEA modes other than VIC 1 use limited quantization range. */
5985 return drm_match_cea_mode(mode) > 1 ?
5986 HDMI_QUANTIZATION_RANGE_LIMITED :
5987 HDMI_QUANTIZATION_RANGE_FULL;
5989 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5991 /* CTA-861 Video Data Block (CTA VDB) */
5992 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5994 struct drm_display_info *info = &connector->display_info;
5995 int i, vic_index, len = cea_db_payload_len(db);
5996 const u8 *svds = cea_db_data(db);
6002 /* Gracefully handle multiple VDBs, however unlikely that is */
6003 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
6007 vic_index = info->vics_len;
6008 info->vics_len += len;
6011 for (i = 0; i < len; i++) {
6012 u8 vic = svd_to_vic(svds[i]);
6014 if (!drm_valid_cea_vic(vic))
6017 info->vics[vic_index++] = vic;
6022 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
6024 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
6025 * using the VICs themselves.
6027 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
6029 struct drm_display_info *info = &connector->display_info;
6030 struct drm_hdmi_info *hdmi = &info->hdmi;
6031 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
6033 for (i = 0; i < len; i++) {
6034 u8 vic = info->vics[i];
6036 if (vic && y420cmdb_map & BIT_ULL(i))
6037 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
6041 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
6043 const struct drm_display_info *info = &connector->display_info;
6046 if (!vic || !info->vics)
6049 for (i = 0; i < info->vics_len; i++) {
6050 if (info->vics[i] == vic)
6057 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
6058 static void parse_cta_y420vdb(struct drm_connector *connector,
6059 const struct cea_db *db)
6061 struct drm_display_info *info = &connector->display_info;
6062 struct drm_hdmi_info *hdmi = &info->hdmi;
6063 const u8 *svds = cea_db_data(db) + 1;
6066 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
6067 u8 vic = svd_to_vic(svds[i]);
6069 if (!drm_valid_cea_vic(vic))
6072 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
6073 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
6077 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
6079 struct drm_display_info *info = &connector->display_info;
6081 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
6082 connector->base.id, connector->name, db[2]);
6084 if (db[2] & EDID_CEA_VCDB_QS)
6085 info->rgb_quant_range_selectable = true;
6089 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
6091 switch (max_frl_rate) {
6094 *max_rate_per_lane = 3;
6098 *max_rate_per_lane = 6;
6102 *max_rate_per_lane = 6;
6106 *max_rate_per_lane = 8;
6110 *max_rate_per_lane = 10;
6114 *max_rate_per_lane = 12;
6119 *max_rate_per_lane = 0;
6123 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
6127 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
6129 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
6130 hdmi->y420_dc_modes = dc_mask;
6133 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
6136 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
6138 if (!hdmi_dsc->v_1p2)
6141 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6142 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6144 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6145 hdmi_dsc->bpc_supported = 16;
6146 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6147 hdmi_dsc->bpc_supported = 12;
6148 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6149 hdmi_dsc->bpc_supported = 10;
6151 /* Supports min 8 BPC if DSC 1.2 is supported*/
6152 hdmi_dsc->bpc_supported = 8;
6154 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6156 u8 dsc_max_frl_rate;
6158 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6159 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6160 &hdmi_dsc->max_frl_rate_per_lane);
6162 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6164 switch (dsc_max_slices) {
6166 hdmi_dsc->max_slices = 1;
6167 hdmi_dsc->clk_per_slice = 340;
6170 hdmi_dsc->max_slices = 2;
6171 hdmi_dsc->clk_per_slice = 340;
6174 hdmi_dsc->max_slices = 4;
6175 hdmi_dsc->clk_per_slice = 340;
6178 hdmi_dsc->max_slices = 8;
6179 hdmi_dsc->clk_per_slice = 340;
6182 hdmi_dsc->max_slices = 8;
6183 hdmi_dsc->clk_per_slice = 400;
6186 hdmi_dsc->max_slices = 12;
6187 hdmi_dsc->clk_per_slice = 400;
6190 hdmi_dsc->max_slices = 16;
6191 hdmi_dsc->clk_per_slice = 400;
6195 hdmi_dsc->max_slices = 0;
6196 hdmi_dsc->clk_per_slice = 0;
6200 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6201 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
6204 /* Sink Capability Data Structure */
6205 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6208 struct drm_display_info *info = &connector->display_info;
6209 struct drm_hdmi_info *hdmi = &info->hdmi;
6210 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
6211 int max_tmds_clock = 0;
6212 u8 max_frl_rate = 0;
6213 bool dsc_support = false;
6215 info->has_hdmi_infoframe = true;
6217 if (hf_scds[6] & 0x80) {
6218 hdmi->scdc.supported = true;
6219 if (hf_scds[6] & 0x40)
6220 hdmi->scdc.read_request = true;
6224 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6225 * And as per the spec, three factors confirm this:
6226 * * Availability of a HF-VSDB block in EDID (check)
6227 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6228 * * SCDC support available (let's check)
6229 * Lets check it out.
6233 struct drm_scdc *scdc = &hdmi->scdc;
6235 /* max clock is 5000 KHz times block value */
6236 max_tmds_clock = hf_scds[5] * 5000;
6238 if (max_tmds_clock > 340000) {
6239 info->max_tmds_clock = max_tmds_clock;
6242 if (scdc->supported) {
6243 scdc->scrambling.supported = true;
6245 /* Few sinks support scrambling for clocks < 340M */
6246 if ((hf_scds[6] & 0x8))
6247 scdc->scrambling.low_rates = true;
6252 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6253 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6254 &hdmi->max_frl_rate_per_lane);
6257 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6259 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6260 drm_parse_dsc_info(hdmi_dsc, hf_scds);
6264 drm_dbg_kms(connector->dev,
6265 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6266 connector->base.id, connector->name,
6267 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6270 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6273 struct drm_display_info *info = &connector->display_info;
6274 unsigned int dc_bpc = 0;
6276 /* HDMI supports at least 8 bpc */
6279 if (cea_db_payload_len(hdmi) < 6)
6282 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6284 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6285 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6286 connector->base.id, connector->name);
6289 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6291 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6292 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6293 connector->base.id, connector->name);
6296 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6298 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6299 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6300 connector->base.id, connector->name);
6304 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6305 connector->base.id, connector->name);
6309 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6310 connector->base.id, connector->name, dc_bpc);
6313 /* YCRCB444 is optional according to spec. */
6314 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6315 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6316 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6317 connector->base.id, connector->name);
6321 * Spec says that if any deep color mode is supported at all,
6322 * then deep color 36 bit must be supported.
6324 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6325 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6326 connector->base.id, connector->name);
6330 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
6332 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6334 struct drm_display_info *info = &connector->display_info;
6335 u8 len = cea_db_payload_len(db);
6337 info->is_hdmi = true;
6339 info->source_physical_address = (db[4] << 8) | db[5];
6342 info->dvi_dual = db[6] & 1;
6344 info->max_tmds_clock = db[7] * 5000;
6347 * Try to infer whether the sink supports HDMI infoframes.
6349 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6350 * supports infoframes if HDMI_Video_present is set.
6352 if (len >= 8 && db[8] & BIT(5))
6353 info->has_hdmi_infoframe = true;
6355 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6356 connector->base.id, connector->name,
6357 info->dvi_dual, info->max_tmds_clock);
6359 drm_parse_hdmi_deep_color_info(connector, db);
6363 * See EDID extension for head-mounted and specialized monitors, specified at:
6364 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6366 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6369 struct drm_display_info *info = &connector->display_info;
6371 bool desktop_usage = db[5] & BIT(6);
6373 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6374 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6375 info->non_desktop = true;
6377 drm_dbg_kms(connector->dev,
6378 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6379 connector->base.id, connector->name, version, db[5]);
6382 static void drm_parse_cea_ext(struct drm_connector *connector,
6383 const struct drm_edid *drm_edid)
6385 struct drm_display_info *info = &connector->display_info;
6386 struct drm_edid_iter edid_iter;
6387 const struct cea_db *db;
6388 struct cea_db_iter iter;
6390 u64 y420cmdb_map = 0;
6392 drm_edid_iter_begin(drm_edid, &edid_iter);
6393 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6394 if (edid_ext[0] != CEA_EXT)
6398 info->cea_rev = edid_ext[1];
6400 if (info->cea_rev != edid_ext[1])
6401 drm_dbg_kms(connector->dev,
6402 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6403 connector->base.id, connector->name,
6404 info->cea_rev, edid_ext[1]);
6406 /* The existence of a CTA extension should imply RGB support */
6407 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6408 if (edid_ext[3] & EDID_CEA_YCRCB444)
6409 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6410 if (edid_ext[3] & EDID_CEA_YCRCB422)
6411 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6412 if (edid_ext[3] & EDID_BASIC_AUDIO)
6413 info->has_audio = true;
6416 drm_edid_iter_end(&edid_iter);
6418 cea_db_iter_edid_begin(drm_edid, &iter);
6419 cea_db_iter_for_each(db, &iter) {
6420 /* FIXME: convert parsers to use struct cea_db */
6421 const u8 *data = (const u8 *)db;
6423 if (cea_db_is_hdmi_vsdb(db))
6424 drm_parse_hdmi_vsdb_video(connector, data);
6425 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6426 cea_db_is_hdmi_forum_scdb(db))
6427 drm_parse_hdmi_forum_scds(connector, data);
6428 else if (cea_db_is_microsoft_vsdb(db))
6429 drm_parse_microsoft_vsdb(connector, data);
6430 else if (cea_db_is_y420cmdb(db))
6431 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
6432 else if (cea_db_is_y420vdb(db))
6433 parse_cta_y420vdb(connector, db);
6434 else if (cea_db_is_vcdb(db))
6435 drm_parse_vcdb(connector, data);
6436 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6437 drm_parse_hdr_metadata_block(connector, data);
6438 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6439 parse_cta_vdb(connector, db);
6440 else if (cea_db_tag(db) == CTA_DB_AUDIO)
6441 info->has_audio = true;
6443 cea_db_iter_end(&iter);
6446 update_cta_y420cmdb(connector, y420cmdb_map);
6450 void get_monitor_range(const struct detailed_timing *timing, void *c)
6452 struct detailed_mode_closure *closure = c;
6453 struct drm_display_info *info = &closure->connector->display_info;
6454 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6455 const struct detailed_non_pixel *data = &timing->data.other_data;
6456 const struct detailed_data_monitor_range *range = &data->data.range;
6457 const struct edid *edid = closure->drm_edid->edid;
6459 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6463 * These limits are used to determine the VRR refresh
6464 * rate range. Only the "range limits only" variant
6465 * of the range descriptor seems to guarantee that
6466 * any and all timings are accepted by the sink, as
6467 * opposed to just timings conforming to the indicated
6468 * formula (GTF/GTF2/CVT). Thus other variants of the
6469 * range descriptor are not accepted here.
6471 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6474 monitor_range->min_vfreq = range->min_vfreq;
6475 monitor_range->max_vfreq = range->max_vfreq;
6477 if (edid->revision >= 4) {
6478 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6479 monitor_range->min_vfreq += 255;
6480 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6481 monitor_range->max_vfreq += 255;
6485 static void drm_get_monitor_range(struct drm_connector *connector,
6486 const struct drm_edid *drm_edid)
6488 const struct drm_display_info *info = &connector->display_info;
6489 struct detailed_mode_closure closure = {
6490 .connector = connector,
6491 .drm_edid = drm_edid,
6494 if (drm_edid->edid->revision < 4)
6497 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6500 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6502 drm_dbg_kms(connector->dev,
6503 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6504 connector->base.id, connector->name,
6505 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6508 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6509 const struct displayid_block *block)
6511 struct displayid_vesa_vendor_specific_block *vesa =
6512 (struct displayid_vesa_vendor_specific_block *)block;
6513 struct drm_display_info *info = &connector->display_info;
6515 if (block->num_bytes < 3) {
6516 drm_dbg_kms(connector->dev,
6517 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6518 connector->base.id, connector->name, block->num_bytes);
6522 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6525 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6526 drm_dbg_kms(connector->dev,
6527 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6528 connector->base.id, connector->name);
6532 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6534 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6535 connector->base.id, connector->name);
6538 info->mso_stream_count = 0;
6541 info->mso_stream_count = 2; /* 2 or 4 links */
6544 info->mso_stream_count = 4; /* 4 links */
6548 if (!info->mso_stream_count) {
6549 info->mso_pixel_overlap = 0;
6553 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6554 if (info->mso_pixel_overlap > 8) {
6555 drm_dbg_kms(connector->dev,
6556 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6557 connector->base.id, connector->name,
6558 info->mso_pixel_overlap);
6559 info->mso_pixel_overlap = 8;
6562 drm_dbg_kms(connector->dev,
6563 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6564 connector->base.id, connector->name,
6565 info->mso_stream_count, info->mso_pixel_overlap);
6568 static void drm_update_mso(struct drm_connector *connector,
6569 const struct drm_edid *drm_edid)
6571 const struct displayid_block *block;
6572 struct displayid_iter iter;
6574 displayid_iter_edid_begin(drm_edid, &iter);
6575 displayid_iter_for_each(block, &iter) {
6576 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6577 drm_parse_vesa_mso_data(connector, block);
6579 displayid_iter_end(&iter);
6582 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6583 * all of the values which would have been set from EDID
6585 static void drm_reset_display_info(struct drm_connector *connector)
6587 struct drm_display_info *info = &connector->display_info;
6590 info->height_mm = 0;
6593 info->color_formats = 0;
6595 info->max_tmds_clock = 0;
6596 info->dvi_dual = false;
6597 info->is_hdmi = false;
6598 info->has_audio = false;
6599 info->has_hdmi_infoframe = false;
6600 info->rgb_quant_range_selectable = false;
6601 memset(&info->hdmi, 0, sizeof(info->hdmi));
6603 info->edid_hdmi_rgb444_dc_modes = 0;
6604 info->edid_hdmi_ycbcr444_dc_modes = 0;
6606 info->non_desktop = 0;
6607 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6608 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6610 info->mso_stream_count = 0;
6611 info->mso_pixel_overlap = 0;
6612 info->max_dsc_bpp = 0;
6620 info->source_physical_address = CEC_PHYS_ADDR_INVALID;
6623 static void update_displayid_info(struct drm_connector *connector,
6624 const struct drm_edid *drm_edid)
6626 struct drm_display_info *info = &connector->display_info;
6627 const struct displayid_block *block;
6628 struct displayid_iter iter;
6630 displayid_iter_edid_begin(drm_edid, &iter);
6631 displayid_iter_for_each(block, &iter) {
6632 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6633 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6634 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6635 info->non_desktop = true;
6638 * We're only interested in the base section here, no need to
6643 displayid_iter_end(&iter);
6646 static void update_display_info(struct drm_connector *connector,
6647 const struct drm_edid *drm_edid)
6649 struct drm_display_info *info = &connector->display_info;
6650 const struct edid *edid;
6652 drm_reset_display_info(connector);
6653 clear_eld(connector);
6658 edid = drm_edid->edid;
6660 info->quirks = edid_get_quirks(drm_edid);
6662 info->width_mm = edid->width_cm * 10;
6663 info->height_mm = edid->height_cm * 10;
6665 drm_get_monitor_range(connector, drm_edid);
6667 if (edid->revision < 3)
6670 if (!drm_edid_is_digital(drm_edid))
6673 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6674 drm_parse_cea_ext(connector, drm_edid);
6676 update_displayid_info(connector, drm_edid);
6679 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6681 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6682 * tells us to assume 8 bpc color depth if the EDID doesn't have
6683 * extensions which tell otherwise.
6685 if (info->bpc == 0 && edid->revision == 3 &&
6686 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6688 drm_dbg_kms(connector->dev,
6689 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6690 connector->base.id, connector->name, info->bpc);
6693 /* Only defined for 1.4 with digital displays */
6694 if (edid->revision < 4)
6697 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6698 case DRM_EDID_DIGITAL_DEPTH_6:
6701 case DRM_EDID_DIGITAL_DEPTH_8:
6704 case DRM_EDID_DIGITAL_DEPTH_10:
6707 case DRM_EDID_DIGITAL_DEPTH_12:
6710 case DRM_EDID_DIGITAL_DEPTH_14:
6713 case DRM_EDID_DIGITAL_DEPTH_16:
6716 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6722 drm_dbg_kms(connector->dev,
6723 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6724 connector->base.id, connector->name, info->bpc);
6726 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6727 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6728 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6729 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6731 drm_update_mso(connector, drm_edid);
6734 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
6735 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6736 connector->base.id, connector->name,
6737 info->non_desktop ? " (redundant quirk)" : "");
6738 info->non_desktop = true;
6741 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
6742 info->max_dsc_bpp = 15;
6744 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6747 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6750 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6753 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6756 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6757 drm_edid_to_eld(connector, drm_edid);
6760 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6761 struct displayid_detailed_timings_1 *timings,
6764 struct drm_display_mode *mode;
6765 unsigned pixel_clock = (timings->pixel_clock[0] |
6766 (timings->pixel_clock[1] << 8) |
6767 (timings->pixel_clock[2] << 16)) + 1;
6768 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6769 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6770 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6771 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6772 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6773 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6774 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6775 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6776 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6777 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6779 mode = drm_mode_create(dev);
6783 /* resolution is kHz for type VII, and 10 kHz for type I */
6784 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6785 mode->hdisplay = hactive;
6786 mode->hsync_start = mode->hdisplay + hsync;
6787 mode->hsync_end = mode->hsync_start + hsync_width;
6788 mode->htotal = mode->hdisplay + hblank;
6790 mode->vdisplay = vactive;
6791 mode->vsync_start = mode->vdisplay + vsync;
6792 mode->vsync_end = mode->vsync_start + vsync_width;
6793 mode->vtotal = mode->vdisplay + vblank;
6796 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6797 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6798 mode->type = DRM_MODE_TYPE_DRIVER;
6800 if (timings->flags & 0x80)
6801 mode->type |= DRM_MODE_TYPE_PREFERRED;
6802 drm_mode_set_name(mode);
6807 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6808 const struct displayid_block *block)
6810 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6813 struct drm_display_mode *newmode;
6815 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6816 /* blocks must be multiple of 20 bytes length */
6817 if (block->num_bytes % 20)
6820 num_timings = block->num_bytes / 20;
6821 for (i = 0; i < num_timings; i++) {
6822 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6824 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6828 drm_mode_probed_add(connector, newmode);
6834 static int add_displayid_detailed_modes(struct drm_connector *connector,
6835 const struct drm_edid *drm_edid)
6837 const struct displayid_block *block;
6838 struct displayid_iter iter;
6841 displayid_iter_edid_begin(drm_edid, &iter);
6842 displayid_iter_for_each(block, &iter) {
6843 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6844 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6845 num_modes += add_displayid_detailed_1_modes(connector, block);
6847 displayid_iter_end(&iter);
6852 static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6853 const struct drm_edid *drm_edid)
6855 const struct drm_display_info *info = &connector->display_info;
6862 * EDID spec says modes should be preferred in this order:
6863 * - preferred detailed mode
6864 * - other detailed modes from base block
6865 * - detailed modes from extension blocks
6866 * - CVT 3-byte code modes
6867 * - standard timing codes
6868 * - established timing codes
6869 * - modes inferred from GTF or CVT range information
6871 * We get this pretty much right.
6873 * XXX order for additional mode types in extension blocks?
6875 num_modes += add_detailed_modes(connector, drm_edid);
6876 num_modes += add_cvt_modes(connector, drm_edid);
6877 num_modes += add_standard_modes(connector, drm_edid);
6878 num_modes += add_established_modes(connector, drm_edid);
6879 num_modes += add_cea_modes(connector, drm_edid);
6880 num_modes += add_alternate_cea_modes(connector, drm_edid);
6881 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6882 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6883 num_modes += add_inferred_modes(connector, drm_edid);
6885 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6886 edid_fixup_preferred(connector);
6891 static void _drm_update_tile_info(struct drm_connector *connector,
6892 const struct drm_edid *drm_edid);
6894 static int _drm_edid_connector_property_update(struct drm_connector *connector,
6895 const struct drm_edid *drm_edid)
6897 struct drm_device *dev = connector->dev;
6900 if (connector->edid_blob_ptr) {
6901 const void *old_edid = connector->edid_blob_ptr->data;
6902 size_t old_edid_size = connector->edid_blob_ptr->length;
6904 if (old_edid && !drm_edid_eq(drm_edid, old_edid, old_edid_size)) {
6905 connector->epoch_counter++;
6906 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6907 connector->base.id, connector->name,
6908 connector->epoch_counter);
6912 ret = drm_property_replace_global_blob(dev,
6913 &connector->edid_blob_ptr,
6914 drm_edid ? drm_edid->size : 0,
6915 drm_edid ? drm_edid->edid : NULL,
6917 dev->mode_config.edid_property);
6919 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6920 connector->base.id, connector->name, ret);
6924 ret = drm_object_property_set_value(&connector->base,
6925 dev->mode_config.non_desktop_property,
6926 connector->display_info.non_desktop);
6928 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6929 connector->base.id, connector->name, ret);
6933 ret = drm_connector_set_tile_property(connector);
6935 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6936 connector->base.id, connector->name, ret);
6944 /* For sysfs edid show implementation */
6945 ssize_t drm_edid_connector_property_show(struct drm_connector *connector,
6946 char *buf, loff_t off, size_t count)
6952 mutex_lock(&connector->dev->mode_config.mutex);
6954 if (!connector->edid_blob_ptr)
6957 edid = connector->edid_blob_ptr->data;
6958 size = connector->edid_blob_ptr->length;
6965 if (off + count > size)
6968 memcpy(buf, edid + off, count);
6972 mutex_unlock(&connector->dev->mode_config.mutex);
6978 * drm_edid_connector_update - Update connector information from EDID
6979 * @connector: Connector
6982 * Update the connector display info, ELD, HDR metadata, relevant properties,
6983 * etc. from the passed in EDID.
6985 * If EDID is NULL, reset the information.
6987 * Must be called before calling drm_edid_connector_add_modes().
6989 * Return: 0 on success, negative error on errors.
6991 int drm_edid_connector_update(struct drm_connector *connector,
6992 const struct drm_edid *drm_edid)
6994 update_display_info(connector, drm_edid);
6996 _drm_update_tile_info(connector, drm_edid);
6998 return _drm_edid_connector_property_update(connector, drm_edid);
7000 EXPORT_SYMBOL(drm_edid_connector_update);
7003 * drm_edid_connector_add_modes - Update probed modes from the EDID property
7004 * @connector: Connector
7006 * Add the modes from the previously updated EDID property to the connector
7007 * probed modes list.
7009 * drm_edid_connector_update() must have been called before this to update the
7012 * Return: The number of modes added, or 0 if we couldn't find any.
7014 int drm_edid_connector_add_modes(struct drm_connector *connector)
7016 const struct drm_edid *drm_edid = NULL;
7019 if (connector->edid_blob_ptr)
7020 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
7021 connector->edid_blob_ptr->length);
7023 count = _drm_edid_connector_add_modes(connector, drm_edid);
7025 drm_edid_free(drm_edid);
7029 EXPORT_SYMBOL(drm_edid_connector_add_modes);
7032 * drm_connector_update_edid_property - update the edid property of a connector
7033 * @connector: drm connector
7034 * @edid: new value of the edid property
7036 * This function creates a new blob modeset object and assigns its id to the
7037 * connector's edid property.
7038 * Since we also parse tile information from EDID's displayID block, we also
7039 * set the connector's tile property here. See drm_connector_set_tile_property()
7042 * This function is deprecated. Use drm_edid_connector_update() instead.
7045 * Zero on success, negative errno on failure.
7047 int drm_connector_update_edid_property(struct drm_connector *connector,
7048 const struct edid *edid)
7050 struct drm_edid drm_edid;
7052 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
7054 EXPORT_SYMBOL(drm_connector_update_edid_property);
7057 * drm_add_edid_modes - add modes from EDID data, if available
7058 * @connector: connector we're probing
7061 * Add the specified modes to the connector's mode list. Also fills out the
7062 * &drm_display_info structure and ELD in @connector with any information which
7063 * can be derived from the edid.
7065 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
7067 * Return: The number of modes added or 0 if we couldn't find any.
7069 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
7071 struct drm_edid _drm_edid;
7072 const struct drm_edid *drm_edid;
7074 if (edid && !drm_edid_is_valid(edid)) {
7075 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
7076 connector->base.id, connector->name);
7080 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
7082 update_display_info(connector, drm_edid);
7084 return _drm_edid_connector_add_modes(connector, drm_edid);
7086 EXPORT_SYMBOL(drm_add_edid_modes);
7089 * drm_add_modes_noedid - add modes for the connectors without EDID
7090 * @connector: connector we're probing
7091 * @hdisplay: the horizontal display limit
7092 * @vdisplay: the vertical display limit
7094 * Add the specified modes to the connector's mode list. Only when the
7095 * hdisplay/vdisplay is not beyond the given limit, it will be added.
7097 * Return: The number of modes added or 0 if we couldn't find any.
7099 int drm_add_modes_noedid(struct drm_connector *connector,
7100 int hdisplay, int vdisplay)
7102 int i, count, num_modes = 0;
7103 struct drm_display_mode *mode;
7104 struct drm_device *dev = connector->dev;
7106 count = ARRAY_SIZE(drm_dmt_modes);
7112 for (i = 0; i < count; i++) {
7113 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
7115 if (hdisplay && vdisplay) {
7117 * Only when two are valid, they will be used to check
7118 * whether the mode should be added to the mode list of
7121 if (ptr->hdisplay > hdisplay ||
7122 ptr->vdisplay > vdisplay)
7125 if (drm_mode_vrefresh(ptr) > 61)
7127 mode = drm_mode_duplicate(dev, ptr);
7129 drm_mode_probed_add(connector, mode);
7135 EXPORT_SYMBOL(drm_add_modes_noedid);
7137 static bool is_hdmi2_sink(const struct drm_connector *connector)
7140 * FIXME: sil-sii8620 doesn't have a connector around when
7141 * we need one, so we have to be prepared for a NULL connector.
7146 return connector->display_info.hdmi.scdc.supported ||
7147 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
7150 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
7151 const struct drm_display_mode *mode)
7153 bool has_hdmi_infoframe = connector ?
7154 connector->display_info.has_hdmi_infoframe : false;
7156 if (!has_hdmi_infoframe)
7159 /* No HDMI VIC when signalling 3D video format */
7160 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7163 return drm_match_hdmi_mode(mode);
7166 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
7167 const struct drm_display_mode *mode)
7170 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7171 * we should send its VIC in vendor infoframes, else send the
7172 * VIC in AVI infoframes. Lets check if this mode is present in
7173 * HDMI 1.4b 4K modes
7175 if (drm_mode_hdmi_vic(connector, mode))
7178 return drm_match_cea_mode(mode);
7182 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7183 * conform to HDMI 1.4.
7185 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7186 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
7188 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7191 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7193 if (!is_hdmi2_sink(connector) && vic > 64 &&
7194 !cta_vdb_has_vic(connector, vic))
7201 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7202 * data from a DRM display mode
7203 * @frame: HDMI AVI infoframe
7204 * @connector: the connector
7205 * @mode: DRM display mode
7207 * Return: 0 on success or a negative error code on failure.
7210 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
7211 const struct drm_connector *connector,
7212 const struct drm_display_mode *mode)
7214 enum hdmi_picture_aspect picture_aspect;
7217 if (!frame || !mode)
7220 hdmi_avi_infoframe_init(frame);
7222 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7223 frame->pixel_repeat = 1;
7225 vic = drm_mode_cea_vic(connector, mode);
7226 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
7228 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7231 * As some drivers don't support atomic, we can't use connector state.
7232 * So just initialize the frame with default values, just the same way
7233 * as it's done with other properties here.
7235 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7239 * Populate picture aspect ratio from either
7240 * user input (if specified) or from the CEA/HDMI mode lists.
7242 picture_aspect = mode->picture_aspect_ratio;
7243 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7245 picture_aspect = drm_get_cea_aspect_ratio(vic);
7247 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7251 * The infoframe can't convey anything but none, 4:3
7252 * and 16:9, so if the user has asked for anything else
7253 * we can only satisfy it by specifying the right VIC.
7255 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
7257 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7259 } else if (hdmi_vic) {
7260 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7266 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7269 frame->video_code = vic_for_avi_infoframe(connector, vic);
7270 frame->picture_aspect = picture_aspect;
7271 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
7272 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
7276 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
7279 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7280 * quantization range information
7281 * @frame: HDMI AVI infoframe
7282 * @connector: the connector
7283 * @mode: DRM display mode
7284 * @rgb_quant_range: RGB quantization range (Q)
7287 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
7288 const struct drm_connector *connector,
7289 const struct drm_display_mode *mode,
7290 enum hdmi_quantization_range rgb_quant_range)
7292 const struct drm_display_info *info = &connector->display_info;
7296 * "A Source shall not send a non-zero Q value that does not correspond
7297 * to the default RGB Quantization Range for the transmitted Picture
7298 * unless the Sink indicates support for the Q bit in a Video
7299 * Capabilities Data Block."
7301 * HDMI 2.0 recommends sending non-zero Q when it does match the
7302 * default RGB quantization range for the mode, even when QS=0.
7304 if (info->rgb_quant_range_selectable ||
7305 rgb_quant_range == drm_default_rgb_quant_range(mode))
7306 frame->quantization_range = rgb_quant_range;
7308 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7312 * "When transmitting any RGB colorimetry, the Source should set the
7313 * YQ-field to match the RGB Quantization Range being transmitted
7314 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7315 * set YQ=1) and the Sink shall ignore the YQ-field."
7317 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7318 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7319 * good way to tell which version of CEA-861 the sink supports, so
7320 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7323 if (!is_hdmi2_sink(connector) ||
7324 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7325 frame->ycc_quantization_range =
7326 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7328 frame->ycc_quantization_range =
7329 HDMI_YCC_QUANTIZATION_RANGE_FULL;
7331 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7333 static enum hdmi_3d_structure
7334 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7336 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7339 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7340 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7341 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7342 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7343 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7344 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7345 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7346 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7347 case DRM_MODE_FLAG_3D_L_DEPTH:
7348 return HDMI_3D_STRUCTURE_L_DEPTH;
7349 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7350 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7351 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7352 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7353 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7354 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7356 return HDMI_3D_STRUCTURE_INVALID;
7361 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7362 * data from a DRM display mode
7363 * @frame: HDMI vendor infoframe
7364 * @connector: the connector
7365 * @mode: DRM display mode
7367 * Note that there's is a need to send HDMI vendor infoframes only when using a
7368 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7369 * function will return -EINVAL, error that can be safely ignored.
7371 * Return: 0 on success or a negative error code on failure.
7374 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7375 const struct drm_connector *connector,
7376 const struct drm_display_mode *mode)
7379 * FIXME: sil-sii8620 doesn't have a connector around when
7380 * we need one, so we have to be prepared for a NULL connector.
7382 bool has_hdmi_infoframe = connector ?
7383 connector->display_info.has_hdmi_infoframe : false;
7386 if (!frame || !mode)
7389 if (!has_hdmi_infoframe)
7392 err = hdmi_vendor_infoframe_init(frame);
7397 * Even if it's not absolutely necessary to send the infoframe
7398 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7399 * know that the sink can handle it. This is based on a
7400 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7401 * have trouble realizing that they should switch from 3D to 2D
7402 * mode if the source simply stops sending the infoframe when
7403 * it wants to switch from 3D to 2D.
7405 frame->vic = drm_mode_hdmi_vic(connector, mode);
7406 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7410 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7412 static void drm_parse_tiled_block(struct drm_connector *connector,
7413 const struct displayid_block *block)
7415 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7417 u8 tile_v_loc, tile_h_loc;
7418 u8 num_v_tile, num_h_tile;
7419 struct drm_tile_group *tg;
7421 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7422 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7424 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7425 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7426 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7427 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7429 connector->has_tile = true;
7430 if (tile->tile_cap & 0x80)
7431 connector->tile_is_single_monitor = true;
7433 connector->num_h_tile = num_h_tile + 1;
7434 connector->num_v_tile = num_v_tile + 1;
7435 connector->tile_h_loc = tile_h_loc;
7436 connector->tile_v_loc = tile_v_loc;
7437 connector->tile_h_size = w + 1;
7438 connector->tile_v_size = h + 1;
7440 drm_dbg_kms(connector->dev,
7441 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7442 connector->base.id, connector->name,
7444 connector->tile_h_size, connector->tile_v_size,
7445 connector->num_h_tile, connector->num_v_tile,
7446 connector->tile_h_loc, connector->tile_v_loc,
7447 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7449 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7451 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7455 if (connector->tile_group != tg) {
7456 /* if we haven't got a pointer,
7457 take the reference, drop ref to old tile group */
7458 if (connector->tile_group)
7459 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7460 connector->tile_group = tg;
7462 /* if same tile group, then release the ref we just took. */
7463 drm_mode_put_tile_group(connector->dev, tg);
7467 static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7468 const struct displayid_block *block)
7470 return (displayid_version(iter) < DISPLAY_ID_STRUCTURE_VER_20 &&
7471 block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7472 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7473 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7476 static void _drm_update_tile_info(struct drm_connector *connector,
7477 const struct drm_edid *drm_edid)
7479 const struct displayid_block *block;
7480 struct displayid_iter iter;
7482 connector->has_tile = false;
7484 displayid_iter_edid_begin(drm_edid, &iter);
7485 displayid_iter_for_each(block, &iter) {
7486 if (displayid_is_tiled_block(&iter, block))
7487 drm_parse_tiled_block(connector, block);
7489 displayid_iter_end(&iter);
7491 if (!connector->has_tile && connector->tile_group) {
7492 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7493 connector->tile_group = NULL;
7498 * drm_edid_is_digital - is digital?
7499 * @drm_edid: The EDID
7501 * Return true if input is digital.
7503 bool drm_edid_is_digital(const struct drm_edid *drm_edid)
7505 return drm_edid && drm_edid->edid &&
7506 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL;
7508 EXPORT_SYMBOL(drm_edid_is_digital);
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