drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

   1 /*
   2  * Copyright 2023 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_12_0_0_offset.h"
  34 #include "gc/gc_12_0_0_sh_mask.h"
  35 #include "hdp/hdp_6_0_0_offset.h"
  36 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
  37
  38 #include "soc15_common.h"
  39 #include "soc15.h"
  40 #include "sdma_v6_0_0_pkt_open.h"
  41 #include "nbio_v4_3.h"
  42 #include "sdma_common.h"
  43 #include "sdma_v7_0.h"
  44 #include "v12_structs.h"
  45
  46 MODULE_FIRMWARE("amdgpu/sdma_7_0_0.bin");
  47 MODULE_FIRMWARE("amdgpu/sdma_7_0_1.bin");
  48
  49 #define SDMA1_REG_OFFSET 0x600
  50 #define SDMA0_HYP_DEC_REG_START 0x5880
  51 #define SDMA0_HYP_DEC_REG_END 0x589a
  52 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  53
  54 static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  55 static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev);
  56 static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  57 static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  58 static int sdma_v7_0_start(struct amdgpu_device *adev);
  59
  60 static u32 sdma_v7_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  61 {
  62         u32 base;
  63
  64         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  65             internal_offset <= SDMA0_HYP_DEC_REG_END) {
  66                 base = adev->reg_offset[GC_HWIP][0][1];
  67                 if (instance != 0)
  68                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
  69         } else {
  70                 base = adev->reg_offset[GC_HWIP][0][0];
  71                 if (instance == 1)
  72                         internal_offset += SDMA1_REG_OFFSET;
  73         }
  74
  75         return base + internal_offset;
  76 }
  77
  78 static unsigned sdma_v7_0_ring_init_cond_exec(struct amdgpu_ring *ring,
  79                                               uint64_t addr)
  80 {
  81         unsigned ret;
  82
  83         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE));
  84         amdgpu_ring_write(ring, lower_32_bits(addr));
  85         amdgpu_ring_write(ring, upper_32_bits(addr));
  86         amdgpu_ring_write(ring, 1);
  87         /* this is the offset we need patch later */
  88         ret = ring->wptr & ring->buf_mask;
  89         /* insert dummy here and patch it later */
  90         amdgpu_ring_write(ring, 0);
  91
  92         return ret;
  93 }
  94
  95 /**
  96  * sdma_v7_0_ring_get_rptr - get the current read pointer
  97  *
  98  * @ring: amdgpu ring pointer
  99  *
 100  * Get the current rptr from the hardware.
 101  */
 102 static uint64_t sdma_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
 103 {
 104         u64 *rptr;
 105
 106         /* XXX check if swapping is necessary on BE */
 107         rptr = (u64 *)ring->rptr_cpu_addr;
 108
 109         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 110         return ((*rptr) >> 2);
 111 }
 112
 113 /**
 114  * sdma_v7_0_ring_get_wptr - get the current write pointer
 115  *
 116  * @ring: amdgpu ring pointer
 117  *
 118  * Get the current wptr from the hardware.
 119  */
 120 static uint64_t sdma_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
 121 {
 122         u64 wptr = 0;
 123
 124         if (ring->use_doorbell) {
 125                 /* XXX check if swapping is necessary on BE */
 126                 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
 127                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 128         }
 129
 130         return wptr >> 2;
 131 }
 132
 133 /**
 134  * sdma_v7_0_ring_set_wptr - commit the write pointer
 135  *
 136  * @ring: amdgpu ring pointer
 137  *
 138  * Write the wptr back to the hardware.
 139  */
 140 static void sdma_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
 141 {
 142         struct amdgpu_device *adev = ring->adev;
 143         uint32_t *wptr_saved;
 144         uint32_t *is_queue_unmap;
 145         uint64_t aggregated_db_index;
 146         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;
 147
 148         DRM_DEBUG("Setting write pointer\n");
 149
 150         if (ring->is_mes_queue) {
 151                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
 152                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
 153                                               sizeof(uint32_t));
 154                 aggregated_db_index =
 155                         amdgpu_mes_get_aggregated_doorbell_index(adev,
 156                                                          ring->hw_prio);
 157
 158                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
 159                              ring->wptr << 2);
 160                 *wptr_saved = ring->wptr << 2;
 161                 if (*is_queue_unmap) {
 162                         WDOORBELL64(aggregated_db_index, ring->wptr << 2);
 163                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 164                                         ring->doorbell_index, ring->wptr << 2);
 165                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 166                 } else {
 167                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 168                                         ring->doorbell_index, ring->wptr << 2);
 169                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 170                 }
 171         } else {
 172                 if (ring->use_doorbell) {
 173                         DRM_DEBUG("Using doorbell -- "
 174                                   "wptr_offs == 0x%08x "
 175                                   "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 176                                   "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 177                                   ring->wptr_offs,
 178                                   lower_32_bits(ring->wptr << 2),
 179                                   upper_32_bits(ring->wptr << 2));
 180                         /* XXX check if swapping is necessary on BE */
 181                         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
 182                                      ring->wptr << 2);
 183                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 184                                   ring->doorbell_index, ring->wptr << 2);
 185                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 186                 } else {
 187                         DRM_DEBUG("Not using doorbell -- "
 188                                   "regSDMA%i_GFX_RB_WPTR == 0x%08x "
 189                                   "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 190                                   ring->me,
 191                                   lower_32_bits(ring->wptr << 2),
 192                                   ring->me,
 193                                   upper_32_bits(ring->wptr << 2));
 194                         WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev,
 195                                                                      ring->me,
 196                                                                      regSDMA0_QUEUE0_RB_WPTR),
 197                                         lower_32_bits(ring->wptr << 2));
 198                         WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev,
 199                                                                      ring->me,
 200                                                                      regSDMA0_QUEUE0_RB_WPTR_HI),
 201                                         upper_32_bits(ring->wptr << 2));
 202                 }
 203         }
 204 }
 205
 206 static void sdma_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 207 {
 208         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 209         int i;
 210
 211         for (i = 0; i < count; i++)
 212                 if (sdma && sdma->burst_nop && (i == 0))
 213                         amdgpu_ring_write(ring, ring->funcs->nop |
 214                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 215                 else
 216                         amdgpu_ring_write(ring, ring->funcs->nop);
 217 }
 218
 219 /**
 220  * sdma_v7_0_ring_emit_ib - Schedule an IB on the DMA engine
 221  *
 222  * @ring: amdgpu ring pointer
 223  * @job: job to retrieve vmid from
 224  * @ib: IB object to schedule
 225  * @flags: unused
 226  *
 227  * Schedule an IB in the DMA ring.
 228  */
 229 static void sdma_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
 230                                    struct amdgpu_job *job,
 231                                    struct amdgpu_ib *ib,
 232                                    uint32_t flags)
 233 {
 234         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 235         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 236
 237         /* An IB packet must end on a 8 DW boundary--the next dword
 238          * must be on a 8-dword boundary. Our IB packet below is 6
 239          * dwords long, thus add x number of NOPs, such that, in
 240          * modular arithmetic,
 241          * wptr + 6 + x = 8k, k >= 0, which in C is,
 242          * (wptr + 6 + x) % 8 = 0.
 243          * The expression below, is a solution of x.
 244          */
 245         sdma_v7_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 246
 247         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) |
 248                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 249         /* base must be 32 byte aligned */
 250         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 251         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 252         amdgpu_ring_write(ring, ib->length_dw);
 253         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 254         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 255 }
 256
 257 /**
 258  * sdma_v7_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
 259  *
 260  * @ring: amdgpu ring pointer
 261  *
 262  * flush the IB by graphics cache rinse.
 263  */
 264 static void sdma_v7_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
 265 {
 266         uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
 267                 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
 268                 SDMA_GCR_GLI_INV(1);
 269
 270         /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
 271         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ));
 272         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
 273         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
 274                           SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
 275         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
 276                           SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
 277         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
 278                           SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 279 }
 280
 281
 282 /**
 283  * sdma_v7_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 284  *
 285  * @ring: amdgpu ring pointer
 286  *
 287  * Emit an hdp flush packet on the requested DMA ring.
 288  */
 289 static void sdma_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 290 {
 291         struct amdgpu_device *adev = ring->adev;
 292         u32 ref_and_mask = 0;
 293         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 294
 295         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 296
 297         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 298                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 299                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 300         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 301         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 302         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 303         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 304         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 305                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 306 }
 307
 308 /**
 309  * sdma_v7_0_ring_emit_fence - emit a fence on the DMA ring
 310  *
 311  * @ring: amdgpu ring pointer
 312  * @addr: address
 313  * @seq: fence seq number
 314  * @flags: fence flags
 315  *
 316  * Add a DMA fence packet to the ring to write
 317  * the fence seq number and DMA trap packet to generate
 318  * an interrupt if needed.
 319  */
 320 static void sdma_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 321                                       unsigned flags)
 322 {
 323         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 324         /* write the fence */
 325         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
 326                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 327         /* zero in first two bits */
 328         BUG_ON(addr & 0x3);
 329         amdgpu_ring_write(ring, lower_32_bits(addr));
 330         amdgpu_ring_write(ring, upper_32_bits(addr));
 331         amdgpu_ring_write(ring, lower_32_bits(seq));
 332
 333         /* optionally write high bits as well */
 334         if (write64bit) {
 335                 addr += 4;
 336                 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
 337                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 338                 /* zero in first two bits */
 339                 BUG_ON(addr & 0x3);
 340                 amdgpu_ring_write(ring, lower_32_bits(addr));
 341                 amdgpu_ring_write(ring, upper_32_bits(addr));
 342                 amdgpu_ring_write(ring, upper_32_bits(seq));
 343         }
 344
 345         if (flags & AMDGPU_FENCE_FLAG_INT) {
 346                 uint32_t ctx = ring->is_mes_queue ?
 347                         (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
 348                 /* generate an interrupt */
 349                 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP));
 350                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
 351         }
 352 }
 353
 354 /**
 355  * sdma_v7_0_gfx_stop - stop the gfx async dma engines
 356  *
 357  * @adev: amdgpu_device pointer
 358  *
 359  * Stop the gfx async dma ring buffers.
 360  */
 361 static void sdma_v7_0_gfx_stop(struct amdgpu_device *adev)
 362 {
 363         u32 rb_cntl, ib_cntl;
 364         int i;
 365
 366         for (i = 0; i < adev->sdma.num_instances; i++) {
 367                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
 368                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);
 369                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
 370                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
 371                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);
 372                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
 373         }
 374 }
 375
 376 /**
 377  * sdma_v7_0_rlc_stop - stop the compute async dma engines
 378  *
 379  * @adev: amdgpu_device pointer
 380  *
 381  * Stop the compute async dma queues.
 382  */
 383 static void sdma_v7_0_rlc_stop(struct amdgpu_device *adev)
 384 {
 385         /* XXX todo */
 386 }
 387
 388 /**
 389  * sdma_v7_0_ctx_switch_enable - stop the async dma engines context switch
 390  *
 391  * @adev: amdgpu_device pointer
 392  * @enable: enable/disable the DMA MEs context switch.
 393  *
 394  * Halt or unhalt the async dma engines context switch.
 395  */
 396 static void sdma_v7_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 397 {
 398 }
 399
 400 /**
 401  * sdma_v7_0_enable - stop the async dma engines
 402  *
 403  * @adev: amdgpu_device pointer
 404  * @enable: enable/disable the DMA MEs.
 405  *
 406  * Halt or unhalt the async dma engines.
 407  */
 408 static void sdma_v7_0_enable(struct amdgpu_device *adev, bool enable)
 409 {
 410         u32 mcu_cntl;
 411         int i;
 412
 413         if (!enable) {
 414                 sdma_v7_0_gfx_stop(adev);
 415                 sdma_v7_0_rlc_stop(adev);
 416         }
 417
 418         if (amdgpu_sriov_vf(adev))
 419                 return;
 420
 421         for (i = 0; i < adev->sdma.num_instances; i++) {
 422                 mcu_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));
 423                 mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_MCU_CNTL, HALT, enable ? 0 : 1);
 424                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), mcu_cntl);
 425         }
 426 }
 427
 428 /**
 429  * sdma_v7_0_gfx_resume - setup and start the async dma engines
 430  *
 431  * @adev: amdgpu_device pointer
 432  *
 433  * Set up the gfx DMA ring buffers and enable them.
 434  * Returns 0 for success, error for failure.
 435  */
 436 static int sdma_v7_0_gfx_resume(struct amdgpu_device *adev)
 437 {
 438         struct amdgpu_ring *ring;
 439         u32 rb_cntl, ib_cntl;
 440         u32 rb_bufsz;
 441         u32 doorbell;
 442         u32 doorbell_offset;
 443         u32 tmp;
 444         u64 wptr_gpu_addr;
 445         int i, r;
 446
 447         for (i = 0; i < adev->sdma.num_instances; i++) {
 448                 ring = &adev->sdma.instance[i].ring;
 449
 450                 //if (!amdgpu_sriov_vf(adev))
 451                 //      WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 452
 453                 /* Set ring buffer size in dwords */
 454                 rb_bufsz = order_base_2(ring->ring_size / 4);
 455                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
 456                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);
 457 #ifdef __BIG_ENDIAN
 458                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);
 459                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,
 460                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 461 #endif
 462                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);
 463                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
 464
 465                 /* Initialize the ring buffer's read and write pointers */
 466                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
 467                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
 468                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
 469                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
 470
 471                 /* setup the wptr shadow polling */
 472                 wptr_gpu_addr = ring->wptr_gpu_addr;
 473                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
 474                        lower_32_bits(wptr_gpu_addr));
 475                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),
 476                        upper_32_bits(wptr_gpu_addr));
 477
 478                 /* set the wb address whether it's enabled or not */
 479                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),
 480                        upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
 481                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),
 482                        lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 483
 484                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 485                 if (amdgpu_sriov_vf(adev))
 486                         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1);
 487                 else
 488                         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
 489                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, MCU_WPTR_POLL_ENABLE, 1);
 490
 491                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
 492                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
 493
 494                 ring->wptr = 0;
 495
 496                 /* before programing wptr to a less value, need set minor_ptr_update first */
 497                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
 498
 499                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 500                         WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 501                         WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 502                 }
 503
 504                 doorbell = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));
 505                 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));
 506
 507                 if (ring->use_doorbell) {
 508                         doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
 509                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,
 510                                         OFFSET, ring->doorbell_index);
 511                 } else {
 512                         doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);
 513                 }
 514                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);
 515                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
 516
 517                 if (i == 0)
 518                         adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 519                                                       ring->doorbell_index,
 520                                                       adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);
 521
 522                 if (amdgpu_sriov_vf(adev))
 523                         sdma_v7_0_ring_set_wptr(ring);
 524
 525                 /* set minor_ptr_update to 0 after wptr programed */
 526                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);
 527
 528                 /* Set up sdma hang watchdog */
 529                 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));
 530                 /* 100ms per unit */
 531                 tmp = REG_SET_FIELD(tmp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT,
 532                                     max(adev->usec_timeout/100000, 1));
 533                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), tmp);
 534
 535                 /* Set up RESP_MODE to non-copy addresses */
 536                 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
 537                 tmp = REG_SET_FIELD(tmp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 538                 tmp = REG_SET_FIELD(tmp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 539                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), tmp);
 540
 541                 /* program default cache read and write policy */
 542                 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));
 543                 /* clean read policy and write policy bits */
 544                 tmp &= 0xFF0FFF;
 545                 tmp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 546                          (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
 547                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), tmp);
 548
 549                 if (!amdgpu_sriov_vf(adev)) {
 550                         /* unhalt engine */
 551                         tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));
 552                         tmp = REG_SET_FIELD(tmp, SDMA0_MCU_CNTL, HALT, 0);
 553                         tmp = REG_SET_FIELD(tmp, SDMA0_MCU_CNTL, RESET, 0);
 554                         WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), tmp);
 555                 }
 556
 557                 /* enable DMA RB */
 558                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);
 559                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
 560
 561                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
 562                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);
 563 #ifdef __BIG_ENDIAN
 564                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);
 565 #endif
 566                 /* enable DMA IBs */
 567                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
 568
 569                 ring->sched.ready = true;
 570
 571                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 572                         sdma_v7_0_ctx_switch_enable(adev, true);
 573                         sdma_v7_0_enable(adev, true);
 574                 }
 575
 576                 r = amdgpu_ring_test_helper(ring);
 577                 if (r) {
 578                         ring->sched.ready = false;
 579                         return r;
 580                 }
 581
 582         }
 583
 584         return 0;
 585 }
 586
 587 /**
 588  * sdma_v7_0_rlc_resume - setup and start the async dma engines
 589  *
 590  * @adev: amdgpu_device pointer
 591  *
 592  * Set up the compute DMA queues and enable them.
 593  * Returns 0 for success, error for failure.
 594  */
 595 static int sdma_v7_0_rlc_resume(struct amdgpu_device *adev)
 596 {
 597         return 0;
 598 }
 599
 600 static void sdma_v12_0_free_ucode_buffer(struct amdgpu_device *adev)
 601 {
 602         int i;
 603
 604         for (i = 0; i < adev->sdma.num_instances; i++) {
 605                 amdgpu_bo_free_kernel(&adev->sdma.instance[i].sdma_fw_obj,
 606                                       &adev->sdma.instance[i].sdma_fw_gpu_addr,
 607                                       (void **)&adev->sdma.instance[i].sdma_fw_ptr);
 608         }
 609 }
 610
 611 /**
 612  * sdma_v7_0_load_microcode - load the sDMA ME ucode
 613  *
 614  * @adev: amdgpu_device pointer
 615  *
 616  * Loads the sDMA0/1 ucode.
 617  * Returns 0 for success, -EINVAL if the ucode is not available.
 618  */
 619 static int sdma_v7_0_load_microcode(struct amdgpu_device *adev)
 620 {
 621         const struct sdma_firmware_header_v3_0 *hdr;
 622         const __le32 *fw_data;
 623         u32 fw_size;
 624         uint32_t tmp, sdma_status, ic_op_cntl;
 625         int i, r, j;
 626
 627         /* halt the MEs */
 628         sdma_v7_0_enable(adev, false);
 629
 630         if (!adev->sdma.instance[0].fw)
 631                 return -EINVAL;
 632
 633         hdr = (const struct sdma_firmware_header_v3_0 *)
 634                 adev->sdma.instance[0].fw->data;
 635         amdgpu_ucode_print_sdma_hdr(&hdr->header);
 636
 637         fw_data = (const __le32 *)(adev->sdma.instance[0].fw->data +
 638                         le32_to_cpu(hdr->ucode_offset_bytes));
 639         fw_size = le32_to_cpu(hdr->ucode_size_bytes);
 640
 641         for (i = 0; i < adev->sdma.num_instances; i++) {
 642                 r = amdgpu_bo_create_reserved(adev, fw_size,
 643                                               PAGE_SIZE,
 644                                               AMDGPU_GEM_DOMAIN_VRAM,
 645                                               &adev->sdma.instance[i].sdma_fw_obj,
 646                                               &adev->sdma.instance[i].sdma_fw_gpu_addr,
 647                                               (void **)&adev->sdma.instance[i].sdma_fw_ptr);
 648                 if (r) {
 649                         dev_err(adev->dev, "(%d) failed to create sdma ucode bo\n", r);
 650                         return r;
 651                 }
 652
 653                 memcpy(adev->sdma.instance[i].sdma_fw_ptr, fw_data, fw_size);
 654
 655                 amdgpu_bo_kunmap(adev->sdma.instance[i].sdma_fw_obj);
 656                 amdgpu_bo_unreserve(adev->sdma.instance[i].sdma_fw_obj);
 657
 658                 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL));
 659                 tmp = REG_SET_FIELD(tmp, SDMA0_IC_CNTL, GPA, 0);
 660                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL), tmp);
 661
 662                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_LO),
 663                         lower_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr));
 664                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_HI),
 665                         upper_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr));
 666
 667                 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL));
 668                 tmp = REG_SET_FIELD(tmp, SDMA0_IC_OP_CNTL, PRIME_ICACHE, 1);
 669                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL), tmp);
 670
 671                 /* Wait for sdma ucode init complete */
 672                 for (j = 0; j < adev->usec_timeout; j++) {
 673                         ic_op_cntl = RREG32_SOC15_IP(GC,
 674                                         sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL));
 675                         sdma_status = RREG32_SOC15_IP(GC,
 676                                         sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
 677                         if ((REG_GET_FIELD(ic_op_cntl, SDMA0_IC_OP_CNTL, ICACHE_PRIMED) == 1) &&
 678                             (REG_GET_FIELD(sdma_status, SDMA0_STATUS_REG, UCODE_INIT_DONE) == 1))
 679                                 break;
 680                         udelay(1);
 681                 }
 682
 683                 if (j >= adev->usec_timeout) {
 684                         dev_err(adev->dev, "failed to init sdma ucode\n");
 685                         return -EINVAL;
 686                 }
 687         }
 688
 689         return 0;
 690 }
 691
 692 static int sdma_v7_0_soft_reset(void *handle)
 693 {
 694         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 695         u32 tmp;
 696         int i;
 697
 698         sdma_v7_0_gfx_stop(adev);
 699
 700         for (i = 0; i < adev->sdma.num_instances; i++) {
 701                 //tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_FREEZE));
 702                 //tmp |= SDMA0_FREEZE__FREEZE_MASK;
 703                 //WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);
 704                 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));
 705                 tmp |= SDMA0_MCU_CNTL__HALT_MASK;
 706                 tmp |= SDMA0_MCU_CNTL__RESET_MASK;
 707                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), tmp);
 708
 709                 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);
 710
 711                 udelay(100);
 712
 713                 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i;
 714                 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
 715                 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
 716
 717                 udelay(100);
 718
 719                 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0);
 720                 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
 721
 722                 udelay(100);
 723         }
 724
 725         return sdma_v7_0_start(adev);
 726 }
 727
 728 static bool sdma_v7_0_check_soft_reset(void *handle)
 729 {
 730         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 731         struct amdgpu_ring *ring;
 732         int i, r;
 733         long tmo = msecs_to_jiffies(1000);
 734
 735         for (i = 0; i < adev->sdma.num_instances; i++) {
 736                 ring = &adev->sdma.instance[i].ring;
 737                 r = amdgpu_ring_test_ib(ring, tmo);
 738                 if (r)
 739                         return true;
 740         }
 741
 742         return false;
 743 }
 744
 745 /**
 746  * sdma_v7_0_start - setup and start the async dma engines
 747  *
 748  * @adev: amdgpu_device pointer
 749  *
 750  * Set up the DMA engines and enable them.
 751  * Returns 0 for success, error for failure.
 752  */
 753 static int sdma_v7_0_start(struct amdgpu_device *adev)
 754 {
 755         int r = 0;
 756
 757         if (amdgpu_sriov_vf(adev)) {
 758                 sdma_v7_0_ctx_switch_enable(adev, false);
 759                 sdma_v7_0_enable(adev, false);
 760
 761                 /* set RB registers */
 762                 r = sdma_v7_0_gfx_resume(adev);
 763                 return r;
 764         }
 765
 766         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 767                 r = sdma_v7_0_load_microcode(adev);
 768                 if (r) {
 769                         sdma_v12_0_free_ucode_buffer(adev);
 770                         return r;
 771                 }
 772
 773                 if (amdgpu_emu_mode == 1)
 774                         msleep(1000);
 775         }
 776
 777         /* unhalt the MEs */
 778         sdma_v7_0_enable(adev, true);
 779         /* enable sdma ring preemption */
 780         sdma_v7_0_ctx_switch_enable(adev, true);
 781
 782         /* start the gfx rings and rlc compute queues */
 783         r = sdma_v7_0_gfx_resume(adev);
 784         if (r)
 785                 return r;
 786         r = sdma_v7_0_rlc_resume(adev);
 787
 788         return r;
 789 }
 790
 791 static int sdma_v7_0_mqd_init(struct amdgpu_device *adev, void *mqd,
 792                               struct amdgpu_mqd_prop *prop)
 793 {
 794         struct v12_sdma_mqd *m = mqd;
 795         uint64_t wb_gpu_addr;
 796
 797         m->sdmax_rlcx_rb_cntl =
 798                 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
 799                 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
 800                 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
 801                 1 << SDMA0_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT;
 802
 803         m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
 804         m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
 805
 806         wb_gpu_addr = prop->wptr_gpu_addr;
 807         m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
 808         m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
 809
 810         wb_gpu_addr = prop->rptr_gpu_addr;
 811         m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
 812         m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
 813
 814         m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 0,
 815                                                         regSDMA0_QUEUE0_IB_CNTL));
 816
 817         m->sdmax_rlcx_doorbell_offset =
 818                 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
 819
 820         m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
 821
 822         m->sdmax_rlcx_doorbell_log = 0;
 823         m->sdmax_rlcx_rb_aql_cntl = 0x4000;     //regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT;
 824         m->sdmax_rlcx_dummy_reg = 0xf;  //regSDMA0_QUEUE0_DUMMY_REG_DEFAULT;
 825
 826         return 0;
 827 }
 828
 829 static void sdma_v7_0_set_mqd_funcs(struct amdgpu_device *adev)
 830 {
 831         adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v12_sdma_mqd);
 832         adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v7_0_mqd_init;
 833 }
 834
 835 /**
 836  * sdma_v7_0_ring_test_ring - simple async dma engine test
 837  *
 838  * @ring: amdgpu_ring structure holding ring information
 839  *
 840  * Test the DMA engine by writing using it to write an
 841  * value to memory.
 842  * Returns 0 for success, error for failure.
 843  */
 844 static int sdma_v7_0_ring_test_ring(struct amdgpu_ring *ring)
 845 {
 846         struct amdgpu_device *adev = ring->adev;
 847         unsigned i;
 848         unsigned index;
 849         int r;
 850         u32 tmp;
 851         u64 gpu_addr;
 852         volatile uint32_t *cpu_ptr = NULL;
 853
 854         tmp = 0xCAFEDEAD;
 855
 856         if (ring->is_mes_queue) {
 857                 uint32_t offset = 0;
 858                 offset = amdgpu_mes_ctx_get_offs(ring,
 859                                          AMDGPU_MES_CTX_PADDING_OFFS);
 860                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 861                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 862                 *cpu_ptr = tmp;
 863         } else {
 864                 r = amdgpu_device_wb_get(adev, &index);
 865                 if (r) {
 866                         dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 867                         return r;
 868                 }
 869
 870                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 871                 adev->wb.wb[index] = cpu_to_le32(tmp);
 872         }
 873
 874         r = amdgpu_ring_alloc(ring, 5);
 875         if (r) {
 876                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 877                 if (!ring->is_mes_queue)
 878                         amdgpu_device_wb_free(adev, index);
 879                 return r;
 880         }
 881
 882         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
 883                           SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 884         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 885         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 886         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 887         amdgpu_ring_write(ring, 0xDEADBEEF);
 888         amdgpu_ring_commit(ring);
 889
 890         for (i = 0; i < adev->usec_timeout; i++) {
 891                 if (ring->is_mes_queue)
 892                         tmp = le32_to_cpu(*cpu_ptr);
 893                 else
 894                         tmp = le32_to_cpu(adev->wb.wb[index]);
 895                 if (tmp == 0xDEADBEEF)
 896                         break;
 897                 if (amdgpu_emu_mode == 1)
 898                         msleep(1);
 899                 else
 900                         udelay(1);
 901         }
 902
 903         if (i >= adev->usec_timeout)
 904                 r = -ETIMEDOUT;
 905
 906         if (!ring->is_mes_queue)
 907                 amdgpu_device_wb_free(adev, index);
 908
 909         return r;
 910 }
 911
 912 /**
 913  * sdma_v7_0_ring_test_ib - test an IB on the DMA engine
 914  *
 915  * @ring: amdgpu_ring structure holding ring information
 916  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 917  *
 918  * Test a simple IB in the DMA ring.
 919  * Returns 0 on success, error on failure.
 920  */
 921 static int sdma_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 922 {
 923         struct amdgpu_device *adev = ring->adev;
 924         struct amdgpu_ib ib;
 925         struct dma_fence *f = NULL;
 926         unsigned index;
 927         long r;
 928         u32 tmp = 0;
 929         u64 gpu_addr;
 930         volatile uint32_t *cpu_ptr = NULL;
 931
 932         tmp = 0xCAFEDEAD;
 933         memset(&ib, 0, sizeof(ib));
 934
 935         if (ring->is_mes_queue) {
 936                 uint32_t offset = 0;
 937                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
 938                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 939                 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 940
 941                 offset = amdgpu_mes_ctx_get_offs(ring,
 942                                          AMDGPU_MES_CTX_PADDING_OFFS);
 943                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 944                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 945                 *cpu_ptr = tmp;
 946         } else {
 947                 r = amdgpu_device_wb_get(adev, &index);
 948                 if (r) {
 949                         dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 950                         return r;
 951                 }
 952
 953                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 954                 adev->wb.wb[index] = cpu_to_le32(tmp);
 955
 956                 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
 957                 if (r) {
 958                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 959                         goto err0;
 960                 }
 961         }
 962
 963         ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
 964                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 965         ib.ptr[1] = lower_32_bits(gpu_addr);
 966         ib.ptr[2] = upper_32_bits(gpu_addr);
 967         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 968         ib.ptr[4] = 0xDEADBEEF;
 969         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 970         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 971         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 972         ib.length_dw = 8;
 973
 974         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 975         if (r)
 976                 goto err1;
 977
 978         r = dma_fence_wait_timeout(f, false, timeout);
 979         if (r == 0) {
 980                 DRM_ERROR("amdgpu: IB test timed out\n");
 981                 r = -ETIMEDOUT;
 982                 goto err1;
 983         } else if (r < 0) {
 984                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 985                 goto err1;
 986         }
 987
 988         if (ring->is_mes_queue)
 989                 tmp = le32_to_cpu(*cpu_ptr);
 990         else
 991                 tmp = le32_to_cpu(adev->wb.wb[index]);
 992
 993         if (tmp == 0xDEADBEEF)
 994                 r = 0;
 995         else
 996                 r = -EINVAL;
 997
 998 err1:
 999         amdgpu_ib_free(adev, &ib, NULL);
1000         dma_fence_put(f);
1001 err0:
1002         if (!ring->is_mes_queue)
1003                 amdgpu_device_wb_free(adev, index);
1004         return r;
1005 }
1006
1007
1008 /**
1009  * sdma_v7_0_vm_copy_pte - update PTEs by copying them from the GART
1010  *
1011  * @ib: indirect buffer to fill with commands
1012  * @pe: addr of the page entry
1013  * @src: src addr to copy from
1014  * @count: number of page entries to update
1015  *
1016  * Update PTEs by copying them from the GART using sDMA.
1017  */
1018 static void sdma_v7_0_vm_copy_pte(struct amdgpu_ib *ib,
1019                                   uint64_t pe, uint64_t src,
1020                                   unsigned count)
1021 {
1022         unsigned bytes = count * 8;
1023
1024         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1025                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1026         ib->ptr[ib->length_dw++] = bytes - 1;
1027         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1028         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1029         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1030         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1031         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1032
1033 }
1034
1035 /**
1036  * sdma_v7_0_vm_write_pte - update PTEs by writing them manually
1037  *
1038  * @ib: indirect buffer to fill with commands
1039  * @pe: addr of the page entry
1040  * @value: dst addr to write into pe
1041  * @count: number of page entries to update
1042  * @incr: increase next addr by incr bytes
1043  *
1044  * Update PTEs by writing them manually using sDMA.
1045  */
1046 static void sdma_v7_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1047                                    uint64_t value, unsigned count,
1048                                    uint32_t incr)
1049 {
1050         unsigned ndw = count * 2;
1051
1052         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1053                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1054         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1055         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1056         ib->ptr[ib->length_dw++] = ndw - 1;
1057         for (; ndw > 0; ndw -= 2) {
1058                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1059                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1060                 value += incr;
1061         }
1062 }
1063
1064 /**
1065  * sdma_v7_0_vm_set_pte_pde - update the page tables using sDMA
1066  *
1067  * @ib: indirect buffer to fill with commands
1068  * @pe: addr of the page entry
1069  * @addr: dst addr to write into pe
1070  * @count: number of page entries to update
1071  * @incr: increase next addr by incr bytes
1072  * @flags: access flags
1073  *
1074  * Update the page tables using sDMA.
1075  */
1076 static void sdma_v7_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1077                                      uint64_t pe,
1078                                      uint64_t addr, unsigned count,
1079                                      uint32_t incr, uint64_t flags)
1080 {
1081         /* for physically contiguous pages (vram) */
1082         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE);
1083         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1084         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1085         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1086         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1087         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1088         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1089         ib->ptr[ib->length_dw++] = incr; /* increment size */
1090         ib->ptr[ib->length_dw++] = 0;
1091         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1092 }
1093
1094 /**
1095  * sdma_v7_0_ring_pad_ib - pad the IB
1096  *
1097  * @ring: amdgpu ring pointer
1098  * @ib: indirect buffer to fill with padding
1099  *
1100  * Pad the IB with NOPs to a boundary multiple of 8.
1101  */
1102 static void sdma_v7_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1103 {
1104         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1105         u32 pad_count;
1106         int i;
1107
1108         pad_count = (-ib->length_dw) & 0x7;
1109         for (i = 0; i < pad_count; i++)
1110                 if (sdma && sdma->burst_nop && (i == 0))
1111                         ib->ptr[ib->length_dw++] =
1112                                 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) |
1113                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1114                 else
1115                         ib->ptr[ib->length_dw++] =
1116                                 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP);
1117 }
1118
1119 /**
1120  * sdma_v7_0_ring_emit_pipeline_sync - sync the pipeline
1121  *
1122  * @ring: amdgpu_ring pointer
1123  *
1124  * Make sure all previous operations are completed (CIK).
1125  */
1126 static void sdma_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1127 {
1128         uint32_t seq = ring->fence_drv.sync_seq;
1129         uint64_t addr = ring->fence_drv.gpu_addr;
1130
1131         /* wait for idle */
1132         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1133                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1134                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1135                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1136         amdgpu_ring_write(ring, addr & 0xfffffffc);
1137         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1138         amdgpu_ring_write(ring, seq); /* reference */
1139         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1140         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1141                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1142 }
1143
1144 /**
1145  * sdma_v7_0_ring_emit_vm_flush - vm flush using sDMA
1146  *
1147  * @ring: amdgpu_ring pointer
1148  * @vmid: vmid number to use
1149  * @pd_addr: address
1150  *
1151  * Update the page table base and flush the VM TLB
1152  * using sDMA.
1153  */
1154 static void sdma_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1155                                          unsigned vmid, uint64_t pd_addr)
1156 {
1157         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1158 }
1159
1160 static void sdma_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
1161                                      uint32_t reg, uint32_t val)
1162 {
1163         /* SRBM WRITE command will not support on sdma v7.
1164          * Use Register WRITE command instead, which OPCODE is same as SRBM WRITE
1165          */
1166         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE));
1167         amdgpu_ring_write(ring, reg << 2);
1168         amdgpu_ring_write(ring, val);
1169 }
1170
1171 static void sdma_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1172                                          uint32_t val, uint32_t mask)
1173 {
1174         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1175                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1176                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1177         amdgpu_ring_write(ring, reg << 2);
1178         amdgpu_ring_write(ring, 0);
1179         amdgpu_ring_write(ring, val); /* reference */
1180         amdgpu_ring_write(ring, mask); /* mask */
1181         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1182                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1183 }
1184
1185 static void sdma_v7_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1186                                                    uint32_t reg0, uint32_t reg1,
1187                                                    uint32_t ref, uint32_t mask)
1188 {
1189         amdgpu_ring_emit_wreg(ring, reg0, ref);
1190         /* wait for a cycle to reset vm_inv_eng*_ack */
1191         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1192         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1193 }
1194
1195 static int sdma_v7_0_early_init(void *handle)
1196 {
1197         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1198         int r;
1199
1200         r = amdgpu_sdma_init_microcode(adev, 0, true);
1201         if (r) {
1202                 DRM_ERROR("Failed to init sdma firmware!\n");
1203                 return r;
1204         }
1205
1206         sdma_v7_0_set_ring_funcs(adev);
1207         sdma_v7_0_set_buffer_funcs(adev);
1208         sdma_v7_0_set_vm_pte_funcs(adev);
1209         sdma_v7_0_set_irq_funcs(adev);
1210         sdma_v7_0_set_mqd_funcs(adev);
1211
1212         return 0;
1213 }
1214
1215 static int sdma_v7_0_sw_init(void *handle)
1216 {
1217         struct amdgpu_ring *ring;
1218         int r, i;
1219         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1220
1221         /* SDMA trap event */
1222         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1223                               GFX_11_0_0__SRCID__SDMA_TRAP,
1224                               &adev->sdma.trap_irq);
1225         if (r)
1226                 return r;
1227
1228         for (i = 0; i < adev->sdma.num_instances; i++) {
1229                 ring = &adev->sdma.instance[i].ring;
1230                 ring->ring_obj = NULL;
1231                 ring->use_doorbell = true;
1232                 ring->me = i;
1233
1234                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1235                                 ring->use_doorbell?"true":"false");
1236
1237                 ring->doorbell_index =
1238                         (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset
1239
1240                 ring->vm_hub = AMDGPU_GFXHUB(0);
1241                 sprintf(ring->name, "sdma%d", i);
1242                 r = amdgpu_ring_init(adev, ring, 1024,
1243                                      &adev->sdma.trap_irq,
1244                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1245                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1246                 if (r)
1247                         return r;
1248         }
1249
1250         return r;
1251 }
1252
1253 static int sdma_v7_0_sw_fini(void *handle)
1254 {
1255         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1256         int i;
1257
1258         for (i = 0; i < adev->sdma.num_instances; i++)
1259                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1260
1261         amdgpu_sdma_destroy_inst_ctx(adev, true);
1262
1263         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)
1264                 sdma_v12_0_free_ucode_buffer(adev);
1265
1266         return 0;
1267 }
1268
1269 static int sdma_v7_0_hw_init(void *handle)
1270 {
1271         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1272
1273         return sdma_v7_0_start(adev);
1274 }
1275
1276 static int sdma_v7_0_hw_fini(void *handle)
1277 {
1278         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279
1280         if (amdgpu_sriov_vf(adev))
1281                 return 0;
1282
1283         sdma_v7_0_ctx_switch_enable(adev, false);
1284         sdma_v7_0_enable(adev, false);
1285
1286         return 0;
1287 }
1288
1289 static int sdma_v7_0_suspend(void *handle)
1290 {
1291         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1292
1293         return sdma_v7_0_hw_fini(adev);
1294 }
1295
1296 static int sdma_v7_0_resume(void *handle)
1297 {
1298         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1299
1300         return sdma_v7_0_hw_init(adev);
1301 }
1302
1303 static bool sdma_v7_0_is_idle(void *handle)
1304 {
1305         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1306         u32 i;
1307
1308         for (i = 0; i < adev->sdma.num_instances; i++) {
1309                 u32 tmp = RREG32(sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
1310
1311                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1312                         return false;
1313         }
1314
1315         return true;
1316 }
1317
1318 static int sdma_v7_0_wait_for_idle(void *handle)
1319 {
1320         unsigned i;
1321         u32 sdma0, sdma1;
1322         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1323
1324         for (i = 0; i < adev->usec_timeout; i++) {
1325                 sdma0 = RREG32(sdma_v7_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));
1326                 sdma1 = RREG32(sdma_v7_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));
1327
1328                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1329                         return 0;
1330                 udelay(1);
1331         }
1332         return -ETIMEDOUT;
1333 }
1334
1335 static int sdma_v7_0_ring_preempt_ib(struct amdgpu_ring *ring)
1336 {
1337         int i, r = 0;
1338         struct amdgpu_device *adev = ring->adev;
1339         u32 index = 0;
1340         u64 sdma_gfx_preempt;
1341
1342         amdgpu_sdma_get_index_from_ring(ring, &index);
1343         sdma_gfx_preempt =
1344                 sdma_v7_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);
1345
1346         /* assert preemption condition */
1347         amdgpu_ring_set_preempt_cond_exec(ring, false);
1348
1349         /* emit the trailing fence */
1350         ring->trail_seq += 1;
1351         r = amdgpu_ring_alloc(ring, 10);
1352         if (r) {
1353                 DRM_ERROR("ring %d failed to be allocated \n", ring->idx);
1354                 return r;
1355         }
1356         sdma_v7_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1357                                   ring->trail_seq, 0);
1358         amdgpu_ring_commit(ring);
1359
1360         /* assert IB preemption */
1361         WREG32(sdma_gfx_preempt, 1);
1362
1363         /* poll the trailing fence */
1364         for (i = 0; i < adev->usec_timeout; i++) {
1365                 if (ring->trail_seq ==
1366                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1367                         break;
1368                 udelay(1);
1369         }
1370
1371         if (i >= adev->usec_timeout) {
1372                 r = -EINVAL;
1373                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1374         }
1375
1376         /* deassert IB preemption */
1377         WREG32(sdma_gfx_preempt, 0);
1378
1379         /* deassert the preemption condition */
1380         amdgpu_ring_set_preempt_cond_exec(ring, true);
1381         return r;
1382 }
1383
1384 static int sdma_v7_0_set_trap_irq_state(struct amdgpu_device *adev,
1385                                         struct amdgpu_irq_src *source,
1386                                         unsigned type,
1387                                         enum amdgpu_interrupt_state state)
1388 {
1389         u32 sdma_cntl;
1390
1391         u32 reg_offset = sdma_v7_0_get_reg_offset(adev, type, regSDMA0_CNTL);
1392
1393         sdma_cntl = RREG32(reg_offset);
1394         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1395                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1396         WREG32(reg_offset, sdma_cntl);
1397
1398         return 0;
1399 }
1400
1401 static int sdma_v7_0_process_trap_irq(struct amdgpu_device *adev,
1402                                       struct amdgpu_irq_src *source,
1403                                       struct amdgpu_iv_entry *entry)
1404 {
1405         int instances, queue;
1406         uint32_t mes_queue_id = entry->src_data[0];
1407
1408         DRM_DEBUG("IH: SDMA trap\n");
1409
1410         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1411                 struct amdgpu_mes_queue *queue;
1412
1413                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1414
1415                 spin_lock(&adev->mes.queue_id_lock);
1416                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1417                 if (queue) {
1418                         DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1419                         amdgpu_fence_process(queue->ring);
1420                 }
1421                 spin_unlock(&adev->mes.queue_id_lock);
1422                 return 0;
1423         }
1424
1425         queue = entry->ring_id & 0xf;
1426         instances = (entry->ring_id & 0xf0) >> 4;
1427         if (instances > 1) {
1428                 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n");
1429                 return -EINVAL;
1430         }
1431
1432         switch (entry->client_id) {
1433         case SOC21_IH_CLIENTID_GFX:
1434                 switch (queue) {
1435                 case 0:
1436                         amdgpu_fence_process(&adev->sdma.instance[instances].ring);
1437                         break;
1438                 default:
1439                         break;
1440                 }
1441                 break;
1442         }
1443         return 0;
1444 }
1445
1446 static int sdma_v7_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1447                                               struct amdgpu_irq_src *source,
1448                                               struct amdgpu_iv_entry *entry)
1449 {
1450         return 0;
1451 }
1452
1453 static int sdma_v7_0_set_clockgating_state(void *handle,
1454                                            enum amd_clockgating_state state)
1455 {
1456         return 0;
1457 }
1458
1459 static int sdma_v7_0_set_powergating_state(void *handle,
1460                                           enum amd_powergating_state state)
1461 {
1462         return 0;
1463 }
1464
1465 static void sdma_v7_0_get_clockgating_state(void *handle, u64 *flags)
1466 {
1467 }
1468
1469 const struct amd_ip_funcs sdma_v7_0_ip_funcs = {
1470         .name = "sdma_v7_0",
1471         .early_init = sdma_v7_0_early_init,
1472         .late_init = NULL,
1473         .sw_init = sdma_v7_0_sw_init,
1474         .sw_fini = sdma_v7_0_sw_fini,
1475         .hw_init = sdma_v7_0_hw_init,
1476         .hw_fini = sdma_v7_0_hw_fini,
1477         .suspend = sdma_v7_0_suspend,
1478         .resume = sdma_v7_0_resume,
1479         .is_idle = sdma_v7_0_is_idle,
1480         .wait_for_idle = sdma_v7_0_wait_for_idle,
1481         .soft_reset = sdma_v7_0_soft_reset,
1482         .check_soft_reset = sdma_v7_0_check_soft_reset,
1483         .set_clockgating_state = sdma_v7_0_set_clockgating_state,
1484         .set_powergating_state = sdma_v7_0_set_powergating_state,
1485         .get_clockgating_state = sdma_v7_0_get_clockgating_state,
1486 };
1487
1488 static const struct amdgpu_ring_funcs sdma_v7_0_ring_funcs = {
1489         .type = AMDGPU_RING_TYPE_SDMA,
1490         .align_mask = 0xf,
1491         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1492         .support_64bit_ptrs = true,
1493         .secure_submission_supported = true,
1494         .get_rptr = sdma_v7_0_ring_get_rptr,
1495         .get_wptr = sdma_v7_0_ring_get_wptr,
1496         .set_wptr = sdma_v7_0_ring_set_wptr,
1497         .emit_frame_size =
1498                 5 + /* sdma_v7_0_ring_init_cond_exec */
1499                 6 + /* sdma_v7_0_ring_emit_hdp_flush */
1500                 6 + /* sdma_v7_0_ring_emit_pipeline_sync */
1501                 /* sdma_v7_0_ring_emit_vm_flush */
1502                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1503                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1504                 10 + 10 + 10, /* sdma_v7_0_ring_emit_fence x3 for user fence, vm fence */
1505         .emit_ib_size = 5 + 7 + 6, /* sdma_v7_0_ring_emit_ib */
1506         .emit_ib = sdma_v7_0_ring_emit_ib,
1507         .emit_mem_sync = sdma_v7_0_ring_emit_mem_sync,
1508         .emit_fence = sdma_v7_0_ring_emit_fence,
1509         .emit_pipeline_sync = sdma_v7_0_ring_emit_pipeline_sync,
1510         .emit_vm_flush = sdma_v7_0_ring_emit_vm_flush,
1511         .emit_hdp_flush = sdma_v7_0_ring_emit_hdp_flush,
1512         .test_ring = sdma_v7_0_ring_test_ring,
1513         .test_ib = sdma_v7_0_ring_test_ib,
1514         .insert_nop = sdma_v7_0_ring_insert_nop,
1515         .pad_ib = sdma_v7_0_ring_pad_ib,
1516         .emit_wreg = sdma_v7_0_ring_emit_wreg,
1517         .emit_reg_wait = sdma_v7_0_ring_emit_reg_wait,
1518         .emit_reg_write_reg_wait = sdma_v7_0_ring_emit_reg_write_reg_wait,
1519         .init_cond_exec = sdma_v7_0_ring_init_cond_exec,
1520         .preempt_ib = sdma_v7_0_ring_preempt_ib,
1521 };
1522
1523 static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev)
1524 {
1525         int i;
1526
1527         for (i = 0; i < adev->sdma.num_instances; i++) {
1528                 adev->sdma.instance[i].ring.funcs = &sdma_v7_0_ring_funcs;
1529                 adev->sdma.instance[i].ring.me = i;
1530         }
1531 }
1532
1533 static const struct amdgpu_irq_src_funcs sdma_v7_0_trap_irq_funcs = {
1534         .set = sdma_v7_0_set_trap_irq_state,
1535         .process = sdma_v7_0_process_trap_irq,
1536 };
1537
1538 static const struct amdgpu_irq_src_funcs sdma_v7_0_illegal_inst_irq_funcs = {
1539         .process = sdma_v7_0_process_illegal_inst_irq,
1540 };
1541
1542 static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1543 {
1544         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1545                                         adev->sdma.num_instances;
1546         adev->sdma.trap_irq.funcs = &sdma_v7_0_trap_irq_funcs;
1547         adev->sdma.illegal_inst_irq.funcs = &sdma_v7_0_illegal_inst_irq_funcs;
1548 }
1549
1550 /**
1551  * sdma_v7_0_emit_copy_buffer - copy buffer using the sDMA engine
1552  *
1553  * @ib: indirect buffer to fill with commands
1554  * @src_offset: src GPU address
1555  * @dst_offset: dst GPU address
1556  * @byte_count: number of bytes to xfer
1557  * @copy_flags: copy flags for the buffers
1558  *
1559  * Copy GPU buffers using the DMA engine.
1560  * Used by the amdgpu ttm implementation to move pages if
1561  * registered as the asic copy callback.
1562  */
1563 static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib,
1564                                        uint64_t src_offset,
1565                                        uint64_t dst_offset,
1566                                        uint32_t byte_count,
1567                                        uint32_t copy_flags)
1568 {
1569         uint32_t num_type, data_format, max_com;
1570
1571         max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED);
1572         data_format = AMDGPU_COPY_FLAGS_GET(copy_flags, DATA_FORMAT);
1573         num_type = AMDGPU_COPY_FLAGS_GET(copy_flags, NUMBER_TYPE);
1574
1575         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1576                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1577                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0) |
1578                 SDMA_PKT_COPY_LINEAR_HEADER_CPV((copy_flags &
1579                         (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)) ? 1 : 0);
1580
1581         ib->ptr[ib->length_dw++] = byte_count - 1;
1582         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1583         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1584         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1585         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1586         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1587
1588         if ((copy_flags & (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)))
1589                 ib->ptr[ib->length_dw++] = SDMA_DCC_DATA_FORMAT(data_format) | SDMA_DCC_NUM_TYPE(num_type) |
1590                         ((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) |
1591                         ((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(1) : 0) |
1592                         SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1);
1593 }
1594
1595 /**
1596  * sdma_v7_0_emit_fill_buffer - fill buffer using the sDMA engine
1597  *
1598  * @ib: indirect buffer to fill
1599  * @src_data: value to write to buffer
1600  * @dst_offset: dst GPU address
1601  * @byte_count: number of bytes to xfer
1602  *
1603  * Fill GPU buffers using the DMA engine.
1604  */
1605 static void sdma_v7_0_emit_fill_buffer(struct amdgpu_ib *ib,
1606                                        uint32_t src_data,
1607                                        uint64_t dst_offset,
1608                                        uint32_t byte_count)
1609 {
1610         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL);
1611         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1612         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1613         ib->ptr[ib->length_dw++] = src_data;
1614         ib->ptr[ib->length_dw++] = byte_count - 1;
1615 }
1616
1617 static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = {
1618         .copy_max_bytes = 0x400000,
1619         .copy_num_dw = 7,
1620         .emit_copy_buffer = sdma_v7_0_emit_copy_buffer,
1621         .fill_max_bytes = 0x400000,
1622         .fill_num_dw = 5,
1623         .emit_fill_buffer = sdma_v7_0_emit_fill_buffer,
1624 };
1625
1626 static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev)
1627 {
1628         adev->mman.buffer_funcs = &sdma_v7_0_buffer_funcs;
1629         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1630 }
1631
1632 static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = {
1633         .copy_pte_num_dw = 7,
1634         .copy_pte = sdma_v7_0_vm_copy_pte,
1635         .write_pte = sdma_v7_0_vm_write_pte,
1636         .set_pte_pde = sdma_v7_0_vm_set_pte_pde,
1637 };
1638
1639 static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1640 {
1641         unsigned i;
1642
1643         adev->vm_manager.vm_pte_funcs = &sdma_v7_0_vm_pte_funcs;
1644         for (i = 0; i < adev->sdma.num_instances; i++) {
1645                 adev->vm_manager.vm_pte_scheds[i] =
1646                         &adev->sdma.instance[i].ring.sched;
1647         }
1648         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1649 }
1650
1651 const struct amdgpu_ip_block_version sdma_v7_0_ip_block = {
1652         .type = AMD_IP_BLOCK_TYPE_SDMA,
1653         .major = 7,
1654         .minor = 0,
1655         .rev = 0,
1656         .funcs = &sdma_v7_0_ip_funcs,
1657 };