drivers/gpu/drm/amd/amdgpu/dce_virtual.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "atom.h"
  28 #include "amdgpu_pll.h"
  29 #include "amdgpu_connectors.h"
  30 #ifdef CONFIG_DRM_AMDGPU_SI
  31 #include "dce_v6_0.h"
  32 #endif
  33 #ifdef CONFIG_DRM_AMDGPU_CIK
  34 #include "dce_v8_0.h"
  35 #endif
  36 #include "dce_v10_0.h"
  37 #include "dce_v11_0.h"
  38 #include "dce_virtual.h"
  39
  40 #define DCE_VIRTUAL_VBLANK_PERIOD 16666666
  41
  42
  43 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev);
  44 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
  45 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
  46                                               int index);
  47 static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
  48                                                         int crtc,
  49                                                         enum amdgpu_interrupt_state state);
  50
  51 static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)
  52 {
  53         return 0;
  54 }
  55
  56 static void dce_virtual_page_flip(struct amdgpu_device *adev,
  57                               int crtc_id, u64 crtc_base, bool async)
  58 {
  59         return;
  60 }
  61
  62 static int dce_virtual_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
  63                                         u32 *vbl, u32 *position)
  64 {
  65         *vbl = 0;
  66         *position = 0;
  67
  68         return -EINVAL;
  69 }
  70
  71 static bool dce_virtual_hpd_sense(struct amdgpu_device *adev,
  72                                enum amdgpu_hpd_id hpd)
  73 {
  74         return true;
  75 }
  76
  77 static void dce_virtual_hpd_set_polarity(struct amdgpu_device *adev,
  78                                       enum amdgpu_hpd_id hpd)
  79 {
  80         return;
  81 }
  82
  83 static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)
  84 {
  85         return 0;
  86 }
  87
  88 /**
  89  * dce_virtual_bandwidth_update - program display watermarks
  90  *
  91  * @adev: amdgpu_device pointer
  92  *
  93  * Calculate and program the display watermarks and line
  94  * buffer allocation (CIK).
  95  */
  96 static void dce_virtual_bandwidth_update(struct amdgpu_device *adev)
  97 {
  98         return;
  99 }
 100
 101 static int dce_virtual_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
 102                                       u16 *green, u16 *blue, uint32_t size,
 103                                       struct drm_modeset_acquire_ctx *ctx)
 104 {
 105         return 0;
 106 }
 107
 108 static void dce_virtual_crtc_destroy(struct drm_crtc *crtc)
 109 {
 110         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 111
 112         drm_crtc_cleanup(crtc);
 113         kfree(amdgpu_crtc);
 114 }
 115
 116 static const struct drm_crtc_funcs dce_virtual_crtc_funcs = {
 117         .cursor_set2 = NULL,
 118         .cursor_move = NULL,
 119         .gamma_set = dce_virtual_crtc_gamma_set,
 120         .set_config = amdgpu_display_crtc_set_config,
 121         .destroy = dce_virtual_crtc_destroy,
 122         .page_flip_target = amdgpu_display_crtc_page_flip_target,
 123 };
 124
 125 static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, int mode)
 126 {
 127         struct drm_device *dev = crtc->dev;
 128         struct amdgpu_device *adev = dev->dev_private;
 129         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 130         unsigned type;
 131
 132         if (amdgpu_sriov_vf(adev))
 133                 return;
 134
 135         switch (mode) {
 136         case DRM_MODE_DPMS_ON:
 137                 amdgpu_crtc->enabled = true;
 138                 /* Make sure VBLANK interrupts are still enabled */
 139                 type = amdgpu_display_crtc_idx_to_irq_type(adev,
 140                                                 amdgpu_crtc->crtc_id);
 141                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
 142                 drm_crtc_vblank_on(crtc);
 143                 break;
 144         case DRM_MODE_DPMS_STANDBY:
 145         case DRM_MODE_DPMS_SUSPEND:
 146         case DRM_MODE_DPMS_OFF:
 147                 drm_crtc_vblank_off(crtc);
 148                 amdgpu_crtc->enabled = false;
 149                 break;
 150         }
 151 }
 152
 153
 154 static void dce_virtual_crtc_prepare(struct drm_crtc *crtc)
 155 {
 156         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 157 }
 158
 159 static void dce_virtual_crtc_commit(struct drm_crtc *crtc)
 160 {
 161         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 162 }
 163
 164 static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
 165 {
 166         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 167
 168         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 169         if (crtc->primary->fb) {
 170                 int r;
 171                 struct amdgpu_bo *abo;
 172
 173                 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
 174                 r = amdgpu_bo_reserve(abo, true);
 175                 if (unlikely(r))
 176                         DRM_ERROR("failed to reserve abo before unpin\n");
 177                 else {
 178                         amdgpu_bo_unpin(abo);
 179                         amdgpu_bo_unreserve(abo);
 180                 }
 181         }
 182
 183         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
 184         amdgpu_crtc->encoder = NULL;
 185         amdgpu_crtc->connector = NULL;
 186 }
 187
 188 static int dce_virtual_crtc_mode_set(struct drm_crtc *crtc,
 189                                   struct drm_display_mode *mode,
 190                                   struct drm_display_mode *adjusted_mode,
 191                                   int x, int y, struct drm_framebuffer *old_fb)
 192 {
 193         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 194
 195         /* update the hw version fpr dpm */
 196         amdgpu_crtc->hw_mode = *adjusted_mode;
 197
 198         return 0;
 199 }
 200
 201 static bool dce_virtual_crtc_mode_fixup(struct drm_crtc *crtc,
 202                                      const struct drm_display_mode *mode,
 203                                      struct drm_display_mode *adjusted_mode)
 204 {
 205         return true;
 206 }
 207
 208
 209 static int dce_virtual_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 210                                   struct drm_framebuffer *old_fb)
 211 {
 212         return 0;
 213 }
 214
 215 static int dce_virtual_crtc_set_base_atomic(struct drm_crtc *crtc,
 216                                          struct drm_framebuffer *fb,
 217                                          int x, int y, enum mode_set_atomic state)
 218 {
 219         return 0;
 220 }
 221
 222 static const struct drm_crtc_helper_funcs dce_virtual_crtc_helper_funcs = {
 223         .dpms = dce_virtual_crtc_dpms,
 224         .mode_fixup = dce_virtual_crtc_mode_fixup,
 225         .mode_set = dce_virtual_crtc_mode_set,
 226         .mode_set_base = dce_virtual_crtc_set_base,
 227         .mode_set_base_atomic = dce_virtual_crtc_set_base_atomic,
 228         .prepare = dce_virtual_crtc_prepare,
 229         .commit = dce_virtual_crtc_commit,
 230         .disable = dce_virtual_crtc_disable,
 231 };
 232
 233 static int dce_virtual_crtc_init(struct amdgpu_device *adev, int index)
 234 {
 235         struct amdgpu_crtc *amdgpu_crtc;
 236
 237         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
 238                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 239         if (amdgpu_crtc == NULL)
 240                 return -ENOMEM;
 241
 242         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_virtual_crtc_funcs);
 243
 244         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
 245         amdgpu_crtc->crtc_id = index;
 246         adev->mode_info.crtcs[index] = amdgpu_crtc;
 247
 248         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
 249         amdgpu_crtc->encoder = NULL;
 250         amdgpu_crtc->connector = NULL;
 251         amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
 252         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs);
 253
 254         return 0;
 255 }
 256
 257 static int dce_virtual_early_init(void *handle)
 258 {
 259         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 260
 261         dce_virtual_set_display_funcs(adev);
 262         dce_virtual_set_irq_funcs(adev);
 263
 264         adev->mode_info.num_hpd = 1;
 265         adev->mode_info.num_dig = 1;
 266         return 0;
 267 }
 268
 269 static struct drm_encoder *
 270 dce_virtual_encoder(struct drm_connector *connector)
 271 {
 272         int enc_id = connector->encoder_ids[0];
 273         struct drm_encoder *encoder;
 274         int i;
 275
 276         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
 277                 if (connector->encoder_ids[i] == 0)
 278                         break;
 279
 280                 encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
 281                 if (!encoder)
 282                         continue;
 283
 284                 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
 285                         return encoder;
 286         }
 287
 288         /* pick the first one */
 289         if (enc_id)
 290                 return drm_encoder_find(connector->dev, NULL, enc_id);
 291         return NULL;
 292 }
 293
 294 static int dce_virtual_get_modes(struct drm_connector *connector)
 295 {
 296         struct drm_device *dev = connector->dev;
 297         struct drm_display_mode *mode = NULL;
 298         unsigned i;
 299         static const struct mode_size {
 300                 int w;
 301                 int h;
 302         } common_modes[17] = {
 303                 { 640,  480},
 304                 { 720,  480},
 305                 { 800,  600},
 306                 { 848,  480},
 307                 {1024,  768},
 308                 {1152,  768},
 309                 {1280,  720},
 310                 {1280,  800},
 311                 {1280,  854},
 312                 {1280,  960},
 313                 {1280, 1024},
 314                 {1440,  900},
 315                 {1400, 1050},
 316                 {1680, 1050},
 317                 {1600, 1200},
 318                 {1920, 1080},
 319                 {1920, 1200}
 320         };
 321
 322         for (i = 0; i < 17; i++) {
 323                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 324                 drm_mode_probed_add(connector, mode);
 325         }
 326
 327         return 0;
 328 }
 329
 330 static int dce_virtual_mode_valid(struct drm_connector *connector,
 331                                   struct drm_display_mode *mode)
 332 {
 333         return MODE_OK;
 334 }
 335
 336 static int
 337 dce_virtual_dpms(struct drm_connector *connector, int mode)
 338 {
 339         return 0;
 340 }
 341
 342 static int
 343 dce_virtual_set_property(struct drm_connector *connector,
 344                          struct drm_property *property,
 345                          uint64_t val)
 346 {
 347         return 0;
 348 }
 349
 350 static void dce_virtual_destroy(struct drm_connector *connector)
 351 {
 352         drm_connector_unregister(connector);
 353         drm_connector_cleanup(connector);
 354         kfree(connector);
 355 }
 356
 357 static void dce_virtual_force(struct drm_connector *connector)
 358 {
 359         return;
 360 }
 361
 362 static const struct drm_connector_helper_funcs dce_virtual_connector_helper_funcs = {
 363         .get_modes = dce_virtual_get_modes,
 364         .mode_valid = dce_virtual_mode_valid,
 365         .best_encoder = dce_virtual_encoder,
 366 };
 367
 368 static const struct drm_connector_funcs dce_virtual_connector_funcs = {
 369         .dpms = dce_virtual_dpms,
 370         .fill_modes = drm_helper_probe_single_connector_modes,
 371         .set_property = dce_virtual_set_property,
 372         .destroy = dce_virtual_destroy,
 373         .force = dce_virtual_force,
 374 };
 375
 376 static int dce_virtual_sw_init(void *handle)
 377 {
 378         int r, i;
 379         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 380
 381         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 229, &adev->crtc_irq);
 382         if (r)
 383                 return r;
 384
 385         adev->ddev->max_vblank_count = 0;
 386
 387         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
 388
 389         adev->ddev->mode_config.max_width = 16384;
 390         adev->ddev->mode_config.max_height = 16384;
 391
 392         adev->ddev->mode_config.preferred_depth = 24;
 393         adev->ddev->mode_config.prefer_shadow = 1;
 394
 395         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
 396
 397         r = amdgpu_display_modeset_create_props(adev);
 398         if (r)
 399                 return r;
 400
 401         adev->ddev->mode_config.max_width = 16384;
 402         adev->ddev->mode_config.max_height = 16384;
 403
 404         /* allocate crtcs, encoders, connectors */
 405         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 406                 r = dce_virtual_crtc_init(adev, i);
 407                 if (r)
 408                         return r;
 409                 r = dce_virtual_connector_encoder_init(adev, i);
 410                 if (r)
 411                         return r;
 412         }
 413
 414         drm_kms_helper_poll_init(adev->ddev);
 415
 416         adev->mode_info.mode_config_initialized = true;
 417         return 0;
 418 }
 419
 420 static int dce_virtual_sw_fini(void *handle)
 421 {
 422         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 423
 424         kfree(adev->mode_info.bios_hardcoded_edid);
 425
 426         drm_kms_helper_poll_fini(adev->ddev);
 427
 428         drm_mode_config_cleanup(adev->ddev);
 429         /* clear crtcs pointer to avoid dce irq finish routine access freed data */
 430         memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS);
 431         adev->mode_info.mode_config_initialized = false;
 432         return 0;
 433 }
 434
 435 static int dce_virtual_hw_init(void *handle)
 436 {
 437         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 438
 439         switch (adev->asic_type) {
 440 #ifdef CONFIG_DRM_AMDGPU_SI
 441         case CHIP_TAHITI:
 442         case CHIP_PITCAIRN:
 443         case CHIP_VERDE:
 444         case CHIP_OLAND:
 445                 dce_v6_0_disable_dce(adev);
 446                 break;
 447 #endif
 448 #ifdef CONFIG_DRM_AMDGPU_CIK
 449         case CHIP_BONAIRE:
 450         case CHIP_HAWAII:
 451         case CHIP_KAVERI:
 452         case CHIP_KABINI:
 453         case CHIP_MULLINS:
 454                 dce_v8_0_disable_dce(adev);
 455                 break;
 456 #endif
 457         case CHIP_FIJI:
 458         case CHIP_TONGA:
 459                 dce_v10_0_disable_dce(adev);
 460                 break;
 461         case CHIP_CARRIZO:
 462         case CHIP_STONEY:
 463         case CHIP_POLARIS11:
 464         case CHIP_POLARIS10:
 465                 dce_v11_0_disable_dce(adev);
 466                 break;
 467         case CHIP_TOPAZ:
 468 #ifdef CONFIG_DRM_AMDGPU_SI
 469         case CHIP_HAINAN:
 470 #endif
 471                 /* no DCE */
 472                 break;
 473         case CHIP_VEGA10:
 474         case CHIP_VEGA12:
 475                 break;
 476         default:
 477                 DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type);
 478         }
 479         return 0;
 480 }
 481
 482 static int dce_virtual_hw_fini(void *handle)
 483 {
 484         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 485         int i = 0;
 486
 487         for (i = 0; i<adev->mode_info.num_crtc; i++)
 488                 if (adev->mode_info.crtcs[i])
 489                         dce_virtual_set_crtc_vblank_interrupt_state(adev, i, AMDGPU_IRQ_STATE_DISABLE);
 490
 491         return 0;
 492 }
 493
 494 static int dce_virtual_suspend(void *handle)
 495 {
 496         return dce_virtual_hw_fini(handle);
 497 }
 498
 499 static int dce_virtual_resume(void *handle)
 500 {
 501         return dce_virtual_hw_init(handle);
 502 }
 503
 504 static bool dce_virtual_is_idle(void *handle)
 505 {
 506         return true;
 507 }
 508
 509 static int dce_virtual_wait_for_idle(void *handle)
 510 {
 511         return 0;
 512 }
 513
 514 static int dce_virtual_soft_reset(void *handle)
 515 {
 516         return 0;
 517 }
 518
 519 static int dce_virtual_set_clockgating_state(void *handle,
 520                                           enum amd_clockgating_state state)
 521 {
 522         return 0;
 523 }
 524
 525 static int dce_virtual_set_powergating_state(void *handle,
 526                                           enum amd_powergating_state state)
 527 {
 528         return 0;
 529 }
 530
 531 static const struct amd_ip_funcs dce_virtual_ip_funcs = {
 532         .name = "dce_virtual",
 533         .early_init = dce_virtual_early_init,
 534         .late_init = NULL,
 535         .sw_init = dce_virtual_sw_init,
 536         .sw_fini = dce_virtual_sw_fini,
 537         .hw_init = dce_virtual_hw_init,
 538         .hw_fini = dce_virtual_hw_fini,
 539         .suspend = dce_virtual_suspend,
 540         .resume = dce_virtual_resume,
 541         .is_idle = dce_virtual_is_idle,
 542         .wait_for_idle = dce_virtual_wait_for_idle,
 543         .soft_reset = dce_virtual_soft_reset,
 544         .set_clockgating_state = dce_virtual_set_clockgating_state,
 545         .set_powergating_state = dce_virtual_set_powergating_state,
 546 };
 547
 548 /* these are handled by the primary encoders */
 549 static void dce_virtual_encoder_prepare(struct drm_encoder *encoder)
 550 {
 551         return;
 552 }
 553
 554 static void dce_virtual_encoder_commit(struct drm_encoder *encoder)
 555 {
 556         return;
 557 }
 558
 559 static void
 560 dce_virtual_encoder_mode_set(struct drm_encoder *encoder,
 561                              struct drm_display_mode *mode,
 562                              struct drm_display_mode *adjusted_mode)
 563 {
 564         return;
 565 }
 566
 567 static void dce_virtual_encoder_disable(struct drm_encoder *encoder)
 568 {
 569         return;
 570 }
 571
 572 static void
 573 dce_virtual_encoder_dpms(struct drm_encoder *encoder, int mode)
 574 {
 575         return;
 576 }
 577
 578 static bool dce_virtual_encoder_mode_fixup(struct drm_encoder *encoder,
 579                                     const struct drm_display_mode *mode,
 580                                     struct drm_display_mode *adjusted_mode)
 581 {
 582         return true;
 583 }
 584
 585 static const struct drm_encoder_helper_funcs dce_virtual_encoder_helper_funcs = {
 586         .dpms = dce_virtual_encoder_dpms,
 587         .mode_fixup = dce_virtual_encoder_mode_fixup,
 588         .prepare = dce_virtual_encoder_prepare,
 589         .mode_set = dce_virtual_encoder_mode_set,
 590         .commit = dce_virtual_encoder_commit,
 591         .disable = dce_virtual_encoder_disable,
 592 };
 593
 594 static void dce_virtual_encoder_destroy(struct drm_encoder *encoder)
 595 {
 596         drm_encoder_cleanup(encoder);
 597         kfree(encoder);
 598 }
 599
 600 static const struct drm_encoder_funcs dce_virtual_encoder_funcs = {
 601         .destroy = dce_virtual_encoder_destroy,
 602 };
 603
 604 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
 605                                               int index)
 606 {
 607         struct drm_encoder *encoder;
 608         struct drm_connector *connector;
 609
 610         /* add a new encoder */
 611         encoder = kzalloc(sizeof(struct drm_encoder), GFP_KERNEL);
 612         if (!encoder)
 613                 return -ENOMEM;
 614         encoder->possible_crtcs = 1 << index;
 615         drm_encoder_init(adev->ddev, encoder, &dce_virtual_encoder_funcs,
 616                          DRM_MODE_ENCODER_VIRTUAL, NULL);
 617         drm_encoder_helper_add(encoder, &dce_virtual_encoder_helper_funcs);
 618
 619         connector = kzalloc(sizeof(struct drm_connector), GFP_KERNEL);
 620         if (!connector) {
 621                 kfree(encoder);
 622                 return -ENOMEM;
 623         }
 624
 625         /* add a new connector */
 626         drm_connector_init(adev->ddev, connector, &dce_virtual_connector_funcs,
 627                            DRM_MODE_CONNECTOR_VIRTUAL);
 628         drm_connector_helper_add(connector, &dce_virtual_connector_helper_funcs);
 629         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 630         connector->interlace_allowed = false;
 631         connector->doublescan_allowed = false;
 632         drm_connector_register(connector);
 633
 634         /* link them */
 635         drm_mode_connector_attach_encoder(connector, encoder);
 636
 637         return 0;
 638 }
 639
 640 static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
 641         .bandwidth_update = &dce_virtual_bandwidth_update,
 642         .vblank_get_counter = &dce_virtual_vblank_get_counter,
 643         .backlight_set_level = NULL,
 644         .backlight_get_level = NULL,
 645         .hpd_sense = &dce_virtual_hpd_sense,
 646         .hpd_set_polarity = &dce_virtual_hpd_set_polarity,
 647         .hpd_get_gpio_reg = &dce_virtual_hpd_get_gpio_reg,
 648         .page_flip = &dce_virtual_page_flip,
 649         .page_flip_get_scanoutpos = &dce_virtual_crtc_get_scanoutpos,
 650         .add_encoder = NULL,
 651         .add_connector = NULL,
 652 };
 653
 654 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev)
 655 {
 656         if (adev->mode_info.funcs == NULL)
 657                 adev->mode_info.funcs = &dce_virtual_display_funcs;
 658 }
 659
 660 static int dce_virtual_pageflip(struct amdgpu_device *adev,
 661                                 unsigned crtc_id)
 662 {
 663         unsigned long flags;
 664         struct amdgpu_crtc *amdgpu_crtc;
 665         struct amdgpu_flip_work *works;
 666
 667         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 668
 669         if (crtc_id >= adev->mode_info.num_crtc) {
 670                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
 671                 return -EINVAL;
 672         }
 673
 674         /* IRQ could occur when in initial stage */
 675         if (amdgpu_crtc == NULL)
 676                 return 0;
 677
 678         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 679         works = amdgpu_crtc->pflip_works;
 680         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
 681                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
 682                         "AMDGPU_FLIP_SUBMITTED(%d)\n",
 683                         amdgpu_crtc->pflip_status,
 684                         AMDGPU_FLIP_SUBMITTED);
 685                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 686                 return 0;
 687         }
 688
 689         /* page flip completed. clean up */
 690         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 691         amdgpu_crtc->pflip_works = NULL;
 692
 693         /* wakeup usersapce */
 694         if (works->event)
 695                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
 696
 697         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 698
 699         drm_crtc_vblank_put(&amdgpu_crtc->base);
 700         schedule_work(&works->unpin_work);
 701
 702         return 0;
 703 }
 704
 705 static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer)
 706 {
 707         struct amdgpu_crtc *amdgpu_crtc = container_of(vblank_timer,
 708                                                        struct amdgpu_crtc, vblank_timer);
 709         struct drm_device *ddev = amdgpu_crtc->base.dev;
 710         struct amdgpu_device *adev = ddev->dev_private;
 711
 712         drm_handle_vblank(ddev, amdgpu_crtc->crtc_id);
 713         dce_virtual_pageflip(adev, amdgpu_crtc->crtc_id);
 714         hrtimer_start(vblank_timer, DCE_VIRTUAL_VBLANK_PERIOD,
 715                       HRTIMER_MODE_REL);
 716
 717         return HRTIMER_NORESTART;
 718 }
 719
 720 static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
 721                                                         int crtc,
 722                                                         enum amdgpu_interrupt_state state)
 723 {
 724         if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) {
 725                 DRM_DEBUG("invalid crtc %d\n", crtc);
 726                 return;
 727         }
 728
 729         if (state && !adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
 730                 DRM_DEBUG("Enable software vsync timer\n");
 731                 hrtimer_init(&adev->mode_info.crtcs[crtc]->vblank_timer,
 732                              CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 733                 hrtimer_set_expires(&adev->mode_info.crtcs[crtc]->vblank_timer,
 734                                     DCE_VIRTUAL_VBLANK_PERIOD);
 735                 adev->mode_info.crtcs[crtc]->vblank_timer.function =
 736                         dce_virtual_vblank_timer_handle;
 737                 hrtimer_start(&adev->mode_info.crtcs[crtc]->vblank_timer,
 738                               DCE_VIRTUAL_VBLANK_PERIOD, HRTIMER_MODE_REL);
 739         } else if (!state && adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
 740                 DRM_DEBUG("Disable software vsync timer\n");
 741                 hrtimer_cancel(&adev->mode_info.crtcs[crtc]->vblank_timer);
 742         }
 743
 744         adev->mode_info.crtcs[crtc]->vsync_timer_enabled = state;
 745         DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state);
 746 }
 747
 748
 749 static int dce_virtual_set_crtc_irq_state(struct amdgpu_device *adev,
 750                                           struct amdgpu_irq_src *source,
 751                                           unsigned type,
 752                                           enum amdgpu_interrupt_state state)
 753 {
 754         if (type > AMDGPU_CRTC_IRQ_VBLANK6)
 755                 return -EINVAL;
 756
 757         dce_virtual_set_crtc_vblank_interrupt_state(adev, type, state);
 758
 759         return 0;
 760 }
 761
 762 static const struct amdgpu_irq_src_funcs dce_virtual_crtc_irq_funcs = {
 763         .set = dce_virtual_set_crtc_irq_state,
 764         .process = NULL,
 765 };
 766
 767 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)
 768 {
 769         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VBLANK6 + 1;
 770         adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs;
 771 }
 772
 773 const struct amdgpu_ip_block_version dce_virtual_ip_block =
 774 {
 775         .type = AMD_IP_BLOCK_TYPE_DCE,
 776         .major = 1,
 777         .minor = 0,
 778         .rev = 0,
 779         .funcs = &dce_virtual_ip_funcs,
 780 };