drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König
  23  */
  24 #ifndef __AMDGPU_RING_H__
  25 #define __AMDGPU_RING_H__
  26
  27 #include <drm/amdgpu_drm.h>
  28 #include <drm/gpu_scheduler.h>
  29 #include <drm/drm_print.h>
  30
  31 /* max number of rings */
  32 #define AMDGPU_MAX_RINGS                18
  33 #define AMDGPU_MAX_GFX_RINGS            1
  34 #define AMDGPU_MAX_COMPUTE_RINGS        8
  35 #define AMDGPU_MAX_VCE_RINGS            3
  36 #define AMDGPU_MAX_UVD_ENC_RINGS        2
  37
  38 /* some special values for the owner field */
  39 #define AMDGPU_FENCE_OWNER_UNDEFINED    ((void *)0ul)
  40 #define AMDGPU_FENCE_OWNER_VM           ((void *)1ul)
  41 #define AMDGPU_FENCE_OWNER_KFD          ((void *)2ul)
  42
  43 #define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
  44 #define AMDGPU_FENCE_FLAG_INT           (1 << 1)
  45
  46 enum amdgpu_ring_type {
  47         AMDGPU_RING_TYPE_GFX,
  48         AMDGPU_RING_TYPE_COMPUTE,
  49         AMDGPU_RING_TYPE_SDMA,
  50         AMDGPU_RING_TYPE_UVD,
  51         AMDGPU_RING_TYPE_VCE,
  52         AMDGPU_RING_TYPE_KIQ,
  53         AMDGPU_RING_TYPE_UVD_ENC,
  54         AMDGPU_RING_TYPE_VCN_DEC,
  55         AMDGPU_RING_TYPE_VCN_ENC
  56 };
  57
  58 struct amdgpu_device;
  59 struct amdgpu_ring;
  60 struct amdgpu_ib;
  61 struct amdgpu_cs_parser;
  62 struct amdgpu_job;
  63
  64 /*
  65  * Fences.
  66  */
  67 struct amdgpu_fence_driver {
  68         uint64_t                        gpu_addr;
  69         volatile uint32_t               *cpu_addr;
  70         /* sync_seq is protected by ring emission lock */
  71         uint32_t                        sync_seq;
  72         atomic_t                        last_seq;
  73         bool                            initialized;
  74         struct amdgpu_irq_src           *irq_src;
  75         unsigned                        irq_type;
  76         struct timer_list               fallback_timer;
  77         unsigned                        num_fences_mask;
  78         spinlock_t                      lock;
  79         struct dma_fence                **fences;
  80 };
  81
  82 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
  83 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
  84 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
  85
  86 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
  87                                   unsigned num_hw_submission);
  88 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
  89                                    struct amdgpu_irq_src *irq_src,
  90                                    unsigned irq_type);
  91 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
  92 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
  93 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence);
  94 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s);
  95 void amdgpu_fence_process(struct amdgpu_ring *ring);
  96 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
  97 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
  98                                       uint32_t wait_seq,
  99                                       signed long timeout);
 100 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
 101
 102 /*
 103  * Rings.
 104  */
 105
 106 /* provided by hw blocks that expose a ring buffer for commands */
 107 struct amdgpu_ring_funcs {
 108         enum amdgpu_ring_type   type;
 109         uint32_t                align_mask;
 110         u32                     nop;
 111         bool                    support_64bit_ptrs;
 112         unsigned                vmhub;
 113
 114         /* ring read/write ptr handling */
 115         u64 (*get_rptr)(struct amdgpu_ring *ring);
 116         u64 (*get_wptr)(struct amdgpu_ring *ring);
 117         void (*set_wptr)(struct amdgpu_ring *ring);
 118         /* validating and patching of IBs */
 119         int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
 120         /* constants to calculate how many DW are needed for an emit */
 121         unsigned emit_frame_size;
 122         unsigned emit_ib_size;
 123         /* command emit functions */
 124         void (*emit_ib)(struct amdgpu_ring *ring,
 125                         struct amdgpu_ib *ib,
 126                         unsigned vmid, bool ctx_switch);
 127         void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
 128                            uint64_t seq, unsigned flags);
 129         void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
 130         void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
 131                               uint64_t pd_addr);
 132         void (*emit_hdp_flush)(struct amdgpu_ring *ring);
 133         void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
 134                                 uint32_t gds_base, uint32_t gds_size,
 135                                 uint32_t gws_base, uint32_t gws_size,
 136                                 uint32_t oa_base, uint32_t oa_size);
 137         /* testing functions */
 138         int (*test_ring)(struct amdgpu_ring *ring);
 139         int (*test_ib)(struct amdgpu_ring *ring, long timeout);
 140         /* insert NOP packets */
 141         void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
 142         void (*insert_start)(struct amdgpu_ring *ring);
 143         void (*insert_end)(struct amdgpu_ring *ring);
 144         /* pad the indirect buffer to the necessary number of dw */
 145         void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
 146         unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
 147         void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
 148         /* note usage for clock and power gating */
 149         void (*begin_use)(struct amdgpu_ring *ring);
 150         void (*end_use)(struct amdgpu_ring *ring);
 151         void (*emit_switch_buffer) (struct amdgpu_ring *ring);
 152         void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
 153         void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
 154         void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
 155         void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
 156                               uint32_t val, uint32_t mask);
 157         void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
 158                                         uint32_t reg0, uint32_t reg1,
 159                                         uint32_t ref, uint32_t mask);
 160         void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
 161         /* priority functions */
 162         void (*set_priority) (struct amdgpu_ring *ring,
 163                               enum drm_sched_priority priority);
 164 };
 165
 166 struct amdgpu_ring {
 167         struct amdgpu_device            *adev;
 168         const struct amdgpu_ring_funcs  *funcs;
 169         struct amdgpu_fence_driver      fence_drv;
 170         struct drm_gpu_scheduler        sched;
 171         struct list_head                lru_list;
 172
 173         struct amdgpu_bo        *ring_obj;
 174         volatile uint32_t       *ring;
 175         unsigned                rptr_offs;
 176         u64                     wptr;
 177         u64                     wptr_old;
 178         unsigned                ring_size;
 179         unsigned                max_dw;
 180         int                     count_dw;
 181         uint64_t                gpu_addr;
 182         uint64_t                ptr_mask;
 183         uint32_t                buf_mask;
 184         bool                    ready;
 185         u32                     idx;
 186         u32                     me;
 187         u32                     pipe;
 188         u32                     queue;
 189         struct amdgpu_bo        *mqd_obj;
 190         uint64_t                mqd_gpu_addr;
 191         void                    *mqd_ptr;
 192         uint64_t                eop_gpu_addr;
 193         u32                     doorbell_index;
 194         bool                    use_doorbell;
 195         bool                    use_pollmem;
 196         unsigned                wptr_offs;
 197         unsigned                fence_offs;
 198         uint64_t                current_ctx;
 199         char                    name[16];
 200         unsigned                cond_exe_offs;
 201         u64                     cond_exe_gpu_addr;
 202         volatile u32            *cond_exe_cpu_addr;
 203         unsigned                vm_inv_eng;
 204         struct dma_fence        *vmid_wait;
 205         bool                    has_compute_vm_bug;
 206
 207         atomic_t                num_jobs[DRM_SCHED_PRIORITY_MAX];
 208         struct mutex            priority_mutex;
 209         /* protected by priority_mutex */
 210         int                     priority;
 211
 212 #if defined(CONFIG_DEBUG_FS)
 213         struct dentry *ent;
 214 #endif
 215 };
 216
 217 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
 218 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
 219 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
 220 void amdgpu_ring_commit(struct amdgpu_ring *ring);
 221 void amdgpu_ring_undo(struct amdgpu_ring *ring);
 222 void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
 223                               enum drm_sched_priority priority);
 224 void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
 225                               enum drm_sched_priority priority);
 226 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 227                      unsigned ring_size, struct amdgpu_irq_src *irq_src,
 228                      unsigned irq_type);
 229 void amdgpu_ring_fini(struct amdgpu_ring *ring);
 230 int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
 231                         int *blacklist, int num_blacklist,
 232                         bool lru_pipe_order, struct amdgpu_ring **ring);
 233 void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring);
 234 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
 235                                                 uint32_t reg0, uint32_t val0,
 236                                                 uint32_t reg1, uint32_t val1);
 237
 238 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
 239 {
 240         int i = 0;
 241         while (i <= ring->buf_mask)
 242                 ring->ring[i++] = ring->funcs->nop;
 243
 244 }
 245
 246 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
 247 {
 248         if (ring->count_dw <= 0)
 249                 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
 250         ring->ring[ring->wptr++ & ring->buf_mask] = v;
 251         ring->wptr &= ring->ptr_mask;
 252         ring->count_dw--;
 253 }
 254
 255 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
 256                                               void *src, int count_dw)
 257 {
 258         unsigned occupied, chunk1, chunk2;
 259         void *dst;
 260
 261         if (unlikely(ring->count_dw < count_dw))
 262                 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
 263
 264         occupied = ring->wptr & ring->buf_mask;
 265         dst = (void *)&ring->ring[occupied];
 266         chunk1 = ring->buf_mask + 1 - occupied;
 267         chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
 268         chunk2 = count_dw - chunk1;
 269         chunk1 <<= 2;
 270         chunk2 <<= 2;
 271
 272         if (chunk1)
 273                 memcpy(dst, src, chunk1);
 274
 275         if (chunk2) {
 276                 src += chunk1;
 277                 dst = (void *)ring->ring;
 278                 memcpy(dst, src, chunk2);
 279         }
 280
 281         ring->wptr += count_dw;
 282         ring->wptr &= ring->ptr_mask;
 283         ring->count_dw -= count_dw;
 284 }
 285
 286 #endif