drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drm_drv.h>
  24 #include <linux/vmalloc.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_psp.h"
  27 #include "amdgpu_ucode.h"
  28 #include "soc15_common.h"
  29 #include "psp_v13_0.h"
  30
  31 #include "mp/mp_13_0_2_offset.h"
  32 #include "mp/mp_13_0_2_sh_mask.h"
  33
  34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
  35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
  36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
  37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
  38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
  39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
  40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
  41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
  42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
  43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
  44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
  45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
  46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
  47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
  48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
  49 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
  50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
  51 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin");
  52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin");
  53 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
  54 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
  55
  56 /* For large FW files the time to complete can be very long */
  57 #define USBC_PD_POLLING_LIMIT_S 240
  58
  59 /* Read USB-PD from LFB */
  60 #define GFX_CMD_USB_PD_USE_LFB 0x480
  61
  62 /* Retry times for vmbx ready wait */
  63 #define PSP_VMBX_POLLING_LIMIT 20000
  64
  65 /* VBIOS gfl defines */
  66 #define MBOX_READY_MASK 0x80000000
  67 #define MBOX_STATUS_MASK 0x0000FFFF
  68 #define MBOX_COMMAND_MASK 0x00FF0000
  69 #define MBOX_READY_FLAG 0x80000000
  70 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
  71 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
  72 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
  73
  74 /* memory training timeout define */
  75 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  76
  77 static int psp_v13_0_init_microcode(struct psp_context *psp)
  78 {
  79         struct amdgpu_device *adev = psp->adev;
  80         char ucode_prefix[30];
  81         int err = 0;
  82
  83         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
  84
  85         switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
  86         case IP_VERSION(13, 0, 2):
  87                 err = psp_init_sos_microcode(psp, ucode_prefix);
  88                 if (err)
  89                         return err;
  90                 /* It's not necessary to load ras ta on Guest side */
  91                 if (!amdgpu_sriov_vf(adev)) {
  92                         err = psp_init_ta_microcode(psp, ucode_prefix);
  93                         if (err)
  94                                 return err;
  95                 }
  96                 break;
  97         case IP_VERSION(13, 0, 1):
  98         case IP_VERSION(13, 0, 3):
  99         case IP_VERSION(13, 0, 5):
 100         case IP_VERSION(13, 0, 8):
 101         case IP_VERSION(13, 0, 11):
 102         case IP_VERSION(14, 0, 0):
 103                 err = psp_init_toc_microcode(psp, ucode_prefix);
 104                 if (err)
 105                         return err;
 106                 err = psp_init_ta_microcode(psp, ucode_prefix);
 107                 if (err)
 108                         return err;
 109                 break;
 110         case IP_VERSION(13, 0, 0):
 111         case IP_VERSION(13, 0, 6):
 112         case IP_VERSION(13, 0, 7):
 113         case IP_VERSION(13, 0, 10):
 114                 err = psp_init_sos_microcode(psp, ucode_prefix);
 115                 if (err)
 116                         return err;
 117                 /* It's not necessary to load ras ta on Guest side */
 118                 err = psp_init_ta_microcode(psp, ucode_prefix);
 119                 if (err)
 120                         return err;
 121                 break;
 122         default:
 123                 BUG();
 124         }
 125
 126         return 0;
 127 }
 128
 129 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
 130 {
 131         struct amdgpu_device *adev = psp->adev;
 132         uint32_t sol_reg;
 133
 134         sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
 135
 136         return sol_reg != 0x0;
 137 }
 138
 139 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)
 140 {
 141         struct amdgpu_device *adev = psp->adev;
 142         int retry_loop, ret;
 143
 144         for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {
 145                 /* Wait for bootloader to signify that is
 146                    ready having bit 31 of C2PMSG_33 set to 1 */
 147                 ret = psp_wait_for(
 148                         psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33),
 149                         0x80000000, 0xffffffff, false);
 150
 151                 if (ret == 0)
 152                         break;
 153         }
 154
 155         if (ret)
 156                 dev_warn(adev->dev, "Bootloader wait timed out");
 157
 158         return ret;
 159 }
 160
 161 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
 162 {
 163         struct amdgpu_device *adev = psp->adev;
 164         int retry_loop, ret;
 165
 166         /* Wait for bootloader to signify that it is ready having bit 31 of
 167          * C2PMSG_35 set to 1. All other bits are expected to be cleared.
 168          * If there is an error in processing command, bits[7:0] will be set.
 169          * This is applicable for PSP v13.0.6 and newer.
 170          */
 171         for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {
 172                 ret = psp_wait_for(
 173                         psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 174                         0x80000000, 0xffffffff, false);
 175
 176                 if (ret == 0)
 177                         return 0;
 178         }
 179
 180         return ret;
 181 }
 182
 183 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp)
 184 {
 185         struct amdgpu_device *adev = psp->adev;
 186
 187         if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) {
 188                 psp_v13_0_wait_for_vmbx_ready(psp);
 189
 190                 return psp_v13_0_wait_for_bootloader(psp);
 191         }
 192
 193         return 0;
 194 }
 195
 196 static int psp_v13_0_bootloader_load_component(struct psp_context       *psp,
 197                                                struct psp_bin_desc      *bin_desc,
 198                                                enum psp_bootloader_cmd  bl_cmd)
 199 {
 200         int ret;
 201         uint32_t psp_gfxdrv_command_reg = 0;
 202         struct amdgpu_device *adev = psp->adev;
 203
 204         /* Check tOS sign of life register to confirm sys driver and sOS
 205          * are already been loaded.
 206          */
 207         if (psp_v13_0_is_sos_alive(psp))
 208                 return 0;
 209
 210         ret = psp_v13_0_wait_for_bootloader(psp);
 211         if (ret)
 212                 return ret;
 213
 214         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 215
 216         /* Copy PSP KDB binary to memory */
 217         memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
 218
 219         /* Provide the PSP KDB to bootloader */
 220         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 221                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 222         psp_gfxdrv_command_reg = bl_cmd;
 223         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 224                psp_gfxdrv_command_reg);
 225
 226         ret = psp_v13_0_wait_for_bootloader(psp);
 227
 228         return ret;
 229 }
 230
 231 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
 232 {
 233         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
 234 }
 235
 236 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
 237 {
 238         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
 239 }
 240
 241 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
 242 {
 243         return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
 244 }
 245
 246 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
 247 {
 248         return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
 249 }
 250
 251 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
 252 {
 253         return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
 254 }
 255
 256 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
 257 {
 258         return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
 259 }
 260
 261 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
 262 {
 263         return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
 264 }
 265
 266 static inline void psp_v13_0_init_sos_version(struct psp_context *psp)
 267 {
 268         struct amdgpu_device *adev = psp->adev;
 269
 270         psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58);
 271 }
 272
 273 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
 274 {
 275         int ret;
 276         unsigned int psp_gfxdrv_command_reg = 0;
 277         struct amdgpu_device *adev = psp->adev;
 278
 279         /* Check sOS sign of life register to confirm sys driver and sOS
 280          * are already been loaded.
 281          */
 282         if (psp_v13_0_is_sos_alive(psp)) {
 283                 psp_v13_0_init_sos_version(psp);
 284                 return 0;
 285         }
 286
 287         ret = psp_v13_0_wait_for_bootloader(psp);
 288         if (ret)
 289                 return ret;
 290
 291         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 292
 293         /* Copy Secure OS binary to PSP memory */
 294         memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
 295
 296         /* Provide the PSP secure OS to bootloader */
 297         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 298                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 299         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 300         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 301                psp_gfxdrv_command_reg);
 302
 303         /* there might be handshake issue with hardware which needs delay */
 304         mdelay(20);
 305         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
 306                            RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
 307                            0, true);
 308
 309         if (!ret)
 310                 psp_v13_0_init_sos_version(psp);
 311
 312         return ret;
 313 }
 314
 315 static int psp_v13_0_ring_stop(struct psp_context *psp,
 316                                enum psp_ring_type ring_type)
 317 {
 318         int ret = 0;
 319         struct amdgpu_device *adev = psp->adev;
 320
 321         if (amdgpu_sriov_vf(adev)) {
 322                 /* Write the ring destroy command*/
 323                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 324                              GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 325                 /* there might be handshake issue with hardware which needs delay */
 326                 mdelay(20);
 327                 /* Wait for response flag (bit 31) */
 328                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 329                                    0x80000000, 0x80000000, false);
 330         } else {
 331                 /* Write the ring destroy command*/
 332                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
 333                              GFX_CTRL_CMD_ID_DESTROY_RINGS);
 334                 /* there might be handshake issue with hardware which needs delay */
 335                 mdelay(20);
 336                 /* Wait for response flag (bit 31) */
 337                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 338                                    0x80000000, 0x80000000, false);
 339         }
 340
 341         return ret;
 342 }
 343
 344 static int psp_v13_0_ring_create(struct psp_context *psp,
 345                                  enum psp_ring_type ring_type)
 346 {
 347         int ret = 0;
 348         unsigned int psp_ring_reg = 0;
 349         struct psp_ring *ring = &psp->km_ring;
 350         struct amdgpu_device *adev = psp->adev;
 351
 352         if (amdgpu_sriov_vf(adev)) {
 353                 ret = psp_v13_0_ring_stop(psp, ring_type);
 354                 if (ret) {
 355                         DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
 356                         return ret;
 357                 }
 358
 359                 /* Write low address of the ring to C2PMSG_102 */
 360                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 361                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
 362                 /* Write high address of the ring to C2PMSG_103 */
 363                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 364                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
 365
 366                 /* Write the ring initialization command to C2PMSG_101 */
 367                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 368                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 369
 370                 /* there might be handshake issue with hardware which needs delay */
 371                 mdelay(20);
 372
 373                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 374                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 375                                    0x80000000, 0x8000FFFF, false);
 376
 377         } else {
 378                 /* Wait for sOS ready for ring creation */
 379                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 380                                    0x80000000, 0x80000000, false);
 381                 if (ret) {
 382                         DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
 383                         return ret;
 384                 }
 385
 386                 /* Write low address of the ring to C2PMSG_69 */
 387                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 388                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
 389                 /* Write high address of the ring to C2PMSG_70 */
 390                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 391                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
 392                 /* Write size of ring to C2PMSG_71 */
 393                 psp_ring_reg = ring->ring_size;
 394                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
 395                 /* Write the ring initialization command to C2PMSG_64 */
 396                 psp_ring_reg = ring_type;
 397                 psp_ring_reg = psp_ring_reg << 16;
 398                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
 399
 400                 /* there might be handshake issue with hardware which needs delay */
 401                 mdelay(20);
 402
 403                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 404                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 405                                    0x80000000, 0x8000FFFF, false);
 406         }
 407
 408         return ret;
 409 }
 410
 411 static int psp_v13_0_ring_destroy(struct psp_context *psp,
 412                                   enum psp_ring_type ring_type)
 413 {
 414         int ret = 0;
 415         struct psp_ring *ring = &psp->km_ring;
 416         struct amdgpu_device *adev = psp->adev;
 417
 418         ret = psp_v13_0_ring_stop(psp, ring_type);
 419         if (ret)
 420                 DRM_ERROR("Fail to stop psp ring\n");
 421
 422         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 423                               &ring->ring_mem_mc_addr,
 424                               (void **)&ring->ring_mem);
 425
 426         return ret;
 427 }
 428
 429 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
 430 {
 431         uint32_t data;
 432         struct amdgpu_device *adev = psp->adev;
 433
 434         if (amdgpu_sriov_vf(adev))
 435                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
 436         else
 437                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 438
 439         return data;
 440 }
 441
 442 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 443 {
 444         struct amdgpu_device *adev = psp->adev;
 445
 446         if (amdgpu_sriov_vf(adev)) {
 447                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
 448                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 449                              GFX_CTRL_CMD_ID_CONSUME_CMD);
 450         } else
 451                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
 452 }
 453
 454 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
 455 {
 456         int ret;
 457         int i;
 458         uint32_t data_32;
 459         int max_wait;
 460         struct amdgpu_device *adev = psp->adev;
 461
 462         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 463         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
 464         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
 465
 466         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 467         for (i = 0; i < max_wait; i++) {
 468                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 469                                    0x80000000, 0x80000000, false);
 470                 if (ret == 0)
 471                         break;
 472         }
 473         if (i < max_wait)
 474                 ret = 0;
 475         else
 476                 ret = -ETIME;
 477
 478         dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
 479                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 480                   (ret == 0) ? "succeed" : "failed",
 481                   i, adev->usec_timeout/1000);
 482         return ret;
 483 }
 484
 485
 486 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
 487 {
 488         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 489         uint32_t *pcache = (uint32_t *)ctx->sys_cache;
 490         struct amdgpu_device *adev = psp->adev;
 491         uint32_t p2c_header[4];
 492         uint32_t sz;
 493         void *buf;
 494         int ret, idx;
 495
 496         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 497                 dev_dbg(adev->dev, "Memory training is not supported.\n");
 498                 return 0;
 499         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 500                 dev_err(adev->dev, "Memory training initialization failure.\n");
 501                 return -EINVAL;
 502         }
 503
 504         if (psp_v13_0_is_sos_alive(psp)) {
 505                 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
 506                 return 0;
 507         }
 508
 509         amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
 510         dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
 511                   pcache[0], pcache[1], pcache[2], pcache[3],
 512                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
 513
 514         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 515                 dev_dbg(adev->dev, "Short training depends on restore.\n");
 516                 ops |= PSP_MEM_TRAIN_RESTORE;
 517         }
 518
 519         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
 520             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 521                 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
 522                 ops |= PSP_MEM_TRAIN_SAVE;
 523         }
 524
 525         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 526             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 527               pcache[3] == p2c_header[3])) {
 528                 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
 529                 ops |= PSP_MEM_TRAIN_SAVE;
 530         }
 531
 532         if ((ops & PSP_MEM_TRAIN_SAVE) &&
 533             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 534                 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
 535                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
 536         }
 537
 538         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 539                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
 540                 ops |= PSP_MEM_TRAIN_SAVE;
 541         }
 542
 543         dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
 544
 545         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 546                 /*
 547                  * Long training will encroach a certain amount on the bottom of VRAM;
 548                  * save the content from the bottom of VRAM to system memory
 549                  * before training, and restore it after training to avoid
 550                  * VRAM corruption.
 551                  */
 552                 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
 553
 554                 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
 555                         dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
 556                                   adev->gmc.visible_vram_size,
 557                                   adev->mman.aper_base_kaddr);
 558                         return -EINVAL;
 559                 }
 560
 561                 buf = vmalloc(sz);
 562                 if (!buf) {
 563                         dev_err(adev->dev, "failed to allocate system memory.\n");
 564                         return -ENOMEM;
 565                 }
 566
 567                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 568                         memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
 569                         ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
 570                         if (ret) {
 571                                 DRM_ERROR("Send long training msg failed.\n");
 572                                 vfree(buf);
 573                                 drm_dev_exit(idx);
 574                                 return ret;
 575                         }
 576
 577                         memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
 578                         adev->hdp.funcs->flush_hdp(adev, NULL);
 579                         vfree(buf);
 580                         drm_dev_exit(idx);
 581                 } else {
 582                         vfree(buf);
 583                         return -ENODEV;
 584                 }
 585         }
 586
 587         if (ops & PSP_MEM_TRAIN_SAVE) {
 588                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
 589         }
 590
 591         if (ops & PSP_MEM_TRAIN_RESTORE) {
 592                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
 593         }
 594
 595         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 596                 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
 597                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
 598                 if (ret) {
 599                         dev_err(adev->dev, "send training msg failed.\n");
 600                         return ret;
 601                 }
 602         }
 603         ctx->training_cnt++;
 604         return 0;
 605 }
 606
 607 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
 608 {
 609         struct amdgpu_device *adev = psp->adev;
 610         uint32_t reg_status;
 611         int ret, i = 0;
 612
 613         /*
 614          * LFB address which is aligned to 1MB address and has to be
 615          * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
 616          * register
 617          */
 618         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 619
 620         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 621                              0x80000000, 0x80000000, false);
 622         if (ret)
 623                 return ret;
 624
 625         /* Fireup interrupt so PSP can pick up the address */
 626         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
 627
 628         /* FW load takes very long time */
 629         do {
 630                 msleep(1000);
 631                 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
 632
 633                 if (reg_status & 0x80000000)
 634                         goto done;
 635
 636         } while (++i < USBC_PD_POLLING_LIMIT_S);
 637
 638         return -ETIME;
 639 done:
 640
 641         if ((reg_status & 0xFFFF) != 0) {
 642                 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
 643                                 reg_status & 0xFFFF);
 644                 return -EIO;
 645         }
 646
 647         return 0;
 648 }
 649
 650 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 651 {
 652         struct amdgpu_device *adev = psp->adev;
 653         int ret;
 654
 655         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 656
 657         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 658                                      0x80000000, 0x80000000, false);
 659         if (!ret)
 660                 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
 661
 662         return ret;
 663 }
 664
 665 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
 666 {
 667         uint32_t reg_status = 0, reg_val = 0;
 668         struct amdgpu_device *adev = psp->adev;
 669         int ret;
 670
 671         /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
 672         reg_val |= (cmd << 16);
 673         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115,  reg_val);
 674
 675         /* Ring the doorbell */
 676         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
 677
 678         if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
 679                 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 680                                                  MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
 681         else
 682                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 683                                    MBOX_READY_FLAG, MBOX_READY_MASK, false);
 684         if (ret) {
 685                 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
 686                 return ret;
 687         }
 688
 689         reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 690         if ((reg_status & 0xFFFF) != 0) {
 691                 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
 692                                 cmd, reg_status & 0xFFFF);
 693                 return -EIO;
 694         }
 695
 696         return 0;
 697 }
 698
 699 static int psp_v13_0_update_spirom(struct psp_context *psp,
 700                                    uint64_t fw_pri_mc_addr)
 701 {
 702         struct amdgpu_device *adev = psp->adev;
 703         int ret;
 704
 705         /* Confirm PSP is ready to start */
 706         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 707                            MBOX_READY_FLAG, MBOX_READY_MASK, false);
 708         if (ret) {
 709                 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
 710                 return ret;
 711         }
 712
 713         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
 714
 715         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
 716         if (ret)
 717                 return ret;
 718
 719         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
 720
 721         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
 722         if (ret)
 723                 return ret;
 724
 725         psp->vbflash_done = true;
 726
 727         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
 728         if (ret)
 729                 return ret;
 730
 731         return 0;
 732 }
 733
 734 static int psp_v13_0_vbflash_status(struct psp_context *psp)
 735 {
 736         struct amdgpu_device *adev = psp->adev;
 737
 738         return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 739 }
 740
 741 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp)
 742 {
 743         struct amdgpu_device *adev = psp->adev;
 744
 745         if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) {
 746                 uint32_t  reg_data;
 747                 /* MP1 fatal error: trigger PSP dram read to unhalt PSP
 748                  * during MP1 triggered sync flood.
 749                  */
 750                 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 751                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10);
 752
 753                 /* delay 1000ms for the mode1 reset for fatal error
 754                  * to be recovered back.
 755                  */
 756                 msleep(1000);
 757         }
 758
 759         return 0;
 760 }
 761
 762
 763 static void psp_v13_0_boot_error_reporting(struct amdgpu_device *adev,
 764                                            uint32_t inst,
 765                                            uint32_t boot_error)
 766 {
 767         uint32_t socket_id;
 768         uint32_t aid_id;
 769         uint32_t hbm_id;
 770         uint32_t reg_data;
 771
 772         socket_id = REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, SOCKET_ID);
 773         aid_id = REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, AID_ID);
 774         hbm_id = REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, HBM_ID);
 775
 776         reg_data = RREG32_SOC15(MP0, inst, regMP0_SMN_C2PMSG_109);
 777         dev_info(adev->dev, "socket: %d, aid: %d, firmware boot failed, fw status is 0x%x\n",
 778                  socket_id, aid_id, reg_data);
 779
 780         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_MEM_TRAINING))
 781                 dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, memory training failed\n",
 782                          socket_id, aid_id, hbm_id);
 783
 784         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_FW_LOAD))
 785                 dev_info(adev->dev, "socket: %d, aid: %d, firmware load failed at boot time\n",
 786                          socket_id, aid_id);
 787
 788         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_WAFL_LINK_TRAINING))
 789                 dev_info(adev->dev, "socket: %d, aid: %d, wafl link training failed\n",
 790                          socket_id, aid_id);
 791
 792         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_XGMI_LINK_TRAINING))
 793                 dev_info(adev->dev, "socket: %d, aid: %d, xgmi link training failed\n",
 794                          socket_id, aid_id);
 795
 796         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_USR_CP_LINK_TRAINING))
 797                 dev_info(adev->dev, "socket: %d, aid: %d, usr cp link training failed\n",
 798                          socket_id, aid_id);
 799
 800         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_USR_DP_LINK_TRAINING))
 801                 dev_info(adev->dev, "socket: %d, aid: %d, usr dp link training failed\n",
 802                          socket_id, aid_id);
 803
 804         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_HBM_MEM_TEST))
 805                 dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, hbm memory test failed\n",
 806                          socket_id, aid_id, hbm_id);
 807
 808         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_HBM_BIST_TEST))
 809                 dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, hbm bist test failed\n",
 810                          socket_id, aid_id, hbm_id);
 811 }
 812
 813 static int psp_v13_0_query_boot_status(struct psp_context *psp)
 814 {
 815         struct amdgpu_device *adev = psp->adev;
 816         int inst_mask = adev->aid_mask;
 817         uint32_t reg_data;
 818         uint32_t i;
 819         int ret = 0;
 820
 821         if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))
 822                 return 0;
 823
 824         if (RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_59) < 0x00a10007)
 825                 return 0;
 826
 827         for_each_inst(i, inst_mask) {
 828                 reg_data = RREG32_SOC15(MP0, i, regMP0_SMN_C2PMSG_126);
 829                 if (!REG_GET_FIELD(reg_data, MP0_SMN_C2PMSG_126, BOOT_STATUS)) {
 830                         psp_v13_0_boot_error_reporting(adev, i, reg_data);
 831                         ret = -EINVAL;
 832                         break;
 833                 }
 834         }
 835
 836         return ret;
 837 }
 838
 839 static const struct psp_funcs psp_v13_0_funcs = {
 840         .init_microcode = psp_v13_0_init_microcode,
 841         .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state,
 842         .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
 843         .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
 844         .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
 845         .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
 846         .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
 847         .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
 848         .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,
 849         .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
 850         .ring_create = psp_v13_0_ring_create,
 851         .ring_stop = psp_v13_0_ring_stop,
 852         .ring_destroy = psp_v13_0_ring_destroy,
 853         .ring_get_wptr = psp_v13_0_ring_get_wptr,
 854         .ring_set_wptr = psp_v13_0_ring_set_wptr,
 855         .mem_training = psp_v13_0_memory_training,
 856         .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
 857         .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
 858         .update_spirom = psp_v13_0_update_spirom,
 859         .vbflash_stat = psp_v13_0_vbflash_status,
 860         .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk,
 861         .query_boot_status = psp_v13_0_query_boot_status,
 862 };
 863
 864 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
 865 {
 866         psp->funcs = &psp_v13_0_funcs;
 867 }