drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/delay.h>
  24 #include <linux/kernel.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_gfx.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_smu.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "imu_v11_0.h"
  34 #include "soc21.h"
  35 #include "nvd.h"
  36
  37 #include "gc/gc_11_0_0_offset.h"
  38 #include "gc/gc_11_0_0_sh_mask.h"
  39 #include "smuio/smuio_13_0_6_offset.h"
  40 #include "smuio/smuio_13_0_6_sh_mask.h"
  41 #include "navi10_enum.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "clearstate_gfx11.h"
  47 #include "v11_structs.h"
  48 #include "gfx_v11_0.h"
  49 #include "gfx_v11_0_3.h"
  50 #include "nbio_v4_3.h"
  51 #include "mes_v11_0.h"
  52
  53 #define GFX11_NUM_GFX_RINGS             1
  54 #define GFX11_MEC_HPD_SIZE      2048
  55
  56 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1        0x1388
  58
  59 #define regCGTT_WD_CLK_CTRL             0x5086
  60 #define regCGTT_WD_CLK_CTRL_BASE_IDX    1
  61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1   0x4e7e
  62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX  1
  63 #define regPC_CONFIG_CNTL_1             0x194d
  64 #define regPC_CONFIG_CNTL_1_BASE_IDX    1
  65
  66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin");
  67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");
  68 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin");
  69 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin");
  70 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin");
  71 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin");
  72 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin");
  73 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin");
  74 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin");
  75 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin");
  76 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin");
  77 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin");
  78 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin");
  79 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin");
  80 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin");
  81 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin");
  82 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin");
  83 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin");
  84 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin");
  85 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin");
  86 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin");
  87 MODULE_FIRMWARE("amdgpu/gc_11_5_0_pfp.bin");
  88 MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin");
  89 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");
  90 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");
  91
  92 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
  93 {
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a)
 103 };
 104
 105 static const struct soc15_reg_golden golden_settings_gc_11_5_0[] = {
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_DEBUG5, 0xffffffff, 0x00000800),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, regGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL, 0xffffffff, 0xf37fff3f),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xfffffffb, 0x00f40188),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL4, 0xf0ffffff, 0x8000b007),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf1ffffff, 0x00880007),
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, regPC_CONFIG_CNTL_1, 0xffffffff, 0x00010000),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL2, 0x007f0000, 0x00000000),
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xffcfffff, 0x0000200a),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, regUTCL1_CTRL_2, 0xffffffff, 0x0000048f)
 120 };
 121
 122 #define DEFAULT_SH_MEM_CONFIG \
 123         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
 124          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
 125          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
 126
 127 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev);
 128 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev);
 129 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev);
 130 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev);
 131 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev);
 132 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev);
 133 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev);
 134 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
 135                                  struct amdgpu_cu_info *cu_info);
 136 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 137 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 138                                    u32 sh_num, u32 instance, int xcc_id);
 139 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
 140
 141 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
 142 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
 143 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
 144                                      uint32_t val);
 145 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
 146 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
 147                                            uint16_t pasid, uint32_t flush_type,
 148                                            bool all_hub, uint8_t dst_sel);
 149 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
 150 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
 151 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
 152                                       bool enable);
 153
 154 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
 155 {
 156         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
 157         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
 158                           PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */
 159                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
 160         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
 161         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
 162         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
 163         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
 164         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
 165         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
 166 }
 167
 168 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring,
 169                                  struct amdgpu_ring *ring)
 170 {
 171         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
 172         uint64_t wptr_addr = ring->wptr_gpu_addr;
 173         uint32_t me = 0, eng_sel = 0;
 174
 175         switch (ring->funcs->type) {
 176         case AMDGPU_RING_TYPE_COMPUTE:
 177                 me = 1;
 178                 eng_sel = 0;
 179                 break;
 180         case AMDGPU_RING_TYPE_GFX:
 181                 me = 0;
 182                 eng_sel = 4;
 183                 break;
 184         case AMDGPU_RING_TYPE_MES:
 185                 me = 2;
 186                 eng_sel = 5;
 187                 break;
 188         default:
 189                 WARN_ON(1);
 190         }
 191
 192         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 193         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
 194         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 195                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
 196                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
 197                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
 198                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
 199                           PACKET3_MAP_QUEUES_ME((me)) |
 200                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
 201                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
 202                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
 203                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
 204         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 205         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 206         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 207         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 208         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 209 }
 210
 211 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 212                                    struct amdgpu_ring *ring,
 213                                    enum amdgpu_unmap_queues_action action,
 214                                    u64 gpu_addr, u64 seq)
 215 {
 216         struct amdgpu_device *adev = kiq_ring->adev;
 217         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 218
 219         if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
 220                 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
 221                 return;
 222         }
 223
 224         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 225         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 226                           PACKET3_UNMAP_QUEUES_ACTION(action) |
 227                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
 228                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
 229                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
 230         amdgpu_ring_write(kiq_ring,
 231                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 232
 233         if (action == PREEMPT_QUEUES_NO_UNMAP) {
 234                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
 235                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
 236                 amdgpu_ring_write(kiq_ring, seq);
 237         } else {
 238                 amdgpu_ring_write(kiq_ring, 0);
 239                 amdgpu_ring_write(kiq_ring, 0);
 240                 amdgpu_ring_write(kiq_ring, 0);
 241         }
 242 }
 243
 244 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring,
 245                                    struct amdgpu_ring *ring,
 246                                    u64 addr,
 247                                    u64 seq)
 248 {
 249         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 250
 251         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 252         amdgpu_ring_write(kiq_ring,
 253                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
 254                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
 255                           PACKET3_QUERY_STATUS_COMMAND(2));
 256         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 257                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
 258                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
 259         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
 260         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
 261         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
 262         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 263 }
 264
 265 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
 266                                 uint16_t pasid, uint32_t flush_type,
 267                                 bool all_hub)
 268 {
 269         gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
 270 }
 271
 272 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = {
 273         .kiq_set_resources = gfx11_kiq_set_resources,
 274         .kiq_map_queues = gfx11_kiq_map_queues,
 275         .kiq_unmap_queues = gfx11_kiq_unmap_queues,
 276         .kiq_query_status = gfx11_kiq_query_status,
 277         .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs,
 278         .set_resources_size = 8,
 279         .map_queues_size = 7,
 280         .unmap_queues_size = 6,
 281         .query_status_size = 7,
 282         .invalidate_tlbs_size = 2,
 283 };
 284
 285 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
 286 {
 287         adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs;
 288 }
 289
 290 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)
 291 {
 292         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 293         case IP_VERSION(11, 0, 1):
 294         case IP_VERSION(11, 0, 4):
 295                 soc15_program_register_sequence(adev,
 296                                                 golden_settings_gc_11_0_1,
 297                                                 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1));
 298                 break;
 299         case IP_VERSION(11, 5, 0):
 300                 soc15_program_register_sequence(adev,
 301                                                 golden_settings_gc_11_5_0,
 302                                                 (const u32)ARRAY_SIZE(golden_settings_gc_11_5_0));
 303                 break;
 304         default:
 305                 break;
 306         }
 307 }
 308
 309 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 310                                        bool wc, uint32_t reg, uint32_t val)
 311 {
 312         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 313         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 314                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
 315         amdgpu_ring_write(ring, reg);
 316         amdgpu_ring_write(ring, 0);
 317         amdgpu_ring_write(ring, val);
 318 }
 319
 320 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 321                                   int mem_space, int opt, uint32_t addr0,
 322                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 323                                   uint32_t inv)
 324 {
 325         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 326         amdgpu_ring_write(ring,
 327                           /* memory (1) or register (0) */
 328                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 329                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
 330                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 331                            WAIT_REG_MEM_ENGINE(eng_sel)));
 332
 333         if (mem_space)
 334                 BUG_ON(addr0 & 0x3); /* Dword align */
 335         amdgpu_ring_write(ring, addr0);
 336         amdgpu_ring_write(ring, addr1);
 337         amdgpu_ring_write(ring, ref);
 338         amdgpu_ring_write(ring, mask);
 339         amdgpu_ring_write(ring, inv); /* poll interval */
 340 }
 341
 342 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring)
 343 {
 344         struct amdgpu_device *adev = ring->adev;
 345         uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
 346         uint32_t tmp = 0;
 347         unsigned i;
 348         int r;
 349
 350         WREG32(scratch, 0xCAFEDEAD);
 351         r = amdgpu_ring_alloc(ring, 5);
 352         if (r) {
 353                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 354                           ring->idx, r);
 355                 return r;
 356         }
 357
 358         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) {
 359                 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);
 360         } else {
 361                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 362                 amdgpu_ring_write(ring, scratch -
 363                                   PACKET3_SET_UCONFIG_REG_START);
 364                 amdgpu_ring_write(ring, 0xDEADBEEF);
 365         }
 366         amdgpu_ring_commit(ring);
 367
 368         for (i = 0; i < adev->usec_timeout; i++) {
 369                 tmp = RREG32(scratch);
 370                 if (tmp == 0xDEADBEEF)
 371                         break;
 372                 if (amdgpu_emu_mode == 1)
 373                         msleep(1);
 374                 else
 375                         udelay(1);
 376         }
 377
 378         if (i >= adev->usec_timeout)
 379                 r = -ETIMEDOUT;
 380         return r;
 381 }
 382
 383 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 384 {
 385         struct amdgpu_device *adev = ring->adev;
 386         struct amdgpu_ib ib;
 387         struct dma_fence *f = NULL;
 388         unsigned index;
 389         uint64_t gpu_addr;
 390         volatile uint32_t *cpu_ptr;
 391         long r;
 392
 393         /* MES KIQ fw hasn't indirect buffer support for now */
 394         if (adev->enable_mes_kiq &&
 395             ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
 396                 return 0;
 397
 398         memset(&ib, 0, sizeof(ib));
 399
 400         if (ring->is_mes_queue) {
 401                 uint32_t padding, offset;
 402
 403                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
 404                 padding = amdgpu_mes_ctx_get_offs(ring,
 405                                                   AMDGPU_MES_CTX_PADDING_OFFS);
 406
 407                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 408                 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 409
 410                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
 411                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
 412                 *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
 413         } else {
 414                 r = amdgpu_device_wb_get(adev, &index);
 415                 if (r)
 416                         return r;
 417
 418                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 419                 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 420                 cpu_ptr = &adev->wb.wb[index];
 421
 422                 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib);
 423                 if (r) {
 424                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 425                         goto err1;
 426                 }
 427         }
 428
 429         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 430         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 431         ib.ptr[2] = lower_32_bits(gpu_addr);
 432         ib.ptr[3] = upper_32_bits(gpu_addr);
 433         ib.ptr[4] = 0xDEADBEEF;
 434         ib.length_dw = 5;
 435
 436         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 437         if (r)
 438                 goto err2;
 439
 440         r = dma_fence_wait_timeout(f, false, timeout);
 441         if (r == 0) {
 442                 r = -ETIMEDOUT;
 443                 goto err2;
 444         } else if (r < 0) {
 445                 goto err2;
 446         }
 447
 448         if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
 449                 r = 0;
 450         else
 451                 r = -EINVAL;
 452 err2:
 453         if (!ring->is_mes_queue)
 454                 amdgpu_ib_free(adev, &ib, NULL);
 455         dma_fence_put(f);
 456 err1:
 457         if (!ring->is_mes_queue)
 458                 amdgpu_device_wb_free(adev, index);
 459         return r;
 460 }
 461
 462 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev)
 463 {
 464         amdgpu_ucode_release(&adev->gfx.pfp_fw);
 465         amdgpu_ucode_release(&adev->gfx.me_fw);
 466         amdgpu_ucode_release(&adev->gfx.rlc_fw);
 467         amdgpu_ucode_release(&adev->gfx.mec_fw);
 468
 469         kfree(adev->gfx.rlc.register_list_format);
 470 }
 471
 472 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix)
 473 {
 474         const struct psp_firmware_header_v1_0 *toc_hdr;
 475         int err = 0;
 476         char fw_name[40];
 477
 478         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix);
 479         err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
 480         if (err)
 481                 goto out;
 482
 483         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
 484         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
 485         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
 486         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
 487         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
 488                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
 489         return 0;
 490 out:
 491         amdgpu_ucode_release(&adev->psp.toc_fw);
 492         return err;
 493 }
 494
 495 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev)
 496 {
 497         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 498         case IP_VERSION(11, 0, 0):
 499         case IP_VERSION(11, 0, 2):
 500         case IP_VERSION(11, 0, 3):
 501                 if ((adev->gfx.me_fw_version >= 1505) &&
 502                     (adev->gfx.pfp_fw_version >= 1600) &&
 503                     (adev->gfx.mec_fw_version >= 512)) {
 504                         if (amdgpu_sriov_vf(adev))
 505                                 adev->gfx.cp_gfx_shadow = true;
 506                         else
 507                                 adev->gfx.cp_gfx_shadow = false;
 508                 }
 509                 break;
 510         default:
 511                 adev->gfx.cp_gfx_shadow = false;
 512                 break;
 513         }
 514 }
 515
 516 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
 517 {
 518         char fw_name[40];
 519         char ucode_prefix[30];
 520         int err;
 521         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 522         uint16_t version_major;
 523         uint16_t version_minor;
 524
 525         DRM_DEBUG("\n");
 526
 527         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 528
 529         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix);
 530         err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
 531         if (err)
 532                 goto out;
 533         /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/
 534         adev->gfx.rs64_enable = amdgpu_ucode_hdr_version(
 535                                 (union amdgpu_firmware_header *)
 536                                 adev->gfx.pfp_fw->data, 2, 0);
 537         if (adev->gfx.rs64_enable) {
 538                 dev_info(adev->dev, "CP RS64 enable\n");
 539                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP);
 540                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);
 541                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK);
 542         } else {
 543                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
 544         }
 545
 546         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix);
 547         err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
 548         if (err)
 549                 goto out;
 550         if (adev->gfx.rs64_enable) {
 551                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME);
 552                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK);
 553                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK);
 554         } else {
 555                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
 556         }
 557
 558         if (!amdgpu_sriov_vf(adev)) {
 559                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
 560                 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
 561                 if (err)
 562                         goto out;
 563                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 564                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 565                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 566                 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
 567                 if (err)
 568                         goto out;
 569         }
 570
 571         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix);
 572         err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
 573         if (err)
 574                 goto out;
 575         if (adev->gfx.rs64_enable) {
 576                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC);
 577                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK);
 578                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK);
 579                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK);
 580                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK);
 581         } else {
 582                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
 583                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
 584         }
 585
 586         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
 587                 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix);
 588
 589         /* only one MEC for gfx 11.0.0. */
 590         adev->gfx.mec2_fw = NULL;
 591
 592         gfx_v11_0_check_fw_cp_gfx_shadow(adev);
 593
 594         if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) {
 595                 err = adev->gfx.imu.funcs->init_microcode(adev);
 596                 if (err)
 597                         DRM_ERROR("Failed to init imu firmware!\n");
 598                 return err;
 599         }
 600
 601 out:
 602         if (err) {
 603                 amdgpu_ucode_release(&adev->gfx.pfp_fw);
 604                 amdgpu_ucode_release(&adev->gfx.me_fw);
 605                 amdgpu_ucode_release(&adev->gfx.rlc_fw);
 606                 amdgpu_ucode_release(&adev->gfx.mec_fw);
 607         }
 608
 609         return err;
 610 }
 611
 612 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev)
 613 {
 614         u32 count = 0;
 615         const struct cs_section_def *sect = NULL;
 616         const struct cs_extent_def *ext = NULL;
 617
 618         /* begin clear state */
 619         count += 2;
 620         /* context control state */
 621         count += 3;
 622
 623         for (sect = gfx11_cs_data; sect->section != NULL; ++sect) {
 624                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 625                         if (sect->id == SECT_CONTEXT)
 626                                 count += 2 + ext->reg_count;
 627                         else
 628                                 return 0;
 629                 }
 630         }
 631
 632         /* set PA_SC_TILE_STEERING_OVERRIDE */
 633         count += 3;
 634         /* end clear state */
 635         count += 2;
 636         /* clear state */
 637         count += 2;
 638
 639         return count;
 640 }
 641
 642 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev,
 643                                     volatile u32 *buffer)
 644 {
 645         u32 count = 0, i;
 646         const struct cs_section_def *sect = NULL;
 647         const struct cs_extent_def *ext = NULL;
 648         int ctx_reg_offset;
 649
 650         if (adev->gfx.rlc.cs_data == NULL)
 651                 return;
 652         if (buffer == NULL)
 653                 return;
 654
 655         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 656         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 657
 658         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 659         buffer[count++] = cpu_to_le32(0x80000000);
 660         buffer[count++] = cpu_to_le32(0x80000000);
 661
 662         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 663                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 664                         if (sect->id == SECT_CONTEXT) {
 665                                 buffer[count++] =
 666                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 667                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 668                                                 PACKET3_SET_CONTEXT_REG_START);
 669                                 for (i = 0; i < ext->reg_count; i++)
 670                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 671                         } else {
 672                                 return;
 673                         }
 674                 }
 675         }
 676
 677         ctx_reg_offset =
 678                 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
 679         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 680         buffer[count++] = cpu_to_le32(ctx_reg_offset);
 681         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
 682
 683         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 684         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 685
 686         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 687         buffer[count++] = cpu_to_le32(0);
 688 }
 689
 690 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev)
 691 {
 692         /* clear state block */
 693         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 694                         &adev->gfx.rlc.clear_state_gpu_addr,
 695                         (void **)&adev->gfx.rlc.cs_ptr);
 696
 697         /* jump table block */
 698         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 699                         &adev->gfx.rlc.cp_table_gpu_addr,
 700                         (void **)&adev->gfx.rlc.cp_table_ptr);
 701 }
 702
 703 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
 704 {
 705         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
 706
 707         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
 708         reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
 709         reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);
 710         reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);
 711         reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);
 712         reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);
 713         reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);
 714         reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);
 715         adev->gfx.rlc.rlcg_reg_access_supported = true;
 716 }
 717
 718 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev)
 719 {
 720         const struct cs_section_def *cs_data;
 721         int r;
 722
 723         adev->gfx.rlc.cs_data = gfx11_cs_data;
 724
 725         cs_data = adev->gfx.rlc.cs_data;
 726
 727         if (cs_data) {
 728                 /* init clear state block */
 729                 r = amdgpu_gfx_rlc_init_csb(adev);
 730                 if (r)
 731                         return r;
 732         }
 733
 734         /* init spm vmid with 0xf */
 735         if (adev->gfx.rlc.funcs->update_spm_vmid)
 736                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
 737
 738         return 0;
 739 }
 740
 741 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev)
 742 {
 743         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
 744         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
 745         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL);
 746 }
 747
 748 static void gfx_v11_0_me_init(struct amdgpu_device *adev)
 749 {
 750         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 751
 752         amdgpu_gfx_graphics_queue_acquire(adev);
 753 }
 754
 755 static int gfx_v11_0_mec_init(struct amdgpu_device *adev)
 756 {
 757         int r;
 758         u32 *hpd;
 759         size_t mec_hpd_size;
 760
 761         bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 762
 763         /* take ownership of the relevant compute queues */
 764         amdgpu_gfx_compute_queue_acquire(adev);
 765         mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE;
 766
 767         if (mec_hpd_size) {
 768                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
 769                                               AMDGPU_GEM_DOMAIN_GTT,
 770                                               &adev->gfx.mec.hpd_eop_obj,
 771                                               &adev->gfx.mec.hpd_eop_gpu_addr,
 772                                               (void **)&hpd);
 773                 if (r) {
 774                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 775                         gfx_v11_0_mec_fini(adev);
 776                         return r;
 777                 }
 778
 779                 memset(hpd, 0, mec_hpd_size);
 780
 781                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 782                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 783         }
 784
 785         return 0;
 786 }
 787
 788 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
 789 {
 790         WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
 791                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 792                 (address << SQ_IND_INDEX__INDEX__SHIFT));
 793         return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
 794 }
 795
 796 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
 797                            uint32_t thread, uint32_t regno,
 798                            uint32_t num, uint32_t *out)
 799 {
 800         WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
 801                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 802                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
 803                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
 804                 (SQ_IND_INDEX__AUTO_INCR_MASK));
 805         while (num--)
 806                 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);
 807 }
 808
 809 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
 810 {
 811         /* in gfx11 the SIMD_ID is specified as part of the INSTANCE
 812          * field when performing a select_se_sh so it should be
 813          * zero here */
 814         WARN_ON(simd != 0);
 815
 816         /* type 3 wave data */
 817         dst[(*no_fields)++] = 3;
 818         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
 819         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
 820         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
 821         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
 822         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
 823         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
 824         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
 825         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
 826         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
 827         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
 828         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
 829         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
 830         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
 831         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
 832         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
 833 }
 834
 835 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 836                                      uint32_t wave, uint32_t start,
 837                                      uint32_t size, uint32_t *dst)
 838 {
 839         WARN_ON(simd != 0);
 840
 841         wave_read_regs(
 842                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
 843                 dst);
 844 }
 845
 846 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 847                                       uint32_t wave, uint32_t thread,
 848                                       uint32_t start, uint32_t size,
 849                                       uint32_t *dst)
 850 {
 851         wave_read_regs(
 852                 adev, wave, thread,
 853                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
 854 }
 855
 856 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev,
 857                                         u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
 858 {
 859         soc21_grbm_select(adev, me, pipe, q, vm);
 860 }
 861
 862 /* all sizes are in bytes */
 863 #define MQD_SHADOW_BASE_SIZE      73728
 864 #define MQD_SHADOW_BASE_ALIGNMENT 256
 865 #define MQD_FWWORKAREA_SIZE       484
 866 #define MQD_FWWORKAREA_ALIGNMENT  256
 867
 868 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev,
 869                                          struct amdgpu_gfx_shadow_info *shadow_info)
 870 {
 871         if (adev->gfx.cp_gfx_shadow) {
 872                 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE;
 873                 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;
 874                 shadow_info->csa_size = MQD_FWWORKAREA_SIZE;
 875                 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT;
 876                 return 0;
 877         } else {
 878                 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));
 879                 return -ENOTSUPP;
 880         }
 881 }
 882
 883 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = {
 884         .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter,
 885         .select_se_sh = &gfx_v11_0_select_se_sh,
 886         .read_wave_data = &gfx_v11_0_read_wave_data,
 887         .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs,
 888         .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs,
 889         .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q,
 890         .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk,
 891         .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info,
 892 };
 893
 894 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
 895 {
 896         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 897         case IP_VERSION(11, 0, 0):
 898         case IP_VERSION(11, 0, 2):
 899                 adev->gfx.config.max_hw_contexts = 8;
 900                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 901                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 902                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
 903                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 904                 break;
 905         case IP_VERSION(11, 0, 3):
 906                 adev->gfx.ras = &gfx_v11_0_3_ras;
 907                 adev->gfx.config.max_hw_contexts = 8;
 908                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 909                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 910                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
 911                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 912                 break;
 913         case IP_VERSION(11, 0, 1):
 914         case IP_VERSION(11, 0, 4):
 915         case IP_VERSION(11, 5, 0):
 916                 adev->gfx.config.max_hw_contexts = 8;
 917                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 918                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 919                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
 920                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300;
 921                 break;
 922         default:
 923                 BUG();
 924                 break;
 925         }
 926
 927         return 0;
 928 }
 929
 930 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
 931                                    int me, int pipe, int queue)
 932 {
 933         int r;
 934         struct amdgpu_ring *ring;
 935         unsigned int irq_type;
 936
 937         ring = &adev->gfx.gfx_ring[ring_id];
 938
 939         ring->me = me;
 940         ring->pipe = pipe;
 941         ring->queue = queue;
 942
 943         ring->ring_obj = NULL;
 944         ring->use_doorbell = true;
 945
 946         if (!ring_id)
 947                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
 948         else
 949                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
 950         ring->vm_hub = AMDGPU_GFXHUB(0);
 951         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 952
 953         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
 954         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
 955                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 956         if (r)
 957                 return r;
 958         return 0;
 959 }
 960
 961 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
 962                                        int mec, int pipe, int queue)
 963 {
 964         int r;
 965         unsigned irq_type;
 966         struct amdgpu_ring *ring;
 967         unsigned int hw_prio;
 968
 969         ring = &adev->gfx.compute_ring[ring_id];
 970
 971         /* mec0 is me1 */
 972         ring->me = mec + 1;
 973         ring->pipe = pipe;
 974         ring->queue = queue;
 975
 976         ring->ring_obj = NULL;
 977         ring->use_doorbell = true;
 978         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
 979         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
 980                                 + (ring_id * GFX11_MEC_HPD_SIZE);
 981         ring->vm_hub = AMDGPU_GFXHUB(0);
 982         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 983
 984         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
 985                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
 986                 + ring->pipe;
 987         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
 988                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
 989         /* type-2 packets are deprecated on MEC, use type-3 instead */
 990         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
 991                              hw_prio, NULL);
 992         if (r)
 993                 return r;
 994
 995         return 0;
 996 }
 997
 998 static struct {
 999         SOC21_FIRMWARE_ID       id;
1000         unsigned int            offset;
1001         unsigned int            size;
1002 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX];
1003
1004 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc)
1005 {
1006         RLC_TABLE_OF_CONTENT *ucode = rlc_toc;
1007
1008         while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) &&
1009                         (ucode->id < SOC21_FIRMWARE_ID_MAX)) {
1010                 rlc_autoload_info[ucode->id].id = ucode->id;
1011                 rlc_autoload_info[ucode->id].offset = ucode->offset * 4;
1012                 rlc_autoload_info[ucode->id].size = ucode->size * 4;
1013
1014                 ucode++;
1015         }
1016 }
1017
1018 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev)
1019 {
1020         uint32_t total_size = 0;
1021         SOC21_FIRMWARE_ID id;
1022
1023         gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr);
1024
1025         for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++)
1026                 total_size += rlc_autoload_info[id].size;
1027
1028         /* In case the offset in rlc toc ucode is aligned */
1029         if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset)
1030                 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset +
1031                         rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size;
1032
1033         return total_size;
1034 }
1035
1036 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev)
1037 {
1038         int r;
1039         uint32_t total_size;
1040
1041         total_size = gfx_v11_0_calc_toc_total_size(adev);
1042
1043         r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024,
1044                                       AMDGPU_GEM_DOMAIN_VRAM |
1045                                       AMDGPU_GEM_DOMAIN_GTT,
1046                                       &adev->gfx.rlc.rlc_autoload_bo,
1047                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
1048                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1049
1050         if (r) {
1051                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
1052                 return r;
1053         }
1054
1055         return 0;
1056 }
1057
1058 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
1059                                               SOC21_FIRMWARE_ID id,
1060                                               const void *fw_data,
1061                                               uint32_t fw_size,
1062                                               uint32_t *fw_autoload_mask)
1063 {
1064         uint32_t toc_offset;
1065         uint32_t toc_fw_size;
1066         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
1067
1068         if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX)
1069                 return;
1070
1071         toc_offset = rlc_autoload_info[id].offset;
1072         toc_fw_size = rlc_autoload_info[id].size;
1073
1074         if (fw_size == 0)
1075                 fw_size = toc_fw_size;
1076
1077         if (fw_size > toc_fw_size)
1078                 fw_size = toc_fw_size;
1079
1080         memcpy(ptr + toc_offset, fw_data, fw_size);
1081
1082         if (fw_size < toc_fw_size)
1083                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
1084
1085         if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME))
1086                 *(uint64_t *)fw_autoload_mask |= 1ULL << id;
1087 }
1088
1089 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev,
1090                                                         uint32_t *fw_autoload_mask)
1091 {
1092         void *data;
1093         uint32_t size;
1094         uint64_t *toc_ptr;
1095
1096         *(uint64_t *)fw_autoload_mask |= 0x1;
1097
1098         DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask);
1099
1100         data = adev->psp.toc.start_addr;
1101         size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size;
1102
1103         toc_ptr = (uint64_t *)data + size / 8 - 1;
1104         *toc_ptr = *(uint64_t *)fw_autoload_mask;
1105
1106         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC,
1107                                         data, size, fw_autoload_mask);
1108 }
1109
1110 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev,
1111                                                         uint32_t *fw_autoload_mask)
1112 {
1113         const __le32 *fw_data;
1114         uint32_t fw_size;
1115         const struct gfx_firmware_header_v1_0 *cp_hdr;
1116         const struct gfx_firmware_header_v2_0 *cpv2_hdr;
1117         const struct rlc_firmware_header_v2_0 *rlc_hdr;
1118         const struct rlc_firmware_header_v2_2 *rlcv22_hdr;
1119         uint16_t version_major, version_minor;
1120
1121         if (adev->gfx.rs64_enable) {
1122                 /* pfp ucode */
1123                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1124                         adev->gfx.pfp_fw->data;
1125                 /* instruction */
1126                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1127                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1128                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1129                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP,
1130                                                 fw_data, fw_size, fw_autoload_mask);
1131                 /* data */
1132                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1133                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1134                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1135                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK,
1136                                                 fw_data, fw_size, fw_autoload_mask);
1137                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK,
1138                                                 fw_data, fw_size, fw_autoload_mask);
1139                 /* me ucode */
1140                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1141                         adev->gfx.me_fw->data;
1142                 /* instruction */
1143                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1144                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1145                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1146                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME,
1147                                                 fw_data, fw_size, fw_autoload_mask);
1148                 /* data */
1149                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1150                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1151                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1152                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK,
1153                                                 fw_data, fw_size, fw_autoload_mask);
1154                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK,
1155                                                 fw_data, fw_size, fw_autoload_mask);
1156                 /* mec ucode */
1157                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1158                         adev->gfx.mec_fw->data;
1159                 /* instruction */
1160                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1161                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1162                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1163                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC,
1164                                                 fw_data, fw_size, fw_autoload_mask);
1165                 /* data */
1166                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1167                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1168                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1169                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK,
1170                                                 fw_data, fw_size, fw_autoload_mask);
1171                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK,
1172                                                 fw_data, fw_size, fw_autoload_mask);
1173                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK,
1174                                                 fw_data, fw_size, fw_autoload_mask);
1175                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK,
1176                                                 fw_data, fw_size, fw_autoload_mask);
1177         } else {
1178                 /* pfp ucode */
1179                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1180                         adev->gfx.pfp_fw->data;
1181                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1182                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1183                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1184                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP,
1185                                                 fw_data, fw_size, fw_autoload_mask);
1186
1187                 /* me ucode */
1188                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1189                         adev->gfx.me_fw->data;
1190                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1191                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1192                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1193                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME,
1194                                                 fw_data, fw_size, fw_autoload_mask);
1195
1196                 /* mec ucode */
1197                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1198                         adev->gfx.mec_fw->data;
1199                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1200                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1201                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1202                         cp_hdr->jt_size * 4;
1203                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC,
1204                                                 fw_data, fw_size, fw_autoload_mask);
1205         }
1206
1207         /* rlc ucode */
1208         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
1209                 adev->gfx.rlc_fw->data;
1210         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1211                         le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
1212         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
1213         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE,
1214                                         fw_data, fw_size, fw_autoload_mask);
1215
1216         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1217         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1218         if (version_major == 2) {
1219                 if (version_minor >= 2) {
1220                         rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1221
1222                         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1223                                         le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes));
1224                         fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes);
1225                         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE,
1226                                         fw_data, fw_size, fw_autoload_mask);
1227
1228                         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1229                                         le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes));
1230                         fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes);
1231                         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT,
1232                                         fw_data, fw_size, fw_autoload_mask);
1233                 }
1234         }
1235 }
1236
1237 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev,
1238                                                         uint32_t *fw_autoload_mask)
1239 {
1240         const __le32 *fw_data;
1241         uint32_t fw_size;
1242         const struct sdma_firmware_header_v2_0 *sdma_hdr;
1243
1244         sdma_hdr = (const struct sdma_firmware_header_v2_0 *)
1245                 adev->sdma.instance[0].fw->data;
1246         fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1247                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
1248         fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes);
1249
1250         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1251                         SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask);
1252
1253         fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1254                         le32_to_cpu(sdma_hdr->ctl_ucode_offset));
1255         fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes);
1256
1257         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1258                         SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask);
1259 }
1260
1261 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev,
1262                                                         uint32_t *fw_autoload_mask)
1263 {
1264         const __le32 *fw_data;
1265         unsigned fw_size;
1266         const struct mes_firmware_header_v1_0 *mes_hdr;
1267         int pipe, ucode_id, data_id;
1268
1269         for (pipe = 0; pipe < 2; pipe++) {
1270                 if (pipe==0) {
1271                         ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0;
1272                         data_id  = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK;
1273                 } else {
1274                         ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1;
1275                         data_id  = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK;
1276                 }
1277
1278                 mes_hdr = (const struct mes_firmware_header_v1_0 *)
1279                         adev->mes.fw[pipe]->data;
1280
1281                 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1282                                 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
1283                 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
1284
1285                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1286                                 ucode_id, fw_data, fw_size, fw_autoload_mask);
1287
1288                 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1289                                 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
1290                 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
1291
1292                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1293                                 data_id, fw_data, fw_size, fw_autoload_mask);
1294         }
1295 }
1296
1297 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
1298 {
1299         uint32_t rlc_g_offset, rlc_g_size;
1300         uint64_t gpu_addr;
1301         uint32_t autoload_fw_id[2];
1302
1303         memset(autoload_fw_id, 0, sizeof(uint32_t) * 2);
1304
1305         /* RLC autoload sequence 2: copy ucode */
1306         gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id);
1307         gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id);
1308         gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id);
1309         gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id);
1310
1311         rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset;
1312         rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size;
1313         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
1314
1315         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
1316         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
1317
1318         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
1319
1320         /* RLC autoload sequence 3: load IMU fw */
1321         if (adev->gfx.imu.funcs->load_microcode)
1322                 adev->gfx.imu.funcs->load_microcode(adev);
1323         /* RLC autoload sequence 4 init IMU fw */
1324         if (adev->gfx.imu.funcs->setup_imu)
1325                 adev->gfx.imu.funcs->setup_imu(adev);
1326         if (adev->gfx.imu.funcs->start_imu)
1327                 adev->gfx.imu.funcs->start_imu(adev);
1328
1329         /* RLC autoload sequence 5 disable gpa mode */
1330         gfx_v11_0_disable_gpa_mode(adev);
1331
1332         return 0;
1333 }
1334
1335 static int gfx_v11_0_sw_init(void *handle)
1336 {
1337         int i, j, k, r, ring_id = 0;
1338         struct amdgpu_kiq *kiq;
1339         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1340
1341         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1342         case IP_VERSION(11, 0, 0):
1343         case IP_VERSION(11, 0, 2):
1344         case IP_VERSION(11, 0, 3):
1345                 adev->gfx.me.num_me = 1;
1346                 adev->gfx.me.num_pipe_per_me = 1;
1347                 adev->gfx.me.num_queue_per_pipe = 1;
1348                 adev->gfx.mec.num_mec = 2;
1349                 adev->gfx.mec.num_pipe_per_mec = 4;
1350                 adev->gfx.mec.num_queue_per_pipe = 4;
1351                 break;
1352         case IP_VERSION(11, 0, 1):
1353         case IP_VERSION(11, 0, 4):
1354         case IP_VERSION(11, 5, 0):
1355                 adev->gfx.me.num_me = 1;
1356                 adev->gfx.me.num_pipe_per_me = 1;
1357                 adev->gfx.me.num_queue_per_pipe = 1;
1358                 adev->gfx.mec.num_mec = 1;
1359                 adev->gfx.mec.num_pipe_per_mec = 4;
1360                 adev->gfx.mec.num_queue_per_pipe = 4;
1361                 break;
1362         default:
1363                 adev->gfx.me.num_me = 1;
1364                 adev->gfx.me.num_pipe_per_me = 1;
1365                 adev->gfx.me.num_queue_per_pipe = 1;
1366                 adev->gfx.mec.num_mec = 1;
1367                 adev->gfx.mec.num_pipe_per_mec = 4;
1368                 adev->gfx.mec.num_queue_per_pipe = 8;
1369                 break;
1370         }
1371
1372         /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */
1373         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) &&
1374             amdgpu_sriov_is_pp_one_vf(adev))
1375                 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG;
1376
1377         /* EOP Event */
1378         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1379                               GFX_11_0_0__SRCID__CP_EOP_INTERRUPT,
1380                               &adev->gfx.eop_irq);
1381         if (r)
1382                 return r;
1383
1384         /* Privileged reg */
1385         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1386                               GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT,
1387                               &adev->gfx.priv_reg_irq);
1388         if (r)
1389                 return r;
1390
1391         /* Privileged inst */
1392         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1393                               GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT,
1394                               &adev->gfx.priv_inst_irq);
1395         if (r)
1396                 return r;
1397
1398         /* FED error */
1399         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1400                                   GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT,
1401                                   &adev->gfx.rlc_gc_fed_irq);
1402         if (r)
1403                 return r;
1404
1405         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1406
1407         gfx_v11_0_me_init(adev);
1408
1409         r = gfx_v11_0_rlc_init(adev);
1410         if (r) {
1411                 DRM_ERROR("Failed to init rlc BOs!\n");
1412                 return r;
1413         }
1414
1415         r = gfx_v11_0_mec_init(adev);
1416         if (r) {
1417                 DRM_ERROR("Failed to init MEC BOs!\n");
1418                 return r;
1419         }
1420
1421         /* set up the gfx ring */
1422         for (i = 0; i < adev->gfx.me.num_me; i++) {
1423                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1424                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1425                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1426                                         continue;
1427
1428                                 r = gfx_v11_0_gfx_ring_init(adev, ring_id,
1429                                                             i, k, j);
1430                                 if (r)
1431                                         return r;
1432                                 ring_id++;
1433                         }
1434                 }
1435         }
1436
1437         ring_id = 0;
1438         /* set up the compute queues - allocate horizontally across pipes */
1439         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1440                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1441                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1442                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
1443                                                                      k, j))
1444                                         continue;
1445
1446                                 r = gfx_v11_0_compute_ring_init(adev, ring_id,
1447                                                                 i, k, j);
1448                                 if (r)
1449                                         return r;
1450
1451                                 ring_id++;
1452                         }
1453                 }
1454         }
1455
1456         if (!adev->enable_mes_kiq) {
1457                 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0);
1458                 if (r) {
1459                         DRM_ERROR("Failed to init KIQ BOs!\n");
1460                         return r;
1461                 }
1462
1463                 kiq = &adev->gfx.kiq[0];
1464                 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0);
1465                 if (r)
1466                         return r;
1467         }
1468
1469         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0);
1470         if (r)
1471                 return r;
1472
1473         /* allocate visible FB for rlc auto-loading fw */
1474         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1475                 r = gfx_v11_0_rlc_autoload_buffer_init(adev);
1476                 if (r)
1477                         return r;
1478         }
1479
1480         r = gfx_v11_0_gpu_early_init(adev);
1481         if (r)
1482                 return r;
1483
1484         if (amdgpu_gfx_ras_sw_init(adev)) {
1485                 dev_err(adev->dev, "Failed to initialize gfx ras block!\n");
1486                 return -EINVAL;
1487         }
1488
1489         return 0;
1490 }
1491
1492 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev)
1493 {
1494         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1495                               &adev->gfx.pfp.pfp_fw_gpu_addr,
1496                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
1497
1498         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj,
1499                               &adev->gfx.pfp.pfp_fw_data_gpu_addr,
1500                               (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
1501 }
1502
1503 static void gfx_v11_0_me_fini(struct amdgpu_device *adev)
1504 {
1505         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1506                               &adev->gfx.me.me_fw_gpu_addr,
1507                               (void **)&adev->gfx.me.me_fw_ptr);
1508
1509         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj,
1510                                &adev->gfx.me.me_fw_data_gpu_addr,
1511                                (void **)&adev->gfx.me.me_fw_data_ptr);
1512 }
1513
1514 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev)
1515 {
1516         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1517                         &adev->gfx.rlc.rlc_autoload_gpu_addr,
1518                         (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1519 }
1520
1521 static int gfx_v11_0_sw_fini(void *handle)
1522 {
1523         int i;
1524         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1525
1526         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1527                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1528         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1529                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1530
1531         amdgpu_gfx_mqd_sw_fini(adev, 0);
1532
1533         if (!adev->enable_mes_kiq) {
1534                 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
1535                 amdgpu_gfx_kiq_fini(adev, 0);
1536         }
1537
1538         gfx_v11_0_pfp_fini(adev);
1539         gfx_v11_0_me_fini(adev);
1540         gfx_v11_0_rlc_fini(adev);
1541         gfx_v11_0_mec_fini(adev);
1542
1543         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1544                 gfx_v11_0_rlc_autoload_buffer_fini(adev);
1545
1546         gfx_v11_0_free_microcode(adev);
1547
1548         return 0;
1549 }
1550
1551 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1552                                    u32 sh_num, u32 instance, int xcc_id)
1553 {
1554         u32 data;
1555
1556         if (instance == 0xffffffff)
1557                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1558                                      INSTANCE_BROADCAST_WRITES, 1);
1559         else
1560                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1561                                      instance);
1562
1563         if (se_num == 0xffffffff)
1564                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1565                                      1);
1566         else
1567                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1568
1569         if (sh_num == 0xffffffff)
1570                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1571                                      1);
1572         else
1573                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1574
1575         WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);
1576 }
1577
1578 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev)
1579 {
1580         u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask;
1581
1582         gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE);
1583         gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask,
1584                                            CC_GC_SA_UNIT_DISABLE,
1585                                            SA_DISABLE);
1586         gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE);
1587         gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask,
1588                                                  GC_USER_SA_UNIT_DISABLE,
1589                                                  SA_DISABLE);
1590         sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
1591                                             adev->gfx.config.max_shader_engines);
1592
1593         return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask));
1594 }
1595
1596 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1597 {
1598         u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask;
1599         u32 rb_mask;
1600
1601         gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);
1602         gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask,
1603                                             CC_RB_BACKEND_DISABLE,
1604                                             BACKEND_DISABLE);
1605         gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);
1606         gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask,
1607                                                  GC_USER_RB_BACKEND_DISABLE,
1608                                                  BACKEND_DISABLE);
1609         rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se *
1610                                             adev->gfx.config.max_shader_engines);
1611
1612         return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask));
1613 }
1614
1615 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev)
1616 {
1617         u32 rb_bitmap_width_per_sa;
1618         u32 max_sa;
1619         u32 active_sa_bitmap;
1620         u32 global_active_rb_bitmap;
1621         u32 active_rb_bitmap = 0;
1622         u32 i;
1623
1624         /* query sa bitmap from SA_UNIT_DISABLE registers */
1625         active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev);
1626         /* query rb bitmap from RB_BACKEND_DISABLE registers */
1627         global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev);
1628
1629         /* generate active rb bitmap according to active sa bitmap */
1630         max_sa = adev->gfx.config.max_shader_engines *
1631                  adev->gfx.config.max_sh_per_se;
1632         rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se /
1633                                  adev->gfx.config.max_sh_per_se;
1634         for (i = 0; i < max_sa; i++) {
1635                 if (active_sa_bitmap & (1 << i))
1636                         active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa));
1637         }
1638
1639         active_rb_bitmap |= global_active_rb_bitmap;
1640         adev->gfx.config.backend_enable_mask = active_rb_bitmap;
1641         adev->gfx.config.num_rbs = hweight32(active_rb_bitmap);
1642 }
1643
1644 #define DEFAULT_SH_MEM_BASES    (0x6000)
1645 #define LDS_APP_BASE           0x1
1646 #define SCRATCH_APP_BASE       0x2
1647
1648 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev)
1649 {
1650         int i;
1651         uint32_t sh_mem_bases;
1652         uint32_t data;
1653
1654         /*
1655          * Configure apertures:
1656          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1657          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1658          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1659          */
1660         sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) |
1661                         SCRATCH_APP_BASE;
1662
1663         mutex_lock(&adev->srbm_mutex);
1664         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1665                 soc21_grbm_select(adev, 0, 0, 0, i);
1666                 /* CP and shaders */
1667                 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1668                 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);
1669
1670                 /* Enable trap for each kfd vmid. */
1671                 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);
1672                 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
1673                 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data);
1674         }
1675         soc21_grbm_select(adev, 0, 0, 0, 0);
1676         mutex_unlock(&adev->srbm_mutex);
1677
1678         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
1679            acccess. These should be enabled by FW for target VMIDs. */
1680         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1681                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0);
1682                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0);
1683                 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0);
1684                 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0);
1685         }
1686 }
1687
1688 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev)
1689 {
1690         int vmid;
1691
1692         /*
1693          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1694          * access. Compute VMIDs should be enabled by FW for target VMIDs,
1695          * the driver can enable them for graphics. VMID0 should maintain
1696          * access so that HWS firmware can save/restore entries.
1697          */
1698         for (vmid = 1; vmid < 16; vmid++) {
1699                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0);
1700                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0);
1701                 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0);
1702                 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0);
1703         }
1704 }
1705
1706 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev)
1707 {
1708         /* TODO: harvest feature to be added later. */
1709 }
1710
1711 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev)
1712 {
1713         /* TCCs are global (not instanced). */
1714         uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) |
1715                                RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE);
1716
1717         adev->gfx.config.tcc_disabled_mask =
1718                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
1719                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
1720 }
1721
1722 static void gfx_v11_0_constants_init(struct amdgpu_device *adev)
1723 {
1724         u32 tmp;
1725         int i;
1726
1727         if (!amdgpu_sriov_vf(adev))
1728                 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1729
1730         gfx_v11_0_setup_rb(adev);
1731         gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info);
1732         gfx_v11_0_get_tcc_info(adev);
1733         adev->gfx.config.pa_sc_tile_steering_override = 0;
1734
1735         /* Set whether texture coordinate truncation is conformant. */
1736         tmp = RREG32_SOC15(GC, 0, regTA_CNTL2);
1737         adev->gfx.config.ta_cntl2_truncate_coord_mode =
1738                 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE);
1739
1740         /* XXX SH_MEM regs */
1741         /* where to put LDS, scratch, GPUVM in FSA64 space */
1742         mutex_lock(&adev->srbm_mutex);
1743         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
1744                 soc21_grbm_select(adev, 0, 0, 0, i);
1745                 /* CP and shaders */
1746                 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1747                 if (i != 0) {
1748                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1749                                 (adev->gmc.private_aperture_start >> 48));
1750                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1751                                 (adev->gmc.shared_aperture_start >> 48));
1752                         WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);
1753                 }
1754         }
1755         soc21_grbm_select(adev, 0, 0, 0, 0);
1756
1757         mutex_unlock(&adev->srbm_mutex);
1758
1759         gfx_v11_0_init_compute_vmid(adev);
1760         gfx_v11_0_init_gds_vmid(adev);
1761 }
1762
1763 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1764                                                bool enable)
1765 {
1766         u32 tmp;
1767
1768         if (amdgpu_sriov_vf(adev))
1769                 return;
1770
1771         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0);
1772
1773         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1774                             enable ? 1 : 0);
1775         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1776                             enable ? 1 : 0);
1777         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1778                             enable ? 1 : 0);
1779         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1780                             enable ? 1 : 0);
1781
1782         WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp);
1783 }
1784
1785 static int gfx_v11_0_init_csb(struct amdgpu_device *adev)
1786 {
1787         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1788
1789         WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,
1790                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
1791         WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,
1792                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1793         WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1794
1795         return 0;
1796 }
1797
1798 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev)
1799 {
1800         u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
1801
1802         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1803         WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
1804 }
1805
1806 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev)
1807 {
1808         WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1809         udelay(50);
1810         WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1811         udelay(50);
1812 }
1813
1814 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1815                                              bool enable)
1816 {
1817         uint32_t rlc_pg_cntl;
1818
1819         rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
1820
1821         if (!enable) {
1822                 /* RLC_PG_CNTL[23] = 0 (default)
1823                  * RLC will wait for handshake acks with SMU
1824                  * GFXOFF will be enabled
1825                  * RLC_PG_CNTL[23] = 1
1826                  * RLC will not issue any message to SMU
1827                  * hence no handshake between SMU & RLC
1828                  * GFXOFF will be disabled
1829                  */
1830                 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1831         } else
1832                 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1833         WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);
1834 }
1835
1836 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev)
1837 {
1838         /* TODO: enable rlc & smu handshake until smu
1839          * and gfxoff feature works as expected */
1840         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1841                 gfx_v11_0_rlc_smu_handshake_cntl(adev, false);
1842
1843         WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1844         udelay(50);
1845 }
1846
1847 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev)
1848 {
1849         uint32_t tmp;
1850
1851         /* enable Save Restore Machine */
1852         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
1853         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1854         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1855         WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
1856 }
1857
1858 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev)
1859 {
1860         const struct rlc_firmware_header_v2_0 *hdr;
1861         const __le32 *fw_data;
1862         unsigned i, fw_size;
1863
1864         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1865         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1866                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1867         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1868
1869         WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,
1870                      RLCG_UCODE_LOADING_START_ADDRESS);
1871
1872         for (i = 0; i < fw_size; i++)
1873                 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,
1874                              le32_to_cpup(fw_data++));
1875
1876         WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1877 }
1878
1879 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev)
1880 {
1881         const struct rlc_firmware_header_v2_2 *hdr;
1882         const __le32 *fw_data;
1883         unsigned i, fw_size;
1884         u32 tmp;
1885
1886         hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1887
1888         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1889                         le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes));
1890         fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4;
1891
1892         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);
1893
1894         for (i = 0; i < fw_size; i++) {
1895                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1896                         msleep(1);
1897                 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,
1898                                 le32_to_cpup(fw_data++));
1899         }
1900
1901         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1902
1903         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1904                         le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes));
1905         fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4;
1906
1907         WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);
1908         for (i = 0; i < fw_size; i++) {
1909                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1910                         msleep(1);
1911                 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,
1912                                 le32_to_cpup(fw_data++));
1913         }
1914
1915         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1916
1917         tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);
1918         tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);
1919         tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);
1920         WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);
1921 }
1922
1923 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev)
1924 {
1925         const struct rlc_firmware_header_v2_3 *hdr;
1926         const __le32 *fw_data;
1927         unsigned i, fw_size;
1928         u32 tmp;
1929
1930         hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data;
1931
1932         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1933                         le32_to_cpu(hdr->rlcp_ucode_offset_bytes));
1934         fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4;
1935
1936         WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0);
1937
1938         for (i = 0; i < fw_size; i++) {
1939                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1940                         msleep(1);
1941                 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA,
1942                                 le32_to_cpup(fw_data++));
1943         }
1944
1945         WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version);
1946
1947         tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);
1948         tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
1949         WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp);
1950
1951         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1952                         le32_to_cpu(hdr->rlcv_ucode_offset_bytes));
1953         fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4;
1954
1955         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0);
1956
1957         for (i = 0; i < fw_size; i++) {
1958                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1959                         msleep(1);
1960                 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA,
1961                                 le32_to_cpup(fw_data++));
1962         }
1963
1964         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version);
1965
1966         tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL);
1967         tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1);
1968         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp);
1969 }
1970
1971 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev)
1972 {
1973         const struct rlc_firmware_header_v2_0 *hdr;
1974         uint16_t version_major;
1975         uint16_t version_minor;
1976
1977         if (!adev->gfx.rlc_fw)
1978                 return -EINVAL;
1979
1980         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1981         amdgpu_ucode_print_rlc_hdr(&hdr->header);
1982
1983         version_major = le16_to_cpu(hdr->header.header_version_major);
1984         version_minor = le16_to_cpu(hdr->header.header_version_minor);
1985
1986         if (version_major == 2) {
1987                 gfx_v11_0_load_rlcg_microcode(adev);
1988                 if (amdgpu_dpm == 1) {
1989                         if (version_minor >= 2)
1990                                 gfx_v11_0_load_rlc_iram_dram_microcode(adev);
1991                         if (version_minor == 3)
1992                                 gfx_v11_0_load_rlcp_rlcv_microcode(adev);
1993                 }
1994
1995                 return 0;
1996         }
1997
1998         return -EINVAL;
1999 }
2000
2001 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev)
2002 {
2003         int r;
2004
2005         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2006                 gfx_v11_0_init_csb(adev);
2007
2008                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
2009                         gfx_v11_0_rlc_enable_srm(adev);
2010         } else {
2011                 if (amdgpu_sriov_vf(adev)) {
2012                         gfx_v11_0_init_csb(adev);
2013                         return 0;
2014                 }
2015
2016                 adev->gfx.rlc.funcs->stop(adev);
2017
2018                 /* disable CG */
2019                 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);
2020
2021                 /* disable PG */
2022                 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);
2023
2024                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
2025                         /* legacy rlc firmware loading */
2026                         r = gfx_v11_0_rlc_load_microcode(adev);
2027                         if (r)
2028                                 return r;
2029                 }
2030
2031                 gfx_v11_0_init_csb(adev);
2032
2033                 adev->gfx.rlc.funcs->start(adev);
2034         }
2035         return 0;
2036 }
2037
2038 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr)
2039 {
2040         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2041         uint32_t tmp;
2042         int i;
2043
2044         /* Trigger an invalidation of the L1 instruction caches */
2045         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2046         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2047         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2048
2049         /* Wait for invalidation complete */
2050         for (i = 0; i < usec_timeout; i++) {
2051                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2052                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2053                                         INVALIDATE_CACHE_COMPLETE))
2054                         break;
2055                 udelay(1);
2056         }
2057
2058         if (i >= usec_timeout) {
2059                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2060                 return -EINVAL;
2061         }
2062
2063         if (amdgpu_emu_mode == 1)
2064                 adev->hdp.funcs->flush_hdp(adev, NULL);
2065
2066         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2067         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2068         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2069         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2070         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2071         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2072
2073         /* Program me ucode address into intruction cache address register */
2074         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2075                         lower_32_bits(addr) & 0xFFFFF000);
2076         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2077                         upper_32_bits(addr));
2078
2079         return 0;
2080 }
2081
2082 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr)
2083 {
2084         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2085         uint32_t tmp;
2086         int i;
2087
2088         /* Trigger an invalidation of the L1 instruction caches */
2089         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2090         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2091         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2092
2093         /* Wait for invalidation complete */
2094         for (i = 0; i < usec_timeout; i++) {
2095                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2096                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2097                                         INVALIDATE_CACHE_COMPLETE))
2098                         break;
2099                 udelay(1);
2100         }
2101
2102         if (i >= usec_timeout) {
2103                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2104                 return -EINVAL;
2105         }
2106
2107         if (amdgpu_emu_mode == 1)
2108                 adev->hdp.funcs->flush_hdp(adev, NULL);
2109
2110         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2111         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2112         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2113         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2114         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2115         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2116
2117         /* Program pfp ucode address into intruction cache address register */
2118         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2119                         lower_32_bits(addr) & 0xFFFFF000);
2120         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2121                         upper_32_bits(addr));
2122
2123         return 0;
2124 }
2125
2126 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr)
2127 {
2128         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2129         uint32_t tmp;
2130         int i;
2131
2132         /* Trigger an invalidation of the L1 instruction caches */
2133         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2134         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2135
2136         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2137
2138         /* Wait for invalidation complete */
2139         for (i = 0; i < usec_timeout; i++) {
2140                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2141                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2142                                         INVALIDATE_CACHE_COMPLETE))
2143                         break;
2144                 udelay(1);
2145         }
2146
2147         if (i >= usec_timeout) {
2148                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2149                 return -EINVAL;
2150         }
2151
2152         if (amdgpu_emu_mode == 1)
2153                 adev->hdp.funcs->flush_hdp(adev, NULL);
2154
2155         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2156         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2157         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2158         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2159         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2160
2161         /* Program mec1 ucode address into intruction cache address register */
2162         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,
2163                         lower_32_bits(addr) & 0xFFFFF000);
2164         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2165                         upper_32_bits(addr));
2166
2167         return 0;
2168 }
2169
2170 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2171 {
2172         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2173         uint32_t tmp;
2174         unsigned i, pipe_id;
2175         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2176
2177         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2178                 adev->gfx.pfp_fw->data;
2179
2180         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2181                 lower_32_bits(addr));
2182         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2183                 upper_32_bits(addr));
2184
2185         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2186         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2187         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2188         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2189         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2190
2191         /*
2192          * Programming any of the CP_PFP_IC_BASE registers
2193          * forces invalidation of the ME L1 I$. Wait for the
2194          * invalidation complete
2195          */
2196         for (i = 0; i < usec_timeout; i++) {
2197                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2198                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2199                         INVALIDATE_CACHE_COMPLETE))
2200                         break;
2201                 udelay(1);
2202         }
2203
2204         if (i >= usec_timeout) {
2205                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2206                 return -EINVAL;
2207         }
2208
2209         /* Prime the L1 instruction caches */
2210         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2211         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2212         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2213         /* Waiting for cache primed*/
2214         for (i = 0; i < usec_timeout; i++) {
2215                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2216                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2217                         ICACHE_PRIMED))
2218                         break;
2219                 udelay(1);
2220         }
2221
2222         if (i >= usec_timeout) {
2223                 dev_err(adev->dev, "failed to prime instruction cache\n");
2224                 return -EINVAL;
2225         }
2226
2227         mutex_lock(&adev->srbm_mutex);
2228         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2229                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2230                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2231                         (pfp_hdr->ucode_start_addr_hi << 30) |
2232                         (pfp_hdr->ucode_start_addr_lo >> 2));
2233                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2234                         pfp_hdr->ucode_start_addr_hi >> 2);
2235
2236                 /*
2237                  * Program CP_ME_CNTL to reset given PIPE to take
2238                  * effect of CP_PFP_PRGRM_CNTR_START.
2239                  */
2240                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2241                 if (pipe_id == 0)
2242                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2243                                         PFP_PIPE0_RESET, 1);
2244                 else
2245                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2246                                         PFP_PIPE1_RESET, 1);
2247                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2248
2249                 /* Clear pfp pipe0 reset bit. */
2250                 if (pipe_id == 0)
2251                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2252                                         PFP_PIPE0_RESET, 0);
2253                 else
2254                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2255                                         PFP_PIPE1_RESET, 0);
2256                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2257
2258                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2259                         lower_32_bits(addr2));
2260                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2261                         upper_32_bits(addr2));
2262         }
2263         soc21_grbm_select(adev, 0, 0, 0, 0);
2264         mutex_unlock(&adev->srbm_mutex);
2265
2266         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2267         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2268         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2269         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2270
2271         /* Invalidate the data caches */
2272         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2273         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2274         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2275
2276         for (i = 0; i < usec_timeout; i++) {
2277                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2278                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2279                         INVALIDATE_DCACHE_COMPLETE))
2280                         break;
2281                 udelay(1);
2282         }
2283
2284         if (i >= usec_timeout) {
2285                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2286                 return -EINVAL;
2287         }
2288
2289         return 0;
2290 }
2291
2292 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2293 {
2294         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2295         uint32_t tmp;
2296         unsigned i, pipe_id;
2297         const struct gfx_firmware_header_v2_0 *me_hdr;
2298
2299         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2300                 adev->gfx.me_fw->data;
2301
2302         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2303                 lower_32_bits(addr));
2304         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2305                 upper_32_bits(addr));
2306
2307         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2308         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2309         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2310         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2311         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2312
2313         /*
2314          * Programming any of the CP_ME_IC_BASE registers
2315          * forces invalidation of the ME L1 I$. Wait for the
2316          * invalidation complete
2317          */
2318         for (i = 0; i < usec_timeout; i++) {
2319                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2320                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2321                         INVALIDATE_CACHE_COMPLETE))
2322                         break;
2323                 udelay(1);
2324         }
2325
2326         if (i >= usec_timeout) {
2327                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2328                 return -EINVAL;
2329         }
2330
2331         /* Prime the instruction caches */
2332         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2333         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
2334         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2335
2336         /* Waiting for instruction cache primed*/
2337         for (i = 0; i < usec_timeout; i++) {
2338                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2339                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2340                         ICACHE_PRIMED))
2341                         break;
2342                 udelay(1);
2343         }
2344
2345         if (i >= usec_timeout) {
2346                 dev_err(adev->dev, "failed to prime instruction cache\n");
2347                 return -EINVAL;
2348         }
2349
2350         mutex_lock(&adev->srbm_mutex);
2351         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2352                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2353                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2354                         (me_hdr->ucode_start_addr_hi << 30) |
2355                         (me_hdr->ucode_start_addr_lo >> 2) );
2356                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2357                         me_hdr->ucode_start_addr_hi>>2);
2358
2359                 /*
2360                  * Program CP_ME_CNTL to reset given PIPE to take
2361                  * effect of CP_PFP_PRGRM_CNTR_START.
2362                  */
2363                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2364                 if (pipe_id == 0)
2365                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2366                                         ME_PIPE0_RESET, 1);
2367                 else
2368                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2369                                         ME_PIPE1_RESET, 1);
2370                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2371
2372                 /* Clear pfp pipe0 reset bit. */
2373                 if (pipe_id == 0)
2374                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2375                                         ME_PIPE0_RESET, 0);
2376                 else
2377                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2378                                         ME_PIPE1_RESET, 0);
2379                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2380
2381                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2382                         lower_32_bits(addr2));
2383                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2384                         upper_32_bits(addr2));
2385         }
2386         soc21_grbm_select(adev, 0, 0, 0, 0);
2387         mutex_unlock(&adev->srbm_mutex);
2388
2389         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2390         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2391         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2392         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2393
2394         /* Invalidate the data caches */
2395         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2396         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2397         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2398
2399         for (i = 0; i < usec_timeout; i++) {
2400                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2401                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2402                         INVALIDATE_DCACHE_COMPLETE))
2403                         break;
2404                 udelay(1);
2405         }
2406
2407         if (i >= usec_timeout) {
2408                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2409                 return -EINVAL;
2410         }
2411
2412         return 0;
2413 }
2414
2415 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2416 {
2417         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2418         uint32_t tmp;
2419         unsigned i;
2420         const struct gfx_firmware_header_v2_0 *mec_hdr;
2421
2422         mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2423                 adev->gfx.mec_fw->data;
2424
2425         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2426         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2427         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2428         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2429         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2430
2431         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
2432         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
2433         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
2434         WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
2435
2436         mutex_lock(&adev->srbm_mutex);
2437         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2438                 soc21_grbm_select(adev, 1, i, 0, 0);
2439
2440                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2);
2441                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
2442                      upper_32_bits(addr2));
2443
2444                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2445                                         mec_hdr->ucode_start_addr_lo >> 2 |
2446                                         mec_hdr->ucode_start_addr_hi << 30);
2447                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2448                                         mec_hdr->ucode_start_addr_hi >> 2);
2449
2450                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr);
2451                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2452                      upper_32_bits(addr));
2453         }
2454         mutex_unlock(&adev->srbm_mutex);
2455         soc21_grbm_select(adev, 0, 0, 0, 0);
2456
2457         /* Trigger an invalidation of the L1 instruction caches */
2458         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2459         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2460         WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
2461
2462         /* Wait for invalidation complete */
2463         for (i = 0; i < usec_timeout; i++) {
2464                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2465                 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
2466                                        INVALIDATE_DCACHE_COMPLETE))
2467                         break;
2468                 udelay(1);
2469         }
2470
2471         if (i >= usec_timeout) {
2472                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2473                 return -EINVAL;
2474         }
2475
2476         /* Trigger an invalidation of the L1 instruction caches */
2477         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2478         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2479         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2480
2481         /* Wait for invalidation complete */
2482         for (i = 0; i < usec_timeout; i++) {
2483                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2484                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2485                                        INVALIDATE_CACHE_COMPLETE))
2486                         break;
2487                 udelay(1);
2488         }
2489
2490         if (i >= usec_timeout) {
2491                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2492                 return -EINVAL;
2493         }
2494
2495         return 0;
2496 }
2497
2498 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev)
2499 {
2500         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2501         const struct gfx_firmware_header_v2_0 *me_hdr;
2502         const struct gfx_firmware_header_v2_0 *mec_hdr;
2503         uint32_t pipe_id, tmp;
2504
2505         mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2506                 adev->gfx.mec_fw->data;
2507         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2508                 adev->gfx.me_fw->data;
2509         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2510                 adev->gfx.pfp_fw->data;
2511
2512         /* config pfp program start addr */
2513         for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2514                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2515                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2516                         (pfp_hdr->ucode_start_addr_hi << 30) |
2517                         (pfp_hdr->ucode_start_addr_lo >> 2));
2518                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2519                         pfp_hdr->ucode_start_addr_hi >> 2);
2520         }
2521         soc21_grbm_select(adev, 0, 0, 0, 0);
2522
2523         /* reset pfp pipe */
2524         tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2525         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);
2526         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);
2527         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2528
2529         /* clear pfp pipe reset */
2530         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);
2531         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);
2532         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2533
2534         /* config me program start addr */
2535         for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2536                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2537                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2538                         (me_hdr->ucode_start_addr_hi << 30) |
2539                         (me_hdr->ucode_start_addr_lo >> 2) );
2540                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2541                         me_hdr->ucode_start_addr_hi>>2);
2542         }
2543         soc21_grbm_select(adev, 0, 0, 0, 0);
2544
2545         /* reset me pipe */
2546         tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2547         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);
2548         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);
2549         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2550
2551         /* clear me pipe reset */
2552         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);
2553         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);
2554         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2555
2556         /* config mec program start addr */
2557         for (pipe_id = 0; pipe_id < 4; pipe_id++) {
2558                 soc21_grbm_select(adev, 1, pipe_id, 0, 0);
2559                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2560                                         mec_hdr->ucode_start_addr_lo >> 2 |
2561                                         mec_hdr->ucode_start_addr_hi << 30);
2562                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2563                                         mec_hdr->ucode_start_addr_hi >> 2);
2564         }
2565         soc21_grbm_select(adev, 0, 0, 0, 0);
2566
2567         /* reset mec pipe */
2568         tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2569         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);
2570         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);
2571         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);
2572         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);
2573         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2574
2575         /* clear mec pipe reset */
2576         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);
2577         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);
2578         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);
2579         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);
2580         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2581 }
2582
2583 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2584 {
2585         uint32_t cp_status;
2586         uint32_t bootload_status;
2587         int i, r;
2588         uint64_t addr, addr2;
2589
2590         for (i = 0; i < adev->usec_timeout; i++) {
2591                 cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
2592
2593                 if (amdgpu_ip_version(adev, GC_HWIP, 0) ==
2594                             IP_VERSION(11, 0, 1) ||
2595                     amdgpu_ip_version(adev, GC_HWIP, 0) ==
2596                             IP_VERSION(11, 0, 4) ||
2597                     amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0))
2598                         bootload_status = RREG32_SOC15(GC, 0,
2599                                         regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
2600                 else
2601                         bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);
2602
2603                 if ((cp_status == 0) &&
2604                     (REG_GET_FIELD(bootload_status,
2605                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2606                         break;
2607                 }
2608                 udelay(1);
2609         }
2610
2611         if (i >= adev->usec_timeout) {
2612                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2613                 return -ETIMEDOUT;
2614         }
2615
2616         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2617                 if (adev->gfx.rs64_enable) {
2618                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2619                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset;
2620                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2621                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset;
2622                         r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2);
2623                         if (r)
2624                                 return r;
2625                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2626                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset;
2627                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2628                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset;
2629                         r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2);
2630                         if (r)
2631                                 return r;
2632                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2633                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset;
2634                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2635                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset;
2636                         r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2);
2637                         if (r)
2638                                 return r;
2639                 } else {
2640                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2641                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset;
2642                         r = gfx_v11_0_config_me_cache(adev, addr);
2643                         if (r)
2644                                 return r;
2645                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2646                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset;
2647                         r = gfx_v11_0_config_pfp_cache(adev, addr);
2648                         if (r)
2649                                 return r;
2650                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2651                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset;
2652                         r = gfx_v11_0_config_mec_cache(adev, addr);
2653                         if (r)
2654                                 return r;
2655                 }
2656         }
2657
2658         return 0;
2659 }
2660
2661 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2662 {
2663         int i;
2664         u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2665
2666         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2667         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2668         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2669
2670         for (i = 0; i < adev->usec_timeout; i++) {
2671                 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)
2672                         break;
2673                 udelay(1);
2674         }
2675
2676         if (i >= adev->usec_timeout)
2677                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2678
2679         return 0;
2680 }
2681
2682 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
2683 {
2684         int r;
2685         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2686         const __le32 *fw_data;
2687         unsigned i, fw_size;
2688
2689         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2690                 adev->gfx.pfp_fw->data;
2691
2692         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2693
2694         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2695                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2696         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
2697
2698         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
2699                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2700                                       &adev->gfx.pfp.pfp_fw_obj,
2701                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
2702                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
2703         if (r) {
2704                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
2705                 gfx_v11_0_pfp_fini(adev);
2706                 return r;
2707         }
2708
2709         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2710
2711         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2712         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2713
2714         gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr);
2715
2716         WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0);
2717
2718         for (i = 0; i < pfp_hdr->jt_size; i++)
2719                 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA,
2720                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
2721
2722         WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2723
2724         return 0;
2725 }
2726
2727 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
2728 {
2729         int r;
2730         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2731         const __le32 *fw_ucode, *fw_data;
2732         unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2733         uint32_t tmp;
2734         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2735
2736         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2737                 adev->gfx.pfp_fw->data;
2738
2739         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2740
2741         /* instruction */
2742         fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data +
2743                 le32_to_cpu(pfp_hdr->ucode_offset_bytes));
2744         fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes);
2745         /* data */
2746         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2747                 le32_to_cpu(pfp_hdr->data_offset_bytes));
2748         fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes);
2749
2750         /* 64kb align */
2751         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2752                                       64 * 1024,
2753                                       AMDGPU_GEM_DOMAIN_VRAM |
2754                                       AMDGPU_GEM_DOMAIN_GTT,
2755                                       &adev->gfx.pfp.pfp_fw_obj,
2756                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
2757                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
2758         if (r) {
2759                 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r);
2760                 gfx_v11_0_pfp_fini(adev);
2761                 return r;
2762         }
2763
2764         r = amdgpu_bo_create_reserved(adev, fw_data_size,
2765                                       64 * 1024,
2766                                       AMDGPU_GEM_DOMAIN_VRAM |
2767                                       AMDGPU_GEM_DOMAIN_GTT,
2768                                       &adev->gfx.pfp.pfp_fw_data_obj,
2769                                       &adev->gfx.pfp.pfp_fw_data_gpu_addr,
2770                                       (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
2771         if (r) {
2772                 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r);
2773                 gfx_v11_0_pfp_fini(adev);
2774                 return r;
2775         }
2776
2777         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size);
2778         memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size);
2779
2780         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2781         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj);
2782         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2783         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
2784
2785         if (amdgpu_emu_mode == 1)
2786                 adev->hdp.funcs->flush_hdp(adev, NULL);
2787
2788         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2789                 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2790         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2791                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2792
2793         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2794         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2795         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2796         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2797         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2798
2799         /*
2800          * Programming any of the CP_PFP_IC_BASE registers
2801          * forces invalidation of the ME L1 I$. Wait for the
2802          * invalidation complete
2803          */
2804         for (i = 0; i < usec_timeout; i++) {
2805                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2806                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2807                         INVALIDATE_CACHE_COMPLETE))
2808                         break;
2809                 udelay(1);
2810         }
2811
2812         if (i >= usec_timeout) {
2813                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2814                 return -EINVAL;
2815         }
2816
2817         /* Prime the L1 instruction caches */
2818         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2819         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2820         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2821         /* Waiting for cache primed*/
2822         for (i = 0; i < usec_timeout; i++) {
2823                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2824                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2825                         ICACHE_PRIMED))
2826                         break;
2827                 udelay(1);
2828         }
2829
2830         if (i >= usec_timeout) {
2831                 dev_err(adev->dev, "failed to prime instruction cache\n");
2832                 return -EINVAL;
2833         }
2834
2835         mutex_lock(&adev->srbm_mutex);
2836         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2837                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2838                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2839                         (pfp_hdr->ucode_start_addr_hi << 30) |
2840                         (pfp_hdr->ucode_start_addr_lo >> 2) );
2841                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2842                         pfp_hdr->ucode_start_addr_hi>>2);
2843
2844                 /*
2845                  * Program CP_ME_CNTL to reset given PIPE to take
2846                  * effect of CP_PFP_PRGRM_CNTR_START.
2847                  */
2848                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2849                 if (pipe_id == 0)
2850                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2851                                         PFP_PIPE0_RESET, 1);
2852                 else
2853                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2854                                         PFP_PIPE1_RESET, 1);
2855                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2856
2857                 /* Clear pfp pipe0 reset bit. */
2858                 if (pipe_id == 0)
2859                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2860                                         PFP_PIPE0_RESET, 0);
2861                 else
2862                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2863                                         PFP_PIPE1_RESET, 0);
2864                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2865
2866                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2867                         lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2868                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2869                         upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2870         }
2871         soc21_grbm_select(adev, 0, 0, 0, 0);
2872         mutex_unlock(&adev->srbm_mutex);
2873
2874         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2875         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2876         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2877         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2878
2879         /* Invalidate the data caches */
2880         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2881         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2882         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2883
2884         for (i = 0; i < usec_timeout; i++) {
2885                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2886                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2887                         INVALIDATE_DCACHE_COMPLETE))
2888                         break;
2889                 udelay(1);
2890         }
2891
2892         if (i >= usec_timeout) {
2893                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2894                 return -EINVAL;
2895         }
2896
2897         return 0;
2898 }
2899
2900 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
2901 {
2902         int r;
2903         const struct gfx_firmware_header_v1_0 *me_hdr;
2904         const __le32 *fw_data;
2905         unsigned i, fw_size;
2906
2907         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2908                 adev->gfx.me_fw->data;
2909
2910         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2911
2912         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2913                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2914         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
2915
2916         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
2917                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2918                                       &adev->gfx.me.me_fw_obj,
2919                                       &adev->gfx.me.me_fw_gpu_addr,
2920                                       (void **)&adev->gfx.me.me_fw_ptr);
2921         if (r) {
2922                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
2923                 gfx_v11_0_me_fini(adev);
2924                 return r;
2925         }
2926
2927         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2928
2929         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2930         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2931
2932         gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr);
2933
2934         WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0);
2935
2936         for (i = 0; i < me_hdr->jt_size; i++)
2937                 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA,
2938                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
2939
2940         WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
2941
2942         return 0;
2943 }
2944
2945 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
2946 {
2947         int r;
2948         const struct gfx_firmware_header_v2_0 *me_hdr;
2949         const __le32 *fw_ucode, *fw_data;
2950         unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2951         uint32_t tmp;
2952         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2953
2954         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2955                 adev->gfx.me_fw->data;
2956
2957         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2958
2959         /* instruction */
2960         fw_ucode = (const __le32 *)(adev->gfx.me_fw->data +
2961                 le32_to_cpu(me_hdr->ucode_offset_bytes));
2962         fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes);
2963         /* data */
2964         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2965                 le32_to_cpu(me_hdr->data_offset_bytes));
2966         fw_data_size = le32_to_cpu(me_hdr->data_size_bytes);
2967
2968         /* 64kb align*/
2969         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2970                                       64 * 1024,
2971                                       AMDGPU_GEM_DOMAIN_VRAM |
2972                                       AMDGPU_GEM_DOMAIN_GTT,
2973                                       &adev->gfx.me.me_fw_obj,
2974                                       &adev->gfx.me.me_fw_gpu_addr,
2975                                       (void **)&adev->gfx.me.me_fw_ptr);
2976         if (r) {
2977                 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r);
2978                 gfx_v11_0_me_fini(adev);
2979                 return r;
2980         }
2981
2982         r = amdgpu_bo_create_reserved(adev, fw_data_size,
2983                                       64 * 1024,
2984                                       AMDGPU_GEM_DOMAIN_VRAM |
2985                                       AMDGPU_GEM_DOMAIN_GTT,
2986                                       &adev->gfx.me.me_fw_data_obj,
2987                                       &adev->gfx.me.me_fw_data_gpu_addr,
2988                                       (void **)&adev->gfx.me.me_fw_data_ptr);
2989         if (r) {
2990                 dev_err(adev->dev, "(%d) failed to create me data bo\n", r);
2991                 gfx_v11_0_pfp_fini(adev);
2992                 return r;
2993         }
2994
2995         memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size);
2996         memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size);
2997
2998         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2999         amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj);
3000         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
3001         amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
3002
3003         if (amdgpu_emu_mode == 1)
3004                 adev->hdp.funcs->flush_hdp(adev, NULL);
3005
3006         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
3007                 lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
3008         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
3009                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
3010
3011         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
3012         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
3013         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
3014         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
3015         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
3016
3017         /*
3018          * Programming any of the CP_ME_IC_BASE registers
3019          * forces invalidation of the ME L1 I$. Wait for the
3020          * invalidation complete
3021          */
3022         for (i = 0; i < usec_timeout; i++) {
3023                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
3024                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
3025                         INVALIDATE_CACHE_COMPLETE))
3026                         break;
3027                 udelay(1);
3028         }
3029
3030         if (i >= usec_timeout) {
3031                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3032                 return -EINVAL;
3033         }
3034
3035         /* Prime the instruction caches */
3036         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
3037         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
3038         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
3039
3040         /* Waiting for instruction cache primed*/
3041         for (i = 0; i < usec_timeout; i++) {
3042                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
3043                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
3044                         ICACHE_PRIMED))
3045                         break;
3046                 udelay(1);
3047         }
3048
3049         if (i >= usec_timeout) {
3050                 dev_err(adev->dev, "failed to prime instruction cache\n");
3051                 return -EINVAL;
3052         }
3053
3054         mutex_lock(&adev->srbm_mutex);
3055         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
3056                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
3057                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
3058                         (me_hdr->ucode_start_addr_hi << 30) |
3059                         (me_hdr->ucode_start_addr_lo >> 2) );
3060                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
3061                         me_hdr->ucode_start_addr_hi>>2);
3062
3063                 /*
3064                  * Program CP_ME_CNTL to reset given PIPE to take
3065                  * effect of CP_PFP_PRGRM_CNTR_START.
3066                  */
3067                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
3068                 if (pipe_id == 0)
3069                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3070                                         ME_PIPE0_RESET, 1);
3071                 else
3072                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3073                                         ME_PIPE1_RESET, 1);
3074                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
3075
3076                 /* Clear pfp pipe0 reset bit. */
3077                 if (pipe_id == 0)
3078                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3079                                         ME_PIPE0_RESET, 0);
3080                 else
3081                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3082                                         ME_PIPE1_RESET, 0);
3083                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
3084
3085                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
3086                         lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
3087                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
3088                         upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
3089         }
3090         soc21_grbm_select(adev, 0, 0, 0, 0);
3091         mutex_unlock(&adev->srbm_mutex);
3092
3093         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
3094         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
3095         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
3096         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
3097
3098         /* Invalidate the data caches */
3099         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
3100         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
3101         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
3102
3103         for (i = 0; i < usec_timeout; i++) {
3104                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
3105                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
3106                         INVALIDATE_DCACHE_COMPLETE))
3107                         break;
3108                 udelay(1);
3109         }
3110
3111         if (i >= usec_timeout) {
3112                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
3113                 return -EINVAL;
3114         }
3115
3116         return 0;
3117 }
3118
3119 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
3120 {
3121         int r;
3122
3123         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw)
3124                 return -EINVAL;
3125
3126         gfx_v11_0_cp_gfx_enable(adev, false);
3127
3128         if (adev->gfx.rs64_enable)
3129                 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev);
3130         else
3131                 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev);
3132         if (r) {
3133                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
3134                 return r;
3135         }
3136
3137         if (adev->gfx.rs64_enable)
3138                 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev);
3139         else
3140                 r = gfx_v11_0_cp_gfx_load_me_microcode(adev);
3141         if (r) {
3142                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
3143                 return r;
3144         }
3145
3146         return 0;
3147 }
3148
3149 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev)
3150 {
3151         struct amdgpu_ring *ring;
3152         const struct cs_section_def *sect = NULL;
3153         const struct cs_extent_def *ext = NULL;
3154         int r, i;
3155         int ctx_reg_offset;
3156
3157         /* init the CP */
3158         WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,
3159                      adev->gfx.config.max_hw_contexts - 1);
3160         WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);
3161
3162         if (!amdgpu_async_gfx_ring)
3163                 gfx_v11_0_cp_gfx_enable(adev, true);
3164
3165         ring = &adev->gfx.gfx_ring[0];
3166         r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev));
3167         if (r) {
3168                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3169                 return r;
3170         }
3171
3172         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3173         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3174
3175         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3176         amdgpu_ring_write(ring, 0x80000000);
3177         amdgpu_ring_write(ring, 0x80000000);
3178
3179         for (sect = gfx11_cs_data; sect->section != NULL; ++sect) {
3180                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3181                         if (sect->id == SECT_CONTEXT) {
3182                                 amdgpu_ring_write(ring,
3183                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
3184                                                           ext->reg_count));
3185                                 amdgpu_ring_write(ring, ext->reg_index -
3186                                                   PACKET3_SET_CONTEXT_REG_START);
3187                                 for (i = 0; i < ext->reg_count; i++)
3188                                         amdgpu_ring_write(ring, ext->extent[i]);
3189                         }
3190                 }
3191         }
3192
3193         ctx_reg_offset =
3194                 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
3195         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
3196         amdgpu_ring_write(ring, ctx_reg_offset);
3197         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
3198
3199         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3200         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3201
3202         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3203         amdgpu_ring_write(ring, 0);
3204
3205         amdgpu_ring_commit(ring);
3206
3207         /* submit cs packet to copy state 0 to next available state */
3208         if (adev->gfx.num_gfx_rings > 1) {
3209                 /* maximum supported gfx ring is 2 */
3210                 ring = &adev->gfx.gfx_ring[1];
3211                 r = amdgpu_ring_alloc(ring, 2);
3212                 if (r) {
3213                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3214                         return r;
3215                 }
3216
3217                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3218                 amdgpu_ring_write(ring, 0);
3219
3220                 amdgpu_ring_commit(ring);
3221         }
3222         return 0;
3223 }
3224
3225 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
3226                                          CP_PIPE_ID pipe)
3227 {
3228         u32 tmp;
3229
3230         tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
3231         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
3232
3233         WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
3234 }
3235
3236 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
3237                                           struct amdgpu_ring *ring)
3238 {
3239         u32 tmp;
3240
3241         tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
3242         if (ring->use_doorbell) {
3243                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3244                                     DOORBELL_OFFSET, ring->doorbell_index);
3245                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3246                                     DOORBELL_EN, 1);
3247         } else {
3248                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3249                                     DOORBELL_EN, 0);
3250         }
3251         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);
3252
3253         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
3254                             DOORBELL_RANGE_LOWER, ring->doorbell_index);
3255         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);
3256
3257         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
3258                      CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
3259 }
3260
3261 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev)
3262 {
3263         struct amdgpu_ring *ring;
3264         u32 tmp;
3265         u32 rb_bufsz;
3266         u64 rb_addr, rptr_addr, wptr_gpu_addr;
3267
3268         /* Set the write pointer delay */
3269         WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);
3270
3271         /* set the RB to use vmid 0 */
3272         WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);
3273
3274         /* Init gfx ring 0 for pipe 0 */
3275         mutex_lock(&adev->srbm_mutex);
3276         gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
3277
3278         /* Set ring buffer size */
3279         ring = &adev->gfx.gfx_ring[0];
3280         rb_bufsz = order_base_2(ring->ring_size / 8);
3281         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3282         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3283         WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
3284
3285         /* Initialize the ring buffer's write pointers */
3286         ring->wptr = 0;
3287         WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));
3288         WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3289
3290         /* set the wb address wether it's enabled or not */
3291         rptr_addr = ring->rptr_gpu_addr;
3292         WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
3293         WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
3294                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3295
3296         wptr_gpu_addr = ring->wptr_gpu_addr;
3297         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
3298                      lower_32_bits(wptr_gpu_addr));
3299         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
3300                      upper_32_bits(wptr_gpu_addr));
3301
3302         mdelay(1);
3303         WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
3304
3305         rb_addr = ring->gpu_addr >> 8;
3306         WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);
3307         WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));
3308
3309         WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);
3310
3311         gfx_v11_0_cp_gfx_set_doorbell(adev, ring);
3312         mutex_unlock(&adev->srbm_mutex);
3313
3314         /* Init gfx ring 1 for pipe 1 */
3315         if (adev->gfx.num_gfx_rings > 1) {
3316                 mutex_lock(&adev->srbm_mutex);
3317                 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
3318                 /* maximum supported gfx ring is 2 */
3319                 ring = &adev->gfx.gfx_ring[1];
3320                 rb_bufsz = order_base_2(ring->ring_size / 8);
3321                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
3322                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
3323                 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
3324                 /* Initialize the ring buffer's write pointers */
3325                 ring->wptr = 0;
3326                 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr));
3327                 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
3328                 /* Set the wb address wether it's enabled or not */
3329                 rptr_addr = ring->rptr_gpu_addr;
3330                 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
3331                 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
3332                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3333                 wptr_gpu_addr = ring->wptr_gpu_addr;
3334                 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
3335                              lower_32_bits(wptr_gpu_addr));
3336                 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
3337                              upper_32_bits(wptr_gpu_addr));
3338
3339                 mdelay(1);
3340                 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
3341
3342                 rb_addr = ring->gpu_addr >> 8;
3343                 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr);
3344                 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr));
3345                 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1);
3346
3347                 gfx_v11_0_cp_gfx_set_doorbell(adev, ring);
3348                 mutex_unlock(&adev->srbm_mutex);
3349         }
3350         /* Switch to pipe 0 */
3351         mutex_lock(&adev->srbm_mutex);
3352         gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
3353         mutex_unlock(&adev->srbm_mutex);
3354
3355         /* start the ring */
3356         gfx_v11_0_cp_gfx_start(adev);
3357
3358         return 0;
3359 }
3360
3361 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3362 {
3363         u32 data;
3364
3365         if (adev->gfx.rs64_enable) {
3366                 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
3367                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,
3368                                                          enable ? 0 : 1);
3369                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,
3370                                                          enable ? 0 : 1);
3371                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,
3372                                                          enable ? 0 : 1);
3373                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,
3374                                                          enable ? 0 : 1);
3375                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,
3376                                                          enable ? 0 : 1);
3377                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,
3378                                                          enable ? 1 : 0);
3379                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,
3380                                                          enable ? 1 : 0);
3381                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,
3382                                                          enable ? 1 : 0);
3383                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,
3384                                                          enable ? 1 : 0);
3385                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,
3386                                                          enable ? 0 : 1);
3387                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);
3388         } else {
3389                 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL);
3390
3391                 if (enable) {
3392                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0);
3393                         if (!adev->enable_mes_kiq)
3394                                 data = REG_SET_FIELD(data, CP_MEC_CNTL,
3395                                                      MEC_ME2_HALT, 0);
3396                 } else {
3397                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1);
3398                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1);
3399                 }
3400                 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data);
3401         }
3402
3403         udelay(50);
3404 }
3405
3406 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3407 {
3408         const struct gfx_firmware_header_v1_0 *mec_hdr;
3409         const __le32 *fw_data;
3410         unsigned i, fw_size;
3411         u32 *fw = NULL;
3412         int r;
3413
3414         if (!adev->gfx.mec_fw)
3415                 return -EINVAL;
3416
3417         gfx_v11_0_cp_compute_enable(adev, false);
3418
3419         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3420         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3421
3422         fw_data = (const __le32 *)
3423                 (adev->gfx.mec_fw->data +
3424                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3425         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
3426
3427         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
3428                                           PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
3429                                           &adev->gfx.mec.mec_fw_obj,
3430                                           &adev->gfx.mec.mec_fw_gpu_addr,
3431                                           (void **)&fw);
3432         if (r) {
3433                 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
3434                 gfx_v11_0_mec_fini(adev);
3435                 return r;
3436         }
3437
3438         memcpy(fw, fw_data, fw_size);
3439
3440         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3441         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3442
3443         gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr);
3444
3445         /* MEC1 */
3446         WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0);
3447
3448         for (i = 0; i < mec_hdr->jt_size; i++)
3449                 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA,
3450                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
3451
3452         WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
3453
3454         return 0;
3455 }
3456
3457 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev)
3458 {
3459         const struct gfx_firmware_header_v2_0 *mec_hdr;
3460         const __le32 *fw_ucode, *fw_data;
3461         u32 tmp, fw_ucode_size, fw_data_size;
3462         u32 i, usec_timeout = 50000; /* Wait for 50 ms */
3463         u32 *fw_ucode_ptr, *fw_data_ptr;
3464         int r;
3465
3466         if (!adev->gfx.mec_fw)
3467                 return -EINVAL;
3468
3469         gfx_v11_0_cp_compute_enable(adev, false);
3470
3471         mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data;
3472         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3473
3474         fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data +
3475                                 le32_to_cpu(mec_hdr->ucode_offset_bytes));
3476         fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes);
3477
3478         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
3479                                 le32_to_cpu(mec_hdr->data_offset_bytes));
3480         fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes);
3481
3482         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
3483                                       64 * 1024,
3484                                       AMDGPU_GEM_DOMAIN_VRAM |
3485                                       AMDGPU_GEM_DOMAIN_GTT,
3486                                       &adev->gfx.mec.mec_fw_obj,
3487                                       &adev->gfx.mec.mec_fw_gpu_addr,
3488                                       (void **)&fw_ucode_ptr);
3489         if (r) {
3490                 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
3491                 gfx_v11_0_mec_fini(adev);
3492                 return r;
3493         }
3494
3495         r = amdgpu_bo_create_reserved(adev, fw_data_size,
3496                                       64 * 1024,
3497                                       AMDGPU_GEM_DOMAIN_VRAM |
3498                                       AMDGPU_GEM_DOMAIN_GTT,
3499                                       &adev->gfx.mec.mec_fw_data_obj,
3500                                       &adev->gfx.mec.mec_fw_data_gpu_addr,
3501                                       (void **)&fw_data_ptr);
3502         if (r) {
3503                 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
3504                 gfx_v11_0_mec_fini(adev);
3505                 return r;
3506         }
3507
3508         memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size);
3509         memcpy(fw_data_ptr, fw_data, fw_data_size);
3510
3511         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3512         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj);
3513         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3514         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj);
3515
3516         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
3517         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
3518         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
3519         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
3520         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
3521
3522         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
3523         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
3524         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
3525         WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
3526
3527         mutex_lock(&adev->srbm_mutex);
3528         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
3529                 soc21_grbm_select(adev, 1, i, 0, 0);
3530
3531                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr);
3532                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
3533                      upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr));
3534
3535                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
3536                                         mec_hdr->ucode_start_addr_lo >> 2 |
3537                                         mec_hdr->ucode_start_addr_hi << 30);
3538                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
3539                                         mec_hdr->ucode_start_addr_hi >> 2);
3540
3541                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr);
3542                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
3543                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
3544         }
3545         mutex_unlock(&adev->srbm_mutex);
3546         soc21_grbm_select(adev, 0, 0, 0, 0);
3547
3548         /* Trigger an invalidation of the L1 instruction caches */
3549         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
3550         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
3551         WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
3552
3553         /* Wait for invalidation complete */
3554         for (i = 0; i < usec_timeout; i++) {
3555                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
3556                 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
3557                                        INVALIDATE_DCACHE_COMPLETE))
3558                         break;
3559                 udelay(1);
3560         }
3561
3562         if (i >= usec_timeout) {
3563                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3564                 return -EINVAL;
3565         }
3566
3567         /* Trigger an invalidation of the L1 instruction caches */
3568         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
3569         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
3570         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
3571
3572         /* Wait for invalidation complete */
3573         for (i = 0; i < usec_timeout; i++) {
3574                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
3575                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
3576                                        INVALIDATE_CACHE_COMPLETE))
3577                         break;
3578                 udelay(1);
3579         }
3580
3581         if (i >= usec_timeout) {
3582                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3583                 return -EINVAL;
3584         }
3585
3586         return 0;
3587 }
3588
3589 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring)
3590 {
3591         uint32_t tmp;
3592         struct amdgpu_device *adev = ring->adev;
3593
3594         /* tell RLC which is KIQ queue */
3595         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
3596         tmp &= 0xffffff00;
3597         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
3598         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3599         tmp |= 0x80;
3600         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3601 }
3602
3603 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev)
3604 {
3605         /* set graphics engine doorbell range */
3606         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,
3607                      (adev->doorbell_index.gfx_ring0 * 2) << 2);
3608         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
3609                      (adev->doorbell_index.gfx_userqueue_end * 2) << 2);
3610
3611         /* set compute engine doorbell range */
3612         WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3613                      (adev->doorbell_index.kiq * 2) << 2);
3614         WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3615                      (adev->doorbell_index.userqueue_end * 2) << 2);
3616 }
3617
3618 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
3619                                   struct amdgpu_mqd_prop *prop)
3620 {
3621         struct v11_gfx_mqd *mqd = m;
3622         uint64_t hqd_gpu_addr, wb_gpu_addr;
3623         uint32_t tmp;
3624         uint32_t rb_bufsz;
3625
3626         /* set up gfx hqd wptr */
3627         mqd->cp_gfx_hqd_wptr = 0;
3628         mqd->cp_gfx_hqd_wptr_hi = 0;
3629
3630         /* set the pointer to the MQD */
3631         mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
3632         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3633
3634         /* set up mqd control */
3635         tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL);
3636         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
3637         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
3638         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
3639         mqd->cp_gfx_mqd_control = tmp;
3640
3641         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
3642         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID);
3643         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
3644         mqd->cp_gfx_hqd_vmid = 0;
3645
3646         /* set up default queue priority level
3647          * 0x0 = low priority, 0x1 = high priority */
3648         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY);
3649         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
3650         mqd->cp_gfx_hqd_queue_priority = tmp;
3651
3652         /* set up time quantum */
3653         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM);
3654         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
3655         mqd->cp_gfx_hqd_quantum = tmp;
3656
3657         /* set up gfx hqd base. this is similar as CP_RB_BASE */
3658         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3659         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
3660         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
3661
3662         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
3663         wb_gpu_addr = prop->rptr_gpu_addr;
3664         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3665         mqd->cp_gfx_hqd_rptr_addr_hi =
3666                 upper_32_bits(wb_gpu_addr) & 0xffff;
3667
3668         /* set up rb_wptr_poll addr */
3669         wb_gpu_addr = prop->wptr_gpu_addr;
3670         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3671         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3672
3673         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3674         rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
3675         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL);
3676         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3677         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3678 #ifdef __BIG_ENDIAN
3679         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3680 #endif
3681         mqd->cp_gfx_hqd_cntl = tmp;
3682
3683         /* set up cp_doorbell_control */
3684         tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
3685         if (prop->use_doorbell) {
3686                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3687                                     DOORBELL_OFFSET, prop->doorbell_index);
3688                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3689                                     DOORBELL_EN, 1);
3690         } else
3691                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3692                                     DOORBELL_EN, 0);
3693         mqd->cp_rb_doorbell_control = tmp;
3694
3695         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3696         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR);
3697
3698         /* active the queue */
3699         mqd->cp_gfx_hqd_active = 1;
3700
3701         return 0;
3702 }
3703
3704 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring)
3705 {
3706         struct amdgpu_device *adev = ring->adev;
3707         struct v11_gfx_mqd *mqd = ring->mqd_ptr;
3708         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3709
3710         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
3711                 memset((void *)mqd, 0, sizeof(*mqd));
3712                 mutex_lock(&adev->srbm_mutex);
3713                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3714                 amdgpu_ring_init_mqd(ring);
3715                 soc21_grbm_select(adev, 0, 0, 0, 0);
3716                 mutex_unlock(&adev->srbm_mutex);
3717                 if (adev->gfx.me.mqd_backup[mqd_idx])
3718                         memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3719         } else {
3720                 /* restore mqd with the backup copy */
3721                 if (adev->gfx.me.mqd_backup[mqd_idx])
3722                         memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3723                 /* reset the ring */
3724                 ring->wptr = 0;
3725                 *ring->wptr_cpu_addr = 0;
3726                 amdgpu_ring_clear_ring(ring);
3727         }
3728
3729         return 0;
3730 }
3731
3732 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3733 {
3734         int r, i;
3735         struct amdgpu_ring *ring;
3736
3737         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3738                 ring = &adev->gfx.gfx_ring[i];
3739
3740                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3741                 if (unlikely(r != 0))
3742                         return r;
3743
3744                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3745                 if (!r) {
3746                         r = gfx_v11_0_gfx_init_queue(ring);
3747                         amdgpu_bo_kunmap(ring->mqd_obj);
3748                         ring->mqd_ptr = NULL;
3749                 }
3750                 amdgpu_bo_unreserve(ring->mqd_obj);
3751                 if (r)
3752                         return r;
3753         }
3754
3755         r = amdgpu_gfx_enable_kgq(adev, 0);
3756         if (r)
3757                 return r;
3758
3759         return gfx_v11_0_cp_gfx_start(adev);
3760 }
3761
3762 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
3763                                       struct amdgpu_mqd_prop *prop)
3764 {
3765         struct v11_compute_mqd *mqd = m;
3766         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3767         uint32_t tmp;
3768
3769         mqd->header = 0xC0310800;
3770         mqd->compute_pipelinestat_enable = 0x00000001;
3771         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3772         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3773         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3774         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3775         mqd->compute_misc_reserved = 0x00000007;
3776
3777         eop_base_addr = prop->eop_gpu_addr >> 8;
3778         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3779         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3780
3781         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3782         tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL);
3783         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3784                         (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1));
3785
3786         mqd->cp_hqd_eop_control = tmp;
3787
3788         /* enable doorbell? */
3789         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
3790
3791         if (prop->use_doorbell) {
3792                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3793                                     DOORBELL_OFFSET, prop->doorbell_index);
3794                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3795                                     DOORBELL_EN, 1);
3796                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3797                                     DOORBELL_SOURCE, 0);
3798                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3799                                     DOORBELL_HIT, 0);
3800         } else {
3801                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3802                                     DOORBELL_EN, 0);
3803         }
3804
3805         mqd->cp_hqd_pq_doorbell_control = tmp;
3806
3807         /* disable the queue if it's active */
3808         mqd->cp_hqd_dequeue_request = 0;
3809         mqd->cp_hqd_pq_rptr = 0;
3810         mqd->cp_hqd_pq_wptr_lo = 0;
3811         mqd->cp_hqd_pq_wptr_hi = 0;
3812
3813         /* set the pointer to the MQD */
3814         mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
3815         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3816
3817         /* set MQD vmid to 0 */
3818         tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
3819         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3820         mqd->cp_mqd_control = tmp;
3821
3822         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3823         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3824         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3825         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3826
3827         /* set up the HQD, this is similar to CP_RB0_CNTL */
3828         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL);
3829         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3830                             (order_base_2(prop->queue_size / 4) - 1));
3831         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3832                             (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
3833         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3834         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3835         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3836         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3837         mqd->cp_hqd_pq_control = tmp;
3838
3839         /* set the wb address whether it's enabled or not */
3840         wb_gpu_addr = prop->rptr_gpu_addr;
3841         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3842         mqd->cp_hqd_pq_rptr_report_addr_hi =
3843                 upper_32_bits(wb_gpu_addr) & 0xffff;
3844
3845         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3846         wb_gpu_addr = prop->wptr_gpu_addr;
3847         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3848         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3849
3850         tmp = 0;
3851         /* enable the doorbell if requested */
3852         if (prop->use_doorbell) {
3853                 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
3854                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3855                                 DOORBELL_OFFSET, prop->doorbell_index);
3856
3857                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3858                                     DOORBELL_EN, 1);
3859                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3860                                     DOORBELL_SOURCE, 0);
3861                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3862                                     DOORBELL_HIT, 0);
3863         }
3864
3865         mqd->cp_hqd_pq_doorbell_control = tmp;
3866
3867         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3868         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR);
3869
3870         /* set the vmid for the queue */
3871         mqd->cp_hqd_vmid = 0;
3872
3873         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE);
3874         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
3875         mqd->cp_hqd_persistent_state = tmp;
3876
3877         /* set MIN_IB_AVAIL_SIZE */
3878         tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL);
3879         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3880         mqd->cp_hqd_ib_control = tmp;
3881
3882         /* set static priority for a compute queue/ring */
3883         mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
3884         mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
3885
3886         mqd->cp_hqd_active = prop->hqd_active;
3887
3888         return 0;
3889 }
3890
3891 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring)
3892 {
3893         struct amdgpu_device *adev = ring->adev;
3894         struct v11_compute_mqd *mqd = ring->mqd_ptr;
3895         int j;
3896
3897         /* inactivate the queue */
3898         if (amdgpu_sriov_vf(adev))
3899                 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
3900
3901         /* disable wptr polling */
3902         WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3903
3904         /* write the EOP addr */
3905         WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,
3906                mqd->cp_hqd_eop_base_addr_lo);
3907         WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,
3908                mqd->cp_hqd_eop_base_addr_hi);
3909
3910         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3911         WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,
3912                mqd->cp_hqd_eop_control);
3913
3914         /* enable doorbell? */
3915         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3916                mqd->cp_hqd_pq_doorbell_control);
3917
3918         /* disable the queue if it's active */
3919         if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
3920                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
3921                 for (j = 0; j < adev->usec_timeout; j++) {
3922                         if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
3923                                 break;
3924                         udelay(1);
3925                 }
3926                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
3927                        mqd->cp_hqd_dequeue_request);
3928                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,
3929                        mqd->cp_hqd_pq_rptr);
3930                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3931                        mqd->cp_hqd_pq_wptr_lo);
3932                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3933                        mqd->cp_hqd_pq_wptr_hi);
3934         }
3935
3936         /* set the pointer to the MQD */
3937         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,
3938                mqd->cp_mqd_base_addr_lo);
3939         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,
3940                mqd->cp_mqd_base_addr_hi);
3941
3942         /* set MQD vmid to 0 */
3943         WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,
3944                mqd->cp_mqd_control);
3945
3946         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3947         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,
3948                mqd->cp_hqd_pq_base_lo);
3949         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,
3950                mqd->cp_hqd_pq_base_hi);
3951
3952         /* set up the HQD, this is similar to CP_RB0_CNTL */
3953         WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,
3954                mqd->cp_hqd_pq_control);
3955
3956         /* set the wb address whether it's enabled or not */
3957         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
3958                 mqd->cp_hqd_pq_rptr_report_addr_lo);
3959         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3960                 mqd->cp_hqd_pq_rptr_report_addr_hi);
3961
3962         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3963         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
3964                mqd->cp_hqd_pq_wptr_poll_addr_lo);
3965         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3966                mqd->cp_hqd_pq_wptr_poll_addr_hi);
3967
3968         /* enable the doorbell if requested */
3969         if (ring->use_doorbell) {
3970                 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3971                         (adev->doorbell_index.kiq * 2) << 2);
3972                 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3973                         (adev->doorbell_index.userqueue_end * 2) << 2);
3974         }
3975
3976         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3977                mqd->cp_hqd_pq_doorbell_control);
3978
3979         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3980         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3981                mqd->cp_hqd_pq_wptr_lo);
3982         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3983                mqd->cp_hqd_pq_wptr_hi);
3984
3985         /* set the vmid for the queue */
3986         WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);
3987
3988         WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,
3989                mqd->cp_hqd_persistent_state);
3990
3991         /* activate the queue */
3992         WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,
3993                mqd->cp_hqd_active);
3994
3995         if (ring->use_doorbell)
3996                 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3997
3998         return 0;
3999 }
4000
4001 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring)
4002 {
4003         struct amdgpu_device *adev = ring->adev;
4004         struct v11_compute_mqd *mqd = ring->mqd_ptr;
4005
4006         gfx_v11_0_kiq_setting(ring);
4007
4008         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
4009                 /* reset MQD to a clean status */
4010                 if (adev->gfx.kiq[0].mqd_backup)
4011                         memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
4012
4013                 /* reset ring buffer */
4014                 ring->wptr = 0;
4015                 amdgpu_ring_clear_ring(ring);
4016
4017                 mutex_lock(&adev->srbm_mutex);
4018                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4019                 gfx_v11_0_kiq_init_register(ring);
4020                 soc21_grbm_select(adev, 0, 0, 0, 0);
4021                 mutex_unlock(&adev->srbm_mutex);
4022         } else {
4023                 memset((void *)mqd, 0, sizeof(*mqd));
4024                 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
4025                         amdgpu_ring_clear_ring(ring);
4026                 mutex_lock(&adev->srbm_mutex);
4027                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4028                 amdgpu_ring_init_mqd(ring);
4029                 gfx_v11_0_kiq_init_register(ring);
4030                 soc21_grbm_select(adev, 0, 0, 0, 0);
4031                 mutex_unlock(&adev->srbm_mutex);
4032
4033                 if (adev->gfx.kiq[0].mqd_backup)
4034                         memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
4035         }
4036
4037         return 0;
4038 }
4039
4040 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring)
4041 {
4042         struct amdgpu_device *adev = ring->adev;
4043         struct v11_compute_mqd *mqd = ring->mqd_ptr;
4044         int mqd_idx = ring - &adev->gfx.compute_ring[0];
4045
4046         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
4047                 memset((void *)mqd, 0, sizeof(*mqd));
4048                 mutex_lock(&adev->srbm_mutex);
4049                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4050                 amdgpu_ring_init_mqd(ring);
4051                 soc21_grbm_select(adev, 0, 0, 0, 0);
4052                 mutex_unlock(&adev->srbm_mutex);
4053
4054                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4055                         memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
4056         } else {
4057                 /* restore MQD to a clean status */
4058                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4059                         memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
4060                 /* reset ring buffer */
4061                 ring->wptr = 0;
4062                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
4063                 amdgpu_ring_clear_ring(ring);
4064         }
4065
4066         return 0;
4067 }
4068
4069 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev)
4070 {
4071         struct amdgpu_ring *ring;
4072         int r;
4073
4074         ring = &adev->gfx.kiq[0].ring;
4075
4076         r = amdgpu_bo_reserve(ring->mqd_obj, false);
4077         if (unlikely(r != 0))
4078                 return r;
4079
4080         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4081         if (unlikely(r != 0)) {
4082                 amdgpu_bo_unreserve(ring->mqd_obj);
4083                 return r;
4084         }
4085
4086         gfx_v11_0_kiq_init_queue(ring);
4087         amdgpu_bo_kunmap(ring->mqd_obj);
4088         ring->mqd_ptr = NULL;
4089         amdgpu_bo_unreserve(ring->mqd_obj);
4090         ring->sched.ready = true;
4091         return 0;
4092 }
4093
4094 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev)
4095 {
4096         struct amdgpu_ring *ring = NULL;
4097         int r = 0, i;
4098
4099         if (!amdgpu_async_gfx_ring)
4100                 gfx_v11_0_cp_compute_enable(adev, true);
4101
4102         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4103                 ring = &adev->gfx.compute_ring[i];
4104
4105                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4106                 if (unlikely(r != 0))
4107                         goto done;
4108                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4109                 if (!r) {
4110                         r = gfx_v11_0_kcq_init_queue(ring);
4111                         amdgpu_bo_kunmap(ring->mqd_obj);
4112                         ring->mqd_ptr = NULL;
4113                 }
4114                 amdgpu_bo_unreserve(ring->mqd_obj);
4115                 if (r)
4116                         goto done;
4117         }
4118
4119         r = amdgpu_gfx_enable_kcq(adev, 0);
4120 done:
4121         return r;
4122 }
4123
4124 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev)
4125 {
4126         int r, i;
4127         struct amdgpu_ring *ring;
4128
4129         if (!(adev->flags & AMD_IS_APU))
4130                 gfx_v11_0_enable_gui_idle_interrupt(adev, false);
4131
4132         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4133                 /* legacy firmware loading */
4134                 r = gfx_v11_0_cp_gfx_load_microcode(adev);
4135                 if (r)
4136                         return r;
4137
4138                 if (adev->gfx.rs64_enable)
4139                         r = gfx_v11_0_cp_compute_load_microcode_rs64(adev);
4140                 else
4141                         r = gfx_v11_0_cp_compute_load_microcode(adev);
4142                 if (r)
4143                         return r;
4144         }
4145
4146         gfx_v11_0_cp_set_doorbell_range(adev);
4147
4148         if (amdgpu_async_gfx_ring) {
4149                 gfx_v11_0_cp_compute_enable(adev, true);
4150                 gfx_v11_0_cp_gfx_enable(adev, true);
4151         }
4152
4153         if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
4154                 r = amdgpu_mes_kiq_hw_init(adev);
4155         else
4156                 r = gfx_v11_0_kiq_resume(adev);
4157         if (r)
4158                 return r;
4159
4160         r = gfx_v11_0_kcq_resume(adev);
4161         if (r)
4162                 return r;
4163
4164         if (!amdgpu_async_gfx_ring) {
4165                 r = gfx_v11_0_cp_gfx_resume(adev);
4166                 if (r)
4167                         return r;
4168         } else {
4169                 r = gfx_v11_0_cp_async_gfx_ring_resume(adev);
4170                 if (r)
4171                         return r;
4172         }
4173
4174         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4175                 ring = &adev->gfx.gfx_ring[i];
4176                 r = amdgpu_ring_test_helper(ring);
4177                 if (r)
4178                         return r;
4179         }
4180
4181         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4182                 ring = &adev->gfx.compute_ring[i];
4183                 r = amdgpu_ring_test_helper(ring);
4184                 if (r)
4185                         return r;
4186         }
4187
4188         return 0;
4189 }
4190
4191 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable)
4192 {
4193         gfx_v11_0_cp_gfx_enable(adev, enable);
4194         gfx_v11_0_cp_compute_enable(adev, enable);
4195 }
4196
4197 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev)
4198 {
4199         int r;
4200         bool value;
4201
4202         r = adev->gfxhub.funcs->gart_enable(adev);
4203         if (r)
4204                 return r;
4205
4206         adev->hdp.funcs->flush_hdp(adev, NULL);
4207
4208         value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
4209                 false : true;
4210
4211         adev->gfxhub.funcs->set_fault_enable_default(adev, value);
4212         amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
4213
4214         return 0;
4215 }
4216
4217 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev)
4218 {
4219         u32 tmp;
4220
4221         /* select RS64 */
4222         if (adev->gfx.rs64_enable) {
4223                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL);
4224                 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1);
4225                 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp);
4226
4227                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL);
4228                 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1);
4229                 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp);
4230         }
4231
4232         if (amdgpu_emu_mode == 1)
4233                 msleep(100);
4234 }
4235
4236 static int get_gb_addr_config(struct amdgpu_device * adev)
4237 {
4238         u32 gb_addr_config;
4239
4240         gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
4241         if (gb_addr_config == 0)
4242                 return -EINVAL;
4243
4244         adev->gfx.config.gb_addr_config_fields.num_pkrs =
4245                 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4246
4247         adev->gfx.config.gb_addr_config = gb_addr_config;
4248
4249         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4250                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4251                                       GB_ADDR_CONFIG, NUM_PIPES);
4252
4253         adev->gfx.config.max_tile_pipes =
4254                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4255
4256         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4257                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4258                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4259         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4260                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4261                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4262         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4263                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4264                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4265         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4266                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4267                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4268
4269         return 0;
4270 }
4271
4272 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev)
4273 {
4274         uint32_t data;
4275
4276         data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);
4277         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
4278         WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);
4279
4280         data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);
4281         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
4282         WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);
4283 }
4284
4285 static int gfx_v11_0_hw_init(void *handle)
4286 {
4287         int r;
4288         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4289
4290         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4291                 if (adev->gfx.imu.funcs) {
4292                         /* RLC autoload sequence 1: Program rlc ram */
4293                         if (adev->gfx.imu.funcs->program_rlc_ram)
4294                                 adev->gfx.imu.funcs->program_rlc_ram(adev);
4295                 }
4296                 /* rlc autoload firmware */
4297                 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev);
4298                 if (r)
4299                         return r;
4300         } else {
4301                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4302                         if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
4303                                 if (adev->gfx.imu.funcs->load_microcode)
4304                                         adev->gfx.imu.funcs->load_microcode(adev);
4305                                 if (adev->gfx.imu.funcs->setup_imu)
4306                                         adev->gfx.imu.funcs->setup_imu(adev);
4307                                 if (adev->gfx.imu.funcs->start_imu)
4308                                         adev->gfx.imu.funcs->start_imu(adev);
4309                         }
4310
4311                         /* disable gpa mode in backdoor loading */
4312                         gfx_v11_0_disable_gpa_mode(adev);
4313                 }
4314         }
4315
4316         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) ||
4317             (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
4318                 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev);
4319                 if (r) {
4320                         dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r);
4321                         return r;
4322                 }
4323         }
4324
4325         adev->gfx.is_poweron = true;
4326
4327         if(get_gb_addr_config(adev))
4328                 DRM_WARN("Invalid gb_addr_config !\n");
4329
4330         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
4331             adev->gfx.rs64_enable)
4332                 gfx_v11_0_config_gfx_rs64(adev);
4333
4334         r = gfx_v11_0_gfxhub_enable(adev);
4335         if (r)
4336                 return r;
4337
4338         if (!amdgpu_emu_mode)
4339                 gfx_v11_0_init_golden_registers(adev);
4340
4341         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ||
4342             (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
4343                 /**
4344                  * For gfx 11, rlc firmware loading relies on smu firmware is
4345                  * loaded firstly, so in direct type, it has to load smc ucode
4346                  * here before rlc.
4347                  */
4348                 if (!(adev->flags & AMD_IS_APU)) {
4349                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
4350                         if (r)
4351                                 return r;
4352                 }
4353         }
4354
4355         gfx_v11_0_constants_init(adev);
4356
4357         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
4358                 gfx_v11_0_select_cp_fw_arch(adev);
4359
4360         if (adev->nbio.funcs->gc_doorbell_init)
4361                 adev->nbio.funcs->gc_doorbell_init(adev);
4362
4363         r = gfx_v11_0_rlc_resume(adev);
4364         if (r)
4365                 return r;
4366
4367         /*
4368          * init golden registers and rlc resume may override some registers,
4369          * reconfig them here
4370          */
4371         gfx_v11_0_tcp_harvest(adev);
4372
4373         r = gfx_v11_0_cp_resume(adev);
4374         if (r)
4375                 return r;
4376
4377         /* get IMU version from HW if it's not set */
4378         if (!adev->gfx.imu_fw_version)
4379                 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0);
4380
4381         return r;
4382 }
4383
4384 static int gfx_v11_0_hw_fini(void *handle)
4385 {
4386         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4387
4388         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4389         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4390
4391         if (!adev->no_hw_access) {
4392                 if (amdgpu_async_gfx_ring) {
4393                         if (amdgpu_gfx_disable_kgq(adev, 0))
4394                                 DRM_ERROR("KGQ disable failed\n");
4395                 }
4396
4397                 if (amdgpu_gfx_disable_kcq(adev, 0))
4398                         DRM_ERROR("KCQ disable failed\n");
4399
4400                 amdgpu_mes_kiq_hw_fini(adev);
4401         }
4402
4403         if (amdgpu_sriov_vf(adev))
4404                 /* Remove the steps disabling CPG and clearing KIQ position,
4405                  * so that CP could perform IDLE-SAVE during switch. Those
4406                  * steps are necessary to avoid a DMAR error in gfx9 but it is
4407                  * not reproduced on gfx11.
4408                  */
4409                 return 0;
4410
4411         gfx_v11_0_cp_enable(adev, false);
4412         gfx_v11_0_enable_gui_idle_interrupt(adev, false);
4413
4414         adev->gfxhub.funcs->gart_disable(adev);
4415
4416         adev->gfx.is_poweron = false;
4417
4418         return 0;
4419 }
4420
4421 static int gfx_v11_0_suspend(void *handle)
4422 {
4423         return gfx_v11_0_hw_fini(handle);
4424 }
4425
4426 static int gfx_v11_0_resume(void *handle)
4427 {
4428         return gfx_v11_0_hw_init(handle);
4429 }
4430
4431 static bool gfx_v11_0_is_idle(void *handle)
4432 {
4433         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4434
4435         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
4436                                 GRBM_STATUS, GUI_ACTIVE))
4437                 return false;
4438         else
4439                 return true;
4440 }
4441
4442 static int gfx_v11_0_wait_for_idle(void *handle)
4443 {
4444         unsigned i;
4445         u32 tmp;
4446         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4447
4448         for (i = 0; i < adev->usec_timeout; i++) {
4449                 /* read MC_STATUS */
4450                 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &
4451                         GRBM_STATUS__GUI_ACTIVE_MASK;
4452
4453                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
4454                         return 0;
4455                 udelay(1);
4456         }
4457         return -ETIMEDOUT;
4458 }
4459
4460 static int gfx_v11_0_soft_reset(void *handle)
4461 {
4462         u32 grbm_soft_reset = 0;
4463         u32 tmp;
4464         int i, j, k;
4465         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4466
4467         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4468         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0);
4469         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0);
4470         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0);
4471         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);
4472         WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
4473
4474         gfx_v11_0_set_safe_mode(adev, 0);
4475
4476         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4477                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4478                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4479                                 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
4480                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);
4481                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);
4482                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);
4483                                 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
4484
4485                                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);
4486                                 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);
4487                         }
4488                 }
4489         }
4490         for (i = 0; i < adev->gfx.me.num_me; ++i) {
4491                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4492                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4493                                 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
4494                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);
4495                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);
4496                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);
4497                                 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
4498
4499                                 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1);
4500                         }
4501                 }
4502         }
4503
4504         WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe);
4505
4506         // Read CP_VMID_RESET register three times.
4507         // to get sufficient time for GFX_HQD_ACTIVE reach 0
4508         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4509         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4510         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4511
4512         for (i = 0; i < adev->usec_timeout; i++) {
4513                 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &&
4514                     !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE))
4515                         break;
4516                 udelay(1);
4517         }
4518         if (i >= adev->usec_timeout) {
4519                 printk("Failed to wait all pipes clean\n");
4520                 return -EINVAL;
4521         }
4522
4523         /**********  trigger soft reset  ***********/
4524         grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
4525         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4526                                         SOFT_RESET_CP, 1);
4527         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4528                                         SOFT_RESET_GFX, 1);
4529         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4530                                         SOFT_RESET_CPF, 1);
4531         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4532                                         SOFT_RESET_CPC, 1);
4533         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4534                                         SOFT_RESET_CPG, 1);
4535         WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);
4536         /**********  exit soft reset  ***********/
4537         grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
4538         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4539                                         SOFT_RESET_CP, 0);
4540         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4541                                         SOFT_RESET_GFX, 0);
4542         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4543                                         SOFT_RESET_CPF, 0);
4544         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4545                                         SOFT_RESET_CPC, 0);
4546         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4547                                         SOFT_RESET_CPG, 0);
4548         WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);
4549
4550         tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL);
4551         tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1);
4552         WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp);
4553
4554         WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0);
4555         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0);
4556
4557         for (i = 0; i < adev->usec_timeout; i++) {
4558                 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET))
4559                         break;
4560                 udelay(1);
4561         }
4562         if (i >= adev->usec_timeout) {
4563                 printk("Failed to wait CP_VMID_RESET to 0\n");
4564                 return -EINVAL;
4565         }
4566
4567         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4568         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4569         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4570         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4571         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4572         WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
4573
4574         gfx_v11_0_unset_safe_mode(adev, 0);
4575
4576         return gfx_v11_0_cp_resume(adev);
4577 }
4578
4579 static bool gfx_v11_0_check_soft_reset(void *handle)
4580 {
4581         int i, r;
4582         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4583         struct amdgpu_ring *ring;
4584         long tmo = msecs_to_jiffies(1000);
4585
4586         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4587                 ring = &adev->gfx.gfx_ring[i];
4588                 r = amdgpu_ring_test_ib(ring, tmo);
4589                 if (r)
4590                         return true;
4591         }
4592
4593         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4594                 ring = &adev->gfx.compute_ring[i];
4595                 r = amdgpu_ring_test_ib(ring, tmo);
4596                 if (r)
4597                         return true;
4598         }
4599
4600         return false;
4601 }
4602
4603 static int gfx_v11_0_post_soft_reset(void *handle)
4604 {
4605         /**
4606          * GFX soft reset will impact MES, need resume MES when do GFX soft reset
4607          */
4608         return amdgpu_mes_resume((struct amdgpu_device *)handle);
4609 }
4610
4611 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4612 {
4613         uint64_t clock;
4614         uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;
4615
4616         if (amdgpu_sriov_vf(adev)) {
4617                 amdgpu_gfx_off_ctrl(adev, false);
4618                 mutex_lock(&adev->gfx.gpu_clock_mutex);
4619                 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);
4620                 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);
4621                 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);
4622                 if (clock_counter_hi_pre != clock_counter_hi_after)
4623                         clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);
4624                 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4625                 amdgpu_gfx_off_ctrl(adev, true);
4626         } else {
4627                 preempt_disable();
4628                 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
4629                 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
4630                 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
4631                 if (clock_counter_hi_pre != clock_counter_hi_after)
4632                         clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
4633                 preempt_enable();
4634         }
4635         clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);
4636
4637         return clock;
4638 }
4639
4640 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4641                                            uint32_t vmid,
4642                                            uint32_t gds_base, uint32_t gds_size,
4643                                            uint32_t gws_base, uint32_t gws_size,
4644                                            uint32_t oa_base, uint32_t oa_size)
4645 {
4646         struct amdgpu_device *adev = ring->adev;
4647
4648         /* GDS Base */
4649         gfx_v11_0_write_data_to_reg(ring, 0, false,
4650                                     SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid,
4651                                     gds_base);
4652
4653         /* GDS Size */
4654         gfx_v11_0_write_data_to_reg(ring, 0, false,
4655                                     SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid,
4656                                     gds_size);
4657
4658         /* GWS */
4659         gfx_v11_0_write_data_to_reg(ring, 0, false,
4660                                     SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid,
4661                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4662
4663         /* OA */
4664         gfx_v11_0_write_data_to_reg(ring, 0, false,
4665                                     SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid,
4666                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
4667 }
4668
4669 static int gfx_v11_0_early_init(void *handle)
4670 {
4671         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4672
4673         adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
4674
4675         adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
4676         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
4677                                           AMDGPU_MAX_COMPUTE_RINGS);
4678
4679         gfx_v11_0_set_kiq_pm4_funcs(adev);
4680         gfx_v11_0_set_ring_funcs(adev);
4681         gfx_v11_0_set_irq_funcs(adev);
4682         gfx_v11_0_set_gds_init(adev);
4683         gfx_v11_0_set_rlc_funcs(adev);
4684         gfx_v11_0_set_mqd_funcs(adev);
4685         gfx_v11_0_set_imu_funcs(adev);
4686
4687         gfx_v11_0_init_rlcg_reg_access_ctrl(adev);
4688
4689         return gfx_v11_0_init_microcode(adev);
4690 }
4691
4692 static int gfx_v11_0_late_init(void *handle)
4693 {
4694         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4695         int r;
4696
4697         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4698         if (r)
4699                 return r;
4700
4701         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4702         if (r)
4703                 return r;
4704
4705         return 0;
4706 }
4707
4708 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev)
4709 {
4710         uint32_t rlc_cntl;
4711
4712         /* if RLC is not enabled, do nothing */
4713         rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);
4714         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
4715 }
4716
4717 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
4718 {
4719         uint32_t data;
4720         unsigned i;
4721
4722         data = RLC_SAFE_MODE__CMD_MASK;
4723         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
4724
4725         WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);
4726
4727         /* wait for RLC_SAFE_MODE */
4728         for (i = 0; i < adev->usec_timeout; i++) {
4729                 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),
4730                                    RLC_SAFE_MODE, CMD))
4731                         break;
4732                 udelay(1);
4733         }
4734 }
4735
4736 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
4737 {
4738         WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);
4739 }
4740
4741 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
4742                                       bool enable)
4743 {
4744         uint32_t def, data;
4745
4746         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK))
4747                 return;
4748
4749         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4750
4751         if (enable)
4752                 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
4753         else
4754                 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
4755
4756         if (def != data)
4757                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4758 }
4759
4760 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev,
4761                                        bool enable)
4762 {
4763         uint32_t def, data;
4764
4765         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
4766                 return;
4767
4768         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4769
4770         if (enable)
4771                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4772         else
4773                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4774
4775         if (def != data)
4776                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4777 }
4778
4779 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev,
4780                                            bool enable)
4781 {
4782         uint32_t def, data;
4783
4784         if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
4785                 return;
4786
4787         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4788
4789         if (enable)
4790                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK;
4791         else
4792                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK;
4793
4794         if (def != data)
4795                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4796 }
4797
4798 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4799                                                        bool enable)
4800 {
4801         uint32_t data, def;
4802
4803         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
4804                 return;
4805
4806         /* It is disabled by HW by default */
4807         if (enable) {
4808                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4809                         /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4810                         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4811
4812                         data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4813                                   RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4814                                   RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4815
4816                         if (def != data)
4817                                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4818                 }
4819         } else {
4820                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4821                         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4822
4823                         data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4824                                  RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4825                                  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4826
4827                         if (def != data)
4828                                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4829                 }
4830         }
4831 }
4832
4833 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4834                                                        bool enable)
4835 {
4836         uint32_t def, data;
4837
4838         if (!(adev->cg_flags &
4839               (AMD_CG_SUPPORT_GFX_CGCG |
4840               AMD_CG_SUPPORT_GFX_CGLS |
4841               AMD_CG_SUPPORT_GFX_3D_CGCG |
4842               AMD_CG_SUPPORT_GFX_3D_CGLS)))
4843                 return;
4844
4845         if (enable) {
4846                 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4847
4848                 /* unset CGCG override */
4849                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4850                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4851                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4852                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4853                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG ||
4854                     adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4855                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4856
4857                 /* update CGCG override bits */
4858                 if (def != data)
4859                         WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4860
4861                 /* enable cgcg FSM(0x0000363F) */
4862                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4863
4864                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
4865                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK;
4866                         data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4867                                  RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4868                 }
4869
4870                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
4871                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK;
4872                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4873                                  RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4874                 }
4875
4876                 if (def != data)
4877                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4878
4879                 /* Program RLC_CGCG_CGLS_CTRL_3D */
4880                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4881
4882                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
4883                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK;
4884                         data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4885                                  RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4886                 }
4887
4888                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
4889                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK;
4890                         data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4891                                  RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4892                 }
4893
4894                 if (def != data)
4895                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4896
4897                 /* set IDLE_POLL_COUNT(0x00900100) */
4898                 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);
4899
4900                 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK);
4901                 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4902                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4903
4904                 if (def != data)
4905                         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);
4906
4907                 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4908                 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4909                 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4910                 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4911                 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4912                 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);
4913
4914                 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4915                 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4916                 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4917
4918                 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4919                 if (adev->sdma.num_instances > 1) {
4920                         data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4921                         data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4922                         WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4923                 }
4924         } else {
4925                 /* Program RLC_CGCG_CGLS_CTRL */
4926                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4927
4928                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4929                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4930
4931                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4932                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4933
4934                 if (def != data)
4935                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4936
4937                 /* Program RLC_CGCG_CGLS_CTRL_3D */
4938                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4939
4940                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
4941                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4942                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4943                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4944
4945                 if (def != data)
4946                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4947
4948                 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4949                 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
4950                 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4951
4952                 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4953                 if (adev->sdma.num_instances > 1) {
4954                         data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4955                         data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
4956                         WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4957                 }
4958         }
4959 }
4960
4961 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4962                                             bool enable)
4963 {
4964         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4965
4966         gfx_v11_0_update_coarse_grain_clock_gating(adev, enable);
4967
4968         gfx_v11_0_update_medium_grain_clock_gating(adev, enable);
4969
4970         gfx_v11_0_update_repeater_fgcg(adev, enable);
4971
4972         gfx_v11_0_update_sram_fgcg(adev, enable);
4973
4974         gfx_v11_0_update_perf_clk(adev, enable);
4975
4976         if (adev->cg_flags &
4977             (AMD_CG_SUPPORT_GFX_MGCG |
4978              AMD_CG_SUPPORT_GFX_CGLS |
4979              AMD_CG_SUPPORT_GFX_CGCG |
4980              AMD_CG_SUPPORT_GFX_3D_CGCG |
4981              AMD_CG_SUPPORT_GFX_3D_CGLS))
4982                 gfx_v11_0_enable_gui_idle_interrupt(adev, enable);
4983
4984         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
4985
4986         return 0;
4987 }
4988
4989 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
4990 {
4991         u32 data;
4992
4993         amdgpu_gfx_off_ctrl(adev, false);
4994
4995         data = RREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL);
4996
4997         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
4998         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
4999
5000         WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
5001
5002         amdgpu_gfx_off_ctrl(adev, true);
5003 }
5004
5005 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = {
5006         .is_rlc_enabled = gfx_v11_0_is_rlc_enabled,
5007         .set_safe_mode = gfx_v11_0_set_safe_mode,
5008         .unset_safe_mode = gfx_v11_0_unset_safe_mode,
5009         .init = gfx_v11_0_rlc_init,
5010         .get_csb_size = gfx_v11_0_get_csb_size,
5011         .get_csb_buffer = gfx_v11_0_get_csb_buffer,
5012         .resume = gfx_v11_0_rlc_resume,
5013         .stop = gfx_v11_0_rlc_stop,
5014         .reset = gfx_v11_0_rlc_reset,
5015         .start = gfx_v11_0_rlc_start,
5016         .update_spm_vmid = gfx_v11_0_update_spm_vmid,
5017 };
5018
5019 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
5020 {
5021         u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
5022
5023         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
5024                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5025         else
5026                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5027
5028         WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data);
5029
5030         // Program RLC_PG_DELAY3 for CGPG hysteresis
5031         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
5032                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
5033                 case IP_VERSION(11, 0, 1):
5034                 case IP_VERSION(11, 0, 4):
5035                 case IP_VERSION(11, 5, 0):
5036                         WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
5037                         break;
5038                 default:
5039                         break;
5040                 }
5041         }
5042 }
5043
5044 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
5045 {
5046         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
5047
5048         gfx_v11_cntl_power_gating(adev, enable);
5049
5050         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
5051 }
5052
5053 static int gfx_v11_0_set_powergating_state(void *handle,
5054                                            enum amd_powergating_state state)
5055 {
5056         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5057         bool enable = (state == AMD_PG_STATE_GATE);
5058
5059         if (amdgpu_sriov_vf(adev))
5060                 return 0;
5061
5062         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
5063         case IP_VERSION(11, 0, 0):
5064         case IP_VERSION(11, 0, 2):
5065         case IP_VERSION(11, 0, 3):
5066                 amdgpu_gfx_off_ctrl(adev, enable);
5067                 break;
5068         case IP_VERSION(11, 0, 1):
5069         case IP_VERSION(11, 0, 4):
5070         case IP_VERSION(11, 5, 0):
5071                 if (!enable)
5072                         amdgpu_gfx_off_ctrl(adev, false);
5073
5074                 gfx_v11_cntl_pg(adev, enable);
5075
5076                 if (enable)
5077                         amdgpu_gfx_off_ctrl(adev, true);
5078
5079                 break;
5080         default:
5081                 break;
5082         }
5083
5084         return 0;
5085 }
5086
5087 static int gfx_v11_0_set_clockgating_state(void *handle,
5088                                           enum amd_clockgating_state state)
5089 {
5090         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5091
5092         if (amdgpu_sriov_vf(adev))
5093                 return 0;
5094
5095         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
5096         case IP_VERSION(11, 0, 0):
5097         case IP_VERSION(11, 0, 1):
5098         case IP_VERSION(11, 0, 2):
5099         case IP_VERSION(11, 0, 3):
5100         case IP_VERSION(11, 0, 4):
5101         case IP_VERSION(11, 5, 0):
5102                 gfx_v11_0_update_gfx_clock_gating(adev,
5103                                 state ==  AMD_CG_STATE_GATE);
5104                 break;
5105         default:
5106                 break;
5107         }
5108
5109         return 0;
5110 }
5111
5112 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags)
5113 {
5114         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5115         int data;
5116
5117         /* AMD_CG_SUPPORT_GFX_MGCG */
5118         data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
5119         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
5120                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
5121
5122         /* AMD_CG_SUPPORT_REPEATER_FGCG */
5123         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK))
5124                 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG;
5125
5126         /* AMD_CG_SUPPORT_GFX_FGCG */
5127         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
5128                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
5129
5130         /* AMD_CG_SUPPORT_GFX_PERF_CLK */
5131         if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK))
5132                 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK;
5133
5134         /* AMD_CG_SUPPORT_GFX_CGCG */
5135         data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
5136         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5137                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
5138
5139         /* AMD_CG_SUPPORT_GFX_CGLS */
5140         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5141                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
5142
5143         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5144         data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
5145         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
5146                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
5147
5148         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
5149         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
5150                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
5151 }
5152
5153 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
5154 {
5155         /* gfx11 is 32bit rptr*/
5156         return *(uint32_t *)ring->rptr_cpu_addr;
5157 }
5158
5159 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
5160 {
5161         struct amdgpu_device *adev = ring->adev;
5162         u64 wptr;
5163
5164         /* XXX check if swapping is necessary on BE */
5165         if (ring->use_doorbell) {
5166                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5167         } else {
5168                 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);
5169                 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;
5170         }
5171
5172         return wptr;
5173 }
5174
5175 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5176 {
5177         struct amdgpu_device *adev = ring->adev;
5178
5179         if (ring->use_doorbell) {
5180                 /* XXX check if swapping is necessary on BE */
5181                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
5182                              ring->wptr);
5183                 WDOORBELL64(ring->doorbell_index, ring->wptr);
5184         } else {
5185                 WREG32_SOC15(GC, 0, regCP_RB0_WPTR,
5186                              lower_32_bits(ring->wptr));
5187                 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,
5188                              upper_32_bits(ring->wptr));
5189         }
5190 }
5191
5192 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
5193 {
5194         /* gfx11 hardware is 32bit rptr */
5195         return *(uint32_t *)ring->rptr_cpu_addr;
5196 }
5197
5198 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
5199 {
5200         u64 wptr;
5201
5202         /* XXX check if swapping is necessary on BE */
5203         if (ring->use_doorbell)
5204                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5205         else
5206                 BUG();
5207         return wptr;
5208 }
5209
5210 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
5211 {
5212         struct amdgpu_device *adev = ring->adev;
5213
5214         /* XXX check if swapping is necessary on BE */
5215         if (ring->use_doorbell) {
5216                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
5217                              ring->wptr);
5218                 WDOORBELL64(ring->doorbell_index, ring->wptr);
5219         } else {
5220                 BUG(); /* only DOORBELL method supported on gfx11 now */
5221         }
5222 }
5223
5224 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
5225 {
5226         struct amdgpu_device *adev = ring->adev;
5227         u32 ref_and_mask, reg_mem_engine;
5228         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
5229
5230         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
5231                 switch (ring->me) {
5232                 case 1:
5233                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
5234                         break;
5235                 case 2:
5236                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
5237                         break;
5238                 default:
5239                         return;
5240                 }
5241                 reg_mem_engine = 0;
5242         } else {
5243                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
5244                 reg_mem_engine = 1; /* pfp */
5245         }
5246
5247         gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
5248                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
5249                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
5250                                ref_and_mask, ref_and_mask, 0x20);
5251 }
5252
5253 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
5254                                        struct amdgpu_job *job,
5255                                        struct amdgpu_ib *ib,
5256                                        uint32_t flags)
5257 {
5258         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5259         u32 header, control = 0;
5260
5261         BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE);
5262
5263         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5264
5265         control |= ib->length_dw | (vmid << 24);
5266
5267         if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
5268                 control |= INDIRECT_BUFFER_PRE_ENB(1);
5269
5270                 if (flags & AMDGPU_IB_PREEMPTED)
5271                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
5272
5273                 if (vmid)
5274                         gfx_v11_0_ring_emit_de_meta(ring,
5275                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
5276         }
5277
5278         if (ring->is_mes_queue)
5279                 /* inherit vmid from mqd */
5280                 control |= 0x400000;
5281
5282         amdgpu_ring_write(ring, header);
5283         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5284         amdgpu_ring_write(ring,
5285 #ifdef __BIG_ENDIAN
5286                 (2 << 0) |
5287 #endif
5288                 lower_32_bits(ib->gpu_addr));
5289         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5290         amdgpu_ring_write(ring, control);
5291 }
5292
5293 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
5294                                            struct amdgpu_job *job,
5295                                            struct amdgpu_ib *ib,
5296                                            uint32_t flags)
5297 {
5298         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5299         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
5300
5301         if (ring->is_mes_queue)
5302                 /* inherit vmid from mqd */
5303                 control |= 0x40000000;
5304
5305         /* Currently, there is a high possibility to get wave ID mismatch
5306          * between ME and GDS, leading to a hw deadlock, because ME generates
5307          * different wave IDs than the GDS expects. This situation happens
5308          * randomly when at least 5 compute pipes use GDS ordered append.
5309          * The wave IDs generated by ME are also wrong after suspend/resume.
5310          * Those are probably bugs somewhere else in the kernel driver.
5311          *
5312          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
5313          * GDS to 0 for this ring (me/pipe).
5314          */
5315         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
5316                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
5317                 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID);
5318                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
5319         }
5320
5321         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
5322         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5323         amdgpu_ring_write(ring,
5324 #ifdef __BIG_ENDIAN
5325                                 (2 << 0) |
5326 #endif
5327                                 lower_32_bits(ib->gpu_addr));
5328         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5329         amdgpu_ring_write(ring, control);
5330 }
5331
5332 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
5333                                      u64 seq, unsigned flags)
5334 {
5335         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
5336         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
5337
5338         /* RELEASE_MEM - flush caches, send int */
5339         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
5340         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
5341                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
5342                                  PACKET3_RELEASE_MEM_GCR_GL2_INV |
5343                                  PACKET3_RELEASE_MEM_GCR_GL2_US |
5344                                  PACKET3_RELEASE_MEM_GCR_GL1_INV |
5345                                  PACKET3_RELEASE_MEM_GCR_GLV_INV |
5346                                  PACKET3_RELEASE_MEM_GCR_GLM_INV |
5347                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
5348                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
5349                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
5350                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
5351         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
5352                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
5353
5354         /*
5355          * the address should be Qword aligned if 64bit write, Dword
5356          * aligned if only send 32bit data low (discard data high)
5357          */
5358         if (write64bit)
5359                 BUG_ON(addr & 0x7);
5360         else
5361                 BUG_ON(addr & 0x3);
5362         amdgpu_ring_write(ring, lower_32_bits(addr));
5363         amdgpu_ring_write(ring, upper_32_bits(addr));
5364         amdgpu_ring_write(ring, lower_32_bits(seq));
5365         amdgpu_ring_write(ring, upper_32_bits(seq));
5366         amdgpu_ring_write(ring, ring->is_mes_queue ?
5367                          (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
5368 }
5369
5370 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
5371 {
5372         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5373         uint32_t seq = ring->fence_drv.sync_seq;
5374         uint64_t addr = ring->fence_drv.gpu_addr;
5375
5376         gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
5377                                upper_32_bits(addr), seq, 0xffffffff, 4);
5378 }
5379
5380 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
5381                                    uint16_t pasid, uint32_t flush_type,
5382                                    bool all_hub, uint8_t dst_sel)
5383 {
5384         amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
5385         amdgpu_ring_write(ring,
5386                           PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
5387                           PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
5388                           PACKET3_INVALIDATE_TLBS_PASID(pasid) |
5389                           PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
5390 }
5391
5392 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
5393                                          unsigned vmid, uint64_t pd_addr)
5394 {
5395         if (ring->is_mes_queue)
5396                 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
5397         else
5398                 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
5399
5400         /* compute doesn't have PFP */
5401         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
5402                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5403                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5404                 amdgpu_ring_write(ring, 0x0);
5405         }
5406 }
5407
5408 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
5409                                           u64 seq, unsigned int flags)
5410 {
5411         struct amdgpu_device *adev = ring->adev;
5412
5413         /* we only allocate 32bit for each seq wb address */
5414         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
5415
5416         /* write fence seq to the "addr" */
5417         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5418         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5419                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
5420         amdgpu_ring_write(ring, lower_32_bits(addr));
5421         amdgpu_ring_write(ring, upper_32_bits(addr));
5422         amdgpu_ring_write(ring, lower_32_bits(seq));
5423
5424         if (flags & AMDGPU_FENCE_FLAG_INT) {
5425                 /* set register to trigger INT */
5426                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5427                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5428                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
5429                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
5430                 amdgpu_ring_write(ring, 0);
5431                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
5432         }
5433 }
5434
5435 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
5436                                          uint32_t flags)
5437 {
5438         uint32_t dw2 = 0;
5439
5440         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
5441         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
5442                 /* set load_global_config & load_global_uconfig */
5443                 dw2 |= 0x8001;
5444                 /* set load_cs_sh_regs */
5445                 dw2 |= 0x01000000;
5446                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
5447                 dw2 |= 0x10002;
5448         }
5449
5450         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5451         amdgpu_ring_write(ring, dw2);
5452         amdgpu_ring_write(ring, 0);
5453 }
5454
5455 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring,
5456                                            u64 shadow_va, u64 csa_va,
5457                                            u64 gds_va, bool init_shadow,
5458                                            int vmid)
5459 {
5460         struct amdgpu_device *adev = ring->adev;
5461
5462         if (!adev->gfx.cp_gfx_shadow)
5463                 return;
5464
5465         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7));
5466         amdgpu_ring_write(ring, lower_32_bits(shadow_va));
5467         amdgpu_ring_write(ring, upper_32_bits(shadow_va));
5468         amdgpu_ring_write(ring, lower_32_bits(gds_va));
5469         amdgpu_ring_write(ring, upper_32_bits(gds_va));
5470         amdgpu_ring_write(ring, lower_32_bits(csa_va));
5471         amdgpu_ring_write(ring, upper_32_bits(csa_va));
5472         amdgpu_ring_write(ring, shadow_va ?
5473                           PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0);
5474         amdgpu_ring_write(ring, init_shadow ?
5475                           PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0);
5476 }
5477
5478 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
5479 {
5480         unsigned ret;
5481
5482         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
5483         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
5484         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
5485         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
5486         ret = ring->wptr & ring->buf_mask;
5487         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
5488
5489         return ret;
5490 }
5491
5492 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
5493 {
5494         unsigned cur;
5495         BUG_ON(offset > ring->buf_mask);
5496         BUG_ON(ring->ring[offset] != 0x55aa55aa);
5497
5498         cur = (ring->wptr - 1) & ring->buf_mask;
5499         if (likely(cur > offset))
5500                 ring->ring[offset] = cur - offset;
5501         else
5502                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
5503 }
5504
5505 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring)
5506 {
5507         int i, r = 0;
5508         struct amdgpu_device *adev = ring->adev;
5509         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
5510         struct amdgpu_ring *kiq_ring = &kiq->ring;
5511         unsigned long flags;
5512
5513         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
5514                 return -EINVAL;
5515
5516         spin_lock_irqsave(&kiq->ring_lock, flags);
5517
5518         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
5519                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
5520                 return -ENOMEM;
5521         }
5522
5523         /* assert preemption condition */
5524         amdgpu_ring_set_preempt_cond_exec(ring, false);
5525
5526         /* assert IB preemption, emit the trailing fence */
5527         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
5528                                    ring->trail_fence_gpu_addr,
5529                                    ++ring->trail_seq);
5530         amdgpu_ring_commit(kiq_ring);
5531
5532         spin_unlock_irqrestore(&kiq->ring_lock, flags);
5533
5534         /* poll the trailing fence */
5535         for (i = 0; i < adev->usec_timeout; i++) {
5536                 if (ring->trail_seq ==
5537                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
5538                         break;
5539                 udelay(1);
5540         }
5541
5542         if (i >= adev->usec_timeout) {
5543                 r = -EINVAL;
5544                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
5545         }
5546
5547         /* deassert preemption condition */
5548         amdgpu_ring_set_preempt_cond_exec(ring, true);
5549         return r;
5550 }
5551
5552 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
5553 {
5554         struct amdgpu_device *adev = ring->adev;
5555         struct v10_de_ib_state de_payload = {0};
5556         uint64_t offset, gds_addr, de_payload_gpu_addr;
5557         void *de_payload_cpu_addr;
5558         int cnt;
5559
5560         if (ring->is_mes_queue) {
5561                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5562                                   gfx[0].gfx_meta_data) +
5563                         offsetof(struct v10_gfx_meta_data, de_payload);
5564                 de_payload_gpu_addr =
5565                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5566                 de_payload_cpu_addr =
5567                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
5568
5569                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5570                                   gfx[0].gds_backup) +
5571                         offsetof(struct v10_gfx_meta_data, de_payload);
5572                 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5573         } else {
5574                 offset = offsetof(struct v10_gfx_meta_data, de_payload);
5575                 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
5576                 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
5577
5578                 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
5579                                  AMDGPU_CSA_SIZE - adev->gds.gds_size,
5580                                  PAGE_SIZE);
5581         }
5582
5583         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
5584         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
5585
5586         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
5587         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
5588         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5589                                  WRITE_DATA_DST_SEL(8) |
5590                                  WR_CONFIRM) |
5591                                  WRITE_DATA_CACHE_POLICY(0));
5592         amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
5593         amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
5594
5595         if (resume)
5596                 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
5597                                            sizeof(de_payload) >> 2);
5598         else
5599                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
5600                                            sizeof(de_payload) >> 2);
5601 }
5602
5603 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
5604                                     bool secure)
5605 {
5606         uint32_t v = secure ? FRAME_TMZ : 0;
5607
5608         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
5609         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
5610 }
5611
5612 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
5613                                      uint32_t reg_val_offs)
5614 {
5615         struct amdgpu_device *adev = ring->adev;
5616
5617         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
5618         amdgpu_ring_write(ring, 0 |     /* src: register*/
5619                                 (5 << 8) |      /* dst: memory */
5620                                 (1 << 20));     /* write confirm */
5621         amdgpu_ring_write(ring, reg);
5622         amdgpu_ring_write(ring, 0);
5623         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
5624                                 reg_val_offs * 4));
5625         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
5626                                 reg_val_offs * 4));
5627 }
5628
5629 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
5630                                    uint32_t val)
5631 {
5632         uint32_t cmd = 0;
5633
5634         switch (ring->funcs->type) {
5635         case AMDGPU_RING_TYPE_GFX:
5636                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
5637                 break;
5638         case AMDGPU_RING_TYPE_KIQ:
5639                 cmd = (1 << 16); /* no inc addr */
5640                 break;
5641         default:
5642                 cmd = WR_CONFIRM;
5643                 break;
5644         }
5645         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5646         amdgpu_ring_write(ring, cmd);
5647         amdgpu_ring_write(ring, reg);
5648         amdgpu_ring_write(ring, 0);
5649         amdgpu_ring_write(ring, val);
5650 }
5651
5652 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
5653                                         uint32_t val, uint32_t mask)
5654 {
5655         gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
5656 }
5657
5658 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
5659                                                    uint32_t reg0, uint32_t reg1,
5660                                                    uint32_t ref, uint32_t mask)
5661 {
5662         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5663
5664         gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
5665                                ref, mask, 0x20);
5666 }
5667
5668 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring,
5669                                          unsigned vmid)
5670 {
5671         struct amdgpu_device *adev = ring->adev;
5672         uint32_t value = 0;
5673
5674         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
5675         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
5676         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
5677         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
5678         WREG32_SOC15(GC, 0, regSQ_CMD, value);
5679 }
5680
5681 static void
5682 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
5683                                       uint32_t me, uint32_t pipe,
5684                                       enum amdgpu_interrupt_state state)
5685 {
5686         uint32_t cp_int_cntl, cp_int_cntl_reg;
5687
5688         if (!me) {
5689                 switch (pipe) {
5690                 case 0:
5691                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
5692                         break;
5693                 case 1:
5694                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);
5695                         break;
5696                 default:
5697                         DRM_DEBUG("invalid pipe %d\n", pipe);
5698                         return;
5699                 }
5700         } else {
5701                 DRM_DEBUG("invalid me %d\n", me);
5702                 return;
5703         }
5704
5705         switch (state) {
5706         case AMDGPU_IRQ_STATE_DISABLE:
5707                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5708                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5709                                             TIME_STAMP_INT_ENABLE, 0);
5710                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5711                                             GENERIC0_INT_ENABLE, 0);
5712                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
5713                 break;
5714         case AMDGPU_IRQ_STATE_ENABLE:
5715                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5716                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5717                                             TIME_STAMP_INT_ENABLE, 1);
5718                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5719                                             GENERIC0_INT_ENABLE, 1);
5720                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
5721                 break;
5722         default:
5723                 break;
5724         }
5725 }
5726
5727 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5728                                                      int me, int pipe,
5729                                                      enum amdgpu_interrupt_state state)
5730 {
5731         u32 mec_int_cntl, mec_int_cntl_reg;
5732
5733         /*
5734          * amdgpu controls only the first MEC. That's why this function only
5735          * handles the setting of interrupts for this specific MEC. All other
5736          * pipes' interrupts are set by amdkfd.
5737          */
5738
5739         if (me == 1) {
5740                 switch (pipe) {
5741                 case 0:
5742                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
5743                         break;
5744                 case 1:
5745                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
5746                         break;
5747                 case 2:
5748                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);
5749                         break;
5750                 case 3:
5751                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);
5752                         break;
5753                 default:
5754                         DRM_DEBUG("invalid pipe %d\n", pipe);
5755                         return;
5756                 }
5757         } else {
5758                 DRM_DEBUG("invalid me %d\n", me);
5759                 return;
5760         }
5761
5762         switch (state) {
5763         case AMDGPU_IRQ_STATE_DISABLE:
5764                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
5765                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5766                                              TIME_STAMP_INT_ENABLE, 0);
5767                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5768                                              GENERIC0_INT_ENABLE, 0);
5769                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5770                 break;
5771         case AMDGPU_IRQ_STATE_ENABLE:
5772                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
5773                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5774                                              TIME_STAMP_INT_ENABLE, 1);
5775                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5776                                              GENERIC0_INT_ENABLE, 1);
5777                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5778                 break;
5779         default:
5780                 break;
5781         }
5782 }
5783
5784 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5785                                             struct amdgpu_irq_src *src,
5786                                             unsigned type,
5787                                             enum amdgpu_interrupt_state state)
5788 {
5789         switch (type) {
5790         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
5791                 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
5792                 break;
5793         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
5794                 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
5795                 break;
5796         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5797                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5798                 break;
5799         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5800                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5801                 break;
5802         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5803                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5804                 break;
5805         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5806                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5807                 break;
5808         default:
5809                 break;
5810         }
5811         return 0;
5812 }
5813
5814 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev,
5815                              struct amdgpu_irq_src *source,
5816                              struct amdgpu_iv_entry *entry)
5817 {
5818         int i;
5819         u8 me_id, pipe_id, queue_id;
5820         struct amdgpu_ring *ring;
5821         uint32_t mes_queue_id = entry->src_data[0];
5822
5823         DRM_DEBUG("IH: CP EOP\n");
5824
5825         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
5826                 struct amdgpu_mes_queue *queue;
5827
5828                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
5829
5830                 spin_lock(&adev->mes.queue_id_lock);
5831                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
5832                 if (queue) {
5833                         DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
5834                         amdgpu_fence_process(queue->ring);
5835                 }
5836                 spin_unlock(&adev->mes.queue_id_lock);
5837         } else {
5838                 me_id = (entry->ring_id & 0x0c) >> 2;
5839                 pipe_id = (entry->ring_id & 0x03) >> 0;
5840                 queue_id = (entry->ring_id & 0x70) >> 4;
5841
5842                 switch (me_id) {
5843                 case 0:
5844                         if (pipe_id == 0)
5845                                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5846                         else
5847                                 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
5848                         break;
5849                 case 1:
5850                 case 2:
5851                         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5852                                 ring = &adev->gfx.compute_ring[i];
5853                                 /* Per-queue interrupt is supported for MEC starting from VI.
5854                                  * The interrupt can only be enabled/disabled per pipe instead
5855                                  * of per queue.
5856                                  */
5857                                 if ((ring->me == me_id) &&
5858                                     (ring->pipe == pipe_id) &&
5859                                     (ring->queue == queue_id))
5860                                         amdgpu_fence_process(ring);
5861                         }
5862                         break;
5863                 }
5864         }
5865
5866         return 0;
5867 }
5868
5869 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
5870                                               struct amdgpu_irq_src *source,
5871                                               unsigned type,
5872                                               enum amdgpu_interrupt_state state)
5873 {
5874         switch (state) {
5875         case AMDGPU_IRQ_STATE_DISABLE:
5876         case AMDGPU_IRQ_STATE_ENABLE:
5877                 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
5878                                PRIV_REG_INT_ENABLE,
5879                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5880                 break;
5881         default:
5882                 break;
5883         }
5884
5885         return 0;
5886 }
5887
5888 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5889                                                struct amdgpu_irq_src *source,
5890                                                unsigned type,
5891                                                enum amdgpu_interrupt_state state)
5892 {
5893         switch (state) {
5894         case AMDGPU_IRQ_STATE_DISABLE:
5895         case AMDGPU_IRQ_STATE_ENABLE:
5896                 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
5897                                PRIV_INSTR_INT_ENABLE,
5898                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5899                 break;
5900         default:
5901                 break;
5902         }
5903
5904         return 0;
5905 }
5906
5907 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev,
5908                                         struct amdgpu_iv_entry *entry)
5909 {
5910         u8 me_id, pipe_id, queue_id;
5911         struct amdgpu_ring *ring;
5912         int i;
5913
5914         me_id = (entry->ring_id & 0x0c) >> 2;
5915         pipe_id = (entry->ring_id & 0x03) >> 0;
5916         queue_id = (entry->ring_id & 0x70) >> 4;
5917
5918         switch (me_id) {
5919         case 0:
5920                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5921                         ring = &adev->gfx.gfx_ring[i];
5922                         /* we only enabled 1 gfx queue per pipe for now */
5923                         if (ring->me == me_id && ring->pipe == pipe_id)
5924                                 drm_sched_fault(&ring->sched);
5925                 }
5926                 break;
5927         case 1:
5928         case 2:
5929                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5930                         ring = &adev->gfx.compute_ring[i];
5931                         if (ring->me == me_id && ring->pipe == pipe_id &&
5932                             ring->queue == queue_id)
5933                                 drm_sched_fault(&ring->sched);
5934                 }
5935                 break;
5936         default:
5937                 BUG();
5938                 break;
5939         }
5940 }
5941
5942 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev,
5943                                   struct amdgpu_irq_src *source,
5944                                   struct amdgpu_iv_entry *entry)
5945 {
5946         DRM_ERROR("Illegal register access in command stream\n");
5947         gfx_v11_0_handle_priv_fault(adev, entry);
5948         return 0;
5949 }
5950
5951 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev,
5952                                    struct amdgpu_irq_src *source,
5953                                    struct amdgpu_iv_entry *entry)
5954 {
5955         DRM_ERROR("Illegal instruction in command stream\n");
5956         gfx_v11_0_handle_priv_fault(adev, entry);
5957         return 0;
5958 }
5959
5960 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev,
5961                                   struct amdgpu_irq_src *source,
5962                                   struct amdgpu_iv_entry *entry)
5963 {
5964         if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq)
5965                 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry);
5966
5967         return 0;
5968 }
5969
5970 #if 0
5971 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
5972                                              struct amdgpu_irq_src *src,
5973                                              unsigned int type,
5974                                              enum amdgpu_interrupt_state state)
5975 {
5976         uint32_t tmp, target;
5977         struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
5978
5979         target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
5980         target += ring->pipe;
5981
5982         switch (type) {
5983         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
5984                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5985                         tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
5986                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5987                                             GENERIC2_INT_ENABLE, 0);
5988                         WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
5989
5990                         tmp = RREG32_SOC15_IP(GC, target);
5991                         tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
5992                                             GENERIC2_INT_ENABLE, 0);
5993                         WREG32_SOC15_IP(GC, target, tmp);
5994                 } else {
5995                         tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
5996                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5997                                             GENERIC2_INT_ENABLE, 1);
5998                         WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
5999
6000                         tmp = RREG32_SOC15_IP(GC, target);
6001                         tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
6002                                             GENERIC2_INT_ENABLE, 1);
6003                         WREG32_SOC15_IP(GC, target, tmp);
6004                 }
6005                 break;
6006         default:
6007                 BUG(); /* kiq only support GENERIC2_INT now */
6008                 break;
6009         }
6010         return 0;
6011 }
6012 #endif
6013
6014 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring)
6015 {
6016         const unsigned int gcr_cntl =
6017                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
6018                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
6019                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
6020                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
6021                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
6022                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
6023                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
6024                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
6025
6026         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
6027         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
6028         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
6029         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
6030         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
6031         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6032         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
6033         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
6034         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
6035 }
6036
6037 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {
6038         .name = "gfx_v11_0",
6039         .early_init = gfx_v11_0_early_init,
6040         .late_init = gfx_v11_0_late_init,
6041         .sw_init = gfx_v11_0_sw_init,
6042         .sw_fini = gfx_v11_0_sw_fini,
6043         .hw_init = gfx_v11_0_hw_init,
6044         .hw_fini = gfx_v11_0_hw_fini,
6045         .suspend = gfx_v11_0_suspend,
6046         .resume = gfx_v11_0_resume,
6047         .is_idle = gfx_v11_0_is_idle,
6048         .wait_for_idle = gfx_v11_0_wait_for_idle,
6049         .soft_reset = gfx_v11_0_soft_reset,
6050         .check_soft_reset = gfx_v11_0_check_soft_reset,
6051         .post_soft_reset = gfx_v11_0_post_soft_reset,
6052         .set_clockgating_state = gfx_v11_0_set_clockgating_state,
6053         .set_powergating_state = gfx_v11_0_set_powergating_state,
6054         .get_clockgating_state = gfx_v11_0_get_clockgating_state,
6055 };
6056
6057 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
6058         .type = AMDGPU_RING_TYPE_GFX,
6059         .align_mask = 0xff,
6060         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6061         .support_64bit_ptrs = true,
6062         .secure_submission_supported = true,
6063         .get_rptr = gfx_v11_0_ring_get_rptr_gfx,
6064         .get_wptr = gfx_v11_0_ring_get_wptr_gfx,
6065         .set_wptr = gfx_v11_0_ring_set_wptr_gfx,
6066         .emit_frame_size = /* totally 242 maximum if 16 IBs */
6067                 5 + /* COND_EXEC */
6068                 9 + /* SET_Q_PREEMPTION_MODE */
6069                 7 + /* PIPELINE_SYNC */
6070                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6071                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6072                 2 + /* VM_FLUSH */
6073                 8 + /* FENCE for VM_FLUSH */
6074                 20 + /* GDS switch */
6075                 5 + /* COND_EXEC */
6076                 7 + /* HDP_flush */
6077                 4 + /* VGT_flush */
6078                 31 + /* DE_META */
6079                 3 + /* CNTX_CTRL */
6080                 5 + /* HDP_INVL */
6081                 8 + 8 + /* FENCE x2 */
6082                 8, /* gfx_v11_0_emit_mem_sync */
6083         .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */
6084         .emit_ib = gfx_v11_0_ring_emit_ib_gfx,
6085         .emit_fence = gfx_v11_0_ring_emit_fence,
6086         .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync,
6087         .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush,
6088         .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch,
6089         .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,
6090         .test_ring = gfx_v11_0_ring_test_ring,
6091         .test_ib = gfx_v11_0_ring_test_ib,
6092         .insert_nop = amdgpu_ring_insert_nop,
6093         .pad_ib = amdgpu_ring_generic_pad_ib,
6094         .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl,
6095         .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow,
6096         .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec,
6097         .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec,
6098         .preempt_ib = gfx_v11_0_ring_preempt_ib,
6099         .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl,
6100         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6101         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6102         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6103         .soft_recovery = gfx_v11_0_ring_soft_recovery,
6104         .emit_mem_sync = gfx_v11_0_emit_mem_sync,
6105 };
6106
6107 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {
6108         .type = AMDGPU_RING_TYPE_COMPUTE,
6109         .align_mask = 0xff,
6110         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6111         .support_64bit_ptrs = true,
6112         .get_rptr = gfx_v11_0_ring_get_rptr_compute,
6113         .get_wptr = gfx_v11_0_ring_get_wptr_compute,
6114         .set_wptr = gfx_v11_0_ring_set_wptr_compute,
6115         .emit_frame_size =
6116                 20 + /* gfx_v11_0_ring_emit_gds_switch */
6117                 7 + /* gfx_v11_0_ring_emit_hdp_flush */
6118                 5 + /* hdp invalidate */
6119                 7 + /* gfx_v11_0_ring_emit_pipeline_sync */
6120                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6121                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6122                 2 + /* gfx_v11_0_ring_emit_vm_flush */
6123                 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */
6124                 8, /* gfx_v11_0_emit_mem_sync */
6125         .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */
6126         .emit_ib = gfx_v11_0_ring_emit_ib_compute,
6127         .emit_fence = gfx_v11_0_ring_emit_fence,
6128         .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync,
6129         .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush,
6130         .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch,
6131         .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,
6132         .test_ring = gfx_v11_0_ring_test_ring,
6133         .test_ib = gfx_v11_0_ring_test_ib,
6134         .insert_nop = amdgpu_ring_insert_nop,
6135         .pad_ib = amdgpu_ring_generic_pad_ib,
6136         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6137         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6138         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6139         .emit_mem_sync = gfx_v11_0_emit_mem_sync,
6140 };
6141
6142 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {
6143         .type = AMDGPU_RING_TYPE_KIQ,
6144         .align_mask = 0xff,
6145         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6146         .support_64bit_ptrs = true,
6147         .get_rptr = gfx_v11_0_ring_get_rptr_compute,
6148         .get_wptr = gfx_v11_0_ring_get_wptr_compute,
6149         .set_wptr = gfx_v11_0_ring_set_wptr_compute,
6150         .emit_frame_size =
6151                 20 + /* gfx_v11_0_ring_emit_gds_switch */
6152                 7 + /* gfx_v11_0_ring_emit_hdp_flush */
6153                 5 + /*hdp invalidate */
6154                 7 + /* gfx_v11_0_ring_emit_pipeline_sync */
6155                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6156                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6157                 2 + /* gfx_v11_0_ring_emit_vm_flush */
6158                 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6159         .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */
6160         .emit_ib = gfx_v11_0_ring_emit_ib_compute,
6161         .emit_fence = gfx_v11_0_ring_emit_fence_kiq,
6162         .test_ring = gfx_v11_0_ring_test_ring,
6163         .test_ib = gfx_v11_0_ring_test_ib,
6164         .insert_nop = amdgpu_ring_insert_nop,
6165         .pad_ib = amdgpu_ring_generic_pad_ib,
6166         .emit_rreg = gfx_v11_0_ring_emit_rreg,
6167         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6168         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6169         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6170 };
6171
6172 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev)
6173 {
6174         int i;
6175
6176         adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq;
6177
6178         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6179                 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx;
6180
6181         for (i = 0; i < adev->gfx.num_compute_rings; i++)
6182                 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute;
6183 }
6184
6185 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = {
6186         .set = gfx_v11_0_set_eop_interrupt_state,
6187         .process = gfx_v11_0_eop_irq,
6188 };
6189
6190 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = {
6191         .set = gfx_v11_0_set_priv_reg_fault_state,
6192         .process = gfx_v11_0_priv_reg_irq,
6193 };
6194
6195 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = {
6196         .set = gfx_v11_0_set_priv_inst_fault_state,
6197         .process = gfx_v11_0_priv_inst_irq,
6198 };
6199
6200 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = {
6201         .process = gfx_v11_0_rlc_gc_fed_irq,
6202 };
6203
6204 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
6205 {
6206         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6207         adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs;
6208
6209         adev->gfx.priv_reg_irq.num_types = 1;
6210         adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs;
6211
6212         adev->gfx.priv_inst_irq.num_types = 1;
6213         adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;
6214
6215         adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */
6216         adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs;
6217
6218 }
6219
6220 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)
6221 {
6222         if (adev->flags & AMD_IS_APU)
6223                 adev->gfx.imu.mode = MISSION_MODE;
6224         else
6225                 adev->gfx.imu.mode = DEBUG_MODE;
6226
6227         adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
6228 }
6229
6230 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev)
6231 {
6232         adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs;
6233 }
6234
6235 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev)
6236 {
6237         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
6238                             adev->gfx.config.max_sh_per_se *
6239                             adev->gfx.config.max_shader_engines;
6240
6241         adev->gds.gds_size = 0x1000;
6242         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
6243         adev->gds.gws_size = 64;
6244         adev->gds.oa_size = 16;
6245 }
6246
6247 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev)
6248 {
6249         /* set gfx eng mqd */
6250         adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
6251                 sizeof(struct v11_gfx_mqd);
6252         adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
6253                 gfx_v11_0_gfx_mqd_init;
6254         /* set compute eng mqd */
6255         adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
6256                 sizeof(struct v11_compute_mqd);
6257         adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
6258                 gfx_v11_0_compute_mqd_init;
6259 }
6260
6261 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
6262                                                           u32 bitmap)
6263 {
6264         u32 data;
6265
6266         if (!bitmap)
6267                 return;
6268
6269         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
6270         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
6271
6272         WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);
6273 }
6274
6275 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
6276 {
6277         u32 data, wgp_bitmask;
6278         data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
6279         data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);
6280
6281         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
6282         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
6283
6284         wgp_bitmask =
6285                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
6286
6287         return (~data) & wgp_bitmask;
6288 }
6289
6290 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
6291 {
6292         u32 wgp_idx, wgp_active_bitmap;
6293         u32 cu_bitmap_per_wgp, cu_active_bitmap;
6294
6295         wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev);
6296         cu_active_bitmap = 0;
6297
6298         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
6299                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
6300                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
6301                 if (wgp_active_bitmap & (1 << wgp_idx))
6302                         cu_active_bitmap |= cu_bitmap_per_wgp;
6303         }
6304
6305         return cu_active_bitmap;
6306 }
6307
6308 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
6309                                  struct amdgpu_cu_info *cu_info)
6310 {
6311         int i, j, k, counter, active_cu_number = 0;
6312         u32 mask, bitmap;
6313         unsigned disable_masks[8 * 2];
6314
6315         if (!adev || !cu_info)
6316                 return -EINVAL;
6317
6318         amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
6319
6320         mutex_lock(&adev->grbm_idx_mutex);
6321         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
6322                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
6323                         mask = 1;
6324                         counter = 0;
6325                         gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0);
6326                         if (i < 8 && j < 2)
6327                                 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(
6328                                         adev, disable_masks[i * 2 + j]);
6329                         bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev);
6330
6331                         /**
6332                          * GFX11 could support more than 4 SEs, while the bitmap
6333                          * in cu_info struct is 4x4 and ioctl interface struct
6334                          * drm_amdgpu_info_device should keep stable.
6335                          * So we use last two columns of bitmap to store cu mask for
6336                          * SEs 4 to 7, the layout of the bitmap is as below:
6337                          *    SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]}
6338                          *    SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]}
6339                          *    SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]}
6340                          *    SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]}
6341                          *    SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]}
6342                          *    SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]}
6343                          *    SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]}
6344                          *    SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]}
6345                          */
6346                         cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap;
6347
6348                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
6349                                 if (bitmap & mask)
6350                                         counter++;
6351
6352                                 mask <<= 1;
6353                         }
6354                         active_cu_number += counter;
6355                 }
6356         }
6357         gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
6358         mutex_unlock(&adev->grbm_idx_mutex);
6359
6360         cu_info->number = active_cu_number;
6361         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
6362
6363         return 0;
6364 }
6365
6366 const struct amdgpu_ip_block_version gfx_v11_0_ip_block =
6367 {
6368         .type = AMD_IP_BLOCK_TYPE_GFX,
6369         .major = 11,
6370         .minor = 0,
6371         .rev = 0,
6372         .funcs = &gfx_v11_0_ip_funcs,
6373 };