drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_gfx.h"
  29 #include "amdgpu_rlc.h"
  30 #include "amdgpu_ras.h"
  31 #include "amdgpu_xcp.h"
  32
  33 /* delay 0.1 second to enable gfx off feature */
  34 #define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(100)
  35
  36 #define GFX_OFF_NO_DELAY 0
  37
  38 /*
  39  * GPU GFX IP block helpers function.
  40  */
  41
  42 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
  43                                 int pipe, int queue)
  44 {
  45         int bit = 0;
  46
  47         bit += mec * adev->gfx.mec.num_pipe_per_mec
  48                 * adev->gfx.mec.num_queue_per_pipe;
  49         bit += pipe * adev->gfx.mec.num_queue_per_pipe;
  50         bit += queue;
  51
  52         return bit;
  53 }
  54
  55 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
  56                                  int *mec, int *pipe, int *queue)
  57 {
  58         *queue = bit % adev->gfx.mec.num_queue_per_pipe;
  59         *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
  60                 % adev->gfx.mec.num_pipe_per_mec;
  61         *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
  62                / adev->gfx.mec.num_pipe_per_mec;
  63
  64 }
  65
  66 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
  67                                      int xcc_id, int mec, int pipe, int queue)
  68 {
  69         return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
  70                         adev->gfx.mec_bitmap[xcc_id].queue_bitmap);
  71 }
  72
  73 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
  74                                int me, int pipe, int queue)
  75 {
  76         int bit = 0;
  77
  78         bit += me * adev->gfx.me.num_pipe_per_me
  79                 * adev->gfx.me.num_queue_per_pipe;
  80         bit += pipe * adev->gfx.me.num_queue_per_pipe;
  81         bit += queue;
  82
  83         return bit;
  84 }
  85
  86 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
  87                                 int *me, int *pipe, int *queue)
  88 {
  89         *queue = bit % adev->gfx.me.num_queue_per_pipe;
  90         *pipe = (bit / adev->gfx.me.num_queue_per_pipe)
  91                 % adev->gfx.me.num_pipe_per_me;
  92         *me = (bit / adev->gfx.me.num_queue_per_pipe)
  93                 / adev->gfx.me.num_pipe_per_me;
  94 }
  95
  96 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
  97                                     int me, int pipe, int queue)
  98 {
  99         return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
 100                         adev->gfx.me.queue_bitmap);
 101 }
 102
 103 /**
 104  * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
 105  *
 106  * @mask: array in which the per-shader array disable masks will be stored
 107  * @max_se: number of SEs
 108  * @max_sh: number of SHs
 109  *
 110  * The bitmask of CUs to be disabled in the shader array determined by se and
 111  * sh is stored in mask[se * max_sh + sh].
 112  */
 113 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
 114 {
 115         unsigned se, sh, cu;
 116         const char *p;
 117
 118         memset(mask, 0, sizeof(*mask) * max_se * max_sh);
 119
 120         if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
 121                 return;
 122
 123         p = amdgpu_disable_cu;
 124         for (;;) {
 125                 char *next;
 126                 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
 127                 if (ret < 3) {
 128                         DRM_ERROR("amdgpu: could not parse disable_cu\n");
 129                         return;
 130                 }
 131
 132                 if (se < max_se && sh < max_sh && cu < 16) {
 133                         DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
 134                         mask[se * max_sh + sh] |= 1u << cu;
 135                 } else {
 136                         DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
 137                                   se, sh, cu);
 138                 }
 139
 140                 next = strchr(p, ',');
 141                 if (!next)
 142                         break;
 143                 p = next + 1;
 144         }
 145 }
 146
 147 static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev)
 148 {
 149         return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1;
 150 }
 151
 152 static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev)
 153 {
 154         if (amdgpu_compute_multipipe != -1) {
 155                 DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
 156                          amdgpu_compute_multipipe);
 157                 return amdgpu_compute_multipipe == 1;
 158         }
 159
 160         if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
 161                 return true;
 162
 163         /* FIXME: spreading the queues across pipes causes perf regressions
 164          * on POLARIS11 compute workloads */
 165         if (adev->asic_type == CHIP_POLARIS11)
 166                 return false;
 167
 168         return adev->gfx.mec.num_mec > 1;
 169 }
 170
 171 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
 172                                                 struct amdgpu_ring *ring)
 173 {
 174         int queue = ring->queue;
 175         int pipe = ring->pipe;
 176
 177         /* Policy: use pipe1 queue0 as high priority graphics queue if we
 178          * have more than one gfx pipe.
 179          */
 180         if (amdgpu_gfx_is_graphics_multipipe_capable(adev) &&
 181             adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) {
 182                 int me = ring->me;
 183                 int bit;
 184
 185                 bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue);
 186                 if (ring == &adev->gfx.gfx_ring[bit])
 187                         return true;
 188         }
 189
 190         return false;
 191 }
 192
 193 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 194                                                struct amdgpu_ring *ring)
 195 {
 196         /* Policy: use 1st queue as high priority compute queue if we
 197          * have more than one compute queue.
 198          */
 199         if (adev->gfx.num_compute_rings > 1 &&
 200             ring == &adev->gfx.compute_ring[0])
 201                 return true;
 202
 203         return false;
 204 }
 205
 206 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
 207 {
 208         int i, j, queue, pipe;
 209         bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev);
 210         int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *
 211                                      adev->gfx.mec.num_queue_per_pipe,
 212                                      adev->gfx.num_compute_rings);
 213         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 214
 215         if (multipipe_policy) {
 216                 /* policy: make queues evenly cross all pipes on MEC1 only
 217                  * for multiple xcc, just use the original policy for simplicity */
 218                 for (j = 0; j < num_xcc; j++) {
 219                         for (i = 0; i < max_queues_per_mec; i++) {
 220                                 pipe = i % adev->gfx.mec.num_pipe_per_mec;
 221                                 queue = (i / adev->gfx.mec.num_pipe_per_mec) %
 222                                          adev->gfx.mec.num_queue_per_pipe;
 223
 224                                 set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
 225                                         adev->gfx.mec_bitmap[j].queue_bitmap);
 226                         }
 227                 }
 228         } else {
 229                 /* policy: amdgpu owns all queues in the given pipe */
 230                 for (j = 0; j < num_xcc; j++) {
 231                         for (i = 0; i < max_queues_per_mec; ++i)
 232                                 set_bit(i, adev->gfx.mec_bitmap[j].queue_bitmap);
 233                 }
 234         }
 235
 236         for (j = 0; j < num_xcc; j++) {
 237                 dev_dbg(adev->dev, "mec queue bitmap weight=%d\n",
 238                         bitmap_weight(adev->gfx.mec_bitmap[j].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));
 239         }
 240 }
 241
 242 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
 243 {
 244         int i, queue, pipe;
 245         bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev);
 246         int max_queues_per_me = adev->gfx.me.num_pipe_per_me *
 247                                         adev->gfx.me.num_queue_per_pipe;
 248
 249         if (multipipe_policy) {
 250                 /* policy: amdgpu owns the first queue per pipe at this stage
 251                  * will extend to mulitple queues per pipe later */
 252                 for (i = 0; i < max_queues_per_me; i++) {
 253                         pipe = i % adev->gfx.me.num_pipe_per_me;
 254                         queue = (i / adev->gfx.me.num_pipe_per_me) %
 255                                 adev->gfx.me.num_queue_per_pipe;
 256
 257                         set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
 258                                 adev->gfx.me.queue_bitmap);
 259                 }
 260         } else {
 261                 for (i = 0; i < max_queues_per_me; ++i)
 262                         set_bit(i, adev->gfx.me.queue_bitmap);
 263         }
 264
 265         /* update the number of active graphics rings */
 266         adev->gfx.num_gfx_rings =
 267                 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 268 }
 269
 270 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
 271                                   struct amdgpu_ring *ring, int xcc_id)
 272 {
 273         int queue_bit;
 274         int mec, pipe, queue;
 275
 276         queue_bit = adev->gfx.mec.num_mec
 277                     * adev->gfx.mec.num_pipe_per_mec
 278                     * adev->gfx.mec.num_queue_per_pipe;
 279
 280         while (--queue_bit >= 0) {
 281                 if (test_bit(queue_bit, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
 282                         continue;
 283
 284                 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 285
 286                 /*
 287                  * 1. Using pipes 2/3 from MEC 2 seems cause problems.
 288                  * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
 289                  * only can be issued on queue 0.
 290                  */
 291                 if ((mec == 1 && pipe > 1) || queue != 0)
 292                         continue;
 293
 294                 ring->me = mec + 1;
 295                 ring->pipe = pipe;
 296                 ring->queue = queue;
 297
 298                 return 0;
 299         }
 300
 301         dev_err(adev->dev, "Failed to find a queue for KIQ\n");
 302         return -EINVAL;
 303 }
 304
 305 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 306                              struct amdgpu_ring *ring,
 307                              struct amdgpu_irq_src *irq, int xcc_id)
 308 {
 309         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 310         int r = 0;
 311
 312         spin_lock_init(&kiq->ring_lock);
 313
 314         ring->adev = NULL;
 315         ring->ring_obj = NULL;
 316         ring->use_doorbell = true;
 317         ring->xcc_id = xcc_id;
 318         ring->vm_hub = AMDGPU_GFXHUB(xcc_id);
 319         ring->doorbell_index =
 320                 (adev->doorbell_index.kiq +
 321                  xcc_id * adev->doorbell_index.xcc_doorbell_range)
 322                 << 1;
 323
 324         r = amdgpu_gfx_kiq_acquire(adev, ring, xcc_id);
 325         if (r)
 326                 return r;
 327
 328         ring->eop_gpu_addr = kiq->eop_gpu_addr;
 329         ring->no_scheduler = true;
 330         sprintf(ring->name, "kiq_%d.%d.%d.%d", xcc_id, ring->me, ring->pipe, ring->queue);
 331         r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0,
 332                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 333         if (r)
 334                 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
 335
 336         return r;
 337 }
 338
 339 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
 340 {
 341         amdgpu_ring_fini(ring);
 342 }
 343
 344 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id)
 345 {
 346         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 347
 348         amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
 349 }
 350
 351 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 352                         unsigned hpd_size, int xcc_id)
 353 {
 354         int r;
 355         u32 *hpd;
 356         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 357
 358         r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
 359                                     AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
 360                                     &kiq->eop_gpu_addr, (void **)&hpd);
 361         if (r) {
 362                 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
 363                 return r;
 364         }
 365
 366         memset(hpd, 0, hpd_size);
 367
 368         r = amdgpu_bo_reserve(kiq->eop_obj, true);
 369         if (unlikely(r != 0))
 370                 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
 371         amdgpu_bo_kunmap(kiq->eop_obj);
 372         amdgpu_bo_unreserve(kiq->eop_obj);
 373
 374         return 0;
 375 }
 376
 377 /* create MQD for each compute/gfx queue */
 378 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 379                            unsigned mqd_size, int xcc_id)
 380 {
 381         int r, i, j;
 382         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 383         struct amdgpu_ring *ring = &kiq->ring;
 384         u32 domain = AMDGPU_GEM_DOMAIN_GTT;
 385
 386         /* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */
 387         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0))
 388                 domain |= AMDGPU_GEM_DOMAIN_VRAM;
 389
 390         /* create MQD for KIQ */
 391         if (!adev->enable_mes_kiq && !ring->mqd_obj) {
 392                 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
 393                  * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
 394                  * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
 395                  * KIQ MQD no matter SRIOV or Bare-metal
 396                  */
 397                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 398                                             AMDGPU_GEM_DOMAIN_VRAM |
 399                                             AMDGPU_GEM_DOMAIN_GTT,
 400                                             &ring->mqd_obj,
 401                                             &ring->mqd_gpu_addr,
 402                                             &ring->mqd_ptr);
 403                 if (r) {
 404                         dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
 405                         return r;
 406                 }
 407
 408                 /* prepare MQD backup */
 409                 kiq->mqd_backup = kmalloc(mqd_size, GFP_KERNEL);
 410                 if (!kiq->mqd_backup)
 411                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 412         }
 413
 414         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 415                 /* create MQD for each KGQ */
 416                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 417                         ring = &adev->gfx.gfx_ring[i];
 418                         if (!ring->mqd_obj) {
 419                                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 420                                                             domain, &ring->mqd_obj,
 421                                                             &ring->mqd_gpu_addr, &ring->mqd_ptr);
 422                                 if (r) {
 423                                         dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 424                                         return r;
 425                                 }
 426
 427                                 ring->mqd_size = mqd_size;
 428                                 /* prepare MQD backup */
 429                                 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
 430                                 if (!adev->gfx.me.mqd_backup[i])
 431                                         dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 432                         }
 433                 }
 434         }
 435
 436         /* create MQD for each KCQ */
 437         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 438                 j = i + xcc_id * adev->gfx.num_compute_rings;
 439                 ring = &adev->gfx.compute_ring[j];
 440                 if (!ring->mqd_obj) {
 441                         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 442                                                     domain, &ring->mqd_obj,
 443                                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
 444                         if (r) {
 445                                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 446                                 return r;
 447                         }
 448
 449                         ring->mqd_size = mqd_size;
 450                         /* prepare MQD backup */
 451                         adev->gfx.mec.mqd_backup[j] = kmalloc(mqd_size, GFP_KERNEL);
 452                         if (!adev->gfx.mec.mqd_backup[j])
 453                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 454                 }
 455         }
 456
 457         return 0;
 458 }
 459
 460 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id)
 461 {
 462         struct amdgpu_ring *ring = NULL;
 463         int i, j;
 464         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 465
 466         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 467                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 468                         ring = &adev->gfx.gfx_ring[i];
 469                         kfree(adev->gfx.me.mqd_backup[i]);
 470                         amdgpu_bo_free_kernel(&ring->mqd_obj,
 471                                               &ring->mqd_gpu_addr,
 472                                               &ring->mqd_ptr);
 473                 }
 474         }
 475
 476         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 477                 j = i + xcc_id * adev->gfx.num_compute_rings;
 478                 ring = &adev->gfx.compute_ring[j];
 479                 kfree(adev->gfx.mec.mqd_backup[j]);
 480                 amdgpu_bo_free_kernel(&ring->mqd_obj,
 481                                       &ring->mqd_gpu_addr,
 482                                       &ring->mqd_ptr);
 483         }
 484
 485         ring = &kiq->ring;
 486         kfree(kiq->mqd_backup);
 487         amdgpu_bo_free_kernel(&ring->mqd_obj,
 488                               &ring->mqd_gpu_addr,
 489                               &ring->mqd_ptr);
 490 }
 491
 492 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id)
 493 {
 494         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 495         struct amdgpu_ring *kiq_ring = &kiq->ring;
 496         int i, r = 0;
 497         int j;
 498
 499         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 500                 return -EINVAL;
 501
 502         spin_lock(&kiq->ring_lock);
 503         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 504                                         adev->gfx.num_compute_rings)) {
 505                 spin_unlock(&kiq->ring_lock);
 506                 return -ENOMEM;
 507         }
 508
 509         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 510                 j = i + xcc_id * adev->gfx.num_compute_rings;
 511                 kiq->pmf->kiq_unmap_queues(kiq_ring,
 512                                            &adev->gfx.compute_ring[j],
 513                                            RESET_QUEUES, 0, 0);
 514         }
 515
 516         if (kiq_ring->sched.ready && !adev->job_hang)
 517                 r = amdgpu_ring_test_helper(kiq_ring);
 518         spin_unlock(&kiq->ring_lock);
 519
 520         return r;
 521 }
 522
 523 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id)
 524 {
 525         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 526         struct amdgpu_ring *kiq_ring = &kiq->ring;
 527         int i, r = 0;
 528         int j;
 529
 530         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 531                 return -EINVAL;
 532
 533         spin_lock(&kiq->ring_lock);
 534         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 535                 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 536                                                 adev->gfx.num_gfx_rings)) {
 537                         spin_unlock(&kiq->ring_lock);
 538                         return -ENOMEM;
 539                 }
 540
 541                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 542                         j = i + xcc_id * adev->gfx.num_gfx_rings;
 543                         kiq->pmf->kiq_unmap_queues(kiq_ring,
 544                                                    &adev->gfx.gfx_ring[j],
 545                                                    PREEMPT_QUEUES, 0, 0);
 546                 }
 547         }
 548
 549         if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang)
 550                 r = amdgpu_ring_test_helper(kiq_ring);
 551         spin_unlock(&kiq->ring_lock);
 552
 553         return r;
 554 }
 555
 556 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
 557                                         int queue_bit)
 558 {
 559         int mec, pipe, queue;
 560         int set_resource_bit = 0;
 561
 562         amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 563
 564         set_resource_bit = mec * 4 * 8 + pipe * 8 + queue;
 565
 566         return set_resource_bit;
 567 }
 568
 569 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id)
 570 {
 571         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 572         struct amdgpu_ring *kiq_ring = &kiq->ring;
 573         uint64_t queue_mask = 0;
 574         int r, i, j;
 575
 576         if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
 577                 return -EINVAL;
 578
 579         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
 580                 if (!test_bit(i, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
 581                         continue;
 582
 583                 /* This situation may be hit in the future if a new HW
 584                  * generation exposes more than 64 queues. If so, the
 585                  * definition of queue_mask needs updating */
 586                 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
 587                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
 588                         break;
 589                 }
 590
 591                 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i));
 592         }
 593
 594         DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
 595                                                         kiq_ring->queue);
 596         amdgpu_device_flush_hdp(adev, NULL);
 597
 598         spin_lock(&kiq->ring_lock);
 599         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 600                                         adev->gfx.num_compute_rings +
 601                                         kiq->pmf->set_resources_size);
 602         if (r) {
 603                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 604                 spin_unlock(&kiq->ring_lock);
 605                 return r;
 606         }
 607
 608         if (adev->enable_mes)
 609                 queue_mask = ~0ULL;
 610
 611         kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
 612         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 613                 j = i + xcc_id * adev->gfx.num_compute_rings;
 614                         kiq->pmf->kiq_map_queues(kiq_ring,
 615                                                  &adev->gfx.compute_ring[j]);
 616         }
 617
 618         r = amdgpu_ring_test_helper(kiq_ring);
 619         spin_unlock(&kiq->ring_lock);
 620         if (r)
 621                 DRM_ERROR("KCQ enable failed\n");
 622
 623         return r;
 624 }
 625
 626 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id)
 627 {
 628         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 629         struct amdgpu_ring *kiq_ring = &kiq->ring;
 630         int r, i, j;
 631
 632         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
 633                 return -EINVAL;
 634
 635         amdgpu_device_flush_hdp(adev, NULL);
 636
 637         spin_lock(&kiq->ring_lock);
 638         /* No need to map kcq on the slave */
 639         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 640                 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 641                                                 adev->gfx.num_gfx_rings);
 642                 if (r) {
 643                         DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 644                         spin_unlock(&kiq->ring_lock);
 645                         return r;
 646                 }
 647
 648                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 649                         j = i + xcc_id * adev->gfx.num_gfx_rings;
 650                         kiq->pmf->kiq_map_queues(kiq_ring,
 651                                                  &adev->gfx.gfx_ring[j]);
 652                 }
 653         }
 654
 655         r = amdgpu_ring_test_helper(kiq_ring);
 656         spin_unlock(&kiq->ring_lock);
 657         if (r)
 658                 DRM_ERROR("KCQ enable failed\n");
 659
 660         return r;
 661 }
 662
 663 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
 664  *
 665  * @adev: amdgpu_device pointer
 666  * @bool enable true: enable gfx off feature, false: disable gfx off feature
 667  *
 668  * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.
 669  * 2. other client can send request to disable gfx off feature, the request should be honored.
 670  * 3. other client can cancel their request of disable gfx off feature
 671  * 4. other client should not send request to enable gfx off feature before disable gfx off feature.
 672  */
 673
 674 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
 675 {
 676         unsigned long delay = GFX_OFF_DELAY_ENABLE;
 677
 678         if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 679                 return;
 680
 681         mutex_lock(&adev->gfx.gfx_off_mutex);
 682
 683         if (enable) {
 684                 /* If the count is already 0, it means there's an imbalance bug somewhere.
 685                  * Note that the bug may be in a different caller than the one which triggers the
 686                  * WARN_ON_ONCE.
 687                  */
 688                 if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0))
 689                         goto unlock;
 690
 691                 adev->gfx.gfx_off_req_count--;
 692
 693                 if (adev->gfx.gfx_off_req_count == 0 &&
 694                     !adev->gfx.gfx_off_state) {
 695                         schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
 696                                               delay);
 697                 }
 698         } else {
 699                 if (adev->gfx.gfx_off_req_count == 0) {
 700                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
 701
 702                         if (adev->gfx.gfx_off_state &&
 703                             !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
 704                                 adev->gfx.gfx_off_state = false;
 705
 706                                 if (adev->gfx.funcs->init_spm_golden) {
 707                                         dev_dbg(adev->dev,
 708                                                 "GFXOFF is disabled, re-init SPM golden settings\n");
 709                                         amdgpu_gfx_init_spm_golden(adev);
 710                                 }
 711                         }
 712                 }
 713
 714                 adev->gfx.gfx_off_req_count++;
 715         }
 716
 717 unlock:
 718         mutex_unlock(&adev->gfx.gfx_off_mutex);
 719 }
 720
 721 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value)
 722 {
 723         int r = 0;
 724
 725         mutex_lock(&adev->gfx.gfx_off_mutex);
 726
 727         r = amdgpu_dpm_set_residency_gfxoff(adev, value);
 728
 729         mutex_unlock(&adev->gfx.gfx_off_mutex);
 730
 731         return r;
 732 }
 733
 734 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *value)
 735 {
 736         int r = 0;
 737
 738         mutex_lock(&adev->gfx.gfx_off_mutex);
 739
 740         r = amdgpu_dpm_get_residency_gfxoff(adev, value);
 741
 742         mutex_unlock(&adev->gfx.gfx_off_mutex);
 743
 744         return r;
 745 }
 746
 747 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value)
 748 {
 749         int r = 0;
 750
 751         mutex_lock(&adev->gfx.gfx_off_mutex);
 752
 753         r = amdgpu_dpm_get_entrycount_gfxoff(adev, value);
 754
 755         mutex_unlock(&adev->gfx.gfx_off_mutex);
 756
 757         return r;
 758 }
 759
 760 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value)
 761 {
 762
 763         int r = 0;
 764
 765         mutex_lock(&adev->gfx.gfx_off_mutex);
 766
 767         r = amdgpu_dpm_get_status_gfxoff(adev, value);
 768
 769         mutex_unlock(&adev->gfx.gfx_off_mutex);
 770
 771         return r;
 772 }
 773
 774 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 775 {
 776         int r;
 777
 778         if (amdgpu_ras_is_supported(adev, ras_block->block)) {
 779                 if (!amdgpu_persistent_edc_harvesting_supported(adev))
 780                         amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX);
 781
 782                 r = amdgpu_ras_block_late_init(adev, ras_block);
 783                 if (r)
 784                         return r;
 785
 786                 if (adev->gfx.cp_ecc_error_irq.funcs) {
 787                         r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
 788                         if (r)
 789                                 goto late_fini;
 790                 }
 791         } else {
 792                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
 793         }
 794
 795         return 0;
 796 late_fini:
 797         amdgpu_ras_block_late_fini(adev, ras_block);
 798         return r;
 799 }
 800
 801 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev)
 802 {
 803         int err = 0;
 804         struct amdgpu_gfx_ras *ras = NULL;
 805
 806         /* adev->gfx.ras is NULL, which means gfx does not
 807          * support ras function, then do nothing here.
 808          */
 809         if (!adev->gfx.ras)
 810                 return 0;
 811
 812         ras = adev->gfx.ras;
 813
 814         err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
 815         if (err) {
 816                 dev_err(adev->dev, "Failed to register gfx ras block!\n");
 817                 return err;
 818         }
 819
 820         strcpy(ras->ras_block.ras_comm.name, "gfx");
 821         ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX;
 822         ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 823         adev->gfx.ras_if = &ras->ras_block.ras_comm;
 824
 825         /* If not define special ras_late_init function, use gfx default ras_late_init */
 826         if (!ras->ras_block.ras_late_init)
 827                 ras->ras_block.ras_late_init = amdgpu_gfx_ras_late_init;
 828
 829         /* If not defined special ras_cb function, use default ras_cb */
 830         if (!ras->ras_block.ras_cb)
 831                 ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb;
 832
 833         return 0;
 834 }
 835
 836 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
 837                                                 struct amdgpu_iv_entry *entry)
 838 {
 839         if (adev->gfx.ras && adev->gfx.ras->poison_consumption_handler)
 840                 return adev->gfx.ras->poison_consumption_handler(adev, entry);
 841
 842         return 0;
 843 }
 844
 845 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
 846                 void *err_data,
 847                 struct amdgpu_iv_entry *entry)
 848 {
 849         /* TODO ue will trigger an interrupt.
 850          *
 851          * When “Full RAS” is enabled, the per-IP interrupt sources should
 852          * be disabled and the driver should only look for the aggregated
 853          * interrupt via sync flood
 854          */
 855         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
 856                 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 857                 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops &&
 858                     adev->gfx.ras->ras_block.hw_ops->query_ras_error_count)
 859                         adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
 860                 amdgpu_ras_reset_gpu(adev);
 861         }
 862         return AMDGPU_RAS_SUCCESS;
 863 }
 864
 865 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
 866                                   struct amdgpu_irq_src *source,
 867                                   struct amdgpu_iv_entry *entry)
 868 {
 869         struct ras_common_if *ras_if = adev->gfx.ras_if;
 870         struct ras_dispatch_if ih_data = {
 871                 .entry = entry,
 872         };
 873
 874         if (!ras_if)
 875                 return 0;
 876
 877         ih_data.head = *ras_if;
 878
 879         DRM_ERROR("CP ECC ERROR IRQ\n");
 880         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
 881         return 0;
 882 }
 883
 884 void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev,
 885                 void *ras_error_status,
 886                 void (*func)(struct amdgpu_device *adev, void *ras_error_status,
 887                                 int xcc_id))
 888 {
 889         int i;
 890         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 891         uint32_t xcc_mask = GENMASK(num_xcc - 1, 0);
 892         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 893
 894         if (err_data) {
 895                 err_data->ue_count = 0;
 896                 err_data->ce_count = 0;
 897         }
 898
 899         for_each_inst(i, xcc_mask)
 900                 func(adev, ras_error_status, i);
 901 }
 902
 903 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
 904 {
 905         signed long r, cnt = 0;
 906         unsigned long flags;
 907         uint32_t seq, reg_val_offs = 0, value = 0;
 908         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 909         struct amdgpu_ring *ring = &kiq->ring;
 910
 911         if (amdgpu_device_skip_hw_access(adev))
 912                 return 0;
 913
 914         if (adev->mes.ring.sched.ready)
 915                 return amdgpu_mes_rreg(adev, reg);
 916
 917         BUG_ON(!ring->funcs->emit_rreg);
 918
 919         spin_lock_irqsave(&kiq->ring_lock, flags);
 920         if (amdgpu_device_wb_get(adev, &reg_val_offs)) {
 921                 pr_err("critical bug! too many kiq readers\n");
 922                 goto failed_unlock;
 923         }
 924         amdgpu_ring_alloc(ring, 32);
 925         amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
 926         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 927         if (r)
 928                 goto failed_undo;
 929
 930         amdgpu_ring_commit(ring);
 931         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 932
 933         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 934
 935         /* don't wait anymore for gpu reset case because this way may
 936          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 937          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 938          * never return if we keep waiting in virt_kiq_rreg, which cause
 939          * gpu_recover() hang there.
 940          *
 941          * also don't wait anymore for IRQ context
 942          * */
 943         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
 944                 goto failed_kiq_read;
 945
 946         might_sleep();
 947         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 948                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 949                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 950         }
 951
 952         if (cnt > MAX_KIQ_REG_TRY)
 953                 goto failed_kiq_read;
 954
 955         mb();
 956         value = adev->wb.wb[reg_val_offs];
 957         amdgpu_device_wb_free(adev, reg_val_offs);
 958         return value;
 959
 960 failed_undo:
 961         amdgpu_ring_undo(ring);
 962 failed_unlock:
 963         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 964 failed_kiq_read:
 965         if (reg_val_offs)
 966                 amdgpu_device_wb_free(adev, reg_val_offs);
 967         dev_err(adev->dev, "failed to read reg:%x\n", reg);
 968         return ~0;
 969 }
 970
 971 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 972 {
 973         signed long r, cnt = 0;
 974         unsigned long flags;
 975         uint32_t seq;
 976         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 977         struct amdgpu_ring *ring = &kiq->ring;
 978
 979         BUG_ON(!ring->funcs->emit_wreg);
 980
 981         if (amdgpu_device_skip_hw_access(adev))
 982                 return;
 983
 984         if (adev->mes.ring.sched.ready) {
 985                 amdgpu_mes_wreg(adev, reg, v);
 986                 return;
 987         }
 988
 989         spin_lock_irqsave(&kiq->ring_lock, flags);
 990         amdgpu_ring_alloc(ring, 32);
 991         amdgpu_ring_emit_wreg(ring, reg, v);
 992         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 993         if (r)
 994                 goto failed_undo;
 995
 996         amdgpu_ring_commit(ring);
 997         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 998
 999         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
1000
1001         /* don't wait anymore for gpu reset case because this way may
1002          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
1003          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
1004          * never return if we keep waiting in virt_kiq_rreg, which cause
1005          * gpu_recover() hang there.
1006          *
1007          * also don't wait anymore for IRQ context
1008          * */
1009         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
1010                 goto failed_kiq_write;
1011
1012         might_sleep();
1013         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
1014
1015                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
1016                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
1017         }
1018
1019         if (cnt > MAX_KIQ_REG_TRY)
1020                 goto failed_kiq_write;
1021
1022         return;
1023
1024 failed_undo:
1025         amdgpu_ring_undo(ring);
1026         spin_unlock_irqrestore(&kiq->ring_lock, flags);
1027 failed_kiq_write:
1028         dev_err(adev->dev, "failed to write reg:%x\n", reg);
1029 }
1030
1031 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
1032 {
1033         if (amdgpu_num_kcq == -1) {
1034                 return 8;
1035         } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
1036                 dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
1037                 return 8;
1038         }
1039         return amdgpu_num_kcq;
1040 }
1041
1042 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev,
1043                                   uint32_t ucode_id)
1044 {
1045         const struct gfx_firmware_header_v1_0 *cp_hdr;
1046         const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
1047         struct amdgpu_firmware_info *info = NULL;
1048         const struct firmware *ucode_fw;
1049         unsigned int fw_size;
1050
1051         switch (ucode_id) {
1052         case AMDGPU_UCODE_ID_CP_PFP:
1053                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1054                         adev->gfx.pfp_fw->data;
1055                 adev->gfx.pfp_fw_version =
1056                         le32_to_cpu(cp_hdr->header.ucode_version);
1057                 adev->gfx.pfp_feature_version =
1058                         le32_to_cpu(cp_hdr->ucode_feature_version);
1059                 ucode_fw = adev->gfx.pfp_fw;
1060                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1061                 break;
1062         case AMDGPU_UCODE_ID_CP_RS64_PFP:
1063                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1064                         adev->gfx.pfp_fw->data;
1065                 adev->gfx.pfp_fw_version =
1066                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1067                 adev->gfx.pfp_feature_version =
1068                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1069                 ucode_fw = adev->gfx.pfp_fw;
1070                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1071                 break;
1072         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
1073         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
1074                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1075                         adev->gfx.pfp_fw->data;
1076                 ucode_fw = adev->gfx.pfp_fw;
1077                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1078                 break;
1079         case AMDGPU_UCODE_ID_CP_ME:
1080                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1081                         adev->gfx.me_fw->data;
1082                 adev->gfx.me_fw_version =
1083                         le32_to_cpu(cp_hdr->header.ucode_version);
1084                 adev->gfx.me_feature_version =
1085                         le32_to_cpu(cp_hdr->ucode_feature_version);
1086                 ucode_fw = adev->gfx.me_fw;
1087                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1088                 break;
1089         case AMDGPU_UCODE_ID_CP_RS64_ME:
1090                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1091                         adev->gfx.me_fw->data;
1092                 adev->gfx.me_fw_version =
1093                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1094                 adev->gfx.me_feature_version =
1095                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1096                 ucode_fw = adev->gfx.me_fw;
1097                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1098                 break;
1099         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
1100         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
1101                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1102                         adev->gfx.me_fw->data;
1103                 ucode_fw = adev->gfx.me_fw;
1104                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1105                 break;
1106         case AMDGPU_UCODE_ID_CP_CE:
1107                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1108                         adev->gfx.ce_fw->data;
1109                 adev->gfx.ce_fw_version =
1110                         le32_to_cpu(cp_hdr->header.ucode_version);
1111                 adev->gfx.ce_feature_version =
1112                         le32_to_cpu(cp_hdr->ucode_feature_version);
1113                 ucode_fw = adev->gfx.ce_fw;
1114                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1115                 break;
1116         case AMDGPU_UCODE_ID_CP_MEC1:
1117                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1118                         adev->gfx.mec_fw->data;
1119                 adev->gfx.mec_fw_version =
1120                         le32_to_cpu(cp_hdr->header.ucode_version);
1121                 adev->gfx.mec_feature_version =
1122                         le32_to_cpu(cp_hdr->ucode_feature_version);
1123                 ucode_fw = adev->gfx.mec_fw;
1124                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1125                           le32_to_cpu(cp_hdr->jt_size) * 4;
1126                 break;
1127         case AMDGPU_UCODE_ID_CP_MEC1_JT:
1128                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1129                         adev->gfx.mec_fw->data;
1130                 ucode_fw = adev->gfx.mec_fw;
1131                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1132                 break;
1133         case AMDGPU_UCODE_ID_CP_MEC2:
1134                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1135                         adev->gfx.mec2_fw->data;
1136                 adev->gfx.mec2_fw_version =
1137                         le32_to_cpu(cp_hdr->header.ucode_version);
1138                 adev->gfx.mec2_feature_version =
1139                         le32_to_cpu(cp_hdr->ucode_feature_version);
1140                 ucode_fw = adev->gfx.mec2_fw;
1141                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1142                           le32_to_cpu(cp_hdr->jt_size) * 4;
1143                 break;
1144         case AMDGPU_UCODE_ID_CP_MEC2_JT:
1145                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1146                         adev->gfx.mec2_fw->data;
1147                 ucode_fw = adev->gfx.mec2_fw;
1148                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1149                 break;
1150         case AMDGPU_UCODE_ID_CP_RS64_MEC:
1151                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1152                         adev->gfx.mec_fw->data;
1153                 adev->gfx.mec_fw_version =
1154                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1155                 adev->gfx.mec_feature_version =
1156                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1157                 ucode_fw = adev->gfx.mec_fw;
1158                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1159                 break;
1160         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
1161         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
1162         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
1163         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
1164                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1165                         adev->gfx.mec_fw->data;
1166                 ucode_fw = adev->gfx.mec_fw;
1167                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1168                 break;
1169         default:
1170                 break;
1171         }
1172
1173         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1174                 info = &adev->firmware.ucode[ucode_id];
1175                 info->ucode_id = ucode_id;
1176                 info->fw = ucode_fw;
1177                 adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE);
1178         }
1179 }
1180
1181 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id)
1182 {
1183         return !(xcc_id % (adev->gfx.num_xcc_per_xcp ?
1184                         adev->gfx.num_xcc_per_xcp : 1));
1185 }
1186
1187 static ssize_t amdgpu_gfx_get_current_compute_partition(struct device *dev,
1188                                                 struct device_attribute *addr,
1189                                                 char *buf)
1190 {
1191         struct drm_device *ddev = dev_get_drvdata(dev);
1192         struct amdgpu_device *adev = drm_to_adev(ddev);
1193         int mode;
1194
1195         mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr,
1196                                                AMDGPU_XCP_FL_NONE);
1197
1198         return sysfs_emit(buf, "%s\n", amdgpu_gfx_compute_mode_desc(mode));
1199 }
1200
1201 static ssize_t amdgpu_gfx_set_compute_partition(struct device *dev,
1202                                                 struct device_attribute *addr,
1203                                                 const char *buf, size_t count)
1204 {
1205         struct drm_device *ddev = dev_get_drvdata(dev);
1206         struct amdgpu_device *adev = drm_to_adev(ddev);
1207         enum amdgpu_gfx_partition mode;
1208         int ret = 0, num_xcc;
1209
1210         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1211         if (num_xcc % 2 != 0)
1212                 return -EINVAL;
1213
1214         if (!strncasecmp("SPX", buf, strlen("SPX"))) {
1215                 mode = AMDGPU_SPX_PARTITION_MODE;
1216         } else if (!strncasecmp("DPX", buf, strlen("DPX"))) {
1217                 /*
1218                  * DPX mode needs AIDs to be in multiple of 2.
1219                  * Each AID connects 2 XCCs.
1220                  */
1221                 if (num_xcc%4)
1222                         return -EINVAL;
1223                 mode = AMDGPU_DPX_PARTITION_MODE;
1224         } else if (!strncasecmp("TPX", buf, strlen("TPX"))) {
1225                 if (num_xcc != 6)
1226                         return -EINVAL;
1227                 mode = AMDGPU_TPX_PARTITION_MODE;
1228         } else if (!strncasecmp("QPX", buf, strlen("QPX"))) {
1229                 if (num_xcc != 8)
1230                         return -EINVAL;
1231                 mode = AMDGPU_QPX_PARTITION_MODE;
1232         } else if (!strncasecmp("CPX", buf, strlen("CPX"))) {
1233                 mode = AMDGPU_CPX_PARTITION_MODE;
1234         } else {
1235                 return -EINVAL;
1236         }
1237
1238         ret = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, mode);
1239
1240         if (ret)
1241                 return ret;
1242
1243         return count;
1244 }
1245
1246 static ssize_t amdgpu_gfx_get_available_compute_partition(struct device *dev,
1247                                                 struct device_attribute *addr,
1248                                                 char *buf)
1249 {
1250         struct drm_device *ddev = dev_get_drvdata(dev);
1251         struct amdgpu_device *adev = drm_to_adev(ddev);
1252         char *supported_partition;
1253
1254         /* TBD */
1255         switch (NUM_XCC(adev->gfx.xcc_mask)) {
1256         case 8:
1257                 supported_partition = "SPX, DPX, QPX, CPX";
1258                 break;
1259         case 6:
1260                 supported_partition = "SPX, TPX, CPX";
1261                 break;
1262         case 4:
1263                 supported_partition = "SPX, DPX, CPX";
1264                 break;
1265         /* this seems only existing in emulation phase */
1266         case 2:
1267                 supported_partition = "SPX, CPX";
1268                 break;
1269         default:
1270                 supported_partition = "Not supported";
1271                 break;
1272         }
1273
1274         return sysfs_emit(buf, "%s\n", supported_partition);
1275 }
1276
1277 static DEVICE_ATTR(current_compute_partition, S_IRUGO | S_IWUSR,
1278                    amdgpu_gfx_get_current_compute_partition,
1279                    amdgpu_gfx_set_compute_partition);
1280
1281 static DEVICE_ATTR(available_compute_partition, S_IRUGO,
1282                    amdgpu_gfx_get_available_compute_partition, NULL);
1283
1284 int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev)
1285 {
1286         int r;
1287
1288         r = device_create_file(adev->dev, &dev_attr_current_compute_partition);
1289         if (r)
1290                 return r;
1291
1292         r = device_create_file(adev->dev, &dev_attr_available_compute_partition);
1293
1294         return r;
1295 }
1296
1297 void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev)
1298 {
1299         device_remove_file(adev->dev, &dev_attr_current_compute_partition);
1300         device_remove_file(adev->dev, &dev_attr_available_compute_partition);
1301 }