drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39 #include "amdgpu_amdkfd.h"
  40
  41 static bool amdgpu_need_backup(struct amdgpu_device *adev)
  42 {
  43         if (adev->flags & AMD_IS_APU)
  44                 return false;
  45
  46         if (amdgpu_gpu_recovery == 0 ||
  47             (amdgpu_gpu_recovery == -1  && !amdgpu_sriov_vf(adev)))
  48                 return false;
  49
  50         return true;
  51 }
  52
  53 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  54 {
  55         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
  56         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
  57
  58         if (bo->kfd_bo)
  59                 amdgpu_amdkfd_unreserve_system_memory_limit(bo);
  60
  61         amdgpu_bo_kunmap(bo);
  62
  63         drm_gem_object_release(&bo->gem_base);
  64         amdgpu_bo_unref(&bo->parent);
  65         if (!list_empty(&bo->shadow_list)) {
  66                 mutex_lock(&adev->shadow_list_lock);
  67                 list_del_init(&bo->shadow_list);
  68                 mutex_unlock(&adev->shadow_list_lock);
  69         }
  70         kfree(bo->metadata);
  71         kfree(bo);
  72 }
  73
  74 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
  75 {
  76         if (bo->destroy == &amdgpu_ttm_bo_destroy)
  77                 return true;
  78         return false;
  79 }
  80
  81 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
  82 {
  83         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
  84         struct ttm_placement *placement = &abo->placement;
  85         struct ttm_place *places = abo->placements;
  86         u64 flags = abo->flags;
  87         u32 c = 0;
  88
  89         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
  90                 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
  91
  92                 places[c].fpfn = 0;
  93                 places[c].lpfn = 0;
  94                 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  95                         TTM_PL_FLAG_VRAM;
  96
  97                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
  98                         places[c].lpfn = visible_pfn;
  99                 else
 100                         places[c].flags |= TTM_PL_FLAG_TOPDOWN;
 101
 102                 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
 103                         places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
 104                 c++;
 105         }
 106
 107         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 108                 places[c].fpfn = 0;
 109                 if (flags & AMDGPU_GEM_CREATE_SHADOW)
 110                         places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 111                 else
 112                         places[c].lpfn = 0;
 113                 places[c].flags = TTM_PL_FLAG_TT;
 114                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 115                         places[c].flags |= TTM_PL_FLAG_WC |
 116                                 TTM_PL_FLAG_UNCACHED;
 117                 else
 118                         places[c].flags |= TTM_PL_FLAG_CACHED;
 119                 c++;
 120         }
 121
 122         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 123                 places[c].fpfn = 0;
 124                 places[c].lpfn = 0;
 125                 places[c].flags = TTM_PL_FLAG_SYSTEM;
 126                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 127                         places[c].flags |= TTM_PL_FLAG_WC |
 128                                 TTM_PL_FLAG_UNCACHED;
 129                 else
 130                         places[c].flags |= TTM_PL_FLAG_CACHED;
 131                 c++;
 132         }
 133
 134         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 135                 places[c].fpfn = 0;
 136                 places[c].lpfn = 0;
 137                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
 138                 c++;
 139         }
 140
 141         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 142                 places[c].fpfn = 0;
 143                 places[c].lpfn = 0;
 144                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
 145                 c++;
 146         }
 147
 148         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 149                 places[c].fpfn = 0;
 150                 places[c].lpfn = 0;
 151                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
 152                 c++;
 153         }
 154
 155         if (!c) {
 156                 places[c].fpfn = 0;
 157                 places[c].lpfn = 0;
 158                 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 159                 c++;
 160         }
 161
 162         placement->num_placement = c;
 163         placement->placement = places;
 164
 165         placement->num_busy_placement = c;
 166         placement->busy_placement = places;
 167 }
 168
 169 /**
 170  * amdgpu_bo_create_reserved - create reserved BO for kernel use
 171  *
 172  * @adev: amdgpu device object
 173  * @size: size for the new BO
 174  * @align: alignment for the new BO
 175  * @domain: where to place it
 176  * @bo_ptr: resulting BO
 177  * @gpu_addr: GPU addr of the pinned BO
 178  * @cpu_addr: optional CPU address mapping
 179  *
 180  * Allocates and pins a BO for kernel internal use, and returns it still
 181  * reserved.
 182  *
 183  * Returns 0 on success, negative error code otherwise.
 184  */
 185 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 186                               unsigned long size, int align,
 187                               u32 domain, struct amdgpu_bo **bo_ptr,
 188                               u64 *gpu_addr, void **cpu_addr)
 189 {
 190         bool free = false;
 191         int r;
 192
 193         if (!*bo_ptr) {
 194                 r = amdgpu_bo_create(adev, size, align, domain,
 195                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 196                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 197                                      ttm_bo_type_kernel, NULL, bo_ptr);
 198                 if (r) {
 199                         dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
 200                                 r);
 201                         return r;
 202                 }
 203                 free = true;
 204         }
 205
 206         r = amdgpu_bo_reserve(*bo_ptr, false);
 207         if (r) {
 208                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 209                 goto error_free;
 210         }
 211
 212         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 213         if (r) {
 214                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 215                 goto error_unreserve;
 216         }
 217
 218         if (cpu_addr) {
 219                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 220                 if (r) {
 221                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 222                         goto error_unreserve;
 223                 }
 224         }
 225
 226         return 0;
 227
 228 error_unreserve:
 229         amdgpu_bo_unreserve(*bo_ptr);
 230
 231 error_free:
 232         if (free)
 233                 amdgpu_bo_unref(bo_ptr);
 234
 235         return r;
 236 }
 237
 238 /**
 239  * amdgpu_bo_create_kernel - create BO for kernel use
 240  *
 241  * @adev: amdgpu device object
 242  * @size: size for the new BO
 243  * @align: alignment for the new BO
 244  * @domain: where to place it
 245  * @bo_ptr: resulting BO
 246  * @gpu_addr: GPU addr of the pinned BO
 247  * @cpu_addr: optional CPU address mapping
 248  *
 249  * Allocates and pins a BO for kernel internal use.
 250  *
 251  * Returns 0 on success, negative error code otherwise.
 252  */
 253 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 254                             unsigned long size, int align,
 255                             u32 domain, struct amdgpu_bo **bo_ptr,
 256                             u64 *gpu_addr, void **cpu_addr)
 257 {
 258         int r;
 259
 260         r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
 261                                       gpu_addr, cpu_addr);
 262
 263         if (r)
 264                 return r;
 265
 266         amdgpu_bo_unreserve(*bo_ptr);
 267
 268         return 0;
 269 }
 270
 271 /**
 272  * amdgpu_bo_free_kernel - free BO for kernel use
 273  *
 274  * @bo: amdgpu BO to free
 275  *
 276  * unmaps and unpin a BO for kernel internal use.
 277  */
 278 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 279                            void **cpu_addr)
 280 {
 281         if (*bo == NULL)
 282                 return;
 283
 284         if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
 285                 if (cpu_addr)
 286                         amdgpu_bo_kunmap(*bo);
 287
 288                 amdgpu_bo_unpin(*bo);
 289                 amdgpu_bo_unreserve(*bo);
 290         }
 291         amdgpu_bo_unref(bo);
 292
 293         if (gpu_addr)
 294                 *gpu_addr = 0;
 295
 296         if (cpu_addr)
 297                 *cpu_addr = NULL;
 298 }
 299
 300 /* Validate bo size is bit bigger then the request domain */
 301 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
 302                                           unsigned long size, u32 domain)
 303 {
 304         struct ttm_mem_type_manager *man = NULL;
 305
 306         /*
 307          * If GTT is part of requested domains the check must succeed to
 308          * allow fall back to GTT
 309          */
 310         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 311                 man = &adev->mman.bdev.man[TTM_PL_TT];
 312
 313                 if (size < (man->size << PAGE_SHIFT))
 314                         return true;
 315                 else
 316                         goto fail;
 317         }
 318
 319         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 320                 man = &adev->mman.bdev.man[TTM_PL_VRAM];
 321
 322                 if (size < (man->size << PAGE_SHIFT))
 323                         return true;
 324                 else
 325                         goto fail;
 326         }
 327
 328
 329         /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
 330         return true;
 331
 332 fail:
 333         DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
 334                   man->size << PAGE_SHIFT);
 335         return false;
 336 }
 337
 338 static int amdgpu_bo_do_create(struct amdgpu_device *adev, unsigned long size,
 339                                int byte_align, u32 domain,
 340                                u64 flags, enum ttm_bo_type type,
 341                                struct reservation_object *resv,
 342                                struct amdgpu_bo **bo_ptr)
 343 {
 344         struct ttm_operation_ctx ctx = {
 345                 .interruptible = (type != ttm_bo_type_kernel),
 346                 .no_wait_gpu = false,
 347                 .resv = resv,
 348                 .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
 349         };
 350         struct amdgpu_bo *bo;
 351         unsigned long page_align;
 352         size_t acc_size;
 353         int r;
 354
 355         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 356         size = ALIGN(size, PAGE_SIZE);
 357
 358         if (!amdgpu_bo_validate_size(adev, size, domain))
 359                 return -ENOMEM;
 360
 361         *bo_ptr = NULL;
 362
 363         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 364                                        sizeof(struct amdgpu_bo));
 365
 366         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 367         if (bo == NULL)
 368                 return -ENOMEM;
 369         drm_gem_private_object_init(adev->ddev, &bo->gem_base, size);
 370         INIT_LIST_HEAD(&bo->shadow_list);
 371         INIT_LIST_HEAD(&bo->va);
 372         bo->preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 373                                          AMDGPU_GEM_DOMAIN_GTT |
 374                                          AMDGPU_GEM_DOMAIN_CPU |
 375                                          AMDGPU_GEM_DOMAIN_GDS |
 376                                          AMDGPU_GEM_DOMAIN_GWS |
 377                                          AMDGPU_GEM_DOMAIN_OA);
 378         bo->allowed_domains = bo->preferred_domains;
 379         if (type != ttm_bo_type_kernel &&
 380             bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 381                 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 382
 383         bo->flags = flags;
 384
 385 #ifdef CONFIG_X86_32
 386         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 387          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 388          */
 389         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 390 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 391         /* Don't try to enable write-combining when it can't work, or things
 392          * may be slow
 393          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 394          */
 395
 396 #ifndef CONFIG_COMPILE_TEST
 397 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 398          thanks to write-combining
 399 #endif
 400
 401         if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 402                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 403                               "better performance thanks to write-combining\n");
 404         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 405 #else
 406         /* For architectures that don't support WC memory,
 407          * mask out the WC flag from the BO
 408          */
 409         if (!drm_arch_can_wc_memory())
 410                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 411 #endif
 412
 413         bo->tbo.bdev = &adev->mman.bdev;
 414         amdgpu_ttm_placement_from_domain(bo, domain);
 415
 416         r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
 417                                  &bo->placement, page_align, &ctx, acc_size,
 418                                  NULL, resv, &amdgpu_ttm_bo_destroy);
 419         if (unlikely(r != 0))
 420                 return r;
 421
 422         if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 423             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 424             bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
 425                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
 426                                              ctx.bytes_moved);
 427         else
 428                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
 429
 430         if (type == ttm_bo_type_kernel)
 431                 bo->tbo.priority = 1;
 432
 433         if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 434             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 435                 struct dma_fence *fence;
 436
 437                 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
 438                 if (unlikely(r))
 439                         goto fail_unreserve;
 440
 441                 amdgpu_bo_fence(bo, fence, false);
 442                 dma_fence_put(bo->tbo.moving);
 443                 bo->tbo.moving = dma_fence_get(fence);
 444                 dma_fence_put(fence);
 445         }
 446         if (!resv)
 447                 amdgpu_bo_unreserve(bo);
 448         *bo_ptr = bo;
 449
 450         trace_amdgpu_bo_create(bo);
 451
 452         /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
 453         if (type == ttm_bo_type_device)
 454                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 455
 456         return 0;
 457
 458 fail_unreserve:
 459         if (!resv)
 460                 ww_mutex_unlock(&bo->tbo.resv->lock);
 461         amdgpu_bo_unref(&bo);
 462         return r;
 463 }
 464
 465 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 466                                    unsigned long size, int byte_align,
 467                                    struct amdgpu_bo *bo)
 468 {
 469         int r;
 470
 471         if (bo->shadow)
 472                 return 0;
 473
 474         r = amdgpu_bo_do_create(adev, size, byte_align, AMDGPU_GEM_DOMAIN_GTT,
 475                                 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 476                                 AMDGPU_GEM_CREATE_SHADOW,
 477                                 ttm_bo_type_kernel,
 478                                 bo->tbo.resv, &bo->shadow);
 479         if (!r) {
 480                 bo->shadow->parent = amdgpu_bo_ref(bo);
 481                 mutex_lock(&adev->shadow_list_lock);
 482                 list_add_tail(&bo->shadow_list, &adev->shadow_list);
 483                 mutex_unlock(&adev->shadow_list_lock);
 484         }
 485
 486         return r;
 487 }
 488
 489 int amdgpu_bo_create(struct amdgpu_device *adev, unsigned long size,
 490                      int byte_align, u32 domain,
 491                      u64 flags, enum ttm_bo_type type,
 492                      struct reservation_object *resv,
 493                      struct amdgpu_bo **bo_ptr)
 494 {
 495         uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
 496         int r;
 497
 498         r = amdgpu_bo_do_create(adev, size, byte_align, domain,
 499                                 parent_flags, type, resv, bo_ptr);
 500         if (r)
 501                 return r;
 502
 503         if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
 504                 if (!resv)
 505                         WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
 506                                                         NULL));
 507
 508                 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
 509
 510                 if (!resv)
 511                         reservation_object_unlock((*bo_ptr)->tbo.resv);
 512
 513                 if (r)
 514                         amdgpu_bo_unref(bo_ptr);
 515         }
 516
 517         return r;
 518 }
 519
 520 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 521                                struct amdgpu_ring *ring,
 522                                struct amdgpu_bo *bo,
 523                                struct reservation_object *resv,
 524                                struct dma_fence **fence,
 525                                bool direct)
 526
 527 {
 528         struct amdgpu_bo *shadow = bo->shadow;
 529         uint64_t bo_addr, shadow_addr;
 530         int r;
 531
 532         if (!shadow)
 533                 return -EINVAL;
 534
 535         bo_addr = amdgpu_bo_gpu_offset(bo);
 536         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 537
 538         r = reservation_object_reserve_shared(bo->tbo.resv);
 539         if (r)
 540                 goto err;
 541
 542         r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
 543                                amdgpu_bo_size(bo), resv, fence,
 544                                direct, false);
 545         if (!r)
 546                 amdgpu_bo_fence(bo, *fence, true);
 547
 548 err:
 549         return r;
 550 }
 551
 552 int amdgpu_bo_validate(struct amdgpu_bo *bo)
 553 {
 554         struct ttm_operation_ctx ctx = { false, false };
 555         uint32_t domain;
 556         int r;
 557
 558         if (bo->pin_count)
 559                 return 0;
 560
 561         domain = bo->preferred_domains;
 562
 563 retry:
 564         amdgpu_ttm_placement_from_domain(bo, domain);
 565         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 566         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 567                 domain = bo->allowed_domains;
 568                 goto retry;
 569         }
 570
 571         return r;
 572 }
 573
 574 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 575                                   struct amdgpu_ring *ring,
 576                                   struct amdgpu_bo *bo,
 577                                   struct reservation_object *resv,
 578                                   struct dma_fence **fence,
 579                                   bool direct)
 580
 581 {
 582         struct amdgpu_bo *shadow = bo->shadow;
 583         uint64_t bo_addr, shadow_addr;
 584         int r;
 585
 586         if (!shadow)
 587                 return -EINVAL;
 588
 589         bo_addr = amdgpu_bo_gpu_offset(bo);
 590         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 591
 592         r = reservation_object_reserve_shared(bo->tbo.resv);
 593         if (r)
 594                 goto err;
 595
 596         r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
 597                                amdgpu_bo_size(bo), resv, fence,
 598                                direct, false);
 599         if (!r)
 600                 amdgpu_bo_fence(bo, *fence, true);
 601
 602 err:
 603         return r;
 604 }
 605
 606 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 607 {
 608         void *kptr;
 609         long r;
 610
 611         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 612                 return -EPERM;
 613
 614         kptr = amdgpu_bo_kptr(bo);
 615         if (kptr) {
 616                 if (ptr)
 617                         *ptr = kptr;
 618                 return 0;
 619         }
 620
 621         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 622                                                 MAX_SCHEDULE_TIMEOUT);
 623         if (r < 0)
 624                 return r;
 625
 626         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 627         if (r)
 628                 return r;
 629
 630         if (ptr)
 631                 *ptr = amdgpu_bo_kptr(bo);
 632
 633         return 0;
 634 }
 635
 636 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
 637 {
 638         bool is_iomem;
 639
 640         return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 641 }
 642
 643 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 644 {
 645         if (bo->kmap.bo)
 646                 ttm_bo_kunmap(&bo->kmap);
 647 }
 648
 649 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 650 {
 651         if (bo == NULL)
 652                 return NULL;
 653
 654         ttm_bo_reference(&bo->tbo);
 655         return bo;
 656 }
 657
 658 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 659 {
 660         struct ttm_buffer_object *tbo;
 661
 662         if ((*bo) == NULL)
 663                 return;
 664
 665         tbo = &((*bo)->tbo);
 666         ttm_bo_unref(&tbo);
 667         if (tbo == NULL)
 668                 *bo = NULL;
 669 }
 670
 671 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 672                              u64 min_offset, u64 max_offset,
 673                              u64 *gpu_addr)
 674 {
 675         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 676         struct ttm_operation_ctx ctx = { false, false };
 677         int r, i;
 678
 679         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 680                 return -EPERM;
 681
 682         if (WARN_ON_ONCE(min_offset > max_offset))
 683                 return -EINVAL;
 684
 685         /* A shared bo cannot be migrated to VRAM */
 686         if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
 687                 return -EINVAL;
 688
 689         if (bo->pin_count) {
 690                 uint32_t mem_type = bo->tbo.mem.mem_type;
 691
 692                 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
 693                         return -EINVAL;
 694
 695                 bo->pin_count++;
 696                 if (gpu_addr)
 697                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 698
 699                 if (max_offset != 0) {
 700                         u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
 701                         WARN_ON_ONCE(max_offset <
 702                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 703                 }
 704
 705                 return 0;
 706         }
 707
 708         bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 709         /* force to pin into visible video ram */
 710         if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
 711                 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 712         amdgpu_ttm_placement_from_domain(bo, domain);
 713         for (i = 0; i < bo->placement.num_placement; i++) {
 714                 unsigned fpfn, lpfn;
 715
 716                 fpfn = min_offset >> PAGE_SHIFT;
 717                 lpfn = max_offset >> PAGE_SHIFT;
 718
 719                 if (fpfn > bo->placements[i].fpfn)
 720                         bo->placements[i].fpfn = fpfn;
 721                 if (!bo->placements[i].lpfn ||
 722                     (lpfn && lpfn < bo->placements[i].lpfn))
 723                         bo->placements[i].lpfn = lpfn;
 724                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 725         }
 726
 727         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 728         if (unlikely(r)) {
 729                 dev_err(adev->dev, "%p pin failed\n", bo);
 730                 goto error;
 731         }
 732
 733         r = amdgpu_ttm_alloc_gart(&bo->tbo);
 734         if (unlikely(r)) {
 735                 dev_err(adev->dev, "%p bind failed\n", bo);
 736                 goto error;
 737         }
 738
 739         bo->pin_count = 1;
 740         if (gpu_addr != NULL)
 741                 *gpu_addr = amdgpu_bo_gpu_offset(bo);
 742
 743         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 744         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 745                 adev->vram_pin_size += amdgpu_bo_size(bo);
 746                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 747                         adev->invisible_pin_size += amdgpu_bo_size(bo);
 748         } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 749                 adev->gart_pin_size += amdgpu_bo_size(bo);
 750         }
 751
 752 error:
 753         return r;
 754 }
 755
 756 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 757 {
 758         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 759 }
 760
 761 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 762 {
 763         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 764         struct ttm_operation_ctx ctx = { false, false };
 765         int r, i;
 766
 767         if (!bo->pin_count) {
 768                 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
 769                 return 0;
 770         }
 771         bo->pin_count--;
 772         if (bo->pin_count)
 773                 return 0;
 774         for (i = 0; i < bo->placement.num_placement; i++) {
 775                 bo->placements[i].lpfn = 0;
 776                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 777         }
 778         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 779         if (unlikely(r)) {
 780                 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
 781                 goto error;
 782         }
 783
 784         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 785                 adev->vram_pin_size -= amdgpu_bo_size(bo);
 786                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 787                         adev->invisible_pin_size -= amdgpu_bo_size(bo);
 788         } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
 789                 adev->gart_pin_size -= amdgpu_bo_size(bo);
 790         }
 791
 792 error:
 793         return r;
 794 }
 795
 796 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 797 {
 798         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 799         if (0 && (adev->flags & AMD_IS_APU)) {
 800                 /* Useless to evict on IGP chips */
 801                 return 0;
 802         }
 803         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 804 }
 805
 806 static const char *amdgpu_vram_names[] = {
 807         "UNKNOWN",
 808         "GDDR1",
 809         "DDR2",
 810         "GDDR3",
 811         "GDDR4",
 812         "GDDR5",
 813         "HBM",
 814         "DDR3",
 815         "DDR4",
 816 };
 817
 818 int amdgpu_bo_init(struct amdgpu_device *adev)
 819 {
 820         /* reserve PAT memory space to WC for VRAM */
 821         arch_io_reserve_memtype_wc(adev->gmc.aper_base,
 822                                    adev->gmc.aper_size);
 823
 824         /* Add an MTRR for the VRAM */
 825         adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
 826                                               adev->gmc.aper_size);
 827         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 828                  adev->gmc.mc_vram_size >> 20,
 829                  (unsigned long long)adev->gmc.aper_size >> 20);
 830         DRM_INFO("RAM width %dbits %s\n",
 831                  adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
 832         return amdgpu_ttm_init(adev);
 833 }
 834
 835 void amdgpu_bo_fini(struct amdgpu_device *adev)
 836 {
 837         amdgpu_ttm_fini(adev);
 838         arch_phys_wc_del(adev->gmc.vram_mtrr);
 839         arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
 840 }
 841
 842 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 843                              struct vm_area_struct *vma)
 844 {
 845         return ttm_fbdev_mmap(vma, &bo->tbo);
 846 }
 847
 848 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 849 {
 850         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 851
 852         if (adev->family <= AMDGPU_FAMILY_CZ &&
 853             AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 854                 return -EINVAL;
 855
 856         bo->tiling_flags = tiling_flags;
 857         return 0;
 858 }
 859
 860 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 861 {
 862         lockdep_assert_held(&bo->tbo.resv->lock.base);
 863
 864         if (tiling_flags)
 865                 *tiling_flags = bo->tiling_flags;
 866 }
 867
 868 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 869                             uint32_t metadata_size, uint64_t flags)
 870 {
 871         void *buffer;
 872
 873         if (!metadata_size) {
 874                 if (bo->metadata_size) {
 875                         kfree(bo->metadata);
 876                         bo->metadata = NULL;
 877                         bo->metadata_size = 0;
 878                 }
 879                 return 0;
 880         }
 881
 882         if (metadata == NULL)
 883                 return -EINVAL;
 884
 885         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 886         if (buffer == NULL)
 887                 return -ENOMEM;
 888
 889         kfree(bo->metadata);
 890         bo->metadata_flags = flags;
 891         bo->metadata = buffer;
 892         bo->metadata_size = metadata_size;
 893
 894         return 0;
 895 }
 896
 897 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 898                            size_t buffer_size, uint32_t *metadata_size,
 899                            uint64_t *flags)
 900 {
 901         if (!buffer && !metadata_size)
 902                 return -EINVAL;
 903
 904         if (buffer) {
 905                 if (buffer_size < bo->metadata_size)
 906                         return -EINVAL;
 907
 908                 if (bo->metadata_size)
 909                         memcpy(buffer, bo->metadata, bo->metadata_size);
 910         }
 911
 912         if (metadata_size)
 913                 *metadata_size = bo->metadata_size;
 914         if (flags)
 915                 *flags = bo->metadata_flags;
 916
 917         return 0;
 918 }
 919
 920 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 921                            bool evict,
 922                            struct ttm_mem_reg *new_mem)
 923 {
 924         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 925         struct amdgpu_bo *abo;
 926         struct ttm_mem_reg *old_mem = &bo->mem;
 927
 928         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 929                 return;
 930
 931         abo = ttm_to_amdgpu_bo(bo);
 932         amdgpu_vm_bo_invalidate(adev, abo, evict);
 933
 934         amdgpu_bo_kunmap(abo);
 935
 936         /* remember the eviction */
 937         if (evict)
 938                 atomic64_inc(&adev->num_evictions);
 939
 940         /* update statistics */
 941         if (!new_mem)
 942                 return;
 943
 944         /* move_notify is called before move happens */
 945         trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 946 }
 947
 948 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 949 {
 950         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 951         struct ttm_operation_ctx ctx = { false, false };
 952         struct amdgpu_bo *abo;
 953         unsigned long offset, size;
 954         int r;
 955
 956         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 957                 return 0;
 958
 959         abo = ttm_to_amdgpu_bo(bo);
 960
 961         /* Remember that this BO was accessed by the CPU */
 962         abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 963
 964         if (bo->mem.mem_type != TTM_PL_VRAM)
 965                 return 0;
 966
 967         size = bo->mem.num_pages << PAGE_SHIFT;
 968         offset = bo->mem.start << PAGE_SHIFT;
 969         if ((offset + size) <= adev->gmc.visible_vram_size)
 970                 return 0;
 971
 972         /* Can't move a pinned BO to visible VRAM */
 973         if (abo->pin_count > 0)
 974                 return -EINVAL;
 975
 976         /* hurrah the memory is not visible ! */
 977         atomic64_inc(&adev->num_vram_cpu_page_faults);
 978         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 979                                          AMDGPU_GEM_DOMAIN_GTT);
 980
 981         /* Avoid costly evictions; only set GTT as a busy placement */
 982         abo->placement.num_busy_placement = 1;
 983         abo->placement.busy_placement = &abo->placements[1];
 984
 985         r = ttm_bo_validate(bo, &abo->placement, &ctx);
 986         if (unlikely(r != 0))
 987                 return r;
 988
 989         offset = bo->mem.start << PAGE_SHIFT;
 990         /* this should never happen */
 991         if (bo->mem.mem_type == TTM_PL_VRAM &&
 992             (offset + size) > adev->gmc.visible_vram_size)
 993                 return -EINVAL;
 994
 995         return 0;
 996 }
 997
 998 /**
 999  * amdgpu_bo_fence - add fence to buffer object
1000  *
1001  * @bo: buffer object in question
1002  * @fence: fence to add
1003  * @shared: true if fence should be added shared
1004  *
1005  */
1006 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1007                      bool shared)
1008 {
1009         struct reservation_object *resv = bo->tbo.resv;
1010
1011         if (shared)
1012                 reservation_object_add_shared_fence(resv, fence);
1013         else
1014                 reservation_object_add_excl_fence(resv, fence);
1015 }
1016
1017 /**
1018  * amdgpu_bo_gpu_offset - return GPU offset of bo
1019  * @bo: amdgpu object for which we query the offset
1020  *
1021  * Returns current GPU offset of the object.
1022  *
1023  * Note: object should either be pinned or reserved when calling this
1024  * function, it might be useful to add check for this for debugging.
1025  */
1026 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1027 {
1028         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1029         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
1030                      !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem));
1031         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
1032                      !bo->pin_count);
1033         WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1034         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1035                      !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1036
1037         return bo->tbo.offset;
1038 }