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1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * core.c - DesignWare USB3 DRD Controller Core file
4  *
5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6  *
7  * Authors: Felipe Balbi <[email protected]>,
8  *          Sebastian Andrzej Siewior <[email protected]>
9  */
10
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/of.h>
26 #include <linux/of_graph.h>
27 #include <linux/acpi.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/reset.h>
30 #include <linux/bitfield.h>
31
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/of.h>
35 #include <linux/usb/otg.h>
36
37 #include "core.h"
38 #include "gadget.h"
39 #include "io.h"
40
41 #include "debug.h"
42 #include "../host/xhci-ext-caps.h"
43
44 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
45
46 /**
47  * dwc3_get_dr_mode - Validates and sets dr_mode
48  * @dwc: pointer to our context structure
49  */
50 static int dwc3_get_dr_mode(struct dwc3 *dwc)
51 {
52         enum usb_dr_mode mode;
53         struct device *dev = dwc->dev;
54         unsigned int hw_mode;
55
56         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
57                 dwc->dr_mode = USB_DR_MODE_OTG;
58
59         mode = dwc->dr_mode;
60         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
61
62         switch (hw_mode) {
63         case DWC3_GHWPARAMS0_MODE_GADGET:
64                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
65                         dev_err(dev,
66                                 "Controller does not support host mode.\n");
67                         return -EINVAL;
68                 }
69                 mode = USB_DR_MODE_PERIPHERAL;
70                 break;
71         case DWC3_GHWPARAMS0_MODE_HOST:
72                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
73                         dev_err(dev,
74                                 "Controller does not support device mode.\n");
75                         return -EINVAL;
76                 }
77                 mode = USB_DR_MODE_HOST;
78                 break;
79         default:
80                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
81                         mode = USB_DR_MODE_HOST;
82                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
83                         mode = USB_DR_MODE_PERIPHERAL;
84
85                 /*
86                  * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
87                  * mode. If the controller supports DRD but the dr_mode is not
88                  * specified or set to OTG, then set the mode to peripheral.
89                  */
90                 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
91                     (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
92                      !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
93                     !DWC3_VER_IS_PRIOR(DWC3, 330A))
94                         mode = USB_DR_MODE_PERIPHERAL;
95         }
96
97         if (mode != dwc->dr_mode) {
98                 dev_warn(dev,
99                          "Configuration mismatch. dr_mode forced to %s\n",
100                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
101
102                 dwc->dr_mode = mode;
103         }
104
105         return 0;
106 }
107
108 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable)
109 {
110         u32 reg;
111         int i;
112
113         for (i = 0; i < dwc->num_usb3_ports; i++) {
114                 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
115                 if (enable && !dwc->dis_u3_susphy_quirk)
116                         reg |= DWC3_GUSB3PIPECTL_SUSPHY;
117                 else
118                         reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
119
120                 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);
121         }
122
123         for (i = 0; i < dwc->num_usb2_ports; i++) {
124                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
125                 if (enable && !dwc->dis_u2_susphy_quirk)
126                         reg |= DWC3_GUSB2PHYCFG_SUSPHY;
127                 else
128                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
129
130                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
131         }
132 }
133
134 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
135 {
136         u32 reg;
137
138         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
139         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
140         reg |= DWC3_GCTL_PRTCAPDIR(mode);
141         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
142
143         dwc->current_dr_role = mode;
144 }
145
146 static void __dwc3_set_mode(struct work_struct *work)
147 {
148         struct dwc3 *dwc = work_to_dwc(work);
149         unsigned long flags;
150         int ret;
151         u32 reg;
152         u32 desired_dr_role;
153         int i;
154
155         mutex_lock(&dwc->mutex);
156         spin_lock_irqsave(&dwc->lock, flags);
157         desired_dr_role = dwc->desired_dr_role;
158         spin_unlock_irqrestore(&dwc->lock, flags);
159
160         pm_runtime_get_sync(dwc->dev);
161
162         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
163                 dwc3_otg_update(dwc, 0);
164
165         if (!desired_dr_role)
166                 goto out;
167
168         if (desired_dr_role == dwc->current_dr_role)
169                 goto out;
170
171         if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
172                 goto out;
173
174         switch (dwc->current_dr_role) {
175         case DWC3_GCTL_PRTCAP_HOST:
176                 dwc3_host_exit(dwc);
177                 break;
178         case DWC3_GCTL_PRTCAP_DEVICE:
179                 dwc3_gadget_exit(dwc);
180                 dwc3_event_buffers_cleanup(dwc);
181                 break;
182         case DWC3_GCTL_PRTCAP_OTG:
183                 dwc3_otg_exit(dwc);
184                 spin_lock_irqsave(&dwc->lock, flags);
185                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
186                 spin_unlock_irqrestore(&dwc->lock, flags);
187                 dwc3_otg_update(dwc, 1);
188                 break;
189         default:
190                 break;
191         }
192
193         /*
194          * When current_dr_role is not set, there's no role switching.
195          * Only perform GCTL.CoreSoftReset when there's DRD role switching.
196          */
197         if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
198                         DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
199                         desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
200                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
201                 reg |= DWC3_GCTL_CORESOFTRESET;
202                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
203
204                 /*
205                  * Wait for internal clocks to synchronized. DWC_usb31 and
206                  * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
207                  * keep it consistent across different IPs, let's wait up to
208                  * 100ms before clearing GCTL.CORESOFTRESET.
209                  */
210                 msleep(100);
211
212                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
213                 reg &= ~DWC3_GCTL_CORESOFTRESET;
214                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
215         }
216
217         spin_lock_irqsave(&dwc->lock, flags);
218
219         dwc3_set_prtcap(dwc, desired_dr_role);
220
221         spin_unlock_irqrestore(&dwc->lock, flags);
222
223         switch (desired_dr_role) {
224         case DWC3_GCTL_PRTCAP_HOST:
225                 ret = dwc3_host_init(dwc);
226                 if (ret) {
227                         dev_err(dwc->dev, "failed to initialize host\n");
228                 } else {
229                         if (dwc->usb2_phy)
230                                 otg_set_vbus(dwc->usb2_phy->otg, true);
231
232                         for (i = 0; i < dwc->num_usb2_ports; i++)
233                                 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
234                         for (i = 0; i < dwc->num_usb3_ports; i++)
235                                 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
236
237                         if (dwc->dis_split_quirk) {
238                                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
239                                 reg |= DWC3_GUCTL3_SPLITDISABLE;
240                                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
241                         }
242                 }
243                 break;
244         case DWC3_GCTL_PRTCAP_DEVICE:
245                 dwc3_core_soft_reset(dwc);
246
247                 dwc3_event_buffers_setup(dwc);
248
249                 if (dwc->usb2_phy)
250                         otg_set_vbus(dwc->usb2_phy->otg, false);
251                 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
252                 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
253
254                 ret = dwc3_gadget_init(dwc);
255                 if (ret)
256                         dev_err(dwc->dev, "failed to initialize peripheral\n");
257                 break;
258         case DWC3_GCTL_PRTCAP_OTG:
259                 dwc3_otg_init(dwc);
260                 dwc3_otg_update(dwc, 0);
261                 break;
262         default:
263                 break;
264         }
265
266 out:
267         pm_runtime_mark_last_busy(dwc->dev);
268         pm_runtime_put_autosuspend(dwc->dev);
269         mutex_unlock(&dwc->mutex);
270 }
271
272 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
273 {
274         unsigned long flags;
275
276         if (dwc->dr_mode != USB_DR_MODE_OTG)
277                 return;
278
279         spin_lock_irqsave(&dwc->lock, flags);
280         dwc->desired_dr_role = mode;
281         spin_unlock_irqrestore(&dwc->lock, flags);
282
283         queue_work(system_freezable_wq, &dwc->drd_work);
284 }
285
286 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
287 {
288         struct dwc3             *dwc = dep->dwc;
289         u32                     reg;
290
291         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
292                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
293                         DWC3_GDBGFIFOSPACE_TYPE(type));
294
295         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
296
297         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
298 }
299
300 /**
301  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
302  * @dwc: pointer to our context structure
303  */
304 int dwc3_core_soft_reset(struct dwc3 *dwc)
305 {
306         u32             reg;
307         int             retries = 1000;
308
309         /*
310          * We're resetting only the device side because, if we're in host mode,
311          * XHCI driver will reset the host block. If dwc3 was configured for
312          * host-only mode, then we can return early.
313          */
314         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
315                 return 0;
316
317         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
318         reg |= DWC3_DCTL_CSFTRST;
319         reg &= ~DWC3_DCTL_RUN_STOP;
320         dwc3_gadget_dctl_write_safe(dwc, reg);
321
322         /*
323          * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
324          * is cleared only after all the clocks are synchronized. This can
325          * take a little more than 50ms. Set the polling rate at 20ms
326          * for 10 times instead.
327          */
328         if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
329                 retries = 10;
330
331         do {
332                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
333                 if (!(reg & DWC3_DCTL_CSFTRST))
334                         goto done;
335
336                 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
337                         msleep(20);
338                 else
339                         udelay(1);
340         } while (--retries);
341
342         dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
343         return -ETIMEDOUT;
344
345 done:
346         /*
347          * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
348          * is cleared, we must wait at least 50ms before accessing the PHY
349          * domain (synchronization delay).
350          */
351         if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
352                 msleep(50);
353
354         return 0;
355 }
356
357 /*
358  * dwc3_frame_length_adjustment - Adjusts frame length if required
359  * @dwc3: Pointer to our controller context structure
360  */
361 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
362 {
363         u32 reg;
364         u32 dft;
365
366         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
367                 return;
368
369         if (dwc->fladj == 0)
370                 return;
371
372         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
373         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
374         if (dft != dwc->fladj) {
375                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
376                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
377                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
378         }
379 }
380
381 /**
382  * dwc3_ref_clk_period - Reference clock period configuration
383  *              Default reference clock period depends on hardware
384  *              configuration. For systems with reference clock that differs
385  *              from the default, this will set clock period in DWC3_GUCTL
386  *              register.
387  * @dwc: Pointer to our controller context structure
388  */
389 static void dwc3_ref_clk_period(struct dwc3 *dwc)
390 {
391         unsigned long period;
392         unsigned long fladj;
393         unsigned long decr;
394         unsigned long rate;
395         u32 reg;
396
397         if (dwc->ref_clk) {
398                 rate = clk_get_rate(dwc->ref_clk);
399                 if (!rate)
400                         return;
401                 period = NSEC_PER_SEC / rate;
402         } else if (dwc->ref_clk_per) {
403                 period = dwc->ref_clk_per;
404                 rate = NSEC_PER_SEC / period;
405         } else {
406                 return;
407         }
408
409         reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
410         reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
411         reg |=  FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
412         dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
413
414         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
415                 return;
416
417         /*
418          * The calculation below is
419          *
420          * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
421          *
422          * but rearranged for fixed-point arithmetic. The division must be
423          * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
424          * neither does rate * period).
425          *
426          * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
427          * nanoseconds of error caused by the truncation which happened during
428          * the division when calculating rate or period (whichever one was
429          * derived from the other). We first calculate the relative error, then
430          * scale it to units of 8 ppm.
431          */
432         fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
433         fladj -= 125000;
434
435         /*
436          * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
437          */
438         decr = 480000000 / rate;
439
440         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
441         reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
442             &  ~DWC3_GFLADJ_240MHZDECR
443             &  ~DWC3_GFLADJ_240MHZDECR_PLS1;
444         reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
445             |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
446             |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
447
448         if (dwc->gfladj_refclk_lpm_sel)
449                 reg |=  DWC3_GFLADJ_REFCLK_LPM_SEL;
450
451         dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
452 }
453
454 /**
455  * dwc3_free_one_event_buffer - Frees one event buffer
456  * @dwc: Pointer to our controller context structure
457  * @evt: Pointer to event buffer to be freed
458  */
459 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
460                 struct dwc3_event_buffer *evt)
461 {
462         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
463 }
464
465 /**
466  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
467  * @dwc: Pointer to our controller context structure
468  * @length: size of the event buffer
469  *
470  * Returns a pointer to the allocated event buffer structure on success
471  * otherwise ERR_PTR(errno).
472  */
473 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
474                 unsigned int length)
475 {
476         struct dwc3_event_buffer        *evt;
477
478         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
479         if (!evt)
480                 return ERR_PTR(-ENOMEM);
481
482         evt->dwc        = dwc;
483         evt->length     = length;
484         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
485         if (!evt->cache)
486                 return ERR_PTR(-ENOMEM);
487
488         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
489                         &evt->dma, GFP_KERNEL);
490         if (!evt->buf)
491                 return ERR_PTR(-ENOMEM);
492
493         return evt;
494 }
495
496 /**
497  * dwc3_free_event_buffers - frees all allocated event buffers
498  * @dwc: Pointer to our controller context structure
499  */
500 static void dwc3_free_event_buffers(struct dwc3 *dwc)
501 {
502         struct dwc3_event_buffer        *evt;
503
504         evt = dwc->ev_buf;
505         if (evt)
506                 dwc3_free_one_event_buffer(dwc, evt);
507 }
508
509 /**
510  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
511  * @dwc: pointer to our controller context structure
512  * @length: size of event buffer
513  *
514  * Returns 0 on success otherwise negative errno. In the error case, dwc
515  * may contain some buffers allocated but not all which were requested.
516  */
517 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
518 {
519         struct dwc3_event_buffer *evt;
520         unsigned int hw_mode;
521
522         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
523         if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
524                 dwc->ev_buf = NULL;
525                 return 0;
526         }
527
528         evt = dwc3_alloc_one_event_buffer(dwc, length);
529         if (IS_ERR(evt)) {
530                 dev_err(dwc->dev, "can't allocate event buffer\n");
531                 return PTR_ERR(evt);
532         }
533         dwc->ev_buf = evt;
534
535         return 0;
536 }
537
538 /**
539  * dwc3_event_buffers_setup - setup our allocated event buffers
540  * @dwc: pointer to our controller context structure
541  *
542  * Returns 0 on success otherwise negative errno.
543  */
544 int dwc3_event_buffers_setup(struct dwc3 *dwc)
545 {
546         struct dwc3_event_buffer        *evt;
547
548         if (!dwc->ev_buf)
549                 return 0;
550
551         evt = dwc->ev_buf;
552         evt->lpos = 0;
553         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
554                         lower_32_bits(evt->dma));
555         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
556                         upper_32_bits(evt->dma));
557         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
558                         DWC3_GEVNTSIZ_SIZE(evt->length));
559         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
560
561         return 0;
562 }
563
564 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
565 {
566         struct dwc3_event_buffer        *evt;
567
568         if (!dwc->ev_buf)
569                 return;
570
571         evt = dwc->ev_buf;
572
573         evt->lpos = 0;
574
575         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
576         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
577         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
578                         | DWC3_GEVNTSIZ_SIZE(0));
579         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
580 }
581
582 static void dwc3_core_num_eps(struct dwc3 *dwc)
583 {
584         struct dwc3_hwparams    *parms = &dwc->hwparams;
585
586         dwc->num_eps = DWC3_NUM_EPS(parms);
587 }
588
589 static void dwc3_cache_hwparams(struct dwc3 *dwc)
590 {
591         struct dwc3_hwparams    *parms = &dwc->hwparams;
592
593         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
594         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
595         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
596         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
597         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
598         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
599         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
600         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
601         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
602
603         if (DWC3_IP_IS(DWC32))
604                 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
605 }
606
607 static void dwc3_config_soc_bus(struct dwc3 *dwc)
608 {
609         if (dwc->gsbuscfg0_reqinfo != DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) {
610                 u32 reg;
611
612                 reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
613                 reg &= ~DWC3_GSBUSCFG0_REQINFO(~0);
614                 reg |= DWC3_GSBUSCFG0_REQINFO(dwc->gsbuscfg0_reqinfo);
615                 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
616         }
617 }
618
619 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
620 {
621         int intf;
622         int ret = 0;
623
624         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
625
626         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
627             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
628              dwc->hsphy_interface &&
629              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
630                 ret = dwc3_ulpi_init(dwc);
631
632         return ret;
633 }
634
635 static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
636 {
637         u32 reg;
638
639         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));
640
641         /*
642          * Make sure UX_EXIT_PX is cleared as that causes issues with some
643          * PHYs. Also, this bit is not supposed to be used in normal operation.
644          */
645         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
646
647         /*
648          * Above DWC_usb3.0 1.94a, it is recommended to set
649          * DWC3_GUSB3PIPECTL_SUSPHY to '0' during coreConsultant configuration.
650          * So default value will be '0' when the core is reset. Application
651          * needs to set it to '1' after the core initialization is completed.
652          *
653          * Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be
654          * cleared after power-on reset, and it can be set after core
655          * initialization.
656          */
657         reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
658
659         if (dwc->u2ss_inp3_quirk)
660                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
661
662         if (dwc->dis_rxdet_inp3_quirk)
663                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
664
665         if (dwc->req_p1p2p3_quirk)
666                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
667
668         if (dwc->del_p1p2p3_quirk)
669                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
670
671         if (dwc->del_phy_power_chg_quirk)
672                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
673
674         if (dwc->lfps_filter_quirk)
675                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
676
677         if (dwc->rx_detect_poll_quirk)
678                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
679
680         if (dwc->tx_de_emphasis_quirk)
681                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
682
683         if (dwc->dis_del_phy_power_chg_quirk)
684                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
685
686         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);
687
688         return 0;
689 }
690
691 static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
692 {
693         u32 reg;
694
695         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));
696
697         /* Select the HS PHY interface */
698         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
699         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
700                 if (dwc->hsphy_interface &&
701                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
702                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
703                         break;
704                 } else if (dwc->hsphy_interface &&
705                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
706                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
707                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
708                 } else {
709                         /* Relying on default value. */
710                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
711                                 break;
712                 }
713                 fallthrough;
714         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
715         default:
716                 break;
717         }
718
719         switch (dwc->hsphy_mode) {
720         case USBPHY_INTERFACE_MODE_UTMI:
721                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
722                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
723                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
724                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
725                 break;
726         case USBPHY_INTERFACE_MODE_UTMIW:
727                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
728                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
729                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
730                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
731                 break;
732         default:
733                 break;
734         }
735
736         /*
737          * Above DWC_usb3.0 1.94a, it is recommended to set
738          * DWC3_GUSB2PHYCFG_SUSPHY to '0' during coreConsultant configuration.
739          * So default value will be '0' when the core is reset. Application
740          * needs to set it to '1' after the core initialization is completed.
741          *
742          * Similarly for DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared
743          * after power-on reset, and it can be set after core initialization.
744          */
745         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
746
747         if (dwc->dis_enblslpm_quirk)
748                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
749         else
750                 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
751
752         if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
753                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
754
755         /*
756          * Some ULPI USB PHY does not support internal VBUS supply, to drive
757          * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL
758          * bit of OTG_CTRL register. Controller configures the USB2 PHY
759          * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus
760          * with an external supply.
761          */
762         if (dwc->ulpi_ext_vbus_drv)
763                 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
764
765         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
766
767         return 0;
768 }
769
770 /**
771  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
772  * @dwc: Pointer to our controller context structure
773  *
774  * Returns 0 on success. The USB PHY interfaces are configured but not
775  * initialized. The PHY interfaces and the PHYs get initialized together with
776  * the core in dwc3_core_init.
777  */
778 static int dwc3_phy_setup(struct dwc3 *dwc)
779 {
780         int i;
781         int ret;
782
783         for (i = 0; i < dwc->num_usb3_ports; i++) {
784                 ret = dwc3_ss_phy_setup(dwc, i);
785                 if (ret)
786                         return ret;
787         }
788
789         for (i = 0; i < dwc->num_usb2_ports; i++) {
790                 ret = dwc3_hs_phy_setup(dwc, i);
791                 if (ret)
792                         return ret;
793         }
794
795         return 0;
796 }
797
798 static int dwc3_phy_init(struct dwc3 *dwc)
799 {
800         int ret;
801         int i;
802         int j;
803
804         usb_phy_init(dwc->usb2_phy);
805         usb_phy_init(dwc->usb3_phy);
806
807         for (i = 0; i < dwc->num_usb2_ports; i++) {
808                 ret = phy_init(dwc->usb2_generic_phy[i]);
809                 if (ret < 0)
810                         goto err_exit_usb2_phy;
811         }
812
813         for (j = 0; j < dwc->num_usb3_ports; j++) {
814                 ret = phy_init(dwc->usb3_generic_phy[j]);
815                 if (ret < 0)
816                         goto err_exit_usb3_phy;
817         }
818
819         return 0;
820
821 err_exit_usb3_phy:
822         while (--j >= 0)
823                 phy_exit(dwc->usb3_generic_phy[j]);
824
825 err_exit_usb2_phy:
826         while (--i >= 0)
827                 phy_exit(dwc->usb2_generic_phy[i]);
828
829         usb_phy_shutdown(dwc->usb3_phy);
830         usb_phy_shutdown(dwc->usb2_phy);
831
832         return ret;
833 }
834
835 static void dwc3_phy_exit(struct dwc3 *dwc)
836 {
837         int i;
838
839         for (i = 0; i < dwc->num_usb3_ports; i++)
840                 phy_exit(dwc->usb3_generic_phy[i]);
841
842         for (i = 0; i < dwc->num_usb2_ports; i++)
843                 phy_exit(dwc->usb2_generic_phy[i]);
844
845         usb_phy_shutdown(dwc->usb3_phy);
846         usb_phy_shutdown(dwc->usb2_phy);
847 }
848
849 static int dwc3_phy_power_on(struct dwc3 *dwc)
850 {
851         int ret;
852         int i;
853         int j;
854
855         usb_phy_set_suspend(dwc->usb2_phy, 0);
856         usb_phy_set_suspend(dwc->usb3_phy, 0);
857
858         for (i = 0; i < dwc->num_usb2_ports; i++) {
859                 ret = phy_power_on(dwc->usb2_generic_phy[i]);
860                 if (ret < 0)
861                         goto err_power_off_usb2_phy;
862         }
863
864         for (j = 0; j < dwc->num_usb3_ports; j++) {
865                 ret = phy_power_on(dwc->usb3_generic_phy[j]);
866                 if (ret < 0)
867                         goto err_power_off_usb3_phy;
868         }
869
870         return 0;
871
872 err_power_off_usb3_phy:
873         while (--j >= 0)
874                 phy_power_off(dwc->usb3_generic_phy[j]);
875
876 err_power_off_usb2_phy:
877         while (--i >= 0)
878                 phy_power_off(dwc->usb2_generic_phy[i]);
879
880         usb_phy_set_suspend(dwc->usb3_phy, 1);
881         usb_phy_set_suspend(dwc->usb2_phy, 1);
882
883         return ret;
884 }
885
886 static void dwc3_phy_power_off(struct dwc3 *dwc)
887 {
888         int i;
889
890         for (i = 0; i < dwc->num_usb3_ports; i++)
891                 phy_power_off(dwc->usb3_generic_phy[i]);
892
893         for (i = 0; i < dwc->num_usb2_ports; i++)
894                 phy_power_off(dwc->usb2_generic_phy[i]);
895
896         usb_phy_set_suspend(dwc->usb3_phy, 1);
897         usb_phy_set_suspend(dwc->usb2_phy, 1);
898 }
899
900 static int dwc3_clk_enable(struct dwc3 *dwc)
901 {
902         int ret;
903
904         ret = clk_prepare_enable(dwc->bus_clk);
905         if (ret)
906                 return ret;
907
908         ret = clk_prepare_enable(dwc->ref_clk);
909         if (ret)
910                 goto disable_bus_clk;
911
912         ret = clk_prepare_enable(dwc->susp_clk);
913         if (ret)
914                 goto disable_ref_clk;
915
916         ret = clk_prepare_enable(dwc->utmi_clk);
917         if (ret)
918                 goto disable_susp_clk;
919
920         ret = clk_prepare_enable(dwc->pipe_clk);
921         if (ret)
922                 goto disable_utmi_clk;
923
924         return 0;
925
926 disable_utmi_clk:
927         clk_disable_unprepare(dwc->utmi_clk);
928 disable_susp_clk:
929         clk_disable_unprepare(dwc->susp_clk);
930 disable_ref_clk:
931         clk_disable_unprepare(dwc->ref_clk);
932 disable_bus_clk:
933         clk_disable_unprepare(dwc->bus_clk);
934         return ret;
935 }
936
937 static void dwc3_clk_disable(struct dwc3 *dwc)
938 {
939         clk_disable_unprepare(dwc->pipe_clk);
940         clk_disable_unprepare(dwc->utmi_clk);
941         clk_disable_unprepare(dwc->susp_clk);
942         clk_disable_unprepare(dwc->ref_clk);
943         clk_disable_unprepare(dwc->bus_clk);
944 }
945
946 static void dwc3_core_exit(struct dwc3 *dwc)
947 {
948         dwc3_event_buffers_cleanup(dwc);
949         dwc3_phy_power_off(dwc);
950         dwc3_phy_exit(dwc);
951         dwc3_clk_disable(dwc);
952         reset_control_assert(dwc->reset);
953 }
954
955 static bool dwc3_core_is_valid(struct dwc3 *dwc)
956 {
957         u32 reg;
958
959         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
960         dwc->ip = DWC3_GSNPS_ID(reg);
961
962         /* This should read as U3 followed by revision number */
963         if (DWC3_IP_IS(DWC3)) {
964                 dwc->revision = reg;
965         } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
966                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
967                 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
968         } else {
969                 return false;
970         }
971
972         return true;
973 }
974
975 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
976 {
977         unsigned int power_opt;
978         unsigned int hw_mode;
979         u32 reg;
980
981         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
982         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
983         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
984         power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
985
986         switch (power_opt) {
987         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
988                 /**
989                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
990                  * issue which would cause xHCI compliance tests to fail.
991                  *
992                  * Because of that we cannot enable clock gating on such
993                  * configurations.
994                  *
995                  * Refers to:
996                  *
997                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
998                  * SOF/ITP Mode Used
999                  */
1000                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
1001                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
1002                                 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
1003                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
1004                 else
1005                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
1006                 break;
1007         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
1008                 /*
1009                  * REVISIT Enabling this bit so that host-mode hibernation
1010                  * will work. Device-mode hibernation is not yet implemented.
1011                  */
1012                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
1013                 break;
1014         default:
1015                 /* nothing */
1016                 break;
1017         }
1018
1019         /*
1020          * This is a workaround for STAR#4846132, which only affects
1021          * DWC_usb31 version2.00a operating in host mode.
1022          *
1023          * There is a problem in DWC_usb31 version 2.00a operating
1024          * in host mode that would cause a CSR read timeout When CSR
1025          * read coincides with RAM Clock Gating Entry. By disable
1026          * Clock Gating, sacrificing power consumption for normal
1027          * operation.
1028          */
1029         if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO &&
1030             hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A))
1031                 reg |= DWC3_GCTL_DSBLCLKGTNG;
1032
1033         /* check if current dwc3 is on simulation board */
1034         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
1035                 dev_info(dwc->dev, "Running with FPGA optimizations\n");
1036                 dwc->is_fpga = true;
1037         }
1038
1039         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
1040                         "disable_scramble cannot be used on non-FPGA builds\n");
1041
1042         if (dwc->disable_scramble_quirk && dwc->is_fpga)
1043                 reg |= DWC3_GCTL_DISSCRAMBLE;
1044         else
1045                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
1046
1047         if (dwc->u2exit_lfps_quirk)
1048                 reg |= DWC3_GCTL_U2EXIT_LFPS;
1049
1050         /*
1051          * WORKAROUND: DWC3 revisions <1.90a have a bug
1052          * where the device can fail to connect at SuperSpeed
1053          * and falls back to high-speed mode which causes
1054          * the device to enter a Connect/Disconnect loop
1055          */
1056         if (DWC3_VER_IS_PRIOR(DWC3, 190A))
1057                 reg |= DWC3_GCTL_U2RSTECN;
1058
1059         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1060 }
1061
1062 static int dwc3_core_get_phy(struct dwc3 *dwc);
1063 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
1064
1065 /* set global incr burst type configuration registers */
1066 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
1067 {
1068         struct device *dev = dwc->dev;
1069         /* incrx_mode : for INCR burst type. */
1070         bool incrx_mode;
1071         /* incrx_size : for size of INCRX burst. */
1072         u32 incrx_size;
1073         u32 *vals;
1074         u32 cfg;
1075         int ntype;
1076         int ret;
1077         int i;
1078
1079         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
1080
1081         /*
1082          * Handle property "snps,incr-burst-type-adjustment".
1083          * Get the number of value from this property:
1084          * result <= 0, means this property is not supported.
1085          * result = 1, means INCRx burst mode supported.
1086          * result > 1, means undefined length burst mode supported.
1087          */
1088         ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
1089         if (ntype <= 0)
1090                 return;
1091
1092         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
1093         if (!vals)
1094                 return;
1095
1096         /* Get INCR burst type, and parse it */
1097         ret = device_property_read_u32_array(dev,
1098                         "snps,incr-burst-type-adjustment", vals, ntype);
1099         if (ret) {
1100                 kfree(vals);
1101                 dev_err(dev, "Error to get property\n");
1102                 return;
1103         }
1104
1105         incrx_size = *vals;
1106
1107         if (ntype > 1) {
1108                 /* INCRX (undefined length) burst mode */
1109                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
1110                 for (i = 1; i < ntype; i++) {
1111                         if (vals[i] > incrx_size)
1112                                 incrx_size = vals[i];
1113                 }
1114         } else {
1115                 /* INCRX burst mode */
1116                 incrx_mode = INCRX_BURST_MODE;
1117         }
1118
1119         kfree(vals);
1120
1121         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
1122         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
1123         if (incrx_mode)
1124                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1125         switch (incrx_size) {
1126         case 256:
1127                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1128                 break;
1129         case 128:
1130                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1131                 break;
1132         case 64:
1133                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1134                 break;
1135         case 32:
1136                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1137                 break;
1138         case 16:
1139                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1140                 break;
1141         case 8:
1142                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1143                 break;
1144         case 4:
1145                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1146                 break;
1147         case 1:
1148                 break;
1149         default:
1150                 dev_err(dev, "Invalid property\n");
1151                 break;
1152         }
1153
1154         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1155 }
1156
1157 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1158 {
1159         u32 scale;
1160         u32 reg;
1161
1162         if (!dwc->susp_clk)
1163                 return;
1164
1165         /*
1166          * The power down scale field specifies how many suspend_clk
1167          * periods fit into a 16KHz clock period. When performing
1168          * the division, round up the remainder.
1169          *
1170          * The power down scale value is calculated using the fastest
1171          * frequency of the suspend_clk. If it isn't fixed (but within
1172          * the accuracy requirement), the driver may not know the max
1173          * rate of the suspend_clk, so only update the power down scale
1174          * if the default is less than the calculated value from
1175          * clk_get_rate() or if the default is questionably high
1176          * (3x or more) to be within the requirement.
1177          */
1178         scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1179         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1180         if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1181             (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1182                 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1183                 reg |= DWC3_GCTL_PWRDNSCALE(scale);
1184                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1185         }
1186 }
1187
1188 static void dwc3_config_threshold(struct dwc3 *dwc)
1189 {
1190         u32 reg;
1191         u8 rx_thr_num;
1192         u8 rx_maxburst;
1193         u8 tx_thr_num;
1194         u8 tx_maxburst;
1195
1196         /*
1197          * Must config both number of packets and max burst settings to enable
1198          * RX and/or TX threshold.
1199          */
1200         if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1201                 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1202                 rx_maxburst = dwc->rx_max_burst_prd;
1203                 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1204                 tx_maxburst = dwc->tx_max_burst_prd;
1205
1206                 if (rx_thr_num && rx_maxburst) {
1207                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1208                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1209
1210                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1211                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1212
1213                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1214                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1215
1216                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1217                 }
1218
1219                 if (tx_thr_num && tx_maxburst) {
1220                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1221                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1222
1223                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1224                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1225
1226                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1227                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1228
1229                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1230                 }
1231         }
1232
1233         rx_thr_num = dwc->rx_thr_num_pkt;
1234         rx_maxburst = dwc->rx_max_burst;
1235         tx_thr_num = dwc->tx_thr_num_pkt;
1236         tx_maxburst = dwc->tx_max_burst;
1237
1238         if (DWC3_IP_IS(DWC3)) {
1239                 if (rx_thr_num && rx_maxburst) {
1240                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1241                         reg |= DWC3_GRXTHRCFG_PKTCNTSEL;
1242
1243                         reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
1244                         reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1245
1246                         reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1247                         reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1248
1249                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1250                 }
1251
1252                 if (tx_thr_num && tx_maxburst) {
1253                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1254                         reg |= DWC3_GTXTHRCFG_PKTCNTSEL;
1255
1256                         reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
1257                         reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1258
1259                         reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1260                         reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1261
1262                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1263                 }
1264         } else {
1265                 if (rx_thr_num && rx_maxburst) {
1266                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1267                         reg |= DWC31_GRXTHRCFG_PKTCNTSEL;
1268
1269                         reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0);
1270                         reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1271
1272                         reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1273                         reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1274
1275                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1276                 }
1277
1278                 if (tx_thr_num && tx_maxburst) {
1279                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1280                         reg |= DWC31_GTXTHRCFG_PKTCNTSEL;
1281
1282                         reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0);
1283                         reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1284
1285                         reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1286                         reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1287
1288                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1289                 }
1290         }
1291 }
1292
1293 /**
1294  * dwc3_core_init - Low-level initialization of DWC3 Core
1295  * @dwc: Pointer to our controller context structure
1296  *
1297  * Returns 0 on success otherwise negative errno.
1298  */
1299 static int dwc3_core_init(struct dwc3 *dwc)
1300 {
1301         unsigned int            hw_mode;
1302         u32                     reg;
1303         int                     ret;
1304
1305         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1306
1307         /*
1308          * Write Linux Version Code to our GUID register so it's easy to figure
1309          * out which kernel version a bug was found.
1310          */
1311         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1312
1313         ret = dwc3_phy_setup(dwc);
1314         if (ret)
1315                 return ret;
1316
1317         if (!dwc->ulpi_ready) {
1318                 ret = dwc3_core_ulpi_init(dwc);
1319                 if (ret) {
1320                         if (ret == -ETIMEDOUT) {
1321                                 dwc3_core_soft_reset(dwc);
1322                                 ret = -EPROBE_DEFER;
1323                         }
1324                         return ret;
1325                 }
1326                 dwc->ulpi_ready = true;
1327         }
1328
1329         if (!dwc->phys_ready) {
1330                 ret = dwc3_core_get_phy(dwc);
1331                 if (ret)
1332                         goto err_exit_ulpi;
1333                 dwc->phys_ready = true;
1334         }
1335
1336         ret = dwc3_phy_init(dwc);
1337         if (ret)
1338                 goto err_exit_ulpi;
1339
1340         ret = dwc3_core_soft_reset(dwc);
1341         if (ret)
1342                 goto err_exit_phy;
1343
1344         dwc3_core_setup_global_control(dwc);
1345         dwc3_core_num_eps(dwc);
1346
1347         /* Set power down scale of suspend_clk */
1348         dwc3_set_power_down_clk_scale(dwc);
1349
1350         /* Adjust Frame Length */
1351         dwc3_frame_length_adjustment(dwc);
1352
1353         /* Adjust Reference Clock Period */
1354         dwc3_ref_clk_period(dwc);
1355
1356         dwc3_set_incr_burst_type(dwc);
1357
1358         dwc3_config_soc_bus(dwc);
1359
1360         ret = dwc3_phy_power_on(dwc);
1361         if (ret)
1362                 goto err_exit_phy;
1363
1364         ret = dwc3_event_buffers_setup(dwc);
1365         if (ret) {
1366                 dev_err(dwc->dev, "failed to setup event buffers\n");
1367                 goto err_power_off_phy;
1368         }
1369
1370         /*
1371          * ENDXFER polling is available on version 3.10a and later of
1372          * the DWC_usb3 controller. It is NOT available in the
1373          * DWC_usb31 controller.
1374          */
1375         if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1376                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1377                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1378                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1379         }
1380
1381         /*
1382          * When configured in HOST mode, after issuing U3/L2 exit controller
1383          * fails to send proper CRC checksum in CRC5 feild. Because of this
1384          * behaviour Transaction Error is generated, resulting in reset and
1385          * re-enumeration of usb device attached. All the termsel, xcvrsel,
1386          * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
1387          * will correct this problem. This option is to support certain
1388          * legacy ULPI PHYs.
1389          */
1390         if (dwc->resume_hs_terminations) {
1391                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1392                 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1393                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1394         }
1395
1396         if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1397                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1398
1399                 /*
1400                  * Enable hardware control of sending remote wakeup
1401                  * in HS when the device is in the L1 state.
1402                  */
1403                 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1404                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1405
1406                 /*
1407                  * Decouple USB 2.0 L1 & L2 events which will allow for
1408                  * gadget driver to only receive U3/L2 suspend & wakeup
1409                  * events and prevent the more frequent L1 LPM transitions
1410                  * from interrupting the driver.
1411                  */
1412                 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1413                         reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1414
1415                 if (dwc->dis_tx_ipgap_linecheck_quirk)
1416                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1417
1418                 if (dwc->parkmode_disable_ss_quirk)
1419                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1420
1421                 if (dwc->parkmode_disable_hs_quirk)
1422                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
1423
1424                 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY)) {
1425                         if (dwc->maximum_speed == USB_SPEED_FULL ||
1426                             dwc->maximum_speed == USB_SPEED_HIGH)
1427                                 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1428                         else
1429                                 reg &= ~DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1430                 }
1431
1432                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1433         }
1434
1435         dwc3_config_threshold(dwc);
1436
1437         /*
1438          * Modify this for all supported Super Speed ports when
1439          * multiport support is added.
1440          */
1441         if (hw_mode != DWC3_GHWPARAMS0_MODE_GADGET &&
1442             (DWC3_IP_IS(DWC31)) &&
1443             dwc->maximum_speed == USB_SPEED_SUPER) {
1444                 reg = dwc3_readl(dwc->regs, DWC3_LLUCTL);
1445                 reg |= DWC3_LLUCTL_FORCE_GEN1;
1446                 dwc3_writel(dwc->regs, DWC3_LLUCTL, reg);
1447         }
1448
1449         return 0;
1450
1451 err_power_off_phy:
1452         dwc3_phy_power_off(dwc);
1453 err_exit_phy:
1454         dwc3_phy_exit(dwc);
1455 err_exit_ulpi:
1456         dwc3_ulpi_exit(dwc);
1457
1458         return ret;
1459 }
1460
1461 static int dwc3_core_get_phy(struct dwc3 *dwc)
1462 {
1463         struct device           *dev = dwc->dev;
1464         struct device_node      *node = dev->of_node;
1465         char phy_name[9];
1466         int ret;
1467         u8 i;
1468
1469         if (node) {
1470                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1471                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1472         } else {
1473                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1474                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1475         }
1476
1477         if (IS_ERR(dwc->usb2_phy)) {
1478                 ret = PTR_ERR(dwc->usb2_phy);
1479                 if (ret == -ENXIO || ret == -ENODEV)
1480                         dwc->usb2_phy = NULL;
1481                 else
1482                         return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1483         }
1484
1485         if (IS_ERR(dwc->usb3_phy)) {
1486                 ret = PTR_ERR(dwc->usb3_phy);
1487                 if (ret == -ENXIO || ret == -ENODEV)
1488                         dwc->usb3_phy = NULL;
1489                 else
1490                         return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1491         }
1492
1493         for (i = 0; i < dwc->num_usb2_ports; i++) {
1494                 if (dwc->num_usb2_ports == 1)
1495                         snprintf(phy_name, sizeof(phy_name), "usb2-phy");
1496                 else
1497                         snprintf(phy_name, sizeof(phy_name),  "usb2-%u", i);
1498
1499                 dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name);
1500                 if (IS_ERR(dwc->usb2_generic_phy[i])) {
1501                         ret = PTR_ERR(dwc->usb2_generic_phy[i]);
1502                         if (ret == -ENOSYS || ret == -ENODEV)
1503                                 dwc->usb2_generic_phy[i] = NULL;
1504                         else
1505                                 return dev_err_probe(dev, ret, "failed to lookup phy %s\n",
1506                                                         phy_name);
1507                 }
1508         }
1509
1510         for (i = 0; i < dwc->num_usb3_ports; i++) {
1511                 if (dwc->num_usb3_ports == 1)
1512                         snprintf(phy_name, sizeof(phy_name), "usb3-phy");
1513                 else
1514                         snprintf(phy_name, sizeof(phy_name), "usb3-%u", i);
1515
1516                 dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name);
1517                 if (IS_ERR(dwc->usb3_generic_phy[i])) {
1518                         ret = PTR_ERR(dwc->usb3_generic_phy[i]);
1519                         if (ret == -ENOSYS || ret == -ENODEV)
1520                                 dwc->usb3_generic_phy[i] = NULL;
1521                         else
1522                                 return dev_err_probe(dev, ret, "failed to lookup phy %s\n",
1523                                                         phy_name);
1524                 }
1525         }
1526
1527         return 0;
1528 }
1529
1530 static int dwc3_core_init_mode(struct dwc3 *dwc)
1531 {
1532         struct device *dev = dwc->dev;
1533         int ret;
1534         int i;
1535
1536         switch (dwc->dr_mode) {
1537         case USB_DR_MODE_PERIPHERAL:
1538                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1539
1540                 if (dwc->usb2_phy)
1541                         otg_set_vbus(dwc->usb2_phy->otg, false);
1542                 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
1543                 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
1544
1545                 ret = dwc3_gadget_init(dwc);
1546                 if (ret)
1547                         return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1548                 break;
1549         case USB_DR_MODE_HOST:
1550                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1551
1552                 if (dwc->usb2_phy)
1553                         otg_set_vbus(dwc->usb2_phy->otg, true);
1554                 for (i = 0; i < dwc->num_usb2_ports; i++)
1555                         phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
1556                 for (i = 0; i < dwc->num_usb3_ports; i++)
1557                         phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
1558
1559                 ret = dwc3_host_init(dwc);
1560                 if (ret)
1561                         return dev_err_probe(dev, ret, "failed to initialize host\n");
1562                 break;
1563         case USB_DR_MODE_OTG:
1564                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1565                 ret = dwc3_drd_init(dwc);
1566                 if (ret)
1567                         return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1568                 break;
1569         default:
1570                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1571                 return -EINVAL;
1572         }
1573
1574         return 0;
1575 }
1576
1577 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1578 {
1579         switch (dwc->dr_mode) {
1580         case USB_DR_MODE_PERIPHERAL:
1581                 dwc3_gadget_exit(dwc);
1582                 break;
1583         case USB_DR_MODE_HOST:
1584                 dwc3_host_exit(dwc);
1585                 break;
1586         case USB_DR_MODE_OTG:
1587                 dwc3_drd_exit(dwc);
1588                 break;
1589         default:
1590                 /* do nothing */
1591                 break;
1592         }
1593
1594         /* de-assert DRVVBUS for HOST and OTG mode */
1595         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1596 }
1597
1598 static void dwc3_get_software_properties(struct dwc3 *dwc)
1599 {
1600         struct device *tmpdev;
1601         u16 gsbuscfg0_reqinfo;
1602         int ret;
1603
1604         dwc->gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED;
1605
1606         /*
1607          * Iterate over all parent nodes for finding swnode properties
1608          * and non-DT (non-ABI) properties.
1609          */
1610         for (tmpdev = dwc->dev; tmpdev; tmpdev = tmpdev->parent) {
1611                 ret = device_property_read_u16(tmpdev,
1612                                                "snps,gsbuscfg0-reqinfo",
1613                                                &gsbuscfg0_reqinfo);
1614                 if (!ret)
1615                         dwc->gsbuscfg0_reqinfo = gsbuscfg0_reqinfo;
1616         }
1617 }
1618
1619 static void dwc3_get_properties(struct dwc3 *dwc)
1620 {
1621         struct device           *dev = dwc->dev;
1622         u8                      lpm_nyet_threshold;
1623         u8                      tx_de_emphasis;
1624         u8                      hird_threshold;
1625         u8                      rx_thr_num_pkt = 0;
1626         u8                      rx_max_burst = 0;
1627         u8                      tx_thr_num_pkt = 0;
1628         u8                      tx_max_burst = 0;
1629         u8                      rx_thr_num_pkt_prd = 0;
1630         u8                      rx_max_burst_prd = 0;
1631         u8                      tx_thr_num_pkt_prd = 0;
1632         u8                      tx_max_burst_prd = 0;
1633         u8                      tx_fifo_resize_max_num;
1634         const char              *usb_psy_name;
1635         int                     ret;
1636
1637         /* default to highest possible threshold */
1638         lpm_nyet_threshold = 0xf;
1639
1640         /* default to -3.5dB de-emphasis */
1641         tx_de_emphasis = 1;
1642
1643         /*
1644          * default to assert utmi_sleep_n and use maximum allowed HIRD
1645          * threshold value of 0b1100
1646          */
1647         hird_threshold = 12;
1648
1649         /*
1650          * default to a TXFIFO size large enough to fit 6 max packets.  This
1651          * allows for systems with larger bus latencies to have some headroom
1652          * for endpoints that have a large bMaxBurst value.
1653          */
1654         tx_fifo_resize_max_num = 6;
1655
1656         dwc->maximum_speed = usb_get_maximum_speed(dev);
1657         dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1658         dwc->dr_mode = usb_get_dr_mode(dev);
1659         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1660
1661         dwc->sysdev_is_parent = device_property_read_bool(dev,
1662                                 "linux,sysdev_is_parent");
1663         if (dwc->sysdev_is_parent)
1664                 dwc->sysdev = dwc->dev->parent;
1665         else
1666                 dwc->sysdev = dwc->dev;
1667
1668         dwc->sys_wakeup = device_may_wakeup(dwc->sysdev);
1669
1670         ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1671         if (ret >= 0) {
1672                 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1673                 if (!dwc->usb_psy)
1674                         dev_err(dev, "couldn't get usb power supply\n");
1675         }
1676
1677         dwc->has_lpm_erratum = device_property_read_bool(dev,
1678                                 "snps,has-lpm-erratum");
1679         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1680                                 &lpm_nyet_threshold);
1681         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1682                                 "snps,is-utmi-l1-suspend");
1683         device_property_read_u8(dev, "snps,hird-threshold",
1684                                 &hird_threshold);
1685         dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1686                                 "snps,dis-start-transfer-quirk");
1687         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1688                                 "snps,usb3_lpm_capable");
1689         dwc->usb2_lpm_disable = device_property_read_bool(dev,
1690                                 "snps,usb2-lpm-disable");
1691         dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1692                                 "snps,usb2-gadget-lpm-disable");
1693         device_property_read_u8(dev, "snps,rx-thr-num-pkt",
1694                                 &rx_thr_num_pkt);
1695         device_property_read_u8(dev, "snps,rx-max-burst",
1696                                 &rx_max_burst);
1697         device_property_read_u8(dev, "snps,tx-thr-num-pkt",
1698                                 &tx_thr_num_pkt);
1699         device_property_read_u8(dev, "snps,tx-max-burst",
1700                                 &tx_max_burst);
1701         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1702                                 &rx_thr_num_pkt_prd);
1703         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1704                                 &rx_max_burst_prd);
1705         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1706                                 &tx_thr_num_pkt_prd);
1707         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1708                                 &tx_max_burst_prd);
1709         dwc->do_fifo_resize = device_property_read_bool(dev,
1710                                                         "tx-fifo-resize");
1711         if (dwc->do_fifo_resize)
1712                 device_property_read_u8(dev, "tx-fifo-max-num",
1713                                         &tx_fifo_resize_max_num);
1714
1715         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1716                                 "snps,disable_scramble_quirk");
1717         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1718                                 "snps,u2exit_lfps_quirk");
1719         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1720                                 "snps,u2ss_inp3_quirk");
1721         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1722                                 "snps,req_p1p2p3_quirk");
1723         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1724                                 "snps,del_p1p2p3_quirk");
1725         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1726                                 "snps,del_phy_power_chg_quirk");
1727         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1728                                 "snps,lfps_filter_quirk");
1729         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1730                                 "snps,rx_detect_poll_quirk");
1731         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1732                                 "snps,dis_u3_susphy_quirk");
1733         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1734                                 "snps,dis_u2_susphy_quirk");
1735         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1736                                 "snps,dis_enblslpm_quirk");
1737         dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1738                                 "snps,dis-u1-entry-quirk");
1739         dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1740                                 "snps,dis-u2-entry-quirk");
1741         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1742                                 "snps,dis_rxdet_inp3_quirk");
1743         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1744                                 "snps,dis-u2-freeclk-exists-quirk");
1745         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1746                                 "snps,dis-del-phy-power-chg-quirk");
1747         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1748                                 "snps,dis-tx-ipgap-linecheck-quirk");
1749         dwc->resume_hs_terminations = device_property_read_bool(dev,
1750                                 "snps,resume-hs-terminations");
1751         dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
1752                                 "snps,ulpi-ext-vbus-drv");
1753         dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1754                                 "snps,parkmode-disable-ss-quirk");
1755         dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
1756                                 "snps,parkmode-disable-hs-quirk");
1757         dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1758                                 "snps,gfladj-refclk-lpm-sel-quirk");
1759
1760         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1761                                 "snps,tx_de_emphasis_quirk");
1762         device_property_read_u8(dev, "snps,tx_de_emphasis",
1763                                 &tx_de_emphasis);
1764         device_property_read_string(dev, "snps,hsphy_interface",
1765                                     &dwc->hsphy_interface);
1766         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1767                                  &dwc->fladj);
1768         device_property_read_u32(dev, "snps,ref-clock-period-ns",
1769                                  &dwc->ref_clk_per);
1770
1771         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1772                                 "snps,dis_metastability_quirk");
1773
1774         dwc->dis_split_quirk = device_property_read_bool(dev,
1775                                 "snps,dis-split-quirk");
1776
1777         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1778         dwc->tx_de_emphasis = tx_de_emphasis;
1779
1780         dwc->hird_threshold = hird_threshold;
1781
1782         dwc->rx_thr_num_pkt = rx_thr_num_pkt;
1783         dwc->rx_max_burst = rx_max_burst;
1784
1785         dwc->tx_thr_num_pkt = tx_thr_num_pkt;
1786         dwc->tx_max_burst = tx_max_burst;
1787
1788         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1789         dwc->rx_max_burst_prd = rx_max_burst_prd;
1790
1791         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1792         dwc->tx_max_burst_prd = tx_max_burst_prd;
1793
1794         dwc->imod_interval = 0;
1795
1796         dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1797 }
1798
1799 /* check whether the core supports IMOD */
1800 bool dwc3_has_imod(struct dwc3 *dwc)
1801 {
1802         return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1803                 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1804                 DWC3_IP_IS(DWC32);
1805 }
1806
1807 static void dwc3_check_params(struct dwc3 *dwc)
1808 {
1809         struct device *dev = dwc->dev;
1810         unsigned int hwparam_gen =
1811                 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1812
1813         /* Check for proper value of imod_interval */
1814         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1815                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1816                 dwc->imod_interval = 0;
1817         }
1818
1819         /*
1820          * Workaround for STAR 9000961433 which affects only version
1821          * 3.00a of the DWC_usb3 core. This prevents the controller
1822          * interrupt from being masked while handling events. IMOD
1823          * allows us to work around this issue. Enable it for the
1824          * affected version.
1825          */
1826         if (!dwc->imod_interval &&
1827             DWC3_VER_IS(DWC3, 300A))
1828                 dwc->imod_interval = 1;
1829
1830         /* Check the maximum_speed parameter */
1831         switch (dwc->maximum_speed) {
1832         case USB_SPEED_FULL:
1833         case USB_SPEED_HIGH:
1834                 break;
1835         case USB_SPEED_SUPER:
1836                 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1837                         dev_warn(dev, "UDC doesn't support Gen 1\n");
1838                 break;
1839         case USB_SPEED_SUPER_PLUS:
1840                 if ((DWC3_IP_IS(DWC32) &&
1841                      hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1842                     (!DWC3_IP_IS(DWC32) &&
1843                      hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1844                         dev_warn(dev, "UDC doesn't support SSP\n");
1845                 break;
1846         default:
1847                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1848                         dwc->maximum_speed);
1849                 fallthrough;
1850         case USB_SPEED_UNKNOWN:
1851                 switch (hwparam_gen) {
1852                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1853                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1854                         break;
1855                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1856                         if (DWC3_IP_IS(DWC32))
1857                                 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1858                         else
1859                                 dwc->maximum_speed = USB_SPEED_SUPER;
1860                         break;
1861                 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1862                         dwc->maximum_speed = USB_SPEED_HIGH;
1863                         break;
1864                 default:
1865                         dwc->maximum_speed = USB_SPEED_SUPER;
1866                         break;
1867                 }
1868                 break;
1869         }
1870
1871         /*
1872          * Currently the controller does not have visibility into the HW
1873          * parameter to determine the maximum number of lanes the HW supports.
1874          * If the number of lanes is not specified in the device property, then
1875          * set the default to support dual-lane for DWC_usb32 and single-lane
1876          * for DWC_usb31 for super-speed-plus.
1877          */
1878         if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1879                 switch (dwc->max_ssp_rate) {
1880                 case USB_SSP_GEN_2x1:
1881                         if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1882                                 dev_warn(dev, "UDC only supports Gen 1\n");
1883                         break;
1884                 case USB_SSP_GEN_1x2:
1885                 case USB_SSP_GEN_2x2:
1886                         if (DWC3_IP_IS(DWC31))
1887                                 dev_warn(dev, "UDC only supports single lane\n");
1888                         break;
1889                 case USB_SSP_GEN_UNKNOWN:
1890                 default:
1891                         switch (hwparam_gen) {
1892                         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1893                                 if (DWC3_IP_IS(DWC32))
1894                                         dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1895                                 else
1896                                         dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1897                                 break;
1898                         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1899                                 if (DWC3_IP_IS(DWC32))
1900                                         dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1901                                 break;
1902                         }
1903                         break;
1904                 }
1905         }
1906 }
1907
1908 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1909 {
1910         struct device *dev = dwc->dev;
1911         struct device_node *np_phy;
1912         struct extcon_dev *edev = NULL;
1913         const char *name;
1914
1915         if (device_property_read_bool(dev, "extcon"))
1916                 return extcon_get_edev_by_phandle(dev, 0);
1917
1918         /*
1919          * Device tree platforms should get extcon via phandle.
1920          * On ACPI platforms, we get the name from a device property.
1921          * This device property is for kernel internal use only and
1922          * is expected to be set by the glue code.
1923          */
1924         if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1925                 return extcon_get_extcon_dev(name);
1926
1927         /*
1928          * Check explicitly if "usb-role-switch" is used since
1929          * extcon_find_edev_by_node() can not be used to check the absence of
1930          * an extcon device. In the absence of an device it will always return
1931          * EPROBE_DEFER.
1932          */
1933         if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) &&
1934             device_property_read_bool(dev, "usb-role-switch"))
1935                 return NULL;
1936
1937         /*
1938          * Try to get an extcon device from the USB PHY controller's "port"
1939          * node. Check if it has the "port" node first, to avoid printing the
1940          * error message from underlying code, as it's a valid case: extcon
1941          * device (and "port" node) may be missing in case of "usb-role-switch"
1942          * or OTG mode.
1943          */
1944         np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1945         if (of_graph_is_present(np_phy)) {
1946                 struct device_node *np_conn;
1947
1948                 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1949                 if (np_conn)
1950                         edev = extcon_find_edev_by_node(np_conn);
1951                 of_node_put(np_conn);
1952         }
1953         of_node_put(np_phy);
1954
1955         return edev;
1956 }
1957
1958 static int dwc3_get_clocks(struct dwc3 *dwc)
1959 {
1960         struct device *dev = dwc->dev;
1961
1962         if (!dev->of_node)
1963                 return 0;
1964
1965         /*
1966          * Clocks are optional, but new DT platforms should support all clocks
1967          * as required by the DT-binding.
1968          * Some devices have different clock names in legacy device trees,
1969          * check for them to retain backwards compatibility.
1970          */
1971         dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1972         if (IS_ERR(dwc->bus_clk)) {
1973                 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1974                                 "could not get bus clock\n");
1975         }
1976
1977         if (dwc->bus_clk == NULL) {
1978                 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1979                 if (IS_ERR(dwc->bus_clk)) {
1980                         return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1981                                         "could not get bus clock\n");
1982                 }
1983         }
1984
1985         dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1986         if (IS_ERR(dwc->ref_clk)) {
1987                 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1988                                 "could not get ref clock\n");
1989         }
1990
1991         if (dwc->ref_clk == NULL) {
1992                 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1993                 if (IS_ERR(dwc->ref_clk)) {
1994                         return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1995                                         "could not get ref clock\n");
1996                 }
1997         }
1998
1999         dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
2000         if (IS_ERR(dwc->susp_clk)) {
2001                 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
2002                                 "could not get suspend clock\n");
2003         }
2004
2005         if (dwc->susp_clk == NULL) {
2006                 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
2007                 if (IS_ERR(dwc->susp_clk)) {
2008                         return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
2009                                         "could not get suspend clock\n");
2010                 }
2011         }
2012
2013         /* specific to Rockchip RK3588 */
2014         dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
2015         if (IS_ERR(dwc->utmi_clk)) {
2016                 return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
2017                                 "could not get utmi clock\n");
2018         }
2019
2020         /* specific to Rockchip RK3588 */
2021         dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
2022         if (IS_ERR(dwc->pipe_clk)) {
2023                 return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
2024                                 "could not get pipe clock\n");
2025         }
2026
2027         return 0;
2028 }
2029
2030 static int dwc3_get_num_ports(struct dwc3 *dwc)
2031 {
2032         void __iomem *base;
2033         u8 major_revision;
2034         u32 offset;
2035         u32 val;
2036
2037         /*
2038          * Remap xHCI address space to access XHCI ext cap regs since it is
2039          * needed to get information on number of ports present.
2040          */
2041         base = ioremap(dwc->xhci_resources[0].start,
2042                        resource_size(&dwc->xhci_resources[0]));
2043         if (!base)
2044                 return -ENOMEM;
2045
2046         offset = 0;
2047         do {
2048                 offset = xhci_find_next_ext_cap(base, offset,
2049                                                 XHCI_EXT_CAPS_PROTOCOL);
2050                 if (!offset)
2051                         break;
2052
2053                 val = readl(base + offset);
2054                 major_revision = XHCI_EXT_PORT_MAJOR(val);
2055
2056                 val = readl(base + offset + 0x08);
2057                 if (major_revision == 0x03) {
2058                         dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val);
2059                 } else if (major_revision <= 0x02) {
2060                         dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val);
2061                 } else {
2062                         dev_warn(dwc->dev, "unrecognized port major revision %d\n",
2063                                  major_revision);
2064                 }
2065         } while (1);
2066
2067         dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
2068                 dwc->num_usb2_ports, dwc->num_usb3_ports);
2069
2070         iounmap(base);
2071
2072         if (dwc->num_usb2_ports > DWC3_USB2_MAX_PORTS ||
2073             dwc->num_usb3_ports > DWC3_USB3_MAX_PORTS)
2074                 return -EINVAL;
2075
2076         return 0;
2077 }
2078
2079 static int dwc3_probe(struct platform_device *pdev)
2080 {
2081         struct device           *dev = &pdev->dev;
2082         struct resource         *res, dwc_res;
2083         unsigned int            hw_mode;
2084         void __iomem            *regs;
2085         struct dwc3             *dwc;
2086         int                     ret;
2087
2088         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
2089         if (!dwc)
2090                 return -ENOMEM;
2091
2092         dwc->dev = dev;
2093
2094         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2095         if (!res) {
2096                 dev_err(dev, "missing memory resource\n");
2097                 return -ENODEV;
2098         }
2099
2100         dwc->xhci_resources[0].start = res->start;
2101         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
2102                                         DWC3_XHCI_REGS_END;
2103         dwc->xhci_resources[0].flags = res->flags;
2104         dwc->xhci_resources[0].name = res->name;
2105
2106         /*
2107          * Request memory region but exclude xHCI regs,
2108          * since it will be requested by the xhci-plat driver.
2109          */
2110         dwc_res = *res;
2111         dwc_res.start += DWC3_GLOBALS_REGS_START;
2112
2113         if (dev->of_node) {
2114                 struct device_node *parent = of_get_parent(dev->of_node);
2115
2116                 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) {
2117                         dwc_res.start -= DWC3_GLOBALS_REGS_START;
2118                         dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
2119                 }
2120
2121                 of_node_put(parent);
2122         }
2123
2124         regs = devm_ioremap_resource(dev, &dwc_res);
2125         if (IS_ERR(regs))
2126                 return PTR_ERR(regs);
2127
2128         dwc->regs       = regs;
2129         dwc->regs_size  = resource_size(&dwc_res);
2130
2131         dwc3_get_properties(dwc);
2132
2133         dwc3_get_software_properties(dwc);
2134
2135         dwc->reset = devm_reset_control_array_get_optional_shared(dev);
2136         if (IS_ERR(dwc->reset)) {
2137                 ret = PTR_ERR(dwc->reset);
2138                 goto err_put_psy;
2139         }
2140
2141         ret = dwc3_get_clocks(dwc);
2142         if (ret)
2143                 goto err_put_psy;
2144
2145         ret = reset_control_deassert(dwc->reset);
2146         if (ret)
2147                 goto err_put_psy;
2148
2149         ret = dwc3_clk_enable(dwc);
2150         if (ret)
2151                 goto err_assert_reset;
2152
2153         if (!dwc3_core_is_valid(dwc)) {
2154                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
2155                 ret = -ENODEV;
2156                 goto err_disable_clks;
2157         }
2158
2159         platform_set_drvdata(pdev, dwc);
2160         dwc3_cache_hwparams(dwc);
2161
2162         if (!dwc->sysdev_is_parent &&
2163             DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
2164                 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
2165                 if (ret)
2166                         goto err_disable_clks;
2167         }
2168
2169         /*
2170          * Currently only DWC3 controllers that are host-only capable
2171          * can have more than one port.
2172          */
2173         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
2174         if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
2175                 ret = dwc3_get_num_ports(dwc);
2176                 if (ret)
2177                         goto err_disable_clks;
2178         } else {
2179                 dwc->num_usb2_ports = 1;
2180                 dwc->num_usb3_ports = 1;
2181         }
2182
2183         spin_lock_init(&dwc->lock);
2184         mutex_init(&dwc->mutex);
2185
2186         pm_runtime_get_noresume(dev);
2187         pm_runtime_set_active(dev);
2188         pm_runtime_use_autosuspend(dev);
2189         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
2190         pm_runtime_enable(dev);
2191
2192         pm_runtime_forbid(dev);
2193
2194         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
2195         if (ret) {
2196                 dev_err(dwc->dev, "failed to allocate event buffers\n");
2197                 ret = -ENOMEM;
2198                 goto err_allow_rpm;
2199         }
2200
2201         dwc->edev = dwc3_get_extcon(dwc);
2202         if (IS_ERR(dwc->edev)) {
2203                 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n");
2204                 goto err_free_event_buffers;
2205         }
2206
2207         ret = dwc3_get_dr_mode(dwc);
2208         if (ret)
2209                 goto err_free_event_buffers;
2210
2211         ret = dwc3_core_init(dwc);
2212         if (ret) {
2213                 dev_err_probe(dev, ret, "failed to initialize core\n");
2214                 goto err_free_event_buffers;
2215         }
2216
2217         dwc3_check_params(dwc);
2218         dwc3_debugfs_init(dwc);
2219
2220         ret = dwc3_core_init_mode(dwc);
2221         if (ret)
2222                 goto err_exit_debugfs;
2223
2224         pm_runtime_put(dev);
2225
2226         dma_set_max_seg_size(dev, UINT_MAX);
2227
2228         return 0;
2229
2230 err_exit_debugfs:
2231         dwc3_debugfs_exit(dwc);
2232         dwc3_event_buffers_cleanup(dwc);
2233         dwc3_phy_power_off(dwc);
2234         dwc3_phy_exit(dwc);
2235         dwc3_ulpi_exit(dwc);
2236 err_free_event_buffers:
2237         dwc3_free_event_buffers(dwc);
2238 err_allow_rpm:
2239         pm_runtime_allow(dev);
2240         pm_runtime_disable(dev);
2241         pm_runtime_dont_use_autosuspend(dev);
2242         pm_runtime_set_suspended(dev);
2243         pm_runtime_put_noidle(dev);
2244 err_disable_clks:
2245         dwc3_clk_disable(dwc);
2246 err_assert_reset:
2247         reset_control_assert(dwc->reset);
2248 err_put_psy:
2249         if (dwc->usb_psy)
2250                 power_supply_put(dwc->usb_psy);
2251
2252         return ret;
2253 }
2254
2255 static void dwc3_remove(struct platform_device *pdev)
2256 {
2257         struct dwc3     *dwc = platform_get_drvdata(pdev);
2258
2259         pm_runtime_get_sync(&pdev->dev);
2260
2261         dwc3_core_exit_mode(dwc);
2262         dwc3_debugfs_exit(dwc);
2263
2264         dwc3_core_exit(dwc);
2265         dwc3_ulpi_exit(dwc);
2266
2267         pm_runtime_allow(&pdev->dev);
2268         pm_runtime_disable(&pdev->dev);
2269         pm_runtime_dont_use_autosuspend(&pdev->dev);
2270         pm_runtime_put_noidle(&pdev->dev);
2271         /*
2272          * HACK: Clear the driver data, which is currently accessed by parent
2273          * glue drivers, before allowing the parent to suspend.
2274          */
2275         platform_set_drvdata(pdev, NULL);
2276         pm_runtime_set_suspended(&pdev->dev);
2277
2278         dwc3_free_event_buffers(dwc);
2279
2280         if (dwc->usb_psy)
2281                 power_supply_put(dwc->usb_psy);
2282 }
2283
2284 #ifdef CONFIG_PM
2285 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
2286 {
2287         int ret;
2288
2289         ret = reset_control_deassert(dwc->reset);
2290         if (ret)
2291                 return ret;
2292
2293         ret = dwc3_clk_enable(dwc);
2294         if (ret)
2295                 goto assert_reset;
2296
2297         ret = dwc3_core_init(dwc);
2298         if (ret)
2299                 goto disable_clks;
2300
2301         return 0;
2302
2303 disable_clks:
2304         dwc3_clk_disable(dwc);
2305 assert_reset:
2306         reset_control_assert(dwc->reset);
2307
2308         return ret;
2309 }
2310
2311 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
2312 {
2313         u32 reg;
2314         int i;
2315
2316         switch (dwc->current_dr_role) {
2317         case DWC3_GCTL_PRTCAP_DEVICE:
2318                 if (pm_runtime_suspended(dwc->dev))
2319                         break;
2320                 dwc3_gadget_suspend(dwc);
2321                 synchronize_irq(dwc->irq_gadget);
2322                 dwc3_core_exit(dwc);
2323                 break;
2324         case DWC3_GCTL_PRTCAP_HOST:
2325                 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2326                         dwc3_core_exit(dwc);
2327                         break;
2328                 }
2329
2330                 /* Let controller to suspend HSPHY before PHY driver suspends */
2331                 if (dwc->dis_u2_susphy_quirk ||
2332                     dwc->dis_enblslpm_quirk) {
2333                         for (i = 0; i < dwc->num_usb2_ports; i++) {
2334                                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
2335                                 reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
2336                                         DWC3_GUSB2PHYCFG_SUSPHY;
2337                                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
2338                         }
2339
2340                         /* Give some time for USB2 PHY to suspend */
2341                         usleep_range(5000, 6000);
2342                 }
2343
2344                 for (i = 0; i < dwc->num_usb2_ports; i++)
2345                         phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]);
2346                 for (i = 0; i < dwc->num_usb3_ports; i++)
2347                         phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]);
2348                 break;
2349         case DWC3_GCTL_PRTCAP_OTG:
2350                 /* do nothing during runtime_suspend */
2351                 if (PMSG_IS_AUTO(msg))
2352                         break;
2353
2354                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2355                         dwc3_gadget_suspend(dwc);
2356                         synchronize_irq(dwc->irq_gadget);
2357                 }
2358
2359                 dwc3_otg_exit(dwc);
2360                 dwc3_core_exit(dwc);
2361                 break;
2362         default:
2363                 /* do nothing */
2364                 break;
2365         }
2366
2367         return 0;
2368 }
2369
2370 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2371 {
2372         int             ret;
2373         u32             reg;
2374         int             i;
2375
2376         switch (dwc->current_dr_role) {
2377         case DWC3_GCTL_PRTCAP_DEVICE:
2378                 ret = dwc3_core_init_for_resume(dwc);
2379                 if (ret)
2380                         return ret;
2381
2382                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2383                 dwc3_gadget_resume(dwc);
2384                 break;
2385         case DWC3_GCTL_PRTCAP_HOST:
2386                 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2387                         ret = dwc3_core_init_for_resume(dwc);
2388                         if (ret)
2389                                 return ret;
2390                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2391                         break;
2392                 }
2393                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2394                 for (i = 0; i < dwc->num_usb2_ports; i++) {
2395                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
2396                         if (dwc->dis_u2_susphy_quirk)
2397                                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2398
2399                         if (dwc->dis_enblslpm_quirk)
2400                                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2401
2402                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
2403                 }
2404
2405                 for (i = 0; i < dwc->num_usb2_ports; i++)
2406                         phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]);
2407                 for (i = 0; i < dwc->num_usb3_ports; i++)
2408                         phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]);
2409                 break;
2410         case DWC3_GCTL_PRTCAP_OTG:
2411                 /* nothing to do on runtime_resume */
2412                 if (PMSG_IS_AUTO(msg))
2413                         break;
2414
2415                 ret = dwc3_core_init_for_resume(dwc);
2416                 if (ret)
2417                         return ret;
2418
2419                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2420
2421                 dwc3_otg_init(dwc);
2422                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2423                         dwc3_otg_host_init(dwc);
2424                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2425                         dwc3_gadget_resume(dwc);
2426                 }
2427
2428                 break;
2429         default:
2430                 /* do nothing */
2431                 break;
2432         }
2433
2434         return 0;
2435 }
2436
2437 static int dwc3_runtime_checks(struct dwc3 *dwc)
2438 {
2439         switch (dwc->current_dr_role) {
2440         case DWC3_GCTL_PRTCAP_DEVICE:
2441                 if (dwc->connected)
2442                         return -EBUSY;
2443                 break;
2444         case DWC3_GCTL_PRTCAP_HOST:
2445         default:
2446                 /* do nothing */
2447                 break;
2448         }
2449
2450         return 0;
2451 }
2452
2453 static int dwc3_runtime_suspend(struct device *dev)
2454 {
2455         struct dwc3     *dwc = dev_get_drvdata(dev);
2456         int             ret;
2457
2458         if (dwc3_runtime_checks(dwc))
2459                 return -EBUSY;
2460
2461         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2462         if (ret)
2463                 return ret;
2464
2465         return 0;
2466 }
2467
2468 static int dwc3_runtime_resume(struct device *dev)
2469 {
2470         struct dwc3     *dwc = dev_get_drvdata(dev);
2471         int             ret;
2472
2473         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2474         if (ret)
2475                 return ret;
2476
2477         switch (dwc->current_dr_role) {
2478         case DWC3_GCTL_PRTCAP_DEVICE:
2479                 dwc3_gadget_process_pending_events(dwc);
2480                 break;
2481         case DWC3_GCTL_PRTCAP_HOST:
2482         default:
2483                 /* do nothing */
2484                 break;
2485         }
2486
2487         pm_runtime_mark_last_busy(dev);
2488
2489         return 0;
2490 }
2491
2492 static int dwc3_runtime_idle(struct device *dev)
2493 {
2494         struct dwc3     *dwc = dev_get_drvdata(dev);
2495
2496         switch (dwc->current_dr_role) {
2497         case DWC3_GCTL_PRTCAP_DEVICE:
2498                 if (dwc3_runtime_checks(dwc))
2499                         return -EBUSY;
2500                 break;
2501         case DWC3_GCTL_PRTCAP_HOST:
2502         default:
2503                 /* do nothing */
2504                 break;
2505         }
2506
2507         pm_runtime_mark_last_busy(dev);
2508         pm_runtime_autosuspend(dev);
2509
2510         return 0;
2511 }
2512 #endif /* CONFIG_PM */
2513
2514 #ifdef CONFIG_PM_SLEEP
2515 static int dwc3_suspend(struct device *dev)
2516 {
2517         struct dwc3     *dwc = dev_get_drvdata(dev);
2518         int             ret;
2519
2520         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2521         if (ret)
2522                 return ret;
2523
2524         pinctrl_pm_select_sleep_state(dev);
2525
2526         return 0;
2527 }
2528
2529 static int dwc3_resume(struct device *dev)
2530 {
2531         struct dwc3     *dwc = dev_get_drvdata(dev);
2532         int             ret;
2533
2534         pinctrl_pm_select_default_state(dev);
2535
2536         pm_runtime_disable(dev);
2537         pm_runtime_set_active(dev);
2538
2539         ret = dwc3_resume_common(dwc, PMSG_RESUME);
2540         if (ret) {
2541                 pm_runtime_set_suspended(dev);
2542                 return ret;
2543         }
2544
2545         pm_runtime_enable(dev);
2546
2547         return 0;
2548 }
2549
2550 static void dwc3_complete(struct device *dev)
2551 {
2552         struct dwc3     *dwc = dev_get_drvdata(dev);
2553         u32             reg;
2554
2555         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2556                         dwc->dis_split_quirk) {
2557                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2558                 reg |= DWC3_GUCTL3_SPLITDISABLE;
2559                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2560         }
2561 }
2562 #else
2563 #define dwc3_complete NULL
2564 #endif /* CONFIG_PM_SLEEP */
2565
2566 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2567         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2568         .complete = dwc3_complete,
2569         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2570                         dwc3_runtime_idle)
2571 };
2572
2573 #ifdef CONFIG_OF
2574 static const struct of_device_id of_dwc3_match[] = {
2575         {
2576                 .compatible = "snps,dwc3"
2577         },
2578         {
2579                 .compatible = "synopsys,dwc3"
2580         },
2581         { },
2582 };
2583 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2584 #endif
2585
2586 #ifdef CONFIG_ACPI
2587
2588 #define ACPI_ID_INTEL_BSW       "808622B7"
2589
2590 static const struct acpi_device_id dwc3_acpi_match[] = {
2591         { ACPI_ID_INTEL_BSW, 0 },
2592         { },
2593 };
2594 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2595 #endif
2596
2597 static struct platform_driver dwc3_driver = {
2598         .probe          = dwc3_probe,
2599         .remove_new     = dwc3_remove,
2600         .driver         = {
2601                 .name   = "dwc3",
2602                 .of_match_table = of_match_ptr(of_dwc3_match),
2603                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2604                 .pm     = &dwc3_dev_pm_ops,
2605         },
2606 };
2607
2608 module_platform_driver(dwc3_driver);
2609
2610 MODULE_ALIAS("platform:dwc3");
2611 MODULE_AUTHOR("Felipe Balbi <[email protected]>");
2612 MODULE_LICENSE("GPL v2");
2613 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
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