drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/phy/pcie.h>
  18 #include <linux/phy/phy.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/regmap.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/reset.h>
  23 #include <linux/slab.h>
  24
  25 #include <dt-bindings/phy/phy-qcom-qmp.h>
  26
  27 #include "phy-qcom-qmp-common.h"
  28
  29 #include "phy-qcom-qmp.h"
  30 #include "phy-qcom-qmp-pcs-misc-v3.h"
  31 #include "phy-qcom-qmp-pcs-pcie-v4.h"
  32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
  33 #include "phy-qcom-qmp-pcs-pcie-v5.h"
  34 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
  35 #include "phy-qcom-qmp-pcs-pcie-v6.h"
  36 #include "phy-qcom-qmp-pcs-pcie-v6_20.h"
  37 #include "phy-qcom-qmp-pcie-qhp.h"
  38
  39 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  40
  41 /* set of registers with offsets different per-PHY */
  42 enum qphy_reg_layout {
  43         /* PCS registers */
  44         QPHY_SW_RESET,
  45         QPHY_START_CTRL,
  46         QPHY_PCS_STATUS,
  47         QPHY_PCS_POWER_DOWN_CONTROL,
  48         /* Keep last to ensure regs_layout arrays are properly initialized */
  49         QPHY_LAYOUT_SIZE
  50 };
  51
  52 static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
  53         [QPHY_SW_RESET]                 = QPHY_V2_PCS_SW_RESET,
  54         [QPHY_START_CTRL]               = QPHY_V2_PCS_START_CONTROL,
  55         [QPHY_PCS_STATUS]               = QPHY_V2_PCS_PCI_PCS_STATUS,
  56         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V2_PCS_POWER_DOWN_CONTROL,
  57 };
  58
  59 static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
  60         [QPHY_SW_RESET]                 = QPHY_V3_PCS_SW_RESET,
  61         [QPHY_START_CTRL]               = QPHY_V3_PCS_START_CONTROL,
  62         [QPHY_PCS_STATUS]               = QPHY_V3_PCS_PCS_STATUS,
  63         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_POWER_DOWN_CONTROL,
  64 };
  65
  66 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
  67         [QPHY_SW_RESET]                 = 0x00,
  68         [QPHY_START_CTRL]               = 0x08,
  69         [QPHY_PCS_STATUS]               = 0x2ac,
  70         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
  71 };
  72
  73 static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
  74         [QPHY_SW_RESET]                 = QPHY_V4_PCS_SW_RESET,
  75         [QPHY_START_CTRL]               = QPHY_V4_PCS_START_CONTROL,
  76         [QPHY_PCS_STATUS]               = QPHY_V4_PCS_PCS_STATUS1,
  77         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V4_PCS_POWER_DOWN_CONTROL,
  78 };
  79
  80 static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
  81         [QPHY_SW_RESET]                 = QPHY_V5_PCS_SW_RESET,
  82         [QPHY_START_CTRL]               = QPHY_V5_PCS_START_CONTROL,
  83         [QPHY_PCS_STATUS]               = QPHY_V5_PCS_PCS_STATUS1,
  84         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V5_PCS_POWER_DOWN_CONTROL,
  85 };
  86
  87 static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
  88         [QPHY_SW_RESET]                 = QPHY_V6_PCS_SW_RESET,
  89         [QPHY_START_CTRL]               = QPHY_V6_PCS_START_CONTROL,
  90         [QPHY_PCS_STATUS]               = QPHY_V6_PCS_PCS_STATUS1,
  91         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V6_PCS_POWER_DOWN_CONTROL,
  92 };
  93
  94 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
  95         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
  96         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
  97         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
  98         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
  99         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 100         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 101         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 102         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 103         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 104         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 105         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 106         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 107         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 108         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 109         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 110         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 111         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 112         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
 113         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
 114         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
 115         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 116         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 117         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 118         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 119         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
 120         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 121         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
 122         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 123         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 124         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 125         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
 126         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 127         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 128         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 129         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 130         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 131         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 132         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 133         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 134         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 135         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 136         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 137 };
 138
 139 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
 140         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 141         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 142         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 143         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 144 };
 145
 146 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
 147         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 148         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
 149         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 150         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
 151         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 152         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 153         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 154         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 155         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 156         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
 157         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 158         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 159         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 160         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 161 };
 162
 163 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
 164         QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 165         QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 166         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 167         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 168         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 169         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 170         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 171         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 172         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
 173         QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 174 };
 175
 176 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
 177         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
 178         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
 179         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
 180         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
 181         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
 182         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
 183         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
 184         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
 185         QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
 186         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
 187         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
 188         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
 189         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
 190         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
 191         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
 192         QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
 193         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
 194         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
 195         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
 196         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
 197         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
 198         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
 199         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
 200         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
 201         QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
 202         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
 203         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
 204         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
 205         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
 206         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
 207         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
 208         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
 209         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
 210         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
 211         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
 212         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
 213         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
 214         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
 215         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
 216         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
 217         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
 218         QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
 219         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
 220         QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
 221         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 222         QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
 223 };
 224
 225 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
 226         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 227         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
 228         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 229 };
 230
 231 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
 232         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
 233         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
 234         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 235         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
 236         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
 237         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 238         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
 239         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 240         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 241         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
 242         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 243         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
 244         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
 245         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 246         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
 247         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01),
 248         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
 249         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
 250         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
 251         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
 252         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
 253         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
 254         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
 255         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
 256         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
 257         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
 258         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
 259         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
 260         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
 261         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 262 };
 263
 264 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
 265         QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
 266         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
 267         QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
 268         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 269         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 270         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
 271         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
 272 };
 273
 274 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {
 275         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
 276         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
 277         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
 278         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 279         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 280         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
 281         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
 282         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
 283         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
 284 };
 285
 286 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
 287         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
 288         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 289         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
 290         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
 291         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
 292         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 293         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 294         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
 295         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
 296         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
 297         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
 298         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
 299         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
 300         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 301         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
 302         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
 303         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 304         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
 305         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 306         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 307         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
 308         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
 309         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
 310         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 311         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
 312         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 313         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
 314         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 315         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 316         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
 317         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 318         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
 319         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
 320         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 321         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
 322         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
 323         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
 324         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 325         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 326         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 327 };
 328
 329 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
 330         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 331         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
 332         QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
 333         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 334         QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36),
 335         QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
 336 };
 337
 338 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
 339         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 340         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 341         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
 342         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
 343         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 344         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 345         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
 346 };
 347
 348 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
 349         QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),
 350         QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),
 351         QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
 352         QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
 353         QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
 354         QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
 355         QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
 356         QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 357         QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
 358         QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
 359         QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
 360 };
 361
 362 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {
 363         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
 364         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
 365         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
 366         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
 367         QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
 368         QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
 369         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
 370         QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
 371         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
 372         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
 373         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 374         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
 375         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
 376         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
 377         QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
 378         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),
 379         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),
 380         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),
 381         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),
 382         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),
 383         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),
 384         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),
 385         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
 386         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
 387         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),
 388         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),
 389         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
 390         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
 391         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 392         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
 393         QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),
 394         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
 395         QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
 396         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
 397         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
 398         QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),
 399         QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),
 400         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),
 401         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),
 402         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),
 403         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),
 404         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
 405         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),
 406         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),
 407         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),
 408         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
 409         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
 410         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),
 411         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),
 412         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
 413         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
 414         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 415         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),
 416         QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
 417         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
 418         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
 419         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
 420 };
 421
 422 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {
 423         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 424         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 425         QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10),
 426         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
 427 };
 428
 429 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {
 430         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
 431         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
 432         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 433         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe),
 434         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4),
 435         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
 436         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 437         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 438         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
 439         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
 440         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 441         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
 442         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
 443         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
 444         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
 445         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
 446         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
 447         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
 448         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
 449         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
 450         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
 451         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
 452         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2),
 453         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
 454         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
 455         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
 456         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 457         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 458         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
 459         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
 460 };
 461
 462 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {
 463         QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83),
 464         QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9),
 465         QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42),
 466         QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40),
 467         QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
 468         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),
 469         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),
 470         QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
 471         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
 472         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 473         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
 474 };
 475
 476 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = {
 477         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),
 478         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
 479         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 480         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
 481         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 482         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
 483         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb),
 484         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
 485         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
 486         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
 487         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
 488         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),
 489         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
 490 };
 491
 492 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] = {
 493         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
 494         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
 495         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
 496         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
 497         QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
 498         QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
 499         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
 500         QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
 501         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
 502         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
 503         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 504         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
 505         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
 506         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
 507         QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
 508         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
 509         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
 510         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
 511         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
 512         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
 513         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
 514         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
 515         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
 516         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
 517         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),
 518         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
 519         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
 520         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
 521         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 522         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
 523         QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a),
 524         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
 525         QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
 526         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
 527         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
 528         QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a),
 529         QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
 530         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
 531         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
 532         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
 533         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
 534         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
 535         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
 536         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
 537         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
 538         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
 539         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),
 540         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
 541         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
 542         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
 543         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 544         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
 545         QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
 546         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01),
 547         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
 548         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
 549         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00),
 550         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00),
 551         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
 552         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
 553         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
 554         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
 555         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
 556         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
 557         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
 558         QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),
 559         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),
 560 };
 561
 562 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = {
 563         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
 564         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
 565         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
 566         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
 567         QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
 568         QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
 569         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
 570         QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
 571         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
 572         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
 573         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 574         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
 575         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
 576         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
 577         QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
 578         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
 579         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
 580         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
 581         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
 582         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
 583         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
 584         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
 585         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
 586         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
 587         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),
 588         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
 589         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
 590         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
 591         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 592         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
 593         QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a),
 594         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
 595         QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
 596         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
 597         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
 598         QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a),
 599         QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
 600         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
 601         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
 602         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
 603         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
 604         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
 605         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
 606         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
 607         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
 608         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
 609         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),
 610         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
 611         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
 612         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
 613         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 614         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
 615         QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
 616         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01),
 617         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
 618         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
 619         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00),
 620         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00),
 621         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
 622         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
 623         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
 624         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
 625         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
 626         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
 627         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
 628         QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),
 629         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),
 630 };
 631
 632 static const struct qmp_phy_init_tbl ipq9574_pcie_rx_tbl[] = {
 633         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
 634         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
 635         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 636         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
 637         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 638         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
 639         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 640         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
 641         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
 642         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 643         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
 644         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x73),
 645         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x80),
 646         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
 647         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
 648         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
 649         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
 650         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
 651         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x00),
 652         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
 653         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
 654         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
 655         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
 656         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
 657         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x02),
 658         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
 659         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
 660         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
 661         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 662         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 663 };
 664
 665 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_tbl[] = {
 666         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
 667         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 668         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
 669         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 670         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
 671         QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
 672 };
 673
 674 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_misc_tbl[] = {
 675         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
 676         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
 677         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
 678         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 679         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
 680         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 681         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x14),
 682         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x10),
 683         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0b),
 684         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
 685         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
 686         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
 687         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
 688         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
 689         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
 690         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
 691         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x06),
 692         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),
 693         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
 694 };
 695
 696 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_tbl[] = {
 697         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
 698         QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
 699         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
 700         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 701         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
 702         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 703 };
 704
 705 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = {
 706         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
 707         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
 708         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
 709         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 710         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
 711         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 712         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14),
 713         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10),
 714         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b),
 715         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00),
 716         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58),
 717         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
 718         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00),
 719         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
 720         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19),
 721         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
 722         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49),
 723         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a),
 724         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02),
 725         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),
 726         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
 727 };
 728
 729 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
 730         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 731         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 732         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
 733         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 734         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 735         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 736         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 737         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 738         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 739         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 740         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 741         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 742         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 743         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 744         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 745         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 746         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 747         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 748         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 749         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 750         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 751         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 752         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 753         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 754         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 755         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 756         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 757         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
 758         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 759         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 760         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
 761         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 762         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 763         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 764         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 765         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 766         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 767         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 768         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 769         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 770         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 771         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 772 };
 773
 774 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
 775         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 776         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 777         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 778         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 779 };
 780
 781 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
 782         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 783         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
 784         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 785         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 786         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 787         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 788         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 789         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 790         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 791         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
 792         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 793         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
 794         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 795         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 796         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 797         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 798 };
 799
 800 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
 801         QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 802
 803         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 804         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 805         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 806         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 807         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 808
 809         QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 810         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 811         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 812         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 813         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 814         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 815         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 816
 817         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
 818         QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 819         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
 820
 821         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
 822 };
 823
 824 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
 825         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
 826         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
 827         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
 828         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
 829         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
 830 };
 831
 832 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
 833         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
 834         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
 835         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
 836         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
 837         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
 838         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
 839         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
 840         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
 841         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
 842         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
 843         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
 844         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
 845         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
 846         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
 847         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
 848         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
 849         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
 850         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
 851         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
 852         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
 853         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
 854         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
 855         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
 856         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
 857         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
 858         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
 859         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
 860         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
 861         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
 862         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
 863         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 864         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
 865         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
 866         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
 867         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
 868         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
 869         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
 870         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
 871         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
 872         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
 873         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
 874         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
 875         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
 876         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
 877         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
 878 };
 879
 880 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
 881         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
 882         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
 883         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
 884         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
 885         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
 886         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
 887         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
 888         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
 889         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
 890         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
 891         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
 892         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
 893         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
 894         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
 895         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
 896         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
 897         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
 898         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
 899         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
 900         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
 901         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
 902         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
 903         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
 904         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
 905         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
 906         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
 907         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
 908         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
 909         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
 910         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
 911         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
 912         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
 913         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
 914         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
 915         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
 916         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
 917         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
 918         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
 919         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
 920         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
 921         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
 922         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
 923         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
 924         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
 925         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
 926         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
 927         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
 928         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
 929         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
 930         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
 931         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
 932         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
 933         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
 934         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
 935         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
 936         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
 937 };
 938
 939 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
 940         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
 941         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
 942         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
 943         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
 944         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
 945         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
 946         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
 947 };
 948
 949 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
 950         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
 951         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
 952         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
 953         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
 954         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
 955         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
 956         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
 957         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
 958         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 959         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 960         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
 961         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
 962         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
 963         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
 964         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
 965         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
 966         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
 967         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
 968         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
 969         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
 970         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
 971         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
 972         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
 973         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 974         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 975         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 976         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 977         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 978         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 979         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 980         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
 981         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
 982         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
 983         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
 984         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
 985         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
 986         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
 987         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
 988         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
 989         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
 990         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
 991         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
 992 };
 993
 994 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
 995         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 996         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
 997 };
 998
 999 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
1000         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
1001         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
1002         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
1003         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
1004         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
1005         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
1006         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
1007         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1008         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1009         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
1010         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
1011         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1012         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
1013         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
1014         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
1015         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
1016         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
1017         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
1018         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
1019         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
1020         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
1021         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
1022         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
1023         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
1024         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
1025         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
1026         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
1027         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
1028         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1029         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1030         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1031         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
1032         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1033         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
1034         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1035         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
1036 };
1037
1038 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
1039         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1040         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1041         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
1042         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
1043         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
1044 };
1045
1046 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
1047         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1048         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1049         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1050         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1051         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
1052         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
1053         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1054 };
1055
1056 static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = {
1057         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
1058         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1059         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1060         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1061         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1062         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1063         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1064         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
1065         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1066         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1067         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1068         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1069         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1070         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1071         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1072         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
1073         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
1074         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
1075         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
1076         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
1077         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
1078         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1079         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
1080         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1081         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
1082         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
1083         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
1084         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
1085         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
1086         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1087         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
1088         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
1089         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
1090         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
1091         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
1092         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
1093         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9),
1094         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1095         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94),
1096         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1097         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1098 };
1099
1100 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
1101         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
1102 };
1103
1104 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = {
1105         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
1106 };
1107
1108 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = {
1109         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
1110 };
1111
1112 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = {
1113         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
1114         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
1115         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1116         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1117         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1118 };
1119
1120 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = {
1121         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
1122         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
1123         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1124         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1125         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
1126         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
1127         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
1128         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
1129         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
1130         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
1131         QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
1132         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
1133         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1134         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1135         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1136         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1137         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1138         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1139 };
1140
1141 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = {
1142         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
1143         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
1144         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
1145 };
1146
1147 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
1148         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1149         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1150         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
1151         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1152 };
1153
1154 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = {
1155         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
1156         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
1157         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
1158         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1159         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1160         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1161 };
1162
1163 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = {
1164         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
1165         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
1166         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
1167         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
1168         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
1169         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
1170         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
1171         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
1172         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
1173         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
1174         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
1175         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1176         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1177         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1178         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1179         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1180         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1181 };
1182
1183 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = {
1184         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
1185         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88),
1186         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
1187         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f),
1188 };
1189
1190 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1191         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
1192         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1193         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1194         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1195 };
1196
1197 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = {
1198         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
1199         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
1200         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
1201         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1202         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1203         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1204         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
1205         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
1206         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
1207         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
1208         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
1209         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
1210         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
1211         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
1212         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1213         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1214         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1215         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1216         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1217         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
1218         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
1219         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1220         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
1221         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
1222         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
1223         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1224         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1225         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1226         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1227         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1228         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
1229         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),
1230         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
1231         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
1232         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1233         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
1234         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
1235         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1236         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1237         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
1238         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1239         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
1240         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
1241         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
1242         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
1243 };
1244
1245 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
1246         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
1247         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88),
1248         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00),
1249         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f),
1250         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4),
1251         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
1252         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
1253         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
1254         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32),
1255         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
1256         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
1257         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1258         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1259         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1260         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1261         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1262         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1263         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1264         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1265         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1266 };
1267
1268 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = {
1269         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1270         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
1271         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
1272         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10),
1273         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
1274         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
1275 };
1276
1277 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = {
1278         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),
1279         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),
1280         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
1281         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
1282         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
1283         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
1284         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00),
1285         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15),
1286         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01),
1287         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01),
1288         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45),
1289         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b),
1290         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
1291         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1292         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
1293         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
1294         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1295         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39),
1296         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
1297         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
1298         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
1299         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
1300         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),
1301         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
1302         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
1303         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xe4),
1304         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xa4),
1305         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),
1306         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
1307         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b),
1308         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
1309         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
1310 };
1311
1312 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = {
1313         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
1314         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),
1315         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
1316         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
1317 };
1318
1319 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
1320         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
1321         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
1322         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
1323         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
1324         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
1325         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
1326         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
1327         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
1328         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
1329         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),
1330         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),
1331         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),
1332 };
1333
1334 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
1335         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
1336         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
1337         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1338         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1339         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
1340         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1341         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
1342         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
1343         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1344         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1345         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1346         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
1347         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
1348         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
1349         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
1350         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
1351         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
1352         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1353         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
1354         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1355         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
1356         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
1357         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1358         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1359         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1360         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1361         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1362         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1363         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1364         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1365         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1366         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1367         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1368         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1369         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1370         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1371         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1372         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1373         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1374         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1375         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
1376 };
1377
1378 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
1379         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
1380 };
1381
1382 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
1383         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1384         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
1385         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1386 };
1387
1388 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
1389         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1390         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
1391         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
1392         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1393         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1394         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
1395         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
1396         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
1397         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1398         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
1399         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1400         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1401         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
1402         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
1403         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
1404         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1405         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
1406         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
1407         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
1408         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
1409         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1410         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
1411         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
1412         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
1413         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1414         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1415         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
1416         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
1417         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1418         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
1419 };
1420
1421 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
1422         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
1423         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
1424         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1425         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
1426         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
1427         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
1428 };
1429
1430 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
1431         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1432         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
1433         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
1434 };
1435
1436 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
1437         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
1438         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
1439 };
1440
1441 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
1442         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1443         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1444         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1445         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
1446         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
1447         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
1448         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1449 };
1450
1451 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
1452         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1453         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
1454 };
1455
1456 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
1457         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1458 };
1459
1460 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
1461         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
1462         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1463         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
1464         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1465 };
1466
1467 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
1468         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
1469         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
1470 };
1471
1472 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1473         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
1474         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1475 };
1476
1477 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
1478         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
1479         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1480         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
1481         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
1482         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1483         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
1484         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1485         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
1486         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
1487         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
1488         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03),
1489         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
1490         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
1491         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
1492 };
1493
1494 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = {
1495         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1496         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1497         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1498         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce),
1499         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b),
1500         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97),
1501         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
1502         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
1503         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a),
1504         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10),
1505         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1506         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1507         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1508         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1509         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1510         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1511         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
1512         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04),
1513         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d),
1514         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a),
1515         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a),
1516         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3),
1517         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0),
1518         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05),
1519         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55),
1520         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55),
1521         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05),
1522         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
1523         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1524         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1525         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8),
1526         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20),
1527 };
1528
1529 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = {
1530         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
1531         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
1532         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
1533         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
1534         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
1535         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
1536         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
1537         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
1538         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
1539         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
1540         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
1541         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
1542         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
1543         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
1544         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
1545         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
1546         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
1547         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
1548         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
1549         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
1550         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
1551         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
1552         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
1553         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
1554         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
1555 };
1556
1557 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
1558         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
1559         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
1560         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
1561         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
1562         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
1563 };
1564
1565 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
1566         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
1567         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
1568         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
1569         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
1570         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
1571         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
1572         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
1573         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
1574         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
1575         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
1576         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
1577         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
1578         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
1579         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
1580         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
1581         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
1582         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
1583         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
1584         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
1585         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
1586         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
1587         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
1588         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
1589         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1590         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
1591 };
1592
1593 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
1594         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
1595         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
1596         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
1597         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
1598 };
1599
1600 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
1601         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
1602         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
1603         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
1604         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
1605         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
1606 };
1607
1608 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = {
1609         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1610         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1611 };
1612
1613 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = {
1614         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
1615         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
1616 };
1617
1618 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_serdes_tbl[] = {
1619         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
1620         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
1621         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
1622         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1623         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
1624         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
1625         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
1626         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
1627         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
1628         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
1629         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
1630         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
1631         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
1632         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
1633         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
1634         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
1635         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
1636         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
1637         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
1638         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
1639         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
1640         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
1641         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
1642         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1643         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
1644         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1645         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1646         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1647         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1648         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
1649         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
1650         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
1651         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE_CONTD, 0x00),
1652         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
1653 };
1654
1655 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_tx_tbl[] = {
1656         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
1657         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
1658         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x00),
1659         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_VMODE_CTRL1, 0x00),
1660         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_PI_QEC_CTRL, 0x00),
1661         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
1662         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1663         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RCV_DETECT_LVL_2, 0x12),
1664 };
1665
1666 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_rx_tbl[] = {
1667         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
1668         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_1, 0x06),
1669         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_2, 0x06),
1670         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1, 0x3e),
1671         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2, 0x1e),
1672         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
1673         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
1674         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1, 0x02),
1675         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2, 0x1d),
1676         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x44),
1677         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL2, 0x00),
1678         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
1679         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1680         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x74),
1681         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1682         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_ENABLES, 0x1c),
1683         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_CNTRL, 0x03),
1684         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
1685         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x04),
1686         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
1687         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
1688         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
1689         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x64),
1690         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
1691         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
1692         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
1693         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DCC_CTRL1, 0x0c),
1694         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1695         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1696         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1697         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1698         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1699         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1700         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1701         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1702         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1703         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
1704         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
1705         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
1706         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
1707         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
1708         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
1709         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
1710         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE2, 0x00),
1711         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
1712         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
1713         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1714         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
1715         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xac),
1716         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
1717         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
1718         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x07),
1719         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
1720         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
1721         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc5),
1722         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xee),
1723         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
1724         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
1725         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
1726         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
1727         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
1728         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_EN_TIMER, 0x28),
1729         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1730 };
1731
1732 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_tbl[] = {
1733         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
1734         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0xaa),
1735         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG2, 0x0d),
1736         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
1737         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
1738 };
1739
1740 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = {
1741         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
1742         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
1743         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
1744         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d),
1745         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
1746         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
1747         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
1748         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
1749 };
1750
1751 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = {
1752         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
1753         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
1754         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
1755         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1756         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
1757         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
1758         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
1759         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
1760         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1761         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1762         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1763         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
1764         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
1765         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1766         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
1767         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
1768         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
1769         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
1770         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
1771         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
1772         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
1773         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
1774         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
1775         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1776         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1777         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1778         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1779         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1780         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1781         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1782         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1783         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1784         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1785         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1786         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1787         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1788         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1789         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1790         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1791         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1792         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
1793 };
1794
1795 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
1796         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
1797 };
1798
1799 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
1800         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
1801         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
1802         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1803         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
1804         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
1805 };
1806
1807 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = {
1808         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
1809         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
1810         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
1811         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
1812         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
1813         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
1814         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
1815         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
1816         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
1817         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1818         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1819         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1820         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1821         QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
1822 };
1823
1824 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = {
1825         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1826         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1827         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
1828         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1829         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1830         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
1831         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
1832         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1833 };
1834
1835 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = {
1836         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
1837         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
1838         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
1839 };
1840
1841 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
1842         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1843         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1844         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
1845         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1846 };
1847
1848 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = {
1849         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
1850         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
1851         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1852         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1853         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1854 };
1855
1856 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = {
1857         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1858         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1859         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1860         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1861 };
1862
1863 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = {
1864         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
1865         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
1866         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1867 };
1868
1869 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = {
1870         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
1871         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
1872         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
1873         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1874         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1875         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1876 };
1877
1878 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
1879         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f),
1880 };
1881
1882 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
1883         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
1884         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1885         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
1886         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
1887         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1888         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
1889         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1890         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1891         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1892         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
1893         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
1894         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
1895         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
1896 };
1897
1898 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = {
1899         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1900         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1901         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1902         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1903         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
1904         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
1905         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
1906         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1907         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1908         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1909         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1910         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1911         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1912         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
1913         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
1914         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
1915         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
1916         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
1917         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1918         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
1919         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1920         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
1921         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
1922         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
1923         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
1924         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
1925         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
1926         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
1927 };
1928
1929 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
1930         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
1931         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
1932         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
1933         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1934 };
1935
1936 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
1937         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
1938         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1939         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
1940         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
1941         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
1942         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
1943         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
1944         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
1945         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
1946         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
1947         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
1948         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
1949         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
1950         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
1951         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
1952         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
1953         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
1954         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
1955         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
1956         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
1957         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
1958         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
1959         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
1960         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
1961
1962         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
1963
1964         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1965
1966         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1967         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1968         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1969         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1970         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1971         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1972         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1973         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1974
1975         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
1976         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
1977         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
1978         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1979         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
1980         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
1981         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
1982         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
1983         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
1984 };
1985
1986 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
1987         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
1988         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
1989         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
1990         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99),
1991 };
1992
1993 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
1994         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
1995         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
1996         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
1997         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
1998 };
1999
2000 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = {
2001         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2002         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2003         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00),
2004 };
2005
2006 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = {
2007         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
2008         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
2009         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
2010         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
2011         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
2012         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
2013         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
2014         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
2015         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
2016         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
2017         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
2018         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
2019         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
2020         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
2021         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
2022         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
2023         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
2024         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
2025         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
2026         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
2027 };
2028
2029 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = {
2030         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
2031 };
2032
2033 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = {
2034         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
2035         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
2036         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
2037         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
2038         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
2039         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93),
2040         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
2041         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
2042         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
2043         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
2044         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
2045         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
2046         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
2047         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
2048         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
2049         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
2050         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
2051         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
2052         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
2053         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
2054         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
2055         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
2056         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
2057         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
2058         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34),
2059         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
2060         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
2061         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
2062         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
2063         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),
2064         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
2065         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
2066         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
2067         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
2068         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
2069         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
2070         QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f),
2071         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
2072 };
2073
2074 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = {
2075         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15),
2076         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
2077         QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02),
2078         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
2079         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18),
2080 };
2081
2082 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = {
2083         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2084         QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11),
2085         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),
2086         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf),
2087         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7),
2088         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea),
2089         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),
2090         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
2091         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
2092         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a),
2093         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89),
2094         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
2095         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94),
2096         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b),
2097         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a),
2098         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89),
2099         QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00),
2100         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09),
2101         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05),
2102         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
2103         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
2104         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
2105         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c),
2106         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
2107         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
2108 };
2109
2110 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = {
2111         QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05),
2112         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77),
2113         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b),
2114         QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f),
2115         QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c),
2116 };
2117
2118 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
2119         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e),
2120         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27),
2121         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
2122         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
2123         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2124         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2125 };
2126
2127 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = {
2128         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
2129         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
2130         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
2131         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
2132         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
2133         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
2134         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
2135         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
2136         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
2137         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
2138         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
2139         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
2140         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
2141         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
2142         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
2143         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
2144         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
2145         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
2146         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
2147         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
2148         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
2149         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
2150         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
2151         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
2152         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
2153         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
2154         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
2155         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
2156         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
2157         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
2158         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
2159         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),
2160         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
2161         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
2162         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
2163         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
2164         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
2165         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
2166         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
2167         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
2168         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
2169         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
2170         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
2171         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
2172         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
2173 };
2174
2175 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
2176         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
2177         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00),
2178         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
2179         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),
2180         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
2181         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
2182         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
2183         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
2184         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38),
2185         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
2186         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
2187         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
2188         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
2189         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
2190         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
2191         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
2192         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
2193         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
2194         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
2195         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
2196         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),
2197 };
2198
2199 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = {
2200         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
2201         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
2202         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
2203         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00),
2204         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
2205         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
2206 };
2207
2208 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = {
2209         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),
2210         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
2211         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),
2212         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
2213         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
2214         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
2215         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c),
2216         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
2217         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),
2218         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
2219         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
2220         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2221         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
2222         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
2223         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
2224         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
2225         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
2226         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
2227         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
2228         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
2229         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),
2230         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
2231         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
2232         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb),
2233         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb),
2234         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0),
2235         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
2236         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78),
2237         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
2238         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
2239         QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),
2240 };
2241
2242 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = {
2243         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
2244         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
2245         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),
2246         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
2247         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
2248         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
2249         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),
2250 };
2251
2252 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
2253         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
2254         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
2255         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
2256         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27),
2257         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27),
2258         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
2259         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
2260         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
2261         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
2262         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
2263         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
2264         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),
2265         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),
2266         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),
2267 };
2268
2269 static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = {
2270         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a),
2271         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
2272         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
2273         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
2274         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82),
2275         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
2276         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
2277         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
2278         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2279         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
2280         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
2281         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2282         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3),
2283         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3),
2284         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00),
2285         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
2286         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06),
2287         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
2288         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
2289         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23),
2290         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b),
2291         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),
2292         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
2293         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43),
2294         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
2295         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
2296 };
2297
2298 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = {
2299         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
2300         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2301         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
2302         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
2303         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2304         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
2305         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2306         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
2307         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
2308         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
2309         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
2310         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
2311         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
2312         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
2313 };
2314
2315 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl[] = {
2316         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
2317         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
2318         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
2319         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2320         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2321         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
2322         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
2323         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
2324         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
2325         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
2326         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
2327         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
2328         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
2329         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
2330         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
2331         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
2332         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
2333         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
2334         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
2335         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2336         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
2337         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
2338         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
2339         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
2340         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
2341         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
2342         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
2343         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
2344 };
2345
2346 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rx_alt_tbl[] = {
2347         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
2348         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2349         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9a),
2350         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
2351         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92),
2352         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
2353         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
2354         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x99),
2355         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
2356         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a),
2357         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb),
2358         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92),
2359         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec),
2360         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
2361         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
2362         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
2363         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),
2364         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8),
2365         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec),
2366         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6),
2367         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
2368         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5),
2369         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e),
2370         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
2371         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
2372         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
2373         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),
2374         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
2375         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
2376         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
2377         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
2378         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
2379         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
2380         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
2381         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
2382         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
2383         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
2384         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
2385         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
2386         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
2387         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
2388         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
2389         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2390         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
2391         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
2392         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
2393         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),
2394         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
2395         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
2396 };
2397
2398 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_tx_tbl[] = {
2399         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
2400         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
2401         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
2402         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
2403         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x0f),
2404 };
2405
2406 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_misc_tbl[] = {
2407         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
2408         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
2409         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
2410         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
2411 };
2412
2413 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl[] = {
2414         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
2415         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2416         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2417 };
2418
2419 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl[] = {
2420         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
2421         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
2422         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
2423         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
2424         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
2425         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),
2426 };
2427
2428 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = {
2429         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
2430         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
2431         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),
2432         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2433         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
2434         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),
2435         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
2436         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2437         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
2438         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
2439         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
2440         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
2441         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
2442         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
2443         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
2444         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
2445         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
2446         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
2447         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
2448         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
2449         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x99),
2450         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
2451         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92),
2452         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
2453         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
2454         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
2455         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
2456         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a),
2457         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xb6),
2458         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92),
2459         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xf0),
2460         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
2461         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
2462         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
2463         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),
2464         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf6),
2465         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xee),
2466         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd2),
2467         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
2468         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf9),
2469         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x3d),
2470         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
2471         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
2472         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
2473         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
2474         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
2475         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
2476         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
2477         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
2478 };
2479
2480 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl[] = {
2481         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
2482         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
2483         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
2484         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),
2485 };
2486
2487 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = {
2488         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
2489         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2490         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
2491         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
2492         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
2493         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
2494         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2495         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
2496         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2497         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
2498         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
2499         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
2500         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
2501         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
2502         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
2503         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
2504 };
2505
2506
2507 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[] = {
2508         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
2509         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
2510         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
2511         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2512         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2513         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
2514         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
2515         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
2516         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
2517         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
2518         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
2519         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
2520         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
2521         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
2522         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
2523         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
2524         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
2525         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2526         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
2527         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
2528         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
2529         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
2530         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
2531         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
2532         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
2533         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
2534 };
2535
2536 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl[] = {
2537         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
2538         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
2539         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
2540         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
2541         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
2542         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
2543         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
2544         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
2545         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
2546         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
2547         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
2548         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
2549         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
2550         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
2551         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
2552         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
2553         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
2554         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
2555         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
2556         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
2557 };
2558
2559 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] = {
2560         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_MX_CTRL7, 0x00),
2561         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_SW_CTRL7, 0x00),
2562 };
2563
2564 struct qmp_pcie_offsets {
2565         u16 serdes;
2566         u16 pcs;
2567         u16 pcs_misc;
2568         u16 tx;
2569         u16 rx;
2570         u16 tx2;
2571         u16 rx2;
2572         u16 ln_shrd;
2573 };
2574
2575 struct qmp_phy_cfg_tbls {
2576         const struct qmp_phy_init_tbl *serdes;
2577         int serdes_num;
2578         const struct qmp_phy_init_tbl *tx;
2579         int tx_num;
2580         const struct qmp_phy_init_tbl *rx;
2581         int rx_num;
2582         const struct qmp_phy_init_tbl *pcs;
2583         int pcs_num;
2584         const struct qmp_phy_init_tbl *pcs_misc;
2585         int pcs_misc_num;
2586         const struct qmp_phy_init_tbl *ln_shrd;
2587         int ln_shrd_num;
2588 };
2589
2590 /* struct qmp_phy_cfg - per-PHY initialization config */
2591 struct qmp_phy_cfg {
2592         int lanes;
2593
2594         const struct qmp_pcie_offsets *offsets;
2595
2596         /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
2597         const struct qmp_phy_cfg_tbls tbls;
2598         /*
2599          * Additional init sequences for PHY blocks, providing additional
2600          * register programming. They are used for providing separate sequences
2601          * for the Root Complex and End Point use cases.
2602          *
2603          * If EP mode is not supported, both tables can be left unset.
2604          */
2605         const struct qmp_phy_cfg_tbls *tbls_rc;
2606         const struct qmp_phy_cfg_tbls *tbls_ep;
2607
2608         const struct qmp_phy_init_tbl *serdes_4ln_tbl;
2609         int serdes_4ln_num;
2610
2611         /* resets to be requested */
2612         const char * const *reset_list;
2613         int num_resets;
2614         /* regulators to be requested */
2615         const char * const *vreg_list;
2616         int num_vregs;
2617
2618         /* array of registers with different offsets */
2619         const unsigned int *regs;
2620
2621         unsigned int pwrdn_ctrl;
2622         /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
2623         unsigned int phy_status;
2624
2625         bool skip_start_delay;
2626
2627         bool has_nocsr_reset;
2628
2629         /* QMP PHY pipe clock interface rate */
2630         unsigned long pipe_clock_rate;
2631
2632         /* QMP PHY AUX clock interface rate */
2633         unsigned long aux_clock_rate;
2634 };
2635
2636 struct qmp_pcie {
2637         struct device *dev;
2638
2639         const struct qmp_phy_cfg *cfg;
2640         bool tcsr_4ln_config;
2641
2642         void __iomem *serdes;
2643         void __iomem *pcs;
2644         void __iomem *pcs_misc;
2645         void __iomem *tx;
2646         void __iomem *rx;
2647         void __iomem *tx2;
2648         void __iomem *rx2;
2649         void __iomem *ln_shrd;
2650
2651         void __iomem *port_b;
2652
2653         struct clk_bulk_data *clks;
2654         struct clk_bulk_data pipe_clks[2];
2655         int num_pipe_clks;
2656
2657         struct reset_control_bulk_data *resets;
2658         struct reset_control *nocsr_reset;
2659         struct regulator_bulk_data *vregs;
2660
2661         struct phy *phy;
2662         int mode;
2663
2664         struct clk_fixed_rate pipe_clk_fixed;
2665         struct clk_fixed_rate aux_clk_fixed;
2666 };
2667
2668 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
2669 {
2670         u32 reg;
2671
2672         reg = readl(base + offset);
2673         reg |= val;
2674         writel(reg, base + offset);
2675
2676         /* ensure that above write is through */
2677         readl(base + offset);
2678 }
2679
2680 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
2681 {
2682         u32 reg;
2683
2684         reg = readl(base + offset);
2685         reg &= ~val;
2686         writel(reg, base + offset);
2687
2688         /* ensure that above write is through */
2689         readl(base + offset);
2690 }
2691
2692 /* list of clocks required by phy */
2693 static const char * const qmp_pciephy_clk_l[] = {
2694         "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux",
2695 };
2696
2697 /* list of regulators */
2698 static const char * const qmp_phy_vreg_l[] = {
2699         "vdda-phy", "vdda-pll",
2700 };
2701
2702 static const char * const sm8550_qmp_phy_vreg_l[] = {
2703         "vdda-phy", "vdda-pll", "vdda-qref",
2704 };
2705
2706 /* list of resets */
2707 static const char * const ipq8074_pciephy_reset_l[] = {
2708         "phy", "common",
2709 };
2710
2711 static const char * const sdm845_pciephy_reset_l[] = {
2712         "phy",
2713 };
2714
2715 static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = {
2716         .serdes         = 0,
2717         .pcs            = 0x1800,
2718         .tx             = 0x0800,
2719         /* no .rx for QHP */
2720 };
2721
2722 static const struct qmp_pcie_offsets qmp_pcie_offsets_v2 = {
2723         .serdes         = 0,
2724         .pcs            = 0x0800,
2725         .tx             = 0x0200,
2726         .rx             = 0x0400,
2727 };
2728
2729 static const struct qmp_pcie_offsets qmp_pcie_offsets_v3 = {
2730         .serdes         = 0,
2731         .pcs            = 0x0800,
2732         .pcs_misc       = 0x0600,
2733         .tx             = 0x0200,
2734         .rx             = 0x0400,
2735 };
2736
2737 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = {
2738         .serdes         = 0,
2739         .pcs            = 0x0800,
2740         .pcs_misc       = 0x0c00,
2741         .tx             = 0x0200,
2742         .rx             = 0x0400,
2743 };
2744
2745 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = {
2746         .serdes         = 0,
2747         .pcs            = 0x0a00,
2748         .pcs_misc       = 0x0e00,
2749         .tx             = 0x0200,
2750         .rx             = 0x0400,
2751         .tx2            = 0x0600,
2752         .rx2            = 0x0800,
2753 };
2754
2755 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = {
2756         .serdes         = 0x1000,
2757         .pcs            = 0x1200,
2758         .pcs_misc       = 0x1600,
2759         .tx             = 0x0000,
2760         .rx             = 0x0200,
2761         .tx2            = 0x0800,
2762         .rx2            = 0x0a00,
2763 };
2764
2765 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = {
2766         .serdes         = 0,
2767         .pcs            = 0x0200,
2768         .pcs_misc       = 0x0600,
2769         .tx             = 0x0e00,
2770         .rx             = 0x1000,
2771         .tx2            = 0x1600,
2772         .rx2            = 0x1800,
2773 };
2774
2775 static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = {
2776         .serdes         = 0,
2777         .pcs            = 0x1000,
2778         .pcs_misc       = 0x1400,
2779         .tx             = 0x0200,
2780         .rx             = 0x0400,
2781         .tx2            = 0x0600,
2782         .rx2            = 0x0800,
2783 };
2784
2785 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = {
2786         .serdes         = 0x1000,
2787         .pcs            = 0x1200,
2788         .pcs_misc       = 0x1400,
2789         .tx             = 0x0000,
2790         .rx             = 0x0200,
2791         .tx2            = 0x0800,
2792         .rx2            = 0x0a00,
2793 };
2794
2795 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = {
2796         .serdes         = 0x2000,
2797         .pcs            = 0x2200,
2798         .pcs_misc       = 0x2400,
2799         .tx             = 0x0,
2800         .rx             = 0x0200,
2801         .tx2            = 0x3800,
2802         .rx2            = 0x3a00,
2803 };
2804
2805 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {
2806         .serdes         = 0x1000,
2807         .pcs            = 0x1200,
2808         .pcs_misc       = 0x1400,
2809         .tx             = 0x0000,
2810         .rx             = 0x0200,
2811         .tx2            = 0x0800,
2812         .rx2            = 0x0a00,
2813         .ln_shrd        = 0x0e00,
2814 };
2815
2816 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
2817         .lanes                  = 1,
2818
2819         .offsets                = &qmp_pcie_offsets_v2,
2820
2821         .tbls = {
2822                 .serdes         = ipq8074_pcie_serdes_tbl,
2823                 .serdes_num     = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
2824                 .tx             = ipq8074_pcie_tx_tbl,
2825                 .tx_num         = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
2826                 .rx             = ipq8074_pcie_rx_tbl,
2827                 .rx_num         = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
2828                 .pcs            = ipq8074_pcie_pcs_tbl,
2829                 .pcs_num        = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
2830         },
2831         .reset_list             = ipq8074_pciephy_reset_l,
2832         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2833         .vreg_list              = NULL,
2834         .num_vregs              = 0,
2835         .regs                   = pciephy_v2_regs_layout,
2836
2837         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2838         .phy_status             = PHYSTATUS,
2839 };
2840
2841 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
2842         .lanes                  = 1,
2843
2844         .offsets                = &qmp_pcie_offsets_v4x1,
2845
2846         .tbls = {
2847                 .serdes         = ipq8074_pcie_gen3_serdes_tbl,
2848                 .serdes_num     = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
2849                 .tx             = ipq8074_pcie_gen3_tx_tbl,
2850                 .tx_num         = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
2851                 .rx             = ipq8074_pcie_gen3_rx_tbl,
2852                 .rx_num         = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),
2853                 .pcs            = ipq8074_pcie_gen3_pcs_tbl,
2854                 .pcs_num        = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),
2855                 .pcs_misc       = ipq8074_pcie_gen3_pcs_misc_tbl,
2856                 .pcs_misc_num   = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl),
2857         },
2858         .reset_list             = ipq8074_pciephy_reset_l,
2859         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2860         .vreg_list              = NULL,
2861         .num_vregs              = 0,
2862         .regs                   = pciephy_v4_regs_layout,
2863
2864         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2865         .phy_status             = PHYSTATUS,
2866
2867         .pipe_clock_rate        = 250000000,
2868 };
2869
2870 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
2871         .lanes                  = 1,
2872
2873         .offsets                = &qmp_pcie_offsets_v4x1,
2874
2875         .tbls = {
2876                 .serdes         = ipq6018_pcie_serdes_tbl,
2877                 .serdes_num     = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
2878                 .tx             = ipq6018_pcie_tx_tbl,
2879                 .tx_num         = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
2880                 .rx             = ipq6018_pcie_rx_tbl,
2881                 .rx_num         = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
2882                 .pcs            = ipq6018_pcie_pcs_tbl,
2883                 .pcs_num        = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
2884                 .pcs_misc       = ipq6018_pcie_pcs_misc_tbl,
2885                 .pcs_misc_num   = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),
2886         },
2887         .reset_list             = ipq8074_pciephy_reset_l,
2888         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2889         .vreg_list              = NULL,
2890         .num_vregs              = 0,
2891         .regs                   = pciephy_v4_regs_layout,
2892
2893         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2894         .phy_status             = PHYSTATUS,
2895 };
2896
2897 static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg = {
2898         .lanes                  = 1,
2899
2900         .offsets                = &qmp_pcie_offsets_v4x1,
2901
2902         .tbls = {
2903                 .serdes         = ipq9574_gen3x1_pcie_serdes_tbl,
2904                 .serdes_num     = ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl),
2905                 .tx             = ipq8074_pcie_gen3_tx_tbl,
2906                 .tx_num         = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
2907                 .rx             = ipq9574_pcie_rx_tbl,
2908                 .rx_num         = ARRAY_SIZE(ipq9574_pcie_rx_tbl),
2909                 .pcs            = ipq9574_gen3x1_pcie_pcs_tbl,
2910                 .pcs_num        = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl),
2911                 .pcs_misc       = ipq9574_gen3x1_pcie_pcs_misc_tbl,
2912                 .pcs_misc_num   = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl),
2913         },
2914         .reset_list             = ipq8074_pciephy_reset_l,
2915         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2916         .vreg_list              = NULL,
2917         .num_vregs              = 0,
2918         .regs                   = pciephy_v4_regs_layout,
2919
2920         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2921         .phy_status             = PHYSTATUS,
2922         .pipe_clock_rate        = 250000000,
2923 };
2924
2925 static const struct qmp_phy_cfg ipq9574_gen3x2_pciephy_cfg = {
2926         .lanes                  = 2,
2927
2928         .offsets                = &qmp_pcie_offsets_ipq9574,
2929
2930         .tbls = {
2931                 .serdes         = ipq9574_gen3x2_pcie_serdes_tbl,
2932                 .serdes_num     = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl),
2933                 .tx             = ipq8074_pcie_gen3_tx_tbl,
2934                 .tx_num         = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
2935                 .rx             = ipq9574_pcie_rx_tbl,
2936                 .rx_num         = ARRAY_SIZE(ipq9574_pcie_rx_tbl),
2937                 .pcs            = ipq9574_gen3x2_pcie_pcs_tbl,
2938                 .pcs_num        = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_tbl),
2939                 .pcs_misc       = ipq9574_gen3x2_pcie_pcs_misc_tbl,
2940                 .pcs_misc_num   = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl),
2941         },
2942         .reset_list             = ipq8074_pciephy_reset_l,
2943         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2944         .vreg_list              = NULL,
2945         .num_vregs              = 0,
2946         .regs                   = pciephy_v5_regs_layout,
2947
2948         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2949         .phy_status             = PHYSTATUS,
2950         .pipe_clock_rate        = 250000000,
2951 };
2952
2953 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
2954         .lanes                  = 1,
2955
2956         .offsets                = &qmp_pcie_offsets_v3,
2957
2958         .tbls = {
2959                 .serdes         = sdm845_qmp_pcie_serdes_tbl,
2960                 .serdes_num     = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
2961                 .tx             = sdm845_qmp_pcie_tx_tbl,
2962                 .tx_num         = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
2963                 .rx             = sdm845_qmp_pcie_rx_tbl,
2964                 .rx_num         = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
2965                 .pcs            = sdm845_qmp_pcie_pcs_tbl,
2966                 .pcs_num        = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
2967                 .pcs_misc       = sdm845_qmp_pcie_pcs_misc_tbl,
2968                 .pcs_misc_num   = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
2969         },
2970         .reset_list             = sdm845_pciephy_reset_l,
2971         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2972         .vreg_list              = qmp_phy_vreg_l,
2973         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2974         .regs                   = pciephy_v3_regs_layout,
2975
2976         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2977         .phy_status             = PHYSTATUS,
2978 };
2979
2980 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
2981         .lanes                  = 1,
2982
2983         .offsets                = &qmp_pcie_offsets_qhp,
2984
2985         .tbls = {
2986                 .serdes         = sdm845_qhp_pcie_serdes_tbl,
2987                 .serdes_num     = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
2988                 .tx             = sdm845_qhp_pcie_tx_tbl,
2989                 .tx_num         = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
2990                 .pcs            = sdm845_qhp_pcie_pcs_tbl,
2991                 .pcs_num        = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
2992         },
2993         .reset_list             = sdm845_pciephy_reset_l,
2994         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2995         .vreg_list              = qmp_phy_vreg_l,
2996         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2997         .regs                   = sdm845_qhp_pciephy_regs_layout,
2998
2999         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3000         .phy_status             = PHYSTATUS,
3001 };
3002
3003 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
3004         .lanes                  = 1,
3005
3006         .offsets                = &qmp_pcie_offsets_v4x1,
3007
3008         .tbls = {
3009                 .serdes         = sm8250_qmp_pcie_serdes_tbl,
3010                 .serdes_num     = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3011                 .tx             = sm8250_qmp_pcie_tx_tbl,
3012                 .tx_num         = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3013                 .rx             = sm8250_qmp_pcie_rx_tbl,
3014                 .rx_num         = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3015                 .pcs            = sm8250_qmp_pcie_pcs_tbl,
3016                 .pcs_num        = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3017                 .pcs_misc       = sm8250_qmp_pcie_pcs_misc_tbl,
3018                 .pcs_misc_num   = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3019         },
3020         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3021                 .serdes         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
3022                 .serdes_num     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
3023                 .rx             = sm8250_qmp_gen3x1_pcie_rx_tbl,
3024                 .rx_num         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
3025                 .pcs            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
3026                 .pcs_num        = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
3027                 .pcs_misc       = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
3028                 .pcs_misc_num   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
3029         },
3030         .reset_list             = sdm845_pciephy_reset_l,
3031         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3032         .vreg_list              = qmp_phy_vreg_l,
3033         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3034         .regs                   = pciephy_v4_regs_layout,
3035
3036         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3037         .phy_status             = PHYSTATUS,
3038 };
3039
3040 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
3041         .lanes                  = 2,
3042
3043         .offsets                = &qmp_pcie_offsets_v4x2,
3044
3045         .tbls = {
3046                 .serdes         = sm8250_qmp_pcie_serdes_tbl,
3047                 .serdes_num     = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3048                 .tx             = sm8250_qmp_pcie_tx_tbl,
3049                 .tx_num         = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3050                 .rx             = sm8250_qmp_pcie_rx_tbl,
3051                 .rx_num         = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3052                 .pcs            = sm8250_qmp_pcie_pcs_tbl,
3053                 .pcs_num        = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3054                 .pcs_misc       = sm8250_qmp_pcie_pcs_misc_tbl,
3055                 .pcs_misc_num   = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3056         },
3057         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3058                 .tx             = sm8250_qmp_gen3x2_pcie_tx_tbl,
3059                 .tx_num         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
3060                 .rx             = sm8250_qmp_gen3x2_pcie_rx_tbl,
3061                 .rx_num         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
3062                 .pcs            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
3063                 .pcs_num        = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
3064                 .pcs_misc       = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
3065                 .pcs_misc_num   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
3066         },
3067         .reset_list             = sdm845_pciephy_reset_l,
3068         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3069         .vreg_list              = qmp_phy_vreg_l,
3070         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3071         .regs                   = pciephy_v4_regs_layout,
3072
3073         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3074         .phy_status             = PHYSTATUS,
3075 };
3076
3077 static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
3078         .lanes                  = 1,
3079
3080         .offsets                = &qmp_pcie_offsets_v3,
3081
3082         .tbls = {
3083                 .serdes         = msm8998_pcie_serdes_tbl,
3084                 .serdes_num     = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
3085                 .tx             = msm8998_pcie_tx_tbl,
3086                 .tx_num         = ARRAY_SIZE(msm8998_pcie_tx_tbl),
3087                 .rx             = msm8998_pcie_rx_tbl,
3088                 .rx_num         = ARRAY_SIZE(msm8998_pcie_rx_tbl),
3089                 .pcs            = msm8998_pcie_pcs_tbl,
3090                 .pcs_num        = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
3091         },
3092         .reset_list             = ipq8074_pciephy_reset_l,
3093         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3094         .vreg_list              = qmp_phy_vreg_l,
3095         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3096         .regs                   = pciephy_v3_regs_layout,
3097
3098         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3099         .phy_status             = PHYSTATUS,
3100
3101         .skip_start_delay       = true,
3102 };
3103
3104 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
3105         .lanes                  = 2,
3106
3107         .offsets                = &qmp_pcie_offsets_v4x2,
3108
3109         .tbls = {
3110                 .serdes         = sc8180x_qmp_pcie_serdes_tbl,
3111                 .serdes_num     = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
3112                 .tx             = sc8180x_qmp_pcie_tx_tbl,
3113                 .tx_num         = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
3114                 .rx             = sc8180x_qmp_pcie_rx_tbl,
3115                 .rx_num         = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
3116                 .pcs            = sc8180x_qmp_pcie_pcs_tbl,
3117                 .pcs_num        = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
3118                 .pcs_misc       = sc8180x_qmp_pcie_pcs_misc_tbl,
3119                 .pcs_misc_num   = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
3120         },
3121         .reset_list             = sdm845_pciephy_reset_l,
3122         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3123         .vreg_list              = qmp_phy_vreg_l,
3124         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3125         .regs                   = pciephy_v4_regs_layout,
3126
3127         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3128         .phy_status             = PHYSTATUS,
3129 };
3130
3131 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = {
3132         .lanes                  = 1,
3133
3134         .offsets                = &qmp_pcie_offsets_v5,
3135
3136         .tbls = {
3137                 .serdes         = sc8280xp_qmp_pcie_serdes_tbl,
3138                 .serdes_num     = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
3139                 .tx             = sc8280xp_qmp_gen3x1_pcie_tx_tbl,
3140                 .tx_num         = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl),
3141                 .rx             = sc8280xp_qmp_gen3x1_pcie_rx_tbl,
3142                 .rx_num         = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl),
3143                 .pcs            = sc8280xp_qmp_gen3x1_pcie_pcs_tbl,
3144                 .pcs_num        = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl),
3145                 .pcs_misc       = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl,
3146                 .pcs_misc_num   = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl),
3147         },
3148
3149         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3150                 .serdes         = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl,
3151                 .serdes_num     = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl),
3152         },
3153
3154         .reset_list             = sdm845_pciephy_reset_l,
3155         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3156         .vreg_list              = qmp_phy_vreg_l,
3157         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3158         .regs                   = pciephy_v5_regs_layout,
3159
3160         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3161         .phy_status             = PHYSTATUS,
3162 };
3163
3164 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = {
3165         .lanes                  = 2,
3166
3167         .offsets                = &qmp_pcie_offsets_v5,
3168
3169         .tbls = {
3170                 .serdes         = sc8280xp_qmp_pcie_serdes_tbl,
3171                 .serdes_num     = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
3172                 .tx             = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
3173                 .tx_num         = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),
3174                 .rx             = sc8280xp_qmp_gen3x2_pcie_rx_tbl,
3175                 .rx_num         = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),
3176                 .pcs            = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
3177                 .pcs_num        = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),
3178                 .pcs_misc       = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
3179                 .pcs_misc_num   = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
3180         },
3181
3182         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3183                 .serdes         = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,
3184                 .serdes_num     = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
3185         },
3186
3187         .reset_list             = sdm845_pciephy_reset_l,
3188         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3189         .vreg_list              = qmp_phy_vreg_l,
3190         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3191         .regs                   = pciephy_v5_regs_layout,
3192
3193         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3194         .phy_status             = PHYSTATUS,
3195 };
3196
3197 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = {
3198         .lanes                  = 4,
3199
3200         .offsets                = &qmp_pcie_offsets_v5,
3201
3202         .tbls = {
3203                 .serdes         = sc8280xp_qmp_pcie_serdes_tbl,
3204                 .serdes_num     = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
3205                 .tx             = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
3206                 .tx_num         = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),
3207                 .rx             = sc8280xp_qmp_gen3x2_pcie_rx_tbl,
3208                 .rx_num         = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),
3209                 .pcs            = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
3210                 .pcs_num        = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),
3211                 .pcs_misc       = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
3212                 .pcs_misc_num   = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
3213         },
3214
3215         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3216                 .serdes         = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,
3217                 .serdes_num     = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
3218         },
3219
3220         .serdes_4ln_tbl         = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl,
3221         .serdes_4ln_num         = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl),
3222
3223         .reset_list             = sdm845_pciephy_reset_l,
3224         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3225         .vreg_list              = qmp_phy_vreg_l,
3226         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3227         .regs                   = pciephy_v5_regs_layout,
3228
3229         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3230         .phy_status             = PHYSTATUS,
3231 };
3232
3233 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
3234         .lanes                  = 2,
3235
3236         .offsets                = &qmp_pcie_offsets_v4_20,
3237
3238         .tbls = {
3239                 .serdes         = sdx55_qmp_pcie_serdes_tbl,
3240                 .serdes_num     = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
3241                 .tx             = sdx55_qmp_pcie_tx_tbl,
3242                 .tx_num         = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
3243                 .rx             = sdx55_qmp_pcie_rx_tbl,
3244                 .rx_num         = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
3245                 .pcs            = sdx55_qmp_pcie_pcs_tbl,
3246                 .pcs_num        = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
3247                 .pcs_misc       = sdx55_qmp_pcie_pcs_misc_tbl,
3248                 .pcs_misc_num   = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
3249         },
3250
3251         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3252                 .serdes         = sdx55_qmp_pcie_rc_serdes_tbl,
3253                 .serdes_num     = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl),
3254                 .pcs_misc       = sdx55_qmp_pcie_rc_pcs_misc_tbl,
3255                 .pcs_misc_num   = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl),
3256         },
3257
3258         .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
3259                 .serdes         = sdx55_qmp_pcie_ep_serdes_tbl,
3260                 .serdes_num     = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl),
3261                 .pcs_misc       = sdx55_qmp_pcie_ep_pcs_misc_tbl,
3262                 .pcs_misc_num   = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl),
3263         },
3264
3265         .reset_list             = sdm845_pciephy_reset_l,
3266         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3267         .vreg_list              = qmp_phy_vreg_l,
3268         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3269         .regs                   = pciephy_v4_regs_layout,
3270
3271         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3272         .phy_status             = PHYSTATUS_4_20,
3273 };
3274
3275 static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {
3276         .lanes                  = 1,
3277
3278         .offsets                = &qmp_pcie_offsets_v5,
3279
3280         .tbls = {
3281                 .serdes         = sm8450_qmp_gen3_pcie_serdes_tbl,
3282                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
3283                 .tx             = sm8350_qmp_gen3x1_pcie_tx_tbl,
3284                 .tx_num         = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl),
3285                 .rx             = sm8450_qmp_gen3_pcie_rx_tbl,
3286                 .rx_num         = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
3287                 .pcs            = sm8450_qmp_gen3_pcie_pcs_tbl,
3288                 .pcs_num        = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
3289                 .pcs_misc       = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
3290                 .pcs_misc_num   = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
3291         },
3292
3293         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3294                 .serdes         = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
3295                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
3296                 .rx             = sm8350_qmp_gen3x1_pcie_rc_rx_tbl,
3297                 .rx_num         = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl),
3298         },
3299
3300         .reset_list             = sdm845_pciephy_reset_l,
3301         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3302         .vreg_list              = qmp_phy_vreg_l,
3303         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3304         .regs                   = pciephy_v5_regs_layout,
3305
3306         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3307         .phy_status             = PHYSTATUS,
3308 };
3309
3310 static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {
3311         .lanes                  = 2,
3312
3313         .offsets                = &qmp_pcie_offsets_v5,
3314
3315         .tbls = {
3316                 .serdes         = sm8450_qmp_gen3_pcie_serdes_tbl,
3317                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
3318                 .tx             = sm8350_qmp_gen3x2_pcie_tx_tbl,
3319                 .tx_num         = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl),
3320                 .rx             = sm8450_qmp_gen3_pcie_rx_tbl,
3321                 .rx_num         = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
3322                 .pcs            = sm8450_qmp_gen3_pcie_pcs_tbl,
3323                 .pcs_num        = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
3324                 .pcs_misc       = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
3325                 .pcs_misc_num   = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
3326         },
3327
3328         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3329                 .rx             = sm8350_qmp_gen3x2_pcie_rc_rx_tbl,
3330                 .rx_num         = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl),
3331                 .pcs            = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,
3332                 .pcs_num        = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl),
3333         },
3334
3335         .reset_list             = sdm845_pciephy_reset_l,
3336         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3337         .vreg_list              = qmp_phy_vreg_l,
3338         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3339         .regs                   = pciephy_v5_regs_layout,
3340
3341         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3342         .phy_status             = PHYSTATUS,
3343 };
3344
3345 static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = {
3346         .lanes                  = 2,
3347
3348         .offsets                = &qmp_pcie_offsets_v6_20,
3349
3350         .tbls = {
3351                         .serdes         = sdx65_qmp_pcie_serdes_tbl,
3352                         .serdes_num     = ARRAY_SIZE(sdx65_qmp_pcie_serdes_tbl),
3353                         .tx             = sdx65_qmp_pcie_tx_tbl,
3354                         .tx_num         = ARRAY_SIZE(sdx65_qmp_pcie_tx_tbl),
3355                         .rx             = sdx65_qmp_pcie_rx_tbl,
3356                         .rx_num         = ARRAY_SIZE(sdx65_qmp_pcie_rx_tbl),
3357                         .pcs            = sdx65_qmp_pcie_pcs_tbl,
3358                         .pcs_num        = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl),
3359                         .pcs_misc       = sdx65_qmp_pcie_pcs_misc_tbl,
3360                         .pcs_misc_num   = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl),
3361                 },
3362         .reset_list             = sdm845_pciephy_reset_l,
3363         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3364         .vreg_list              = qmp_phy_vreg_l,
3365         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3366         .regs                   = pciephy_v6_regs_layout,
3367
3368         .pwrdn_ctrl             = SW_PWRDN,
3369         .phy_status             = PHYSTATUS_4_20,
3370 };
3371
3372 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
3373         .lanes                  = 1,
3374
3375         .offsets                = &qmp_pcie_offsets_v5,
3376
3377         .tbls = {
3378                 .serdes         = sm8450_qmp_gen3_pcie_serdes_tbl,
3379                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
3380                 .tx             = sm8450_qmp_gen3x1_pcie_tx_tbl,
3381                 .tx_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
3382                 .rx             = sm8450_qmp_gen3_pcie_rx_tbl,
3383                 .rx_num         = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
3384                 .pcs            = sm8450_qmp_gen3_pcie_pcs_tbl,
3385                 .pcs_num        = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
3386                 .pcs_misc       = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
3387                 .pcs_misc_num   = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
3388         },
3389
3390         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3391                 .serdes         = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
3392                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
3393                 .rx             = sm8450_qmp_gen3x1_pcie_rc_rx_tbl,
3394                 .rx_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl),
3395         },
3396
3397         .reset_list             = sdm845_pciephy_reset_l,
3398         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3399         .vreg_list              = qmp_phy_vreg_l,
3400         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3401         .regs                   = pciephy_v5_regs_layout,
3402
3403         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3404         .phy_status             = PHYSTATUS,
3405 };
3406
3407 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
3408         .lanes                  = 2,
3409
3410         .offsets                = &qmp_pcie_offsets_v5_20,
3411
3412         .tbls = {
3413                 .serdes         = sm8450_qmp_gen4x2_pcie_serdes_tbl,
3414                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
3415                 .tx             = sm8450_qmp_gen4x2_pcie_tx_tbl,
3416                 .tx_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
3417                 .rx             = sm8450_qmp_gen4x2_pcie_rx_tbl,
3418                 .rx_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
3419                 .pcs            = sm8450_qmp_gen4x2_pcie_pcs_tbl,
3420                 .pcs_num        = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
3421                 .pcs_misc       = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
3422                 .pcs_misc_num   = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
3423         },
3424
3425         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3426                 .serdes         = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl,
3427                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl),
3428                 .pcs_misc       = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl,
3429                 .pcs_misc_num   = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl),
3430         },
3431
3432         .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
3433                 .serdes         = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl,
3434                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl),
3435                 .pcs_misc       = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
3436                 .pcs_misc_num   = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
3437         },
3438
3439         .reset_list             = sdm845_pciephy_reset_l,
3440         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3441         .vreg_list              = qmp_phy_vreg_l,
3442         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3443         .regs                   = pciephy_v5_regs_layout,
3444
3445         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3446         .phy_status             = PHYSTATUS_4_20,
3447
3448         /* 20MHz PHY AUX Clock */
3449         .aux_clock_rate         = 20000000,
3450 };
3451
3452 static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = {
3453         .lanes = 2,
3454
3455         .offsets                = &qmp_pcie_offsets_v5,
3456
3457         .tbls = {
3458                 .serdes         = sm8550_qmp_gen3x2_pcie_serdes_tbl,
3459                 .serdes_num     = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl),
3460                 .tx             = sm8550_qmp_gen3x2_pcie_tx_tbl,
3461                 .tx_num         = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl),
3462                 .rx             = sm8550_qmp_gen3x2_pcie_rx_tbl,
3463                 .rx_num         = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl),
3464                 .pcs            = sm8550_qmp_gen3x2_pcie_pcs_tbl,
3465                 .pcs_num        = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl),
3466                 .pcs_misc       = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,
3467                 .pcs_misc_num   = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),
3468         },
3469         .reset_list             = sdm845_pciephy_reset_l,
3470         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3471         .vreg_list              = qmp_phy_vreg_l,
3472         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3473         .regs                   = pciephy_v5_regs_layout,
3474
3475         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3476         .phy_status             = PHYSTATUS,
3477 };
3478
3479 static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
3480         .lanes = 2,
3481
3482         .offsets                = &qmp_pcie_offsets_v6_20,
3483
3484         .tbls = {
3485                 .serdes                 = sm8550_qmp_gen4x2_pcie_serdes_tbl,
3486                 .serdes_num             = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),
3487                 .tx                     = sm8550_qmp_gen4x2_pcie_tx_tbl,
3488                 .tx_num                 = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),
3489                 .rx                     = sm8550_qmp_gen4x2_pcie_rx_tbl,
3490                 .rx_num                 = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl),
3491                 .pcs                    = sm8550_qmp_gen4x2_pcie_pcs_tbl,
3492                 .pcs_num                = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),
3493                 .pcs_misc               = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,
3494                 .pcs_misc_num           = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),
3495                 .ln_shrd                = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,
3496                 .ln_shrd_num            = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),
3497         },
3498         .reset_list             = sdm845_pciephy_reset_l,
3499         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3500         .vreg_list              = sm8550_qmp_phy_vreg_l,
3501         .num_vregs              = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
3502         .regs                   = pciephy_v6_regs_layout,
3503
3504         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3505         .phy_status             = PHYSTATUS_4_20,
3506         .has_nocsr_reset        = true,
3507
3508         /* 20MHz PHY AUX Clock */
3509         .aux_clock_rate         = 20000000,
3510 };
3511
3512 static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = {
3513         .lanes = 2,
3514
3515         .offsets                = &qmp_pcie_offsets_v6_20,
3516
3517         .tbls = {
3518                 .serdes                 = sm8550_qmp_gen4x2_pcie_serdes_tbl,
3519                 .serdes_num             = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),
3520                 .tx                     = sm8550_qmp_gen4x2_pcie_tx_tbl,
3521                 .tx_num                 = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),
3522                 .rx                     = sm8650_qmp_gen4x2_pcie_rx_tbl,
3523                 .rx_num                 = ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl),
3524                 .pcs                    = sm8550_qmp_gen4x2_pcie_pcs_tbl,
3525                 .pcs_num                = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),
3526                 .pcs_misc               = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,
3527                 .pcs_misc_num           = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),
3528                 .ln_shrd                = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,
3529                 .ln_shrd_num            = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),
3530         },
3531         .reset_list             = sdm845_pciephy_reset_l,
3532         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3533         .vreg_list              = sm8550_qmp_phy_vreg_l,
3534         .num_vregs              = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
3535         .regs                   = pciephy_v6_regs_layout,
3536
3537         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3538         .phy_status             = PHYSTATUS_4_20,
3539         .has_nocsr_reset        = true,
3540
3541         /* 20MHz PHY AUX Clock */
3542         .aux_clock_rate         = 20000000,
3543 };
3544
3545 static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {
3546         .lanes                  = 2,
3547         .offsets                = &qmp_pcie_offsets_v5_20,
3548
3549         .tbls = {
3550                 .serdes         = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl,
3551                 .serdes_num             = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl),
3552                 .tx             = sa8775p_qmp_gen4_pcie_tx_tbl,
3553                 .tx_num         = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
3554                 .rx             = sa8775p_qmp_gen4x2_pcie_rx_alt_tbl,
3555                 .rx_num         = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rx_alt_tbl),
3556                 .pcs            = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl,
3557                 .pcs_num                = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl),
3558                 .pcs_misc               = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
3559                 .pcs_misc_num   = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
3560         },
3561
3562         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3563                 .serdes         = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl,
3564                 .serdes_num     = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl),
3565                 .pcs_misc       = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,
3566                 .pcs_misc_num   = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
3567         },
3568
3569         .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
3570                 .serdes         = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,
3571                 .serdes_num     = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),
3572                 .pcs_misc       = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
3573                 .pcs_misc_num   = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
3574                 .pcs            = sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl,
3575                 .pcs_num        = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl),
3576         },
3577
3578         .reset_list             = sdm845_pciephy_reset_l,
3579         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3580         .vreg_list              = qmp_phy_vreg_l,
3581         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3582         .regs                   = pciephy_v5_regs_layout,
3583
3584         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3585         .phy_status             = PHYSTATUS_4_20,
3586 };
3587
3588 static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = {
3589         .lanes = 4,
3590         .offsets                = &qmp_pcie_offsets_v5_30,
3591
3592         .tbls = {
3593                 .serdes         = sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl,
3594                 .serdes_num             = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl),
3595                 .tx             = sa8775p_qmp_gen4_pcie_tx_tbl,
3596                 .tx_num         = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
3597                 .rx                     = sa8775p_qmp_gen4x4_pcie_rx_alt_tbl,
3598                 .rx_num         = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rx_alt_tbl),
3599                 .pcs            = sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl,
3600                 .pcs_num                = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl),
3601                 .pcs_misc               = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
3602                 .pcs_misc_num   = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
3603         },
3604
3605         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3606                 .serdes         = sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl,
3607                 .serdes_num     = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl),
3608                 .pcs_misc       = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,
3609                 .pcs_misc_num   = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
3610         },
3611
3612         .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
3613                 .serdes         = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,
3614                 .serdes_num     = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),
3615                 .pcs_misc       = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
3616                 .pcs_misc_num   = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
3617         },
3618
3619         .reset_list             = sdm845_pciephy_reset_l,
3620         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3621         .vreg_list              = qmp_phy_vreg_l,
3622         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3623         .regs                   = pciephy_v5_regs_layout,
3624
3625         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3626         .phy_status             = PHYSTATUS_4_20,
3627 };
3628
3629 static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = {
3630         .lanes = 2,
3631
3632         .offsets                = &qmp_pcie_offsets_v6_20,
3633
3634         .tbls = {
3635                 .serdes                 = x1e80100_qmp_gen4x2_pcie_serdes_tbl,
3636                 .serdes_num             = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl),
3637                 .tx                     = x1e80100_qmp_gen4x2_pcie_tx_tbl,
3638                 .tx_num                 = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl),
3639                 .rx                     = x1e80100_qmp_gen4x2_pcie_rx_tbl,
3640                 .rx_num                 = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl),
3641                 .pcs                    = x1e80100_qmp_gen4x2_pcie_pcs_tbl,
3642                 .pcs_num                = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl),
3643                 .pcs_misc               = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl,
3644                 .pcs_misc_num           = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl),
3645                 .ln_shrd                = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl,
3646                 .ln_shrd_num            = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl),
3647         },
3648         .reset_list             = sdm845_pciephy_reset_l,
3649         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3650         .vreg_list              = sm8550_qmp_phy_vreg_l,
3651         .num_vregs              = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
3652         .regs                   = pciephy_v6_regs_layout,
3653
3654         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3655         .phy_status             = PHYSTATUS_4_20,
3656         .has_nocsr_reset        = true,
3657 };
3658
3659 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
3660 {
3661         const struct qmp_phy_cfg *cfg = qmp->cfg;
3662         const struct qmp_pcie_offsets *offs = cfg->offsets;
3663         void __iomem *tx3, *rx3, *tx4, *rx4;
3664
3665         tx3 = qmp->port_b + offs->tx;
3666         rx3 = qmp->port_b + offs->rx;
3667         tx4 = qmp->port_b + offs->tx2;
3668         rx4 = qmp->port_b + offs->rx2;
3669
3670         qmp_configure_lane(tx3, tbls->tx, tbls->tx_num, 1);
3671         qmp_configure_lane(rx3, tbls->rx, tbls->rx_num, 1);
3672
3673         qmp_configure_lane(tx4, tbls->tx, tbls->tx_num, 2);
3674         qmp_configure_lane(rx4, tbls->rx, tbls->rx_num, 2);
3675 }
3676
3677 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
3678 {
3679         const struct qmp_phy_cfg *cfg = qmp->cfg;
3680         void __iomem *serdes = qmp->serdes;
3681         void __iomem *tx = qmp->tx;
3682         void __iomem *rx = qmp->rx;
3683         void __iomem *tx2 = qmp->tx2;
3684         void __iomem *rx2 = qmp->rx2;
3685         void __iomem *pcs = qmp->pcs;
3686         void __iomem *pcs_misc = qmp->pcs_misc;
3687         void __iomem *ln_shrd = qmp->ln_shrd;
3688
3689         if (!tbls)
3690                 return;
3691
3692         qmp_configure(serdes, tbls->serdes, tbls->serdes_num);
3693
3694         qmp_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
3695         qmp_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
3696
3697         if (cfg->lanes >= 2) {
3698                 qmp_configure_lane(tx2, tbls->tx, tbls->tx_num, 2);
3699                 qmp_configure_lane(rx2, tbls->rx, tbls->rx_num, 2);
3700         }
3701
3702         qmp_configure(pcs, tbls->pcs, tbls->pcs_num);
3703         qmp_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
3704
3705         if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
3706                 qmp_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);
3707                 qmp_pcie_init_port_b(qmp, tbls);
3708         }
3709
3710         qmp_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);
3711 }
3712
3713 static int qmp_pcie_init(struct phy *phy)
3714 {
3715         struct qmp_pcie *qmp = phy_get_drvdata(phy);
3716         const struct qmp_phy_cfg *cfg = qmp->cfg;
3717         int ret;
3718
3719         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
3720         if (ret) {
3721                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
3722                 return ret;
3723         }
3724
3725         ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
3726         if (ret) {
3727                 dev_err(qmp->dev, "reset assert failed\n");
3728                 goto err_disable_regulators;
3729         }
3730
3731         ret = reset_control_assert(qmp->nocsr_reset);
3732         if (ret) {
3733                 dev_err(qmp->dev, "no-csr reset assert failed\n");
3734                 goto err_assert_reset;
3735         }
3736
3737         usleep_range(200, 300);
3738
3739         ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
3740         if (ret) {
3741                 dev_err(qmp->dev, "reset deassert failed\n");
3742                 goto err_assert_reset;
3743         }
3744
3745         ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
3746         if (ret)
3747                 goto err_assert_reset;
3748
3749         return 0;
3750
3751 err_assert_reset:
3752         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
3753 err_disable_regulators:
3754         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
3755
3756         return ret;
3757 }
3758
3759 static int qmp_pcie_exit(struct phy *phy)
3760 {
3761         struct qmp_pcie *qmp = phy_get_drvdata(phy);
3762         const struct qmp_phy_cfg *cfg = qmp->cfg;
3763
3764         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
3765
3766         clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
3767
3768         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
3769
3770         return 0;
3771 }
3772
3773 static int qmp_pcie_power_on(struct phy *phy)
3774 {
3775         struct qmp_pcie *qmp = phy_get_drvdata(phy);
3776         const struct qmp_phy_cfg *cfg = qmp->cfg;
3777         const struct qmp_phy_cfg_tbls *mode_tbls;
3778         void __iomem *pcs = qmp->pcs;
3779         void __iomem *status;
3780         unsigned int mask, val;
3781         int ret;
3782
3783         qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
3784                         cfg->pwrdn_ctrl);
3785
3786         if (qmp->mode == PHY_MODE_PCIE_RC)
3787                 mode_tbls = cfg->tbls_rc;
3788         else
3789                 mode_tbls = cfg->tbls_ep;
3790
3791         qmp_pcie_init_registers(qmp, &cfg->tbls);
3792         qmp_pcie_init_registers(qmp, mode_tbls);
3793
3794         ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);
3795         if (ret)
3796                 return ret;
3797
3798         ret = reset_control_deassert(qmp->nocsr_reset);
3799         if (ret) {
3800                 dev_err(qmp->dev, "no-csr reset deassert failed\n");
3801                 goto err_disable_pipe_clk;
3802         }
3803
3804         /* Pull PHY out of reset state */
3805         qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3806
3807         /* start SerDes and Phy-Coding-Sublayer */
3808         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
3809
3810         if (!cfg->skip_start_delay)
3811                 usleep_range(1000, 1200);
3812
3813         status = pcs + cfg->regs[QPHY_PCS_STATUS];
3814         mask = cfg->phy_status;
3815         ret = readl_poll_timeout(status, val, !(val & mask), 200,
3816                                  PHY_INIT_COMPLETE_TIMEOUT);
3817         if (ret) {
3818                 dev_err(qmp->dev, "phy initialization timed-out\n");
3819                 goto err_disable_pipe_clk;
3820         }
3821
3822         return 0;
3823
3824 err_disable_pipe_clk:
3825         clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
3826
3827         return ret;
3828 }
3829
3830 static int qmp_pcie_power_off(struct phy *phy)
3831 {
3832         struct qmp_pcie *qmp = phy_get_drvdata(phy);
3833         const struct qmp_phy_cfg *cfg = qmp->cfg;
3834
3835         clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
3836
3837         /* PHY reset */
3838         qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3839
3840         /* stop SerDes and Phy-Coding-Sublayer */
3841         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
3842                         SERDES_START | PCS_START);
3843
3844         /* Put PHY into POWER DOWN state: active low */
3845         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
3846                         cfg->pwrdn_ctrl);
3847
3848         return 0;
3849 }
3850
3851 static int qmp_pcie_enable(struct phy *phy)
3852 {
3853         int ret;
3854
3855         ret = qmp_pcie_init(phy);
3856         if (ret)
3857                 return ret;
3858
3859         ret = qmp_pcie_power_on(phy);
3860         if (ret)
3861                 qmp_pcie_exit(phy);
3862
3863         return ret;
3864 }
3865
3866 static int qmp_pcie_disable(struct phy *phy)
3867 {
3868         int ret;
3869
3870         ret = qmp_pcie_power_off(phy);
3871         if (ret)
3872                 return ret;
3873
3874         return qmp_pcie_exit(phy);
3875 }
3876
3877 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode)
3878 {
3879         struct qmp_pcie *qmp = phy_get_drvdata(phy);
3880
3881         switch (submode) {
3882         case PHY_MODE_PCIE_RC:
3883         case PHY_MODE_PCIE_EP:
3884                 qmp->mode = submode;
3885                 break;
3886         default:
3887                 dev_err(&phy->dev, "Unsupported submode %d\n", submode);
3888                 return -EINVAL;
3889         }
3890
3891         return 0;
3892 }
3893
3894 static const struct phy_ops qmp_pcie_phy_ops = {
3895         .power_on       = qmp_pcie_enable,
3896         .power_off      = qmp_pcie_disable,
3897         .set_mode       = qmp_pcie_set_mode,
3898         .owner          = THIS_MODULE,
3899 };
3900
3901 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp)
3902 {
3903         const struct qmp_phy_cfg *cfg = qmp->cfg;
3904         struct device *dev = qmp->dev;
3905         int num = cfg->num_vregs;
3906         int i;
3907
3908         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
3909         if (!qmp->vregs)
3910                 return -ENOMEM;
3911
3912         for (i = 0; i < num; i++)
3913                 qmp->vregs[i].supply = cfg->vreg_list[i];
3914
3915         return devm_regulator_bulk_get(dev, num, qmp->vregs);
3916 }
3917
3918 static int qmp_pcie_reset_init(struct qmp_pcie *qmp)
3919 {
3920         const struct qmp_phy_cfg *cfg = qmp->cfg;
3921         struct device *dev = qmp->dev;
3922         int i;
3923         int ret;
3924
3925         qmp->resets = devm_kcalloc(dev, cfg->num_resets,
3926                                    sizeof(*qmp->resets), GFP_KERNEL);
3927         if (!qmp->resets)
3928                 return -ENOMEM;
3929
3930         for (i = 0; i < cfg->num_resets; i++)
3931                 qmp->resets[i].id = cfg->reset_list[i];
3932
3933         ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
3934         if (ret)
3935                 return dev_err_probe(dev, ret, "failed to get resets\n");
3936
3937         if (cfg->has_nocsr_reset) {
3938                 qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr");
3939                 if (IS_ERR(qmp->nocsr_reset))
3940                         return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
3941                                                 "failed to get no-csr reset\n");
3942         }
3943
3944         return 0;
3945 }
3946
3947 static int qmp_pcie_clk_init(struct qmp_pcie *qmp)
3948 {
3949         struct device *dev = qmp->dev;
3950         int num = ARRAY_SIZE(qmp_pciephy_clk_l);
3951         int i;
3952
3953         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
3954         if (!qmp->clks)
3955                 return -ENOMEM;
3956
3957         for (i = 0; i < num; i++)
3958                 qmp->clks[i].id = qmp_pciephy_clk_l[i];
3959
3960         return devm_clk_bulk_get_optional(dev, num, qmp->clks);
3961 }
3962
3963 static void phy_clk_release_provider(void *res)
3964 {
3965         of_clk_del_provider(res);
3966 }
3967
3968 /*
3969  * Register a fixed rate pipe clock.
3970  *
3971  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
3972  * controls it. The <s>_pipe_clk coming out of the GCC is requested
3973  * by the PHY driver for its operations.
3974  * We register the <s>_pipe_clksrc here. The gcc driver takes care
3975  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
3976  * Below picture shows this relationship.
3977  *
3978  *         +---------------+
3979  *         |   PHY block   |<<---------------------------------------+
3980  *         |               |                                         |
3981  *         |   +-------+   |                   +-----+               |
3982  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
3983  *    clk  |   +-------+   |                   +-----+
3984  *         +---------------+
3985  */
3986 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np)
3987 {
3988         struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
3989         struct clk_init_data init = { };
3990         int ret;
3991
3992         ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name);
3993         if (ret) {
3994                 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
3995                 return ret;
3996         }
3997
3998         init.ops = &clk_fixed_rate_ops;
3999
4000         /*
4001          * Controllers using QMP PHY-s use 125MHz pipe clock interface
4002          * unless other frequency is specified in the PHY config.
4003          */
4004         if (qmp->cfg->pipe_clock_rate)
4005                 fixed->fixed_rate = qmp->cfg->pipe_clock_rate;
4006         else
4007                 fixed->fixed_rate = 125000000;
4008
4009         fixed->hw.init = &init;
4010
4011         return devm_clk_hw_register(qmp->dev, &fixed->hw);
4012 }
4013
4014 /*
4015  * Register a fixed rate PHY aux clock.
4016  *
4017  * The <s>_phy_aux_clksrc generated by PHY goes to the GCC that gate
4018  * controls it. The <s>_phy_aux_clk coming out of the GCC is requested
4019  * by the PHY driver for its operations.
4020  * We register the <s>_phy_aux_clksrc here. The gcc driver takes care
4021  * of assigning this <s>_phy_aux_clksrc as parent to <s>_phy_aux_clk.
4022  * Below picture shows this relationship.
4023  *
4024  *         +---------------+
4025  *         |   PHY block   |<<---------------------------------------------+
4026  *         |               |                                               |
4027  *         |   +-------+   |                      +-----+                  |
4028  *   I/P---^-->|  PLL  |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+
4029  *    clk  |   +-------+   |                      +-----+
4030  *         +---------------+
4031  */
4032 static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np)
4033 {
4034         struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed;
4035         struct clk_init_data init = { };
4036         char name[64];
4037
4038         snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev));
4039
4040         init.name = name;
4041         init.ops = &clk_fixed_rate_ops;
4042
4043         fixed->fixed_rate = qmp->cfg->aux_clock_rate;
4044         fixed->hw.init = &init;
4045
4046         return devm_clk_hw_register(qmp->dev, &fixed->hw);
4047 }
4048
4049 static struct clk_hw *qmp_pcie_clk_hw_get(struct of_phandle_args *clkspec, void *data)
4050 {
4051         struct qmp_pcie *qmp = data;
4052
4053         /* Support legacy bindings */
4054         if (!clkspec->args_count)
4055                 return &qmp->pipe_clk_fixed.hw;
4056
4057         switch (clkspec->args[0]) {
4058         case QMP_PCIE_PIPE_CLK:
4059                 return &qmp->pipe_clk_fixed.hw;
4060         case QMP_PCIE_PHY_AUX_CLK:
4061                 return &qmp->aux_clk_fixed.hw;
4062         }
4063
4064         return ERR_PTR(-EINVAL);
4065 }
4066
4067 static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np)
4068 {
4069         int ret;
4070
4071         ret = phy_pipe_clk_register(qmp, np);
4072         if (ret)
4073                 return ret;
4074
4075         if (qmp->cfg->aux_clock_rate) {
4076                 ret = phy_aux_clk_register(qmp, np);
4077                 if (ret)
4078                         return ret;
4079
4080                 ret = of_clk_add_hw_provider(np, qmp_pcie_clk_hw_get, qmp);
4081                 if (ret)
4082                         return ret;
4083         } else {
4084                 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw);
4085                 if (ret)
4086                         return ret;
4087         }
4088
4089         /*
4090          * Roll a devm action because the clock provider is the child node, but
4091          * the child node is not actually a device.
4092          */
4093         return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
4094 }
4095
4096 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np)
4097 {
4098         struct platform_device *pdev = to_platform_device(qmp->dev);
4099         const struct qmp_phy_cfg *cfg = qmp->cfg;
4100         struct device *dev = qmp->dev;
4101         struct clk *clk;
4102
4103         qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
4104         if (IS_ERR(qmp->serdes))
4105                 return PTR_ERR(qmp->serdes);
4106
4107         /*
4108          * Get memory resources for the PHY:
4109          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
4110          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
4111          * For single lane PHYs: pcs_misc (optional) -> 3.
4112          */
4113         qmp->tx = devm_of_iomap(dev, np, 0, NULL);
4114         if (IS_ERR(qmp->tx))
4115                 return PTR_ERR(qmp->tx);
4116
4117         if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy"))
4118                 qmp->rx = qmp->tx;
4119         else
4120                 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
4121         if (IS_ERR(qmp->rx))
4122                 return PTR_ERR(qmp->rx);
4123
4124         qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
4125         if (IS_ERR(qmp->pcs))
4126                 return PTR_ERR(qmp->pcs);
4127
4128         if (cfg->lanes >= 2) {
4129                 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
4130                 if (IS_ERR(qmp->tx2))
4131                         return PTR_ERR(qmp->tx2);
4132
4133                 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
4134                 if (IS_ERR(qmp->rx2))
4135                         return PTR_ERR(qmp->rx2);
4136
4137                 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
4138         } else {
4139                 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
4140         }
4141
4142         if (IS_ERR(qmp->pcs_misc) &&
4143             of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
4144                 qmp->pcs_misc = qmp->pcs + 0x400;
4145
4146         if (IS_ERR(qmp->pcs_misc)) {
4147                 if (cfg->tbls.pcs_misc ||
4148                     (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) ||
4149                     (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) {
4150                         return PTR_ERR(qmp->pcs_misc);
4151                 }
4152         }
4153
4154         clk = devm_get_clk_from_child(dev, np, NULL);
4155         if (IS_ERR(clk)) {
4156                 return dev_err_probe(dev, PTR_ERR(clk),
4157                                      "failed to get pipe clock\n");
4158         }
4159
4160         qmp->num_pipe_clks = 1;
4161         qmp->pipe_clks[0].id = "pipe";
4162         qmp->pipe_clks[0].clk = clk;
4163
4164         return 0;
4165 }
4166
4167 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp)
4168 {
4169         struct regmap *tcsr;
4170         unsigned int args[2];
4171         int ret;
4172
4173         tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node,
4174                                                     "qcom,4ln-config-sel",
4175                                                     ARRAY_SIZE(args), args);
4176         if (IS_ERR(tcsr)) {
4177                 ret = PTR_ERR(tcsr);
4178                 if (ret == -ENOENT)
4179                         return 0;
4180
4181                 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret);
4182                 return ret;
4183         }
4184
4185         ret = regmap_test_bits(tcsr, args[0], BIT(args[1]));
4186         if (ret < 0) {
4187                 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret);
4188                 return ret;
4189         }
4190
4191         qmp->tcsr_4ln_config = ret;
4192
4193         dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config);
4194
4195         return 0;
4196 }
4197
4198 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)
4199 {
4200         struct platform_device *pdev = to_platform_device(qmp->dev);
4201         const struct qmp_phy_cfg *cfg = qmp->cfg;
4202         const struct qmp_pcie_offsets *offs = cfg->offsets;
4203         struct device *dev = qmp->dev;
4204         void __iomem *base;
4205         int ret;
4206
4207         if (!offs)
4208                 return -EINVAL;
4209
4210         ret = qmp_pcie_get_4ln_config(qmp);
4211         if (ret)
4212                 return ret;
4213
4214         base = devm_platform_ioremap_resource(pdev, 0);
4215         if (IS_ERR(base))
4216                 return PTR_ERR(base);
4217
4218         qmp->serdes = base + offs->serdes;
4219         qmp->pcs = base + offs->pcs;
4220         qmp->pcs_misc = base + offs->pcs_misc;
4221         qmp->tx = base + offs->tx;
4222         qmp->rx = base + offs->rx;
4223
4224         if (cfg->lanes >= 2) {
4225                 qmp->tx2 = base + offs->tx2;
4226                 qmp->rx2 = base + offs->rx2;
4227         }
4228
4229         if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
4230                 qmp->port_b = devm_platform_ioremap_resource(pdev, 1);
4231                 if (IS_ERR(qmp->port_b))
4232                         return PTR_ERR(qmp->port_b);
4233         }
4234
4235         if (cfg->tbls.ln_shrd)
4236                 qmp->ln_shrd = base + offs->ln_shrd;
4237
4238         qmp->num_pipe_clks = 2;
4239         qmp->pipe_clks[0].id = "pipe";
4240         qmp->pipe_clks[1].id = "pipediv2";
4241
4242         ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);
4243         if (ret)
4244                 return ret;
4245
4246         ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);
4247         if (ret)
4248                 return ret;
4249
4250         return 0;
4251 }
4252
4253 static int qmp_pcie_probe(struct platform_device *pdev)
4254 {
4255         struct device *dev = &pdev->dev;
4256         struct phy_provider *phy_provider;
4257         struct device_node *np;
4258         struct qmp_pcie *qmp;
4259         int ret;
4260
4261         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
4262         if (!qmp)
4263                 return -ENOMEM;
4264
4265         qmp->dev = dev;
4266
4267         qmp->cfg = of_device_get_match_data(dev);
4268         if (!qmp->cfg)
4269                 return -EINVAL;
4270
4271         WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl);
4272         WARN_ON_ONCE(!qmp->cfg->phy_status);
4273
4274         ret = qmp_pcie_clk_init(qmp);
4275         if (ret)
4276                 return ret;
4277
4278         ret = qmp_pcie_reset_init(qmp);
4279         if (ret)
4280                 return ret;
4281
4282         ret = qmp_pcie_vreg_init(qmp);
4283         if (ret)
4284                 return ret;
4285
4286         /* Check for legacy binding with child node. */
4287         np = of_get_next_available_child(dev->of_node, NULL);
4288         if (np) {
4289                 ret = qmp_pcie_parse_dt_legacy(qmp, np);
4290         } else {
4291                 np = of_node_get(dev->of_node);
4292                 ret = qmp_pcie_parse_dt(qmp);
4293         }
4294         if (ret)
4295                 goto err_node_put;
4296
4297         ret = qmp_pcie_register_clocks(qmp, np);
4298         if (ret)
4299                 goto err_node_put;
4300
4301         qmp->mode = PHY_MODE_PCIE_RC;
4302
4303         qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops);
4304         if (IS_ERR(qmp->phy)) {
4305                 ret = PTR_ERR(qmp->phy);
4306                 dev_err(dev, "failed to create PHY: %d\n", ret);
4307                 goto err_node_put;
4308         }
4309
4310         phy_set_drvdata(qmp->phy, qmp);
4311
4312         of_node_put(np);
4313
4314         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
4315
4316         return PTR_ERR_OR_ZERO(phy_provider);
4317
4318 err_node_put:
4319         of_node_put(np);
4320         return ret;
4321 }
4322
4323 static const struct of_device_id qmp_pcie_of_match_table[] = {
4324         {
4325                 .compatible = "qcom,ipq6018-qmp-pcie-phy",
4326                 .data = &ipq6018_pciephy_cfg,
4327         }, {
4328                 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
4329                 .data = &ipq8074_pciephy_gen3_cfg,
4330         }, {
4331                 .compatible = "qcom,ipq8074-qmp-pcie-phy",
4332                 .data = &ipq8074_pciephy_cfg,
4333         }, {
4334                 .compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy",
4335                 .data = &ipq9574_gen3x1_pciephy_cfg,
4336         }, {
4337                 .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
4338                 .data = &ipq9574_gen3x2_pciephy_cfg,
4339         }, {
4340                 .compatible = "qcom,msm8998-qmp-pcie-phy",
4341                 .data = &msm8998_pciephy_cfg,
4342         }, {
4343                 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
4344                 .data = &sa8775p_qmp_gen4x2_pciephy_cfg,
4345         }, {
4346                 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",
4347                 .data = &sa8775p_qmp_gen4x4_pciephy_cfg,
4348         }, {
4349                 .compatible = "qcom,sc8180x-qmp-pcie-phy",
4350                 .data = &sc8180x_pciephy_cfg,
4351         }, {
4352                 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
4353                 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg,
4354         }, {
4355                 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
4356                 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg,
4357         }, {
4358                 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",
4359                 .data = &sc8280xp_qmp_gen3x4_pciephy_cfg,
4360         }, {
4361                 .compatible = "qcom,sdm845-qhp-pcie-phy",
4362                 .data = &sdm845_qhp_pciephy_cfg,
4363         }, {
4364                 .compatible = "qcom,sdm845-qmp-pcie-phy",
4365                 .data = &sdm845_qmp_pciephy_cfg,
4366         }, {
4367                 .compatible = "qcom,sdx55-qmp-pcie-phy",
4368                 .data = &sdx55_qmp_pciephy_cfg,
4369         }, {
4370                 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",
4371                 .data = &sdx65_qmp_pciephy_cfg,
4372         }, {
4373                 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
4374                 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
4375         }, {
4376                 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
4377                 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
4378         }, {
4379                 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
4380                 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
4381         }, {
4382                 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
4383                 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
4384         }, {
4385                 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
4386                 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
4387         }, {
4388                 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
4389                 .data = &sm8350_qmp_gen3x1_pciephy_cfg,
4390         }, {
4391                 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
4392                 .data = &sm8350_qmp_gen3x2_pciephy_cfg,
4393         }, {
4394                 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
4395                 .data = &sm8450_qmp_gen3x1_pciephy_cfg,
4396         }, {
4397                 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
4398                 .data = &sm8450_qmp_gen4x2_pciephy_cfg,
4399         }, {
4400                 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
4401                 .data = &sm8550_qmp_gen3x2_pciephy_cfg,
4402         }, {
4403                 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
4404                 .data = &sm8550_qmp_gen4x2_pciephy_cfg,
4405         }, {
4406                 .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy",
4407                 .data = &sm8550_qmp_gen3x2_pciephy_cfg,
4408         }, {
4409                 .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy",
4410                 .data = &sm8650_qmp_gen4x2_pciephy_cfg,
4411         }, {
4412                 .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy",
4413                 .data = &sm8550_qmp_gen3x2_pciephy_cfg,
4414         }, {
4415                 .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy",
4416                 .data = &x1e80100_qmp_gen4x2_pciephy_cfg,
4417         },
4418         { },
4419 };
4420 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table);
4421
4422 static struct platform_driver qmp_pcie_driver = {
4423         .probe          = qmp_pcie_probe,
4424         .driver = {
4425                 .name   = "qcom-qmp-pcie-phy",
4426                 .of_match_table = qmp_pcie_of_match_table,
4427         },
4428 };
4429
4430 module_platform_driver(qmp_pcie_driver);
4431
4432 MODULE_AUTHOR("Vivek Gautam <[email protected]>");
4433 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver");
4434 MODULE_LICENSE("GPL v2");