drivers/net/phy/realtek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* drivers/net/phy/realtek.c
   3  *
   4  * Driver for Realtek PHYs
   5  *
   6  * Author: Johnson Leung <[email protected]>
   7  *
   8  * Copyright (c) 2004 Freescale Semiconductor, Inc.
   9  */
  10 #include <linux/bitops.h>
  11 #include <linux/of.h>
  12 #include <linux/phy.h>
  13 #include <linux/module.h>
  14 #include <linux/delay.h>
  15 #include <linux/clk.h>
  16
  17 #define RTL821x_PHYSR                           0x11
  18 #define RTL821x_PHYSR_DUPLEX                    BIT(13)
  19 #define RTL821x_PHYSR_SPEED                     GENMASK(15, 14)
  20
  21 #define RTL821x_INER                            0x12
  22 #define RTL8211B_INER_INIT                      0x6400
  23 #define RTL8211E_INER_LINK_STATUS               BIT(10)
  24 #define RTL8211F_INER_LINK_STATUS               BIT(4)
  25
  26 #define RTL821x_INSR                            0x13
  27
  28 #define RTL821x_EXT_PAGE_SELECT                 0x1e
  29 #define RTL821x_PAGE_SELECT                     0x1f
  30
  31 #define RTL8211F_PHYCR1                         0x18
  32 #define RTL8211F_PHYCR2                         0x19
  33 #define RTL8211F_INSR                           0x1d
  34
  35 #define RTL8211F_LEDCR                          0x10
  36 #define RTL8211F_LEDCR_MODE                     BIT(15)
  37 #define RTL8211F_LEDCR_ACT_TXRX                 BIT(4)
  38 #define RTL8211F_LEDCR_LINK_1000                BIT(3)
  39 #define RTL8211F_LEDCR_LINK_100                 BIT(1)
  40 #define RTL8211F_LEDCR_LINK_10                  BIT(0)
  41 #define RTL8211F_LEDCR_MASK                     GENMASK(4, 0)
  42 #define RTL8211F_LEDCR_SHIFT                    5
  43
  44 #define RTL8211F_TX_DELAY                       BIT(8)
  45 #define RTL8211F_RX_DELAY                       BIT(3)
  46
  47 #define RTL8211F_ALDPS_PLL_OFF                  BIT(1)
  48 #define RTL8211F_ALDPS_ENABLE                   BIT(2)
  49 #define RTL8211F_ALDPS_XTAL_OFF                 BIT(12)
  50
  51 #define RTL8211E_CTRL_DELAY                     BIT(13)
  52 #define RTL8211E_TX_DELAY                       BIT(12)
  53 #define RTL8211E_RX_DELAY                       BIT(11)
  54
  55 #define RTL8211F_CLKOUT_EN                      BIT(0)
  56
  57 #define RTL8201F_ISR                            0x1e
  58 #define RTL8201F_ISR_ANERR                      BIT(15)
  59 #define RTL8201F_ISR_DUPLEX                     BIT(13)
  60 #define RTL8201F_ISR_LINK                       BIT(11)
  61 #define RTL8201F_ISR_MASK                       (RTL8201F_ISR_ANERR | \
  62                                                  RTL8201F_ISR_DUPLEX | \
  63                                                  RTL8201F_ISR_LINK)
  64 #define RTL8201F_IER                            0x13
  65
  66 #define RTL822X_VND1_SERDES_OPTION                      0x697a
  67 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK            GENMASK(5, 0)
  68 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII         0
  69 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX               2
  70
  71 #define RTL822X_VND1_SERDES_CTRL3                       0x7580
  72 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK             GENMASK(5, 0)
  73 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII                    0x02
  74 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX                0x16
  75
  76 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
  77  * is set, they cannot be accessed by C45-over-C22.
  78  */
  79 #define RTL822X_VND2_GBCR                               0xa412
  80
  81 #define RTL822X_VND2_GANLPAR                            0xa414
  82
  83 #define RTL822X_VND2_PHYSR                              0xa434
  84
  85 #define RTL8366RB_POWER_SAVE                    0x15
  86 #define RTL8366RB_POWER_SAVE_ON                 BIT(12)
  87
  88 #define RTL9000A_GINMR                          0x14
  89 #define RTL9000A_GINMR_LINK_STATUS              BIT(4)
  90
  91 #define RTLGEN_SPEED_MASK                       0x0630
  92
  93 #define RTL_GENERIC_PHYID                       0x001cc800
  94 #define RTL_8211FVD_PHYID                       0x001cc878
  95 #define RTL_8221B_VB_CG                         0x001cc849
  96 #define RTL_8221B_VN_CG                         0x001cc84a
  97 #define RTL_8251B                               0x001cc862
  98
  99 #define RTL8211F_LED_COUNT                      3
 100
 101 MODULE_DESCRIPTION("Realtek PHY driver");
 102 MODULE_AUTHOR("Johnson Leung");
 103 MODULE_LICENSE("GPL");
 104
 105 struct rtl821x_priv {
 106         u16 phycr1;
 107         u16 phycr2;
 108         bool has_phycr2;
 109         struct clk *clk;
 110 };
 111
 112 static int rtl821x_read_page(struct phy_device *phydev)
 113 {
 114         return __phy_read(phydev, RTL821x_PAGE_SELECT);
 115 }
 116
 117 static int rtl821x_write_page(struct phy_device *phydev, int page)
 118 {
 119         return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
 120 }
 121
 122 static int rtl821x_probe(struct phy_device *phydev)
 123 {
 124         struct device *dev = &phydev->mdio.dev;
 125         struct rtl821x_priv *priv;
 126         u32 phy_id = phydev->drv->phy_id;
 127         int ret;
 128
 129         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 130         if (!priv)
 131                 return -ENOMEM;
 132
 133         priv->clk = devm_clk_get_optional_enabled(dev, NULL);
 134         if (IS_ERR(priv->clk))
 135                 return dev_err_probe(dev, PTR_ERR(priv->clk),
 136                                      "failed to get phy clock\n");
 137
 138         ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
 139         if (ret < 0)
 140                 return ret;
 141
 142         priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
 143         if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
 144                 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
 145
 146         priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
 147         if (priv->has_phycr2) {
 148                 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
 149                 if (ret < 0)
 150                         return ret;
 151
 152                 priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
 153                 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
 154                         priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
 155         }
 156
 157         phydev->priv = priv;
 158
 159         return 0;
 160 }
 161
 162 static int rtl8201_ack_interrupt(struct phy_device *phydev)
 163 {
 164         int err;
 165
 166         err = phy_read(phydev, RTL8201F_ISR);
 167
 168         return (err < 0) ? err : 0;
 169 }
 170
 171 static int rtl821x_ack_interrupt(struct phy_device *phydev)
 172 {
 173         int err;
 174
 175         err = phy_read(phydev, RTL821x_INSR);
 176
 177         return (err < 0) ? err : 0;
 178 }
 179
 180 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
 181 {
 182         int err;
 183
 184         err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
 185
 186         return (err < 0) ? err : 0;
 187 }
 188
 189 static int rtl8201_config_intr(struct phy_device *phydev)
 190 {
 191         u16 val;
 192         int err;
 193
 194         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 195                 err = rtl8201_ack_interrupt(phydev);
 196                 if (err)
 197                         return err;
 198
 199                 val = BIT(13) | BIT(12) | BIT(11);
 200                 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
 201         } else {
 202                 val = 0;
 203                 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
 204                 if (err)
 205                         return err;
 206
 207                 err = rtl8201_ack_interrupt(phydev);
 208         }
 209
 210         return err;
 211 }
 212
 213 static int rtl8211b_config_intr(struct phy_device *phydev)
 214 {
 215         int err;
 216
 217         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 218                 err = rtl821x_ack_interrupt(phydev);
 219                 if (err)
 220                         return err;
 221
 222                 err = phy_write(phydev, RTL821x_INER,
 223                                 RTL8211B_INER_INIT);
 224         } else {
 225                 err = phy_write(phydev, RTL821x_INER, 0);
 226                 if (err)
 227                         return err;
 228
 229                 err = rtl821x_ack_interrupt(phydev);
 230         }
 231
 232         return err;
 233 }
 234
 235 static int rtl8211e_config_intr(struct phy_device *phydev)
 236 {
 237         int err;
 238
 239         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 240                 err = rtl821x_ack_interrupt(phydev);
 241                 if (err)
 242                         return err;
 243
 244                 err = phy_write(phydev, RTL821x_INER,
 245                                 RTL8211E_INER_LINK_STATUS);
 246         } else {
 247                 err = phy_write(phydev, RTL821x_INER, 0);
 248                 if (err)
 249                         return err;
 250
 251                 err = rtl821x_ack_interrupt(phydev);
 252         }
 253
 254         return err;
 255 }
 256
 257 static int rtl8211f_config_intr(struct phy_device *phydev)
 258 {
 259         u16 val;
 260         int err;
 261
 262         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 263                 err = rtl8211f_ack_interrupt(phydev);
 264                 if (err)
 265                         return err;
 266
 267                 val = RTL8211F_INER_LINK_STATUS;
 268                 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
 269         } else {
 270                 val = 0;
 271                 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
 272                 if (err)
 273                         return err;
 274
 275                 err = rtl8211f_ack_interrupt(phydev);
 276         }
 277
 278         return err;
 279 }
 280
 281 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
 282 {
 283         int irq_status;
 284
 285         irq_status = phy_read(phydev, RTL8201F_ISR);
 286         if (irq_status < 0) {
 287                 phy_error(phydev);
 288                 return IRQ_NONE;
 289         }
 290
 291         if (!(irq_status & RTL8201F_ISR_MASK))
 292                 return IRQ_NONE;
 293
 294         phy_trigger_machine(phydev);
 295
 296         return IRQ_HANDLED;
 297 }
 298
 299 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
 300 {
 301         int irq_status, irq_enabled;
 302
 303         irq_status = phy_read(phydev, RTL821x_INSR);
 304         if (irq_status < 0) {
 305                 phy_error(phydev);
 306                 return IRQ_NONE;
 307         }
 308
 309         irq_enabled = phy_read(phydev, RTL821x_INER);
 310         if (irq_enabled < 0) {
 311                 phy_error(phydev);
 312                 return IRQ_NONE;
 313         }
 314
 315         if (!(irq_status & irq_enabled))
 316                 return IRQ_NONE;
 317
 318         phy_trigger_machine(phydev);
 319
 320         return IRQ_HANDLED;
 321 }
 322
 323 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
 324 {
 325         int irq_status;
 326
 327         irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
 328         if (irq_status < 0) {
 329                 phy_error(phydev);
 330                 return IRQ_NONE;
 331         }
 332
 333         if (!(irq_status & RTL8211F_INER_LINK_STATUS))
 334                 return IRQ_NONE;
 335
 336         phy_trigger_machine(phydev);
 337
 338         return IRQ_HANDLED;
 339 }
 340
 341 static int rtl8211_config_aneg(struct phy_device *phydev)
 342 {
 343         int ret;
 344
 345         ret = genphy_config_aneg(phydev);
 346         if (ret < 0)
 347                 return ret;
 348
 349         /* Quirk was copied from vendor driver. Unfortunately it includes no
 350          * description of the magic numbers.
 351          */
 352         if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
 353                 phy_write(phydev, 0x17, 0x2138);
 354                 phy_write(phydev, 0x0e, 0x0260);
 355         } else {
 356                 phy_write(phydev, 0x17, 0x2108);
 357                 phy_write(phydev, 0x0e, 0x0000);
 358         }
 359
 360         return 0;
 361 }
 362
 363 static int rtl8211c_config_init(struct phy_device *phydev)
 364 {
 365         /* RTL8211C has an issue when operating in Gigabit slave mode */
 366         return phy_set_bits(phydev, MII_CTRL1000,
 367                             CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
 368 }
 369
 370 static int rtl8211f_config_init(struct phy_device *phydev)
 371 {
 372         struct rtl821x_priv *priv = phydev->priv;
 373         struct device *dev = &phydev->mdio.dev;
 374         u16 val_txdly, val_rxdly;
 375         int ret;
 376
 377         ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
 378                                        RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
 379                                        priv->phycr1);
 380         if (ret < 0) {
 381                 dev_err(dev, "aldps mode  configuration failed: %pe\n",
 382                         ERR_PTR(ret));
 383                 return ret;
 384         }
 385
 386         switch (phydev->interface) {
 387         case PHY_INTERFACE_MODE_RGMII:
 388                 val_txdly = 0;
 389                 val_rxdly = 0;
 390                 break;
 391
 392         case PHY_INTERFACE_MODE_RGMII_RXID:
 393                 val_txdly = 0;
 394                 val_rxdly = RTL8211F_RX_DELAY;
 395                 break;
 396
 397         case PHY_INTERFACE_MODE_RGMII_TXID:
 398                 val_txdly = RTL8211F_TX_DELAY;
 399                 val_rxdly = 0;
 400                 break;
 401
 402         case PHY_INTERFACE_MODE_RGMII_ID:
 403                 val_txdly = RTL8211F_TX_DELAY;
 404                 val_rxdly = RTL8211F_RX_DELAY;
 405                 break;
 406
 407         default: /* the rest of the modes imply leaving delay as is. */
 408                 return 0;
 409         }
 410
 411         ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
 412                                        val_txdly);
 413         if (ret < 0) {
 414                 dev_err(dev, "Failed to update the TX delay register\n");
 415                 return ret;
 416         } else if (ret) {
 417                 dev_dbg(dev,
 418                         "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
 419                         val_txdly ? "Enabling" : "Disabling");
 420         } else {
 421                 dev_dbg(dev,
 422                         "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
 423                         val_txdly ? "enabled" : "disabled");
 424         }
 425
 426         ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
 427                                        val_rxdly);
 428         if (ret < 0) {
 429                 dev_err(dev, "Failed to update the RX delay register\n");
 430                 return ret;
 431         } else if (ret) {
 432                 dev_dbg(dev,
 433                         "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
 434                         val_rxdly ? "Enabling" : "Disabling");
 435         } else {
 436                 dev_dbg(dev,
 437                         "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
 438                         val_rxdly ? "enabled" : "disabled");
 439         }
 440
 441         if (priv->has_phycr2) {
 442                 ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
 443                                        RTL8211F_CLKOUT_EN, priv->phycr2);
 444                 if (ret < 0) {
 445                         dev_err(dev, "clkout configuration failed: %pe\n",
 446                                 ERR_PTR(ret));
 447                         return ret;
 448                 }
 449
 450                 return genphy_soft_reset(phydev);
 451         }
 452
 453         return 0;
 454 }
 455
 456 static int rtl821x_suspend(struct phy_device *phydev)
 457 {
 458         struct rtl821x_priv *priv = phydev->priv;
 459         int ret = 0;
 460
 461         if (!phydev->wol_enabled) {
 462                 ret = genphy_suspend(phydev);
 463
 464                 if (ret)
 465                         return ret;
 466
 467                 clk_disable_unprepare(priv->clk);
 468         }
 469
 470         return ret;
 471 }
 472
 473 static int rtl821x_resume(struct phy_device *phydev)
 474 {
 475         struct rtl821x_priv *priv = phydev->priv;
 476         int ret;
 477
 478         if (!phydev->wol_enabled)
 479                 clk_prepare_enable(priv->clk);
 480
 481         ret = genphy_resume(phydev);
 482         if (ret < 0)
 483                 return ret;
 484
 485         msleep(20);
 486
 487         return 0;
 488 }
 489
 490 static int rtl8211f_led_hw_is_supported(struct phy_device *phydev, u8 index,
 491                                         unsigned long rules)
 492 {
 493         const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) |
 494                                    BIT(TRIGGER_NETDEV_LINK_100) |
 495                                    BIT(TRIGGER_NETDEV_LINK_1000) |
 496                                    BIT(TRIGGER_NETDEV_RX) |
 497                                    BIT(TRIGGER_NETDEV_TX);
 498
 499         /* The RTL8211F PHY supports these LED settings on up to three LEDs:
 500          * - Link: Configurable subset of 10/100/1000 link rates
 501          * - Active: Blink on activity, RX or TX is not differentiated
 502          * The Active option has two modes, A and B:
 503          * - A: Link and Active indication at configurable, but matching,
 504          *      subset of 10/100/1000 link rates
 505          * - B: Link indication at configurable subset of 10/100/1000 link
 506          *      rates and Active indication always at all three 10+100+1000
 507          *      link rates.
 508          * This code currently uses mode B only.
 509          */
 510
 511         if (index >= RTL8211F_LED_COUNT)
 512                 return -EINVAL;
 513
 514         /* Filter out any other unsupported triggers. */
 515         if (rules & ~mask)
 516                 return -EOPNOTSUPP;
 517
 518         /* RX and TX are not differentiated, either both are set or not set. */
 519         if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX)))
 520                 return -EOPNOTSUPP;
 521
 522         return 0;
 523 }
 524
 525 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index,
 526                                        unsigned long *rules)
 527 {
 528         int val;
 529
 530         val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR);
 531         if (val < 0)
 532                 return val;
 533
 534         val >>= RTL8211F_LEDCR_SHIFT * index;
 535         val &= RTL8211F_LEDCR_MASK;
 536
 537         if (val & RTL8211F_LEDCR_LINK_10)
 538                 set_bit(TRIGGER_NETDEV_LINK_10, rules);
 539
 540         if (val & RTL8211F_LEDCR_LINK_100)
 541                 set_bit(TRIGGER_NETDEV_LINK_100, rules);
 542
 543         if (val & RTL8211F_LEDCR_LINK_1000)
 544                 set_bit(TRIGGER_NETDEV_LINK_1000, rules);
 545
 546         if (val & RTL8211F_LEDCR_ACT_TXRX) {
 547                 set_bit(TRIGGER_NETDEV_RX, rules);
 548                 set_bit(TRIGGER_NETDEV_TX, rules);
 549         }
 550
 551         return 0;
 552 }
 553
 554 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index,
 555                                        unsigned long rules)
 556 {
 557         const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index);
 558         u16 reg = RTL8211F_LEDCR_MODE;  /* Mode B */
 559
 560         if (index >= RTL8211F_LED_COUNT)
 561                 return -EINVAL;
 562
 563         if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
 564                 reg |= RTL8211F_LEDCR_LINK_10;
 565
 566         if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
 567                 reg |= RTL8211F_LEDCR_LINK_100;
 568
 569         if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
 570                 reg |= RTL8211F_LEDCR_LINK_1000;
 571
 572         if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
 573             test_bit(TRIGGER_NETDEV_TX, &rules)) {
 574                 reg |= RTL8211F_LEDCR_ACT_TXRX;
 575         }
 576
 577         reg <<= RTL8211F_LEDCR_SHIFT * index;
 578
 579         return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg);
 580 }
 581
 582 static int rtl8211e_config_init(struct phy_device *phydev)
 583 {
 584         int ret = 0, oldpage;
 585         u16 val;
 586
 587         /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
 588         switch (phydev->interface) {
 589         case PHY_INTERFACE_MODE_RGMII:
 590                 val = RTL8211E_CTRL_DELAY | 0;
 591                 break;
 592         case PHY_INTERFACE_MODE_RGMII_ID:
 593                 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
 594                 break;
 595         case PHY_INTERFACE_MODE_RGMII_RXID:
 596                 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
 597                 break;
 598         case PHY_INTERFACE_MODE_RGMII_TXID:
 599                 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
 600                 break;
 601         default: /* the rest of the modes imply leaving delays as is. */
 602                 return 0;
 603         }
 604
 605         /* According to a sample driver there is a 0x1c config register on the
 606          * 0xa4 extension page (0x7) layout. It can be used to disable/enable
 607          * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
 608          * The configuration register definition:
 609          * 14 = reserved
 610          * 13 = Force Tx RX Delay controlled by bit12 bit11,
 611          * 12 = RX Delay, 11 = TX Delay
 612          * 10:0 = Test && debug settings reserved by realtek
 613          */
 614         oldpage = phy_select_page(phydev, 0x7);
 615         if (oldpage < 0)
 616                 goto err_restore_page;
 617
 618         ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
 619         if (ret)
 620                 goto err_restore_page;
 621
 622         ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
 623                            | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
 624                            val);
 625
 626 err_restore_page:
 627         return phy_restore_page(phydev, oldpage, ret);
 628 }
 629
 630 static int rtl8211b_suspend(struct phy_device *phydev)
 631 {
 632         phy_write(phydev, MII_MMD_DATA, BIT(9));
 633
 634         return genphy_suspend(phydev);
 635 }
 636
 637 static int rtl8211b_resume(struct phy_device *phydev)
 638 {
 639         phy_write(phydev, MII_MMD_DATA, 0);
 640
 641         return genphy_resume(phydev);
 642 }
 643
 644 static int rtl8366rb_config_init(struct phy_device *phydev)
 645 {
 646         int ret;
 647
 648         ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
 649                            RTL8366RB_POWER_SAVE_ON);
 650         if (ret) {
 651                 dev_err(&phydev->mdio.dev,
 652                         "error enabling power management\n");
 653         }
 654
 655         return ret;
 656 }
 657
 658 /* get actual speed to cover the downshift case */
 659 static void rtlgen_decode_speed(struct phy_device *phydev, int val)
 660 {
 661         switch (val & RTLGEN_SPEED_MASK) {
 662         case 0x0000:
 663                 phydev->speed = SPEED_10;
 664                 break;
 665         case 0x0010:
 666                 phydev->speed = SPEED_100;
 667                 break;
 668         case 0x0020:
 669                 phydev->speed = SPEED_1000;
 670                 break;
 671         case 0x0200:
 672                 phydev->speed = SPEED_10000;
 673                 break;
 674         case 0x0210:
 675                 phydev->speed = SPEED_2500;
 676                 break;
 677         case 0x0220:
 678                 phydev->speed = SPEED_5000;
 679                 break;
 680         default:
 681                 break;
 682         }
 683 }
 684
 685 static int rtlgen_read_status(struct phy_device *phydev)
 686 {
 687         int ret, val;
 688
 689         ret = genphy_read_status(phydev);
 690         if (ret < 0)
 691                 return ret;
 692
 693         if (!phydev->link)
 694                 return 0;
 695
 696         val = phy_read_paged(phydev, 0xa43, 0x12);
 697         if (val < 0)
 698                 return val;
 699
 700         rtlgen_decode_speed(phydev, val);
 701
 702         return 0;
 703 }
 704
 705 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
 706 {
 707         int ret;
 708
 709         if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
 710                 rtl821x_write_page(phydev, 0xa5c);
 711                 ret = __phy_read(phydev, 0x12);
 712                 rtl821x_write_page(phydev, 0);
 713         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
 714                 rtl821x_write_page(phydev, 0xa5d);
 715                 ret = __phy_read(phydev, 0x10);
 716                 rtl821x_write_page(phydev, 0);
 717         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
 718                 rtl821x_write_page(phydev, 0xa5d);
 719                 ret = __phy_read(phydev, 0x11);
 720                 rtl821x_write_page(phydev, 0);
 721         } else {
 722                 ret = -EOPNOTSUPP;
 723         }
 724
 725         return ret;
 726 }
 727
 728 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
 729                             u16 val)
 730 {
 731         int ret;
 732
 733         if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
 734                 rtl821x_write_page(phydev, 0xa5d);
 735                 ret = __phy_write(phydev, 0x10, val);
 736                 rtl821x_write_page(phydev, 0);
 737         } else {
 738                 ret = -EOPNOTSUPP;
 739         }
 740
 741         return ret;
 742 }
 743
 744 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
 745 {
 746         int ret = rtlgen_read_mmd(phydev, devnum, regnum);
 747
 748         if (ret != -EOPNOTSUPP)
 749                 return ret;
 750
 751         if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
 752                 rtl821x_write_page(phydev, 0xa6e);
 753                 ret = __phy_read(phydev, 0x16);
 754                 rtl821x_write_page(phydev, 0);
 755         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
 756                 rtl821x_write_page(phydev, 0xa6d);
 757                 ret = __phy_read(phydev, 0x12);
 758                 rtl821x_write_page(phydev, 0);
 759         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
 760                 rtl821x_write_page(phydev, 0xa6d);
 761                 ret = __phy_read(phydev, 0x10);
 762                 rtl821x_write_page(phydev, 0);
 763         }
 764
 765         return ret;
 766 }
 767
 768 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
 769                              u16 val)
 770 {
 771         int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
 772
 773         if (ret != -EOPNOTSUPP)
 774                 return ret;
 775
 776         if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
 777                 rtl821x_write_page(phydev, 0xa6d);
 778                 ret = __phy_write(phydev, 0x12, val);
 779                 rtl821x_write_page(phydev, 0);
 780         }
 781
 782         return ret;
 783 }
 784
 785 static int rtl822xb_config_init(struct phy_device *phydev)
 786 {
 787         bool has_2500, has_sgmii;
 788         u16 mode;
 789         int ret;
 790
 791         has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
 792                             phydev->host_interfaces) ||
 793                    phydev->interface == PHY_INTERFACE_MODE_2500BASEX;
 794
 795         has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII,
 796                              phydev->host_interfaces) ||
 797                     phydev->interface == PHY_INTERFACE_MODE_SGMII;
 798
 799         /* fill in possible interfaces */
 800         __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces,
 801                      has_2500);
 802         __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces,
 803                      has_sgmii);
 804
 805         if (!has_2500 && !has_sgmii)
 806                 return 0;
 807
 808         /* determine SerDes option mode */
 809         if (has_2500 && !has_sgmii) {
 810                 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX;
 811                 phydev->rate_matching = RATE_MATCH_PAUSE;
 812         } else {
 813                 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII;
 814                 phydev->rate_matching = RATE_MATCH_NONE;
 815         }
 816
 817         /* the following sequence with magic numbers sets up the SerDes
 818          * option mode
 819          */
 820         ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0);
 821         if (ret < 0)
 822                 return ret;
 823
 824         ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1,
 825                                      RTL822X_VND1_SERDES_OPTION,
 826                                      RTL822X_VND1_SERDES_OPTION_MODE_MASK,
 827                                      mode);
 828         if (ret < 0)
 829                 return ret;
 830
 831         ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503);
 832         if (ret < 0)
 833                 return ret;
 834
 835         ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455);
 836         if (ret < 0)
 837                 return ret;
 838
 839         return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020);
 840 }
 841
 842 static int rtl822xb_get_rate_matching(struct phy_device *phydev,
 843                                       phy_interface_t iface)
 844 {
 845         int val;
 846
 847         /* Only rate matching at 2500base-x */
 848         if (iface != PHY_INTERFACE_MODE_2500BASEX)
 849                 return RATE_MATCH_NONE;
 850
 851         val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION);
 852         if (val < 0)
 853                 return val;
 854
 855         if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) ==
 856             RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX)
 857                 return RATE_MATCH_PAUSE;
 858
 859         /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */
 860         return RATE_MATCH_NONE;
 861 }
 862
 863 static int rtl822x_get_features(struct phy_device *phydev)
 864 {
 865         int val;
 866
 867         val = phy_read_paged(phydev, 0xa61, 0x13);
 868         if (val < 0)
 869                 return val;
 870
 871         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 872                          phydev->supported, val & MDIO_PMA_SPEED_2_5G);
 873         linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 874                          phydev->supported, val & MDIO_PMA_SPEED_5G);
 875         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 876                          phydev->supported, val & MDIO_SPEED_10G);
 877
 878         return genphy_read_abilities(phydev);
 879 }
 880
 881 static int rtl822x_config_aneg(struct phy_device *phydev)
 882 {
 883         int ret = 0;
 884
 885         if (phydev->autoneg == AUTONEG_ENABLE) {
 886                 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
 887
 888                 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
 889                                                MDIO_AN_10GBT_CTRL_ADV2_5G |
 890                                                MDIO_AN_10GBT_CTRL_ADV5G,
 891                                                adv);
 892                 if (ret < 0)
 893                         return ret;
 894         }
 895
 896         return __genphy_config_aneg(phydev, ret);
 897 }
 898
 899 static void rtl822xb_update_interface(struct phy_device *phydev)
 900 {
 901         int val;
 902
 903         if (!phydev->link)
 904                 return;
 905
 906         /* Change interface according to serdes mode */
 907         val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3);
 908         if (val < 0)
 909                 return;
 910
 911         switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) {
 912         case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX:
 913                 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
 914                 break;
 915         case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII:
 916                 phydev->interface = PHY_INTERFACE_MODE_SGMII;
 917                 break;
 918         }
 919 }
 920
 921 static int rtl822x_read_status(struct phy_device *phydev)
 922 {
 923         if (phydev->autoneg == AUTONEG_ENABLE) {
 924                 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
 925
 926                 if (lpadv < 0)
 927                         return lpadv;
 928
 929                 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising,
 930                                                   lpadv);
 931         }
 932
 933         return rtlgen_read_status(phydev);
 934 }
 935
 936 static int rtl822xb_read_status(struct phy_device *phydev)
 937 {
 938         int ret;
 939
 940         ret = rtl822x_read_status(phydev);
 941         if (ret < 0)
 942                 return ret;
 943
 944         rtl822xb_update_interface(phydev);
 945
 946         return 0;
 947 }
 948
 949 static int rtl822x_c45_get_features(struct phy_device *phydev)
 950 {
 951         linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
 952                          phydev->supported);
 953
 954         return genphy_c45_pma_read_abilities(phydev);
 955 }
 956
 957 static int rtl822x_c45_config_aneg(struct phy_device *phydev)
 958 {
 959         bool changed = false;
 960         int ret, val;
 961
 962         if (phydev->autoneg == AUTONEG_DISABLE)
 963                 return genphy_c45_pma_setup_forced(phydev);
 964
 965         ret = genphy_c45_an_config_aneg(phydev);
 966         if (ret < 0)
 967                 return ret;
 968         if (ret > 0)
 969                 changed = true;
 970
 971         val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
 972
 973         /* Vendor register as C45 has no standardized support for 1000BaseT */
 974         ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL822X_VND2_GBCR,
 975                                      ADVERTISE_1000FULL, val);
 976         if (ret < 0)
 977                 return ret;
 978         if (ret > 0)
 979                 changed = true;
 980
 981         return genphy_c45_check_and_restart_aneg(phydev, changed);
 982 }
 983
 984 static int rtl822x_c45_read_status(struct phy_device *phydev)
 985 {
 986         int ret, val;
 987
 988         ret = genphy_c45_read_status(phydev);
 989         if (ret < 0)
 990                 return ret;
 991
 992         /* Vendor register as C45 has no standardized support for 1000BaseT */
 993         if (phydev->autoneg == AUTONEG_ENABLE) {
 994                 val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
 995                                    RTL822X_VND2_GANLPAR);
 996                 if (val < 0)
 997                         return val;
 998
 999                 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
1000         }
1001
1002         if (!phydev->link)
1003                 return 0;
1004
1005         /* Read actual speed from vendor register. */
1006         val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_PHYSR);
1007         if (val < 0)
1008                 return val;
1009
1010         rtlgen_decode_speed(phydev, val);
1011
1012         return 0;
1013 }
1014
1015 static int rtl822xb_c45_read_status(struct phy_device *phydev)
1016 {
1017         int ret;
1018
1019         ret = rtl822x_c45_read_status(phydev);
1020         if (ret < 0)
1021                 return ret;
1022
1023         rtl822xb_update_interface(phydev);
1024
1025         return 0;
1026 }
1027
1028 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
1029 {
1030         int val;
1031
1032         phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
1033         val = phy_read(phydev, 0x13);
1034         phy_write(phydev, RTL821x_PAGE_SELECT, 0);
1035
1036         return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
1037 }
1038
1039 static int rtlgen_match_phy_device(struct phy_device *phydev)
1040 {
1041         return phydev->phy_id == RTL_GENERIC_PHYID &&
1042                !rtlgen_supports_2_5gbps(phydev);
1043 }
1044
1045 static int rtl8226_match_phy_device(struct phy_device *phydev)
1046 {
1047         return phydev->phy_id == RTL_GENERIC_PHYID &&
1048                rtlgen_supports_2_5gbps(phydev);
1049 }
1050
1051 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
1052                                bool is_c45)
1053 {
1054         if (phydev->is_c45)
1055                 return is_c45 && (id == phydev->c45_ids.device_ids[1]);
1056         else
1057                 return !is_c45 && (id == phydev->phy_id);
1058 }
1059
1060 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
1061 {
1062         return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
1063 }
1064
1065 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev)
1066 {
1067         return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true);
1068 }
1069
1070 static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev)
1071 {
1072         return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false);
1073 }
1074
1075 static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev)
1076 {
1077         return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
1078 }
1079
1080 static int rtlgen_resume(struct phy_device *phydev)
1081 {
1082         int ret = genphy_resume(phydev);
1083
1084         /* Internal PHY's from RTL8168h up may not be instantly ready */
1085         msleep(20);
1086
1087         return ret;
1088 }
1089
1090 static int rtlgen_c45_resume(struct phy_device *phydev)
1091 {
1092         int ret = genphy_c45_pma_resume(phydev);
1093
1094         msleep(20);
1095
1096         return ret;
1097 }
1098
1099 static int rtl9000a_config_init(struct phy_device *phydev)
1100 {
1101         phydev->autoneg = AUTONEG_DISABLE;
1102         phydev->speed = SPEED_100;
1103         phydev->duplex = DUPLEX_FULL;
1104
1105         return 0;
1106 }
1107
1108 static int rtl9000a_config_aneg(struct phy_device *phydev)
1109 {
1110         int ret;
1111         u16 ctl = 0;
1112
1113         switch (phydev->master_slave_set) {
1114         case MASTER_SLAVE_CFG_MASTER_FORCE:
1115                 ctl |= CTL1000_AS_MASTER;
1116                 break;
1117         case MASTER_SLAVE_CFG_SLAVE_FORCE:
1118                 break;
1119         case MASTER_SLAVE_CFG_UNKNOWN:
1120         case MASTER_SLAVE_CFG_UNSUPPORTED:
1121                 return 0;
1122         default:
1123                 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1124                 return -EOPNOTSUPP;
1125         }
1126
1127         ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
1128         if (ret == 1)
1129                 ret = genphy_soft_reset(phydev);
1130
1131         return ret;
1132 }
1133
1134 static int rtl9000a_read_status(struct phy_device *phydev)
1135 {
1136         int ret;
1137
1138         phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1139         phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1140
1141         ret = genphy_update_link(phydev);
1142         if (ret)
1143                 return ret;
1144
1145         ret = phy_read(phydev, MII_CTRL1000);
1146         if (ret < 0)
1147                 return ret;
1148         if (ret & CTL1000_AS_MASTER)
1149                 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1150         else
1151                 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1152
1153         ret = phy_read(phydev, MII_STAT1000);
1154         if (ret < 0)
1155                 return ret;
1156         if (ret & LPA_1000MSRES)
1157                 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
1158         else
1159                 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
1160
1161         return 0;
1162 }
1163
1164 static int rtl9000a_ack_interrupt(struct phy_device *phydev)
1165 {
1166         int err;
1167
1168         err = phy_read(phydev, RTL8211F_INSR);
1169
1170         return (err < 0) ? err : 0;
1171 }
1172
1173 static int rtl9000a_config_intr(struct phy_device *phydev)
1174 {
1175         u16 val;
1176         int err;
1177
1178         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1179                 err = rtl9000a_ack_interrupt(phydev);
1180                 if (err)
1181                         return err;
1182
1183                 val = (u16)~RTL9000A_GINMR_LINK_STATUS;
1184                 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1185         } else {
1186                 val = ~0;
1187                 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1188                 if (err)
1189                         return err;
1190
1191                 err = rtl9000a_ack_interrupt(phydev);
1192         }
1193
1194         return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1195 }
1196
1197 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
1198 {
1199         int irq_status;
1200
1201         irq_status = phy_read(phydev, RTL8211F_INSR);
1202         if (irq_status < 0) {
1203                 phy_error(phydev);
1204                 return IRQ_NONE;
1205         }
1206
1207         if (!(irq_status & RTL8211F_INER_LINK_STATUS))
1208                 return IRQ_NONE;
1209
1210         phy_trigger_machine(phydev);
1211
1212         return IRQ_HANDLED;
1213 }
1214
1215 static struct phy_driver realtek_drvs[] = {
1216         {
1217                 PHY_ID_MATCH_EXACT(0x00008201),
1218                 .name           = "RTL8201CP Ethernet",
1219                 .read_page      = rtl821x_read_page,
1220                 .write_page     = rtl821x_write_page,
1221         }, {
1222                 PHY_ID_MATCH_EXACT(0x001cc816),
1223                 .name           = "RTL8201F Fast Ethernet",
1224                 .config_intr    = &rtl8201_config_intr,
1225                 .handle_interrupt = rtl8201_handle_interrupt,
1226                 .suspend        = genphy_suspend,
1227                 .resume         = genphy_resume,
1228                 .read_page      = rtl821x_read_page,
1229                 .write_page     = rtl821x_write_page,
1230         }, {
1231                 PHY_ID_MATCH_MODEL(0x001cc880),
1232                 .name           = "RTL8208 Fast Ethernet",
1233                 .read_mmd       = genphy_read_mmd_unsupported,
1234                 .write_mmd      = genphy_write_mmd_unsupported,
1235                 .suspend        = genphy_suspend,
1236                 .resume         = genphy_resume,
1237                 .read_page      = rtl821x_read_page,
1238                 .write_page     = rtl821x_write_page,
1239         }, {
1240                 PHY_ID_MATCH_EXACT(0x001cc910),
1241                 .name           = "RTL8211 Gigabit Ethernet",
1242                 .config_aneg    = rtl8211_config_aneg,
1243                 .read_mmd       = &genphy_read_mmd_unsupported,
1244                 .write_mmd      = &genphy_write_mmd_unsupported,
1245                 .read_page      = rtl821x_read_page,
1246                 .write_page     = rtl821x_write_page,
1247         }, {
1248                 PHY_ID_MATCH_EXACT(0x001cc912),
1249                 .name           = "RTL8211B Gigabit Ethernet",
1250                 .config_intr    = &rtl8211b_config_intr,
1251                 .handle_interrupt = rtl821x_handle_interrupt,
1252                 .read_mmd       = &genphy_read_mmd_unsupported,
1253                 .write_mmd      = &genphy_write_mmd_unsupported,
1254                 .suspend        = rtl8211b_suspend,
1255                 .resume         = rtl8211b_resume,
1256                 .read_page      = rtl821x_read_page,
1257                 .write_page     = rtl821x_write_page,
1258         }, {
1259                 PHY_ID_MATCH_EXACT(0x001cc913),
1260                 .name           = "RTL8211C Gigabit Ethernet",
1261                 .config_init    = rtl8211c_config_init,
1262                 .read_mmd       = &genphy_read_mmd_unsupported,
1263                 .write_mmd      = &genphy_write_mmd_unsupported,
1264                 .read_page      = rtl821x_read_page,
1265                 .write_page     = rtl821x_write_page,
1266         }, {
1267                 PHY_ID_MATCH_EXACT(0x001cc914),
1268                 .name           = "RTL8211DN Gigabit Ethernet",
1269                 .config_intr    = rtl8211e_config_intr,
1270                 .handle_interrupt = rtl821x_handle_interrupt,
1271                 .suspend        = genphy_suspend,
1272                 .resume         = genphy_resume,
1273                 .read_page      = rtl821x_read_page,
1274                 .write_page     = rtl821x_write_page,
1275         }, {
1276                 PHY_ID_MATCH_EXACT(0x001cc915),
1277                 .name           = "RTL8211E Gigabit Ethernet",
1278                 .config_init    = &rtl8211e_config_init,
1279                 .config_intr    = &rtl8211e_config_intr,
1280                 .handle_interrupt = rtl821x_handle_interrupt,
1281                 .suspend        = genphy_suspend,
1282                 .resume         = genphy_resume,
1283                 .read_page      = rtl821x_read_page,
1284                 .write_page     = rtl821x_write_page,
1285         }, {
1286                 PHY_ID_MATCH_EXACT(0x001cc916),
1287                 .name           = "RTL8211F Gigabit Ethernet",
1288                 .probe          = rtl821x_probe,
1289                 .config_init    = &rtl8211f_config_init,
1290                 .read_status    = rtlgen_read_status,
1291                 .config_intr    = &rtl8211f_config_intr,
1292                 .handle_interrupt = rtl8211f_handle_interrupt,
1293                 .suspend        = rtl821x_suspend,
1294                 .resume         = rtl821x_resume,
1295                 .read_page      = rtl821x_read_page,
1296                 .write_page     = rtl821x_write_page,
1297                 .flags          = PHY_ALWAYS_CALL_SUSPEND,
1298                 .led_hw_is_supported = rtl8211f_led_hw_is_supported,
1299                 .led_hw_control_get = rtl8211f_led_hw_control_get,
1300                 .led_hw_control_set = rtl8211f_led_hw_control_set,
1301         }, {
1302                 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
1303                 .name           = "RTL8211F-VD Gigabit Ethernet",
1304                 .probe          = rtl821x_probe,
1305                 .config_init    = &rtl8211f_config_init,
1306                 .read_status    = rtlgen_read_status,
1307                 .config_intr    = &rtl8211f_config_intr,
1308                 .handle_interrupt = rtl8211f_handle_interrupt,
1309                 .suspend        = rtl821x_suspend,
1310                 .resume         = rtl821x_resume,
1311                 .read_page      = rtl821x_read_page,
1312                 .write_page     = rtl821x_write_page,
1313                 .flags          = PHY_ALWAYS_CALL_SUSPEND,
1314         }, {
1315                 .name           = "Generic FE-GE Realtek PHY",
1316                 .match_phy_device = rtlgen_match_phy_device,
1317                 .read_status    = rtlgen_read_status,
1318                 .suspend        = genphy_suspend,
1319                 .resume         = rtlgen_resume,
1320                 .read_page      = rtl821x_read_page,
1321                 .write_page     = rtl821x_write_page,
1322                 .read_mmd       = rtlgen_read_mmd,
1323                 .write_mmd      = rtlgen_write_mmd,
1324         }, {
1325                 .name           = "RTL8226 2.5Gbps PHY",
1326                 .match_phy_device = rtl8226_match_phy_device,
1327                 .get_features   = rtl822x_get_features,
1328                 .config_aneg    = rtl822x_config_aneg,
1329                 .read_status    = rtl822x_read_status,
1330                 .suspend        = genphy_suspend,
1331                 .resume         = rtlgen_resume,
1332                 .read_page      = rtl821x_read_page,
1333                 .write_page     = rtl821x_write_page,
1334                 .read_mmd       = rtl822x_read_mmd,
1335                 .write_mmd      = rtl822x_write_mmd,
1336         }, {
1337                 PHY_ID_MATCH_EXACT(0x001cc840),
1338                 .name           = "RTL8226B_RTL8221B 2.5Gbps PHY",
1339                 .get_features   = rtl822x_get_features,
1340                 .config_aneg    = rtl822x_config_aneg,
1341                 .config_init    = rtl822xb_config_init,
1342                 .get_rate_matching = rtl822xb_get_rate_matching,
1343                 .read_status    = rtl822xb_read_status,
1344                 .suspend        = genphy_suspend,
1345                 .resume         = rtlgen_resume,
1346                 .read_page      = rtl821x_read_page,
1347                 .write_page     = rtl821x_write_page,
1348                 .read_mmd       = rtl822x_read_mmd,
1349                 .write_mmd      = rtl822x_write_mmd,
1350         }, {
1351                 PHY_ID_MATCH_EXACT(0x001cc838),
1352                 .name           = "RTL8226-CG 2.5Gbps PHY",
1353                 .get_features   = rtl822x_get_features,
1354                 .config_aneg    = rtl822x_config_aneg,
1355                 .read_status    = rtl822x_read_status,
1356                 .suspend        = genphy_suspend,
1357                 .resume         = rtlgen_resume,
1358                 .read_page      = rtl821x_read_page,
1359                 .write_page     = rtl821x_write_page,
1360         }, {
1361                 PHY_ID_MATCH_EXACT(0x001cc848),
1362                 .name           = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1363                 .get_features   = rtl822x_get_features,
1364                 .config_aneg    = rtl822x_config_aneg,
1365                 .config_init    = rtl822xb_config_init,
1366                 .get_rate_matching = rtl822xb_get_rate_matching,
1367                 .read_status    = rtl822xb_read_status,
1368                 .suspend        = genphy_suspend,
1369                 .resume         = rtlgen_resume,
1370                 .read_page      = rtl821x_read_page,
1371                 .write_page     = rtl821x_write_page,
1372         }, {
1373                 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
1374                 .name           = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
1375                 .get_features   = rtl822x_get_features,
1376                 .config_aneg    = rtl822x_config_aneg,
1377                 .config_init    = rtl822xb_config_init,
1378                 .get_rate_matching = rtl822xb_get_rate_matching,
1379                 .read_status    = rtl822xb_read_status,
1380                 .suspend        = genphy_suspend,
1381                 .resume         = rtlgen_resume,
1382                 .read_page      = rtl821x_read_page,
1383                 .write_page     = rtl821x_write_page,
1384         }, {
1385                 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
1386                 .name           = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
1387                 .config_init    = rtl822xb_config_init,
1388                 .get_rate_matching = rtl822xb_get_rate_matching,
1389                 .get_features   = rtl822x_c45_get_features,
1390                 .config_aneg    = rtl822x_c45_config_aneg,
1391                 .read_status    = rtl822xb_c45_read_status,
1392                 .suspend        = genphy_c45_pma_suspend,
1393                 .resume         = rtlgen_c45_resume,
1394         }, {
1395                 .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
1396                 .name           = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
1397                 .get_features   = rtl822x_get_features,
1398                 .config_aneg    = rtl822x_config_aneg,
1399                 .config_init    = rtl822xb_config_init,
1400                 .get_rate_matching = rtl822xb_get_rate_matching,
1401                 .read_status    = rtl822xb_read_status,
1402                 .suspend        = genphy_suspend,
1403                 .resume         = rtlgen_resume,
1404                 .read_page      = rtl821x_read_page,
1405                 .write_page     = rtl821x_write_page,
1406         }, {
1407                 .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
1408                 .name           = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
1409                 .config_init    = rtl822xb_config_init,
1410                 .get_rate_matching = rtl822xb_get_rate_matching,
1411                 .get_features   = rtl822x_c45_get_features,
1412                 .config_aneg    = rtl822x_c45_config_aneg,
1413                 .read_status    = rtl822xb_c45_read_status,
1414                 .suspend        = genphy_c45_pma_suspend,
1415                 .resume         = rtlgen_c45_resume,
1416         }, {
1417                 PHY_ID_MATCH_EXACT(0x001cc862),
1418                 .name           = "RTL8251B 5Gbps PHY",
1419                 .get_features   = rtl822x_get_features,
1420                 .config_aneg    = rtl822x_config_aneg,
1421                 .read_status    = rtl822x_read_status,
1422                 .suspend        = genphy_suspend,
1423                 .resume         = rtlgen_resume,
1424                 .read_page      = rtl821x_read_page,
1425                 .write_page     = rtl821x_write_page,
1426         }, {
1427                 PHY_ID_MATCH_EXACT(0x001ccad0),
1428                 .name           = "RTL8224 2.5Gbps PHY",
1429                 .get_features   = rtl822x_c45_get_features,
1430                 .config_aneg    = rtl822x_c45_config_aneg,
1431                 .read_status    = rtl822x_c45_read_status,
1432                 .suspend        = genphy_c45_pma_suspend,
1433                 .resume         = rtlgen_c45_resume,
1434         }, {
1435                 PHY_ID_MATCH_EXACT(0x001cc961),
1436                 .name           = "RTL8366RB Gigabit Ethernet",
1437                 .config_init    = &rtl8366rb_config_init,
1438                 /* These interrupts are handled by the irq controller
1439                  * embedded inside the RTL8366RB, they get unmasked when the
1440                  * irq is requested and ACKed by reading the status register,
1441                  * which is done by the irqchip code.
1442                  */
1443                 .config_intr    = genphy_no_config_intr,
1444                 .handle_interrupt = genphy_handle_interrupt_no_ack,
1445                 .suspend        = genphy_suspend,
1446                 .resume         = genphy_resume,
1447         }, {
1448                 PHY_ID_MATCH_EXACT(0x001ccb00),
1449                 .name           = "RTL9000AA_RTL9000AN Ethernet",
1450                 .features       = PHY_BASIC_T1_FEATURES,
1451                 .config_init    = rtl9000a_config_init,
1452                 .config_aneg    = rtl9000a_config_aneg,
1453                 .read_status    = rtl9000a_read_status,
1454                 .config_intr    = rtl9000a_config_intr,
1455                 .handle_interrupt = rtl9000a_handle_interrupt,
1456                 .suspend        = genphy_suspend,
1457                 .resume         = genphy_resume,
1458                 .read_page      = rtl821x_read_page,
1459                 .write_page     = rtl821x_write_page,
1460         }, {
1461                 PHY_ID_MATCH_EXACT(0x001cc942),
1462                 .name           = "RTL8365MB-VC Gigabit Ethernet",
1463                 /* Interrupt handling analogous to RTL8366RB */
1464                 .config_intr    = genphy_no_config_intr,
1465                 .handle_interrupt = genphy_handle_interrupt_no_ack,
1466                 .suspend        = genphy_suspend,
1467                 .resume         = genphy_resume,
1468         }, {
1469                 PHY_ID_MATCH_EXACT(0x001cc960),
1470                 .name           = "RTL8366S Gigabit Ethernet",
1471                 .suspend        = genphy_suspend,
1472                 .resume         = genphy_resume,
1473                 .read_mmd       = genphy_read_mmd_unsupported,
1474                 .write_mmd      = genphy_write_mmd_unsupported,
1475         },
1476 };
1477
1478 module_phy_driver(realtek_drvs);
1479
1480 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
1481         { PHY_ID_MATCH_VENDOR(0x001cc800) },
1482         { }
1483 };
1484
1485 MODULE_DEVICE_TABLE(mdio, realtek_tbl);