drivers/net/ethernet/intel/igc/igc_main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c)  2018 Intel Corporation */
   3
   4 #include <linux/module.h>
   5 #include <linux/types.h>
   6 #include <linux/if_vlan.h>
   7 #include <linux/tcp.h>
   8 #include <linux/udp.h>
   9 #include <linux/ip.h>
  10 #include <linux/pm_runtime.h>
  11 #include <net/pkt_sched.h>
  12 #include <linux/bpf_trace.h>
  13 #include <net/xdp_sock_drv.h>
  14 #include <linux/pci.h>
  15 #include <linux/mdio.h>
  16
  17 #include <net/ipv6.h>
  18
  19 #include "igc.h"
  20 #include "igc_hw.h"
  21 #include "igc_tsn.h"
  22 #include "igc_xdp.h"
  23
  24 #define DRV_SUMMARY     "Intel(R) 2.5G Ethernet Linux Driver"
  25
  26 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  27
  28 #define IGC_XDP_PASS            0
  29 #define IGC_XDP_CONSUMED        BIT(0)
  30 #define IGC_XDP_TX              BIT(1)
  31 #define IGC_XDP_REDIRECT        BIT(2)
  32
  33 static int debug = -1;
  34
  35 MODULE_DESCRIPTION(DRV_SUMMARY);
  36 MODULE_LICENSE("GPL v2");
  37 module_param(debug, int, 0);
  38 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  39
  40 char igc_driver_name[] = "igc";
  41 static const char igc_driver_string[] = DRV_SUMMARY;
  42 static const char igc_copyright[] =
  43         "Copyright(c) 2018 Intel Corporation.";
  44
  45 static const struct igc_info *igc_info_tbl[] = {
  46         [board_base] = &igc_base_info,
  47 };
  48
  49 static const struct pci_device_id igc_pci_tbl[] = {
  50         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LM), board_base },
  51         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_V), board_base },
  52         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_I), board_base },
  53         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I220_V), board_base },
  54         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K), board_base },
  55         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K2), board_base },
  56         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_K), board_base },
  57         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LMVP), board_base },
  58         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_LMVP), board_base },
  59         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_IT), board_base },
  60         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_LM), board_base },
  61         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_V), board_base },
  62         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_IT), board_base },
  63         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I221_V), board_base },
  64         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_BLANK_NVM), board_base },
  65         { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_BLANK_NVM), board_base },
  66         /* required last entry */
  67         {0, }
  68 };
  69
  70 MODULE_DEVICE_TABLE(pci, igc_pci_tbl);
  71
  72 enum latency_range {
  73         lowest_latency = 0,
  74         low_latency = 1,
  75         bulk_latency = 2,
  76         latency_invalid = 255
  77 };
  78
  79 void igc_reset(struct igc_adapter *adapter)
  80 {
  81         struct net_device *dev = adapter->netdev;
  82         struct igc_hw *hw = &adapter->hw;
  83         struct igc_fc_info *fc = &hw->fc;
  84         u32 pba, hwm;
  85
  86         /* Repartition PBA for greater than 9k MTU if required */
  87         pba = IGC_PBA_34K;
  88
  89         /* flow control settings
  90          * The high water mark must be low enough to fit one full frame
  91          * after transmitting the pause frame.  As such we must have enough
  92          * space to allow for us to complete our current transmit and then
  93          * receive the frame that is in progress from the link partner.
  94          * Set it to:
  95          * - the full Rx FIFO size minus one full Tx plus one full Rx frame
  96          */
  97         hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
  98
  99         fc->high_water = hwm & 0xFFFFFFF0;      /* 16-byte granularity */
 100         fc->low_water = fc->high_water - 16;
 101         fc->pause_time = 0xFFFF;
 102         fc->send_xon = 1;
 103         fc->current_mode = fc->requested_mode;
 104
 105         hw->mac.ops.reset_hw(hw);
 106
 107         if (hw->mac.ops.init_hw(hw))
 108                 netdev_err(dev, "Error on hardware initialization\n");
 109
 110         /* Re-establish EEE setting */
 111         igc_set_eee_i225(hw, true, true, true);
 112
 113         if (!netif_running(adapter->netdev))
 114                 igc_power_down_phy_copper_base(&adapter->hw);
 115
 116         /* Enable HW to recognize an 802.1Q VLAN Ethernet packet */
 117         wr32(IGC_VET, ETH_P_8021Q);
 118
 119         /* Re-enable PTP, where applicable. */
 120         igc_ptp_reset(adapter);
 121
 122         /* Re-enable TSN offloading, where applicable. */
 123         igc_tsn_reset(adapter);
 124
 125         igc_get_phy_info(hw);
 126 }
 127
 128 /**
 129  * igc_power_up_link - Power up the phy link
 130  * @adapter: address of board private structure
 131  */
 132 static void igc_power_up_link(struct igc_adapter *adapter)
 133 {
 134         igc_reset_phy(&adapter->hw);
 135
 136         igc_power_up_phy_copper(&adapter->hw);
 137
 138         igc_setup_link(&adapter->hw);
 139 }
 140
 141 /**
 142  * igc_release_hw_control - release control of the h/w to f/w
 143  * @adapter: address of board private structure
 144  *
 145  * igc_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 146  * For ASF and Pass Through versions of f/w this means that the
 147  * driver is no longer loaded.
 148  */
 149 static void igc_release_hw_control(struct igc_adapter *adapter)
 150 {
 151         struct igc_hw *hw = &adapter->hw;
 152         u32 ctrl_ext;
 153
 154         if (!pci_device_is_present(adapter->pdev))
 155                 return;
 156
 157         /* Let firmware take over control of h/w */
 158         ctrl_ext = rd32(IGC_CTRL_EXT);
 159         wr32(IGC_CTRL_EXT,
 160              ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD);
 161 }
 162
 163 /**
 164  * igc_get_hw_control - get control of the h/w from f/w
 165  * @adapter: address of board private structure
 166  *
 167  * igc_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 168  * For ASF and Pass Through versions of f/w this means that
 169  * the driver is loaded.
 170  */
 171 static void igc_get_hw_control(struct igc_adapter *adapter)
 172 {
 173         struct igc_hw *hw = &adapter->hw;
 174         u32 ctrl_ext;
 175
 176         /* Let firmware know the driver has taken over */
 177         ctrl_ext = rd32(IGC_CTRL_EXT);
 178         wr32(IGC_CTRL_EXT,
 179              ctrl_ext | IGC_CTRL_EXT_DRV_LOAD);
 180 }
 181
 182 static void igc_unmap_tx_buffer(struct device *dev, struct igc_tx_buffer *buf)
 183 {
 184         dma_unmap_single(dev, dma_unmap_addr(buf, dma),
 185                          dma_unmap_len(buf, len), DMA_TO_DEVICE);
 186
 187         dma_unmap_len_set(buf, len, 0);
 188 }
 189
 190 /**
 191  * igc_clean_tx_ring - Free Tx Buffers
 192  * @tx_ring: ring to be cleaned
 193  */
 194 static void igc_clean_tx_ring(struct igc_ring *tx_ring)
 195 {
 196         u16 i = tx_ring->next_to_clean;
 197         struct igc_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
 198         u32 xsk_frames = 0;
 199
 200         while (i != tx_ring->next_to_use) {
 201                 union igc_adv_tx_desc *eop_desc, *tx_desc;
 202
 203                 switch (tx_buffer->type) {
 204                 case IGC_TX_BUFFER_TYPE_XSK:
 205                         xsk_frames++;
 206                         break;
 207                 case IGC_TX_BUFFER_TYPE_XDP:
 208                         xdp_return_frame(tx_buffer->xdpf);
 209                         igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
 210                         break;
 211                 case IGC_TX_BUFFER_TYPE_SKB:
 212                         dev_kfree_skb_any(tx_buffer->skb);
 213                         igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
 214                         break;
 215                 default:
 216                         netdev_warn_once(tx_ring->netdev, "Unknown Tx buffer type\n");
 217                         break;
 218                 }
 219
 220                 /* check for eop_desc to determine the end of the packet */
 221                 eop_desc = tx_buffer->next_to_watch;
 222                 tx_desc = IGC_TX_DESC(tx_ring, i);
 223
 224                 /* unmap remaining buffers */
 225                 while (tx_desc != eop_desc) {
 226                         tx_buffer++;
 227                         tx_desc++;
 228                         i++;
 229                         if (unlikely(i == tx_ring->count)) {
 230                                 i = 0;
 231                                 tx_buffer = tx_ring->tx_buffer_info;
 232                                 tx_desc = IGC_TX_DESC(tx_ring, 0);
 233                         }
 234
 235                         /* unmap any remaining paged data */
 236                         if (dma_unmap_len(tx_buffer, len))
 237                                 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
 238                 }
 239
 240                 tx_buffer->next_to_watch = NULL;
 241
 242                 /* move us one more past the eop_desc for start of next pkt */
 243                 tx_buffer++;
 244                 i++;
 245                 if (unlikely(i == tx_ring->count)) {
 246                         i = 0;
 247                         tx_buffer = tx_ring->tx_buffer_info;
 248                 }
 249         }
 250
 251         if (tx_ring->xsk_pool && xsk_frames)
 252                 xsk_tx_completed(tx_ring->xsk_pool, xsk_frames);
 253
 254         /* reset BQL for queue */
 255         netdev_tx_reset_queue(txring_txq(tx_ring));
 256
 257         /* Zero out the buffer ring */
 258         memset(tx_ring->tx_buffer_info, 0,
 259                sizeof(*tx_ring->tx_buffer_info) * tx_ring->count);
 260
 261         /* Zero out the descriptor ring */
 262         memset(tx_ring->desc, 0, tx_ring->size);
 263
 264         /* reset next_to_use and next_to_clean */
 265         tx_ring->next_to_use = 0;
 266         tx_ring->next_to_clean = 0;
 267 }
 268
 269 /**
 270  * igc_free_tx_resources - Free Tx Resources per Queue
 271  * @tx_ring: Tx descriptor ring for a specific queue
 272  *
 273  * Free all transmit software resources
 274  */
 275 void igc_free_tx_resources(struct igc_ring *tx_ring)
 276 {
 277         igc_disable_tx_ring(tx_ring);
 278
 279         vfree(tx_ring->tx_buffer_info);
 280         tx_ring->tx_buffer_info = NULL;
 281
 282         /* if not set, then don't free */
 283         if (!tx_ring->desc)
 284                 return;
 285
 286         dma_free_coherent(tx_ring->dev, tx_ring->size,
 287                           tx_ring->desc, tx_ring->dma);
 288
 289         tx_ring->desc = NULL;
 290 }
 291
 292 /**
 293  * igc_free_all_tx_resources - Free Tx Resources for All Queues
 294  * @adapter: board private structure
 295  *
 296  * Free all transmit software resources
 297  */
 298 static void igc_free_all_tx_resources(struct igc_adapter *adapter)
 299 {
 300         int i;
 301
 302         for (i = 0; i < adapter->num_tx_queues; i++)
 303                 igc_free_tx_resources(adapter->tx_ring[i]);
 304 }
 305
 306 /**
 307  * igc_clean_all_tx_rings - Free Tx Buffers for all queues
 308  * @adapter: board private structure
 309  */
 310 static void igc_clean_all_tx_rings(struct igc_adapter *adapter)
 311 {
 312         int i;
 313
 314         for (i = 0; i < adapter->num_tx_queues; i++)
 315                 if (adapter->tx_ring[i])
 316                         igc_clean_tx_ring(adapter->tx_ring[i]);
 317 }
 318
 319 static void igc_disable_tx_ring_hw(struct igc_ring *ring)
 320 {
 321         struct igc_hw *hw = &ring->q_vector->adapter->hw;
 322         u8 idx = ring->reg_idx;
 323         u32 txdctl;
 324
 325         txdctl = rd32(IGC_TXDCTL(idx));
 326         txdctl &= ~IGC_TXDCTL_QUEUE_ENABLE;
 327         txdctl |= IGC_TXDCTL_SWFLUSH;
 328         wr32(IGC_TXDCTL(idx), txdctl);
 329 }
 330
 331 /**
 332  * igc_disable_all_tx_rings_hw - Disable all transmit queue operation
 333  * @adapter: board private structure
 334  */
 335 static void igc_disable_all_tx_rings_hw(struct igc_adapter *adapter)
 336 {
 337         int i;
 338
 339         for (i = 0; i < adapter->num_tx_queues; i++) {
 340                 struct igc_ring *tx_ring = adapter->tx_ring[i];
 341
 342                 igc_disable_tx_ring_hw(tx_ring);
 343         }
 344 }
 345
 346 /**
 347  * igc_setup_tx_resources - allocate Tx resources (Descriptors)
 348  * @tx_ring: tx descriptor ring (for a specific queue) to setup
 349  *
 350  * Return 0 on success, negative on failure
 351  */
 352 int igc_setup_tx_resources(struct igc_ring *tx_ring)
 353 {
 354         struct net_device *ndev = tx_ring->netdev;
 355         struct device *dev = tx_ring->dev;
 356         int size = 0;
 357
 358         size = sizeof(struct igc_tx_buffer) * tx_ring->count;
 359         tx_ring->tx_buffer_info = vzalloc(size);
 360         if (!tx_ring->tx_buffer_info)
 361                 goto err;
 362
 363         /* round up to nearest 4K */
 364         tx_ring->size = tx_ring->count * sizeof(union igc_adv_tx_desc);
 365         tx_ring->size = ALIGN(tx_ring->size, 4096);
 366
 367         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 368                                            &tx_ring->dma, GFP_KERNEL);
 369
 370         if (!tx_ring->desc)
 371                 goto err;
 372
 373         tx_ring->next_to_use = 0;
 374         tx_ring->next_to_clean = 0;
 375
 376         return 0;
 377
 378 err:
 379         vfree(tx_ring->tx_buffer_info);
 380         netdev_err(ndev, "Unable to allocate memory for Tx descriptor ring\n");
 381         return -ENOMEM;
 382 }
 383
 384 /**
 385  * igc_setup_all_tx_resources - wrapper to allocate Tx resources for all queues
 386  * @adapter: board private structure
 387  *
 388  * Return 0 on success, negative on failure
 389  */
 390 static int igc_setup_all_tx_resources(struct igc_adapter *adapter)
 391 {
 392         struct net_device *dev = adapter->netdev;
 393         int i, err = 0;
 394
 395         for (i = 0; i < adapter->num_tx_queues; i++) {
 396                 err = igc_setup_tx_resources(adapter->tx_ring[i]);
 397                 if (err) {
 398                         netdev_err(dev, "Error on Tx queue %u setup\n", i);
 399                         for (i--; i >= 0; i--)
 400                                 igc_free_tx_resources(adapter->tx_ring[i]);
 401                         break;
 402                 }
 403         }
 404
 405         return err;
 406 }
 407
 408 static void igc_clean_rx_ring_page_shared(struct igc_ring *rx_ring)
 409 {
 410         u16 i = rx_ring->next_to_clean;
 411
 412         dev_kfree_skb(rx_ring->skb);
 413         rx_ring->skb = NULL;
 414
 415         /* Free all the Rx ring sk_buffs */
 416         while (i != rx_ring->next_to_alloc) {
 417                 struct igc_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
 418
 419                 /* Invalidate cache lines that may have been written to by
 420                  * device so that we avoid corrupting memory.
 421                  */
 422                 dma_sync_single_range_for_cpu(rx_ring->dev,
 423                                               buffer_info->dma,
 424                                               buffer_info->page_offset,
 425                                               igc_rx_bufsz(rx_ring),
 426                                               DMA_FROM_DEVICE);
 427
 428                 /* free resources associated with mapping */
 429                 dma_unmap_page_attrs(rx_ring->dev,
 430                                      buffer_info->dma,
 431                                      igc_rx_pg_size(rx_ring),
 432                                      DMA_FROM_DEVICE,
 433                                      IGC_RX_DMA_ATTR);
 434                 __page_frag_cache_drain(buffer_info->page,
 435                                         buffer_info->pagecnt_bias);
 436
 437                 i++;
 438                 if (i == rx_ring->count)
 439                         i = 0;
 440         }
 441 }
 442
 443 static void igc_clean_rx_ring_xsk_pool(struct igc_ring *ring)
 444 {
 445         struct igc_rx_buffer *bi;
 446         u16 i;
 447
 448         for (i = 0; i < ring->count; i++) {
 449                 bi = &ring->rx_buffer_info[i];
 450                 if (!bi->xdp)
 451                         continue;
 452
 453                 xsk_buff_free(bi->xdp);
 454                 bi->xdp = NULL;
 455         }
 456 }
 457
 458 /**
 459  * igc_clean_rx_ring - Free Rx Buffers per Queue
 460  * @ring: ring to free buffers from
 461  */
 462 static void igc_clean_rx_ring(struct igc_ring *ring)
 463 {
 464         if (ring->xsk_pool)
 465                 igc_clean_rx_ring_xsk_pool(ring);
 466         else
 467                 igc_clean_rx_ring_page_shared(ring);
 468
 469         clear_ring_uses_large_buffer(ring);
 470
 471         ring->next_to_alloc = 0;
 472         ring->next_to_clean = 0;
 473         ring->next_to_use = 0;
 474 }
 475
 476 /**
 477  * igc_clean_all_rx_rings - Free Rx Buffers for all queues
 478  * @adapter: board private structure
 479  */
 480 static void igc_clean_all_rx_rings(struct igc_adapter *adapter)
 481 {
 482         int i;
 483
 484         for (i = 0; i < adapter->num_rx_queues; i++)
 485                 if (adapter->rx_ring[i])
 486                         igc_clean_rx_ring(adapter->rx_ring[i]);
 487 }
 488
 489 /**
 490  * igc_free_rx_resources - Free Rx Resources
 491  * @rx_ring: ring to clean the resources from
 492  *
 493  * Free all receive software resources
 494  */
 495 void igc_free_rx_resources(struct igc_ring *rx_ring)
 496 {
 497         igc_clean_rx_ring(rx_ring);
 498
 499         xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
 500
 501         vfree(rx_ring->rx_buffer_info);
 502         rx_ring->rx_buffer_info = NULL;
 503
 504         /* if not set, then don't free */
 505         if (!rx_ring->desc)
 506                 return;
 507
 508         dma_free_coherent(rx_ring->dev, rx_ring->size,
 509                           rx_ring->desc, rx_ring->dma);
 510
 511         rx_ring->desc = NULL;
 512 }
 513
 514 /**
 515  * igc_free_all_rx_resources - Free Rx Resources for All Queues
 516  * @adapter: board private structure
 517  *
 518  * Free all receive software resources
 519  */
 520 static void igc_free_all_rx_resources(struct igc_adapter *adapter)
 521 {
 522         int i;
 523
 524         for (i = 0; i < adapter->num_rx_queues; i++)
 525                 igc_free_rx_resources(adapter->rx_ring[i]);
 526 }
 527
 528 /**
 529  * igc_setup_rx_resources - allocate Rx resources (Descriptors)
 530  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
 531  *
 532  * Returns 0 on success, negative on failure
 533  */
 534 int igc_setup_rx_resources(struct igc_ring *rx_ring)
 535 {
 536         struct net_device *ndev = rx_ring->netdev;
 537         struct device *dev = rx_ring->dev;
 538         u8 index = rx_ring->queue_index;
 539         int size, desc_len, res;
 540
 541         /* XDP RX-queue info */
 542         if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq))
 543                 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
 544         res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, ndev, index,
 545                                rx_ring->q_vector->napi.napi_id);
 546         if (res < 0) {
 547                 netdev_err(ndev, "Failed to register xdp_rxq index %u\n",
 548                            index);
 549                 return res;
 550         }
 551
 552         size = sizeof(struct igc_rx_buffer) * rx_ring->count;
 553         rx_ring->rx_buffer_info = vzalloc(size);
 554         if (!rx_ring->rx_buffer_info)
 555                 goto err;
 556
 557         desc_len = sizeof(union igc_adv_rx_desc);
 558
 559         /* Round up to nearest 4K */
 560         rx_ring->size = rx_ring->count * desc_len;
 561         rx_ring->size = ALIGN(rx_ring->size, 4096);
 562
 563         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 564                                            &rx_ring->dma, GFP_KERNEL);
 565
 566         if (!rx_ring->desc)
 567                 goto err;
 568
 569         rx_ring->next_to_alloc = 0;
 570         rx_ring->next_to_clean = 0;
 571         rx_ring->next_to_use = 0;
 572
 573         return 0;
 574
 575 err:
 576         xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
 577         vfree(rx_ring->rx_buffer_info);
 578         rx_ring->rx_buffer_info = NULL;
 579         netdev_err(ndev, "Unable to allocate memory for Rx descriptor ring\n");
 580         return -ENOMEM;
 581 }
 582
 583 /**
 584  * igc_setup_all_rx_resources - wrapper to allocate Rx resources
 585  *                                (Descriptors) for all queues
 586  * @adapter: board private structure
 587  *
 588  * Return 0 on success, negative on failure
 589  */
 590 static int igc_setup_all_rx_resources(struct igc_adapter *adapter)
 591 {
 592         struct net_device *dev = adapter->netdev;
 593         int i, err = 0;
 594
 595         for (i = 0; i < adapter->num_rx_queues; i++) {
 596                 err = igc_setup_rx_resources(adapter->rx_ring[i]);
 597                 if (err) {
 598                         netdev_err(dev, "Error on Rx queue %u setup\n", i);
 599                         for (i--; i >= 0; i--)
 600                                 igc_free_rx_resources(adapter->rx_ring[i]);
 601                         break;
 602                 }
 603         }
 604
 605         return err;
 606 }
 607
 608 static struct xsk_buff_pool *igc_get_xsk_pool(struct igc_adapter *adapter,
 609                                               struct igc_ring *ring)
 610 {
 611         if (!igc_xdp_is_enabled(adapter) ||
 612             !test_bit(IGC_RING_FLAG_AF_XDP_ZC, &ring->flags))
 613                 return NULL;
 614
 615         return xsk_get_pool_from_qid(ring->netdev, ring->queue_index);
 616 }
 617
 618 /**
 619  * igc_configure_rx_ring - Configure a receive ring after Reset
 620  * @adapter: board private structure
 621  * @ring: receive ring to be configured
 622  *
 623  * Configure the Rx unit of the MAC after a reset.
 624  */
 625 static void igc_configure_rx_ring(struct igc_adapter *adapter,
 626                                   struct igc_ring *ring)
 627 {
 628         struct igc_hw *hw = &adapter->hw;
 629         union igc_adv_rx_desc *rx_desc;
 630         int reg_idx = ring->reg_idx;
 631         u32 srrctl = 0, rxdctl = 0;
 632         u64 rdba = ring->dma;
 633         u32 buf_size;
 634
 635         xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
 636         ring->xsk_pool = igc_get_xsk_pool(adapter, ring);
 637         if (ring->xsk_pool) {
 638                 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
 639                                                    MEM_TYPE_XSK_BUFF_POOL,
 640                                                    NULL));
 641                 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq);
 642         } else {
 643                 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
 644                                                    MEM_TYPE_PAGE_SHARED,
 645                                                    NULL));
 646         }
 647
 648         if (igc_xdp_is_enabled(adapter))
 649                 set_ring_uses_large_buffer(ring);
 650
 651         /* disable the queue */
 652         wr32(IGC_RXDCTL(reg_idx), 0);
 653
 654         /* Set DMA base address registers */
 655         wr32(IGC_RDBAL(reg_idx),
 656              rdba & 0x00000000ffffffffULL);
 657         wr32(IGC_RDBAH(reg_idx), rdba >> 32);
 658         wr32(IGC_RDLEN(reg_idx),
 659              ring->count * sizeof(union igc_adv_rx_desc));
 660
 661         /* initialize head and tail */
 662         ring->tail = adapter->io_addr + IGC_RDT(reg_idx);
 663         wr32(IGC_RDH(reg_idx), 0);
 664         writel(0, ring->tail);
 665
 666         /* reset next-to- use/clean to place SW in sync with hardware */
 667         ring->next_to_clean = 0;
 668         ring->next_to_use = 0;
 669
 670         if (ring->xsk_pool)
 671                 buf_size = xsk_pool_get_rx_frame_size(ring->xsk_pool);
 672         else if (ring_uses_large_buffer(ring))
 673                 buf_size = IGC_RXBUFFER_3072;
 674         else
 675                 buf_size = IGC_RXBUFFER_2048;
 676
 677         srrctl = rd32(IGC_SRRCTL(reg_idx));
 678         srrctl &= ~(IGC_SRRCTL_BSIZEPKT_MASK | IGC_SRRCTL_BSIZEHDR_MASK |
 679                     IGC_SRRCTL_DESCTYPE_MASK);
 680         srrctl |= IGC_SRRCTL_BSIZEHDR(IGC_RX_HDR_LEN);
 681         srrctl |= IGC_SRRCTL_BSIZEPKT(buf_size);
 682         srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF;
 683
 684         wr32(IGC_SRRCTL(reg_idx), srrctl);
 685
 686         rxdctl |= IGC_RX_PTHRESH;
 687         rxdctl |= IGC_RX_HTHRESH << 8;
 688         rxdctl |= IGC_RX_WTHRESH << 16;
 689
 690         /* initialize rx_buffer_info */
 691         memset(ring->rx_buffer_info, 0,
 692                sizeof(struct igc_rx_buffer) * ring->count);
 693
 694         /* initialize Rx descriptor 0 */
 695         rx_desc = IGC_RX_DESC(ring, 0);
 696         rx_desc->wb.upper.length = 0;
 697
 698         /* enable receive descriptor fetching */
 699         rxdctl |= IGC_RXDCTL_QUEUE_ENABLE;
 700
 701         wr32(IGC_RXDCTL(reg_idx), rxdctl);
 702 }
 703
 704 /**
 705  * igc_configure_rx - Configure receive Unit after Reset
 706  * @adapter: board private structure
 707  *
 708  * Configure the Rx unit of the MAC after a reset.
 709  */
 710 static void igc_configure_rx(struct igc_adapter *adapter)
 711 {
 712         int i;
 713
 714         /* Setup the HW Rx Head and Tail Descriptor Pointers and
 715          * the Base and Length of the Rx Descriptor Ring
 716          */
 717         for (i = 0; i < adapter->num_rx_queues; i++)
 718                 igc_configure_rx_ring(adapter, adapter->rx_ring[i]);
 719 }
 720
 721 /**
 722  * igc_configure_tx_ring - Configure transmit ring after Reset
 723  * @adapter: board private structure
 724  * @ring: tx ring to configure
 725  *
 726  * Configure a transmit ring after a reset.
 727  */
 728 static void igc_configure_tx_ring(struct igc_adapter *adapter,
 729                                   struct igc_ring *ring)
 730 {
 731         struct igc_hw *hw = &adapter->hw;
 732         int reg_idx = ring->reg_idx;
 733         u64 tdba = ring->dma;
 734         u32 txdctl = 0;
 735
 736         ring->xsk_pool = igc_get_xsk_pool(adapter, ring);
 737
 738         /* disable the queue */
 739         wr32(IGC_TXDCTL(reg_idx), 0);
 740         wrfl();
 741
 742         wr32(IGC_TDLEN(reg_idx),
 743              ring->count * sizeof(union igc_adv_tx_desc));
 744         wr32(IGC_TDBAL(reg_idx),
 745              tdba & 0x00000000ffffffffULL);
 746         wr32(IGC_TDBAH(reg_idx), tdba >> 32);
 747
 748         ring->tail = adapter->io_addr + IGC_TDT(reg_idx);
 749         wr32(IGC_TDH(reg_idx), 0);
 750         writel(0, ring->tail);
 751
 752         txdctl |= IGC_TX_PTHRESH;
 753         txdctl |= IGC_TX_HTHRESH << 8;
 754         txdctl |= IGC_TX_WTHRESH << 16;
 755
 756         txdctl |= IGC_TXDCTL_QUEUE_ENABLE;
 757         wr32(IGC_TXDCTL(reg_idx), txdctl);
 758 }
 759
 760 /**
 761  * igc_configure_tx - Configure transmit Unit after Reset
 762  * @adapter: board private structure
 763  *
 764  * Configure the Tx unit of the MAC after a reset.
 765  */
 766 static void igc_configure_tx(struct igc_adapter *adapter)
 767 {
 768         int i;
 769
 770         for (i = 0; i < adapter->num_tx_queues; i++)
 771                 igc_configure_tx_ring(adapter, adapter->tx_ring[i]);
 772 }
 773
 774 /**
 775  * igc_setup_mrqc - configure the multiple receive queue control registers
 776  * @adapter: Board private structure
 777  */
 778 static void igc_setup_mrqc(struct igc_adapter *adapter)
 779 {
 780         struct igc_hw *hw = &adapter->hw;
 781         u32 j, num_rx_queues;
 782         u32 mrqc, rxcsum;
 783         u32 rss_key[10];
 784
 785         netdev_rss_key_fill(rss_key, sizeof(rss_key));
 786         for (j = 0; j < 10; j++)
 787                 wr32(IGC_RSSRK(j), rss_key[j]);
 788
 789         num_rx_queues = adapter->rss_queues;
 790
 791         if (adapter->rss_indir_tbl_init != num_rx_queues) {
 792                 for (j = 0; j < IGC_RETA_SIZE; j++)
 793                         adapter->rss_indir_tbl[j] =
 794                         (j * num_rx_queues) / IGC_RETA_SIZE;
 795                 adapter->rss_indir_tbl_init = num_rx_queues;
 796         }
 797         igc_write_rss_indir_tbl(adapter);
 798
 799         /* Disable raw packet checksumming so that RSS hash is placed in
 800          * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
 801          * offloads as they are enabled by default
 802          */
 803         rxcsum = rd32(IGC_RXCSUM);
 804         rxcsum |= IGC_RXCSUM_PCSD;
 805
 806         /* Enable Receive Checksum Offload for SCTP */
 807         rxcsum |= IGC_RXCSUM_CRCOFL;
 808
 809         /* Don't need to set TUOFL or IPOFL, they default to 1 */
 810         wr32(IGC_RXCSUM, rxcsum);
 811
 812         /* Generate RSS hash based on packet types, TCP/UDP
 813          * port numbers and/or IPv4/v6 src and dst addresses
 814          */
 815         mrqc = IGC_MRQC_RSS_FIELD_IPV4 |
 816                IGC_MRQC_RSS_FIELD_IPV4_TCP |
 817                IGC_MRQC_RSS_FIELD_IPV6 |
 818                IGC_MRQC_RSS_FIELD_IPV6_TCP |
 819                IGC_MRQC_RSS_FIELD_IPV6_TCP_EX;
 820
 821         if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV4_UDP)
 822                 mrqc |= IGC_MRQC_RSS_FIELD_IPV4_UDP;
 823         if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV6_UDP)
 824                 mrqc |= IGC_MRQC_RSS_FIELD_IPV6_UDP;
 825
 826         mrqc |= IGC_MRQC_ENABLE_RSS_MQ;
 827
 828         wr32(IGC_MRQC, mrqc);
 829 }
 830
 831 /**
 832  * igc_setup_rctl - configure the receive control registers
 833  * @adapter: Board private structure
 834  */
 835 static void igc_setup_rctl(struct igc_adapter *adapter)
 836 {
 837         struct igc_hw *hw = &adapter->hw;
 838         u32 rctl;
 839
 840         rctl = rd32(IGC_RCTL);
 841
 842         rctl &= ~(3 << IGC_RCTL_MO_SHIFT);
 843         rctl &= ~(IGC_RCTL_LBM_TCVR | IGC_RCTL_LBM_MAC);
 844
 845         rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | IGC_RCTL_RDMTS_HALF |
 846                 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT);
 847
 848         /* enable stripping of CRC. Newer features require
 849          * that the HW strips the CRC.
 850          */
 851         rctl |= IGC_RCTL_SECRC;
 852
 853         /* disable store bad packets and clear size bits. */
 854         rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_SZ_256);
 855
 856         /* enable LPE to allow for reception of jumbo frames */
 857         rctl |= IGC_RCTL_LPE;
 858
 859         /* disable queue 0 to prevent tail write w/o re-config */
 860         wr32(IGC_RXDCTL(0), 0);
 861
 862         /* This is useful for sniffing bad packets. */
 863         if (adapter->netdev->features & NETIF_F_RXALL) {
 864                 /* UPE and MPE will be handled by normal PROMISC logic
 865                  * in set_rx_mode
 866                  */
 867                 rctl |= (IGC_RCTL_SBP | /* Receive bad packets */
 868                          IGC_RCTL_BAM | /* RX All Bcast Pkts */
 869                          IGC_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
 870
 871                 rctl &= ~(IGC_RCTL_DPF | /* Allow filtered pause */
 872                           IGC_RCTL_CFIEN); /* Disable VLAN CFIEN Filter */
 873         }
 874
 875         wr32(IGC_RCTL, rctl);
 876 }
 877
 878 /**
 879  * igc_setup_tctl - configure the transmit control registers
 880  * @adapter: Board private structure
 881  */
 882 static void igc_setup_tctl(struct igc_adapter *adapter)
 883 {
 884         struct igc_hw *hw = &adapter->hw;
 885         u32 tctl;
 886
 887         /* disable queue 0 which icould be enabled by default */
 888         wr32(IGC_TXDCTL(0), 0);
 889
 890         /* Program the Transmit Control Register */
 891         tctl = rd32(IGC_TCTL);
 892         tctl &= ~IGC_TCTL_CT;
 893         tctl |= IGC_TCTL_PSP | IGC_TCTL_RTLC |
 894                 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT);
 895
 896         /* Enable transmits */
 897         tctl |= IGC_TCTL_EN;
 898
 899         wr32(IGC_TCTL, tctl);
 900 }
 901
 902 /**
 903  * igc_set_mac_filter_hw() - Set MAC address filter in hardware
 904  * @adapter: Pointer to adapter where the filter should be set
 905  * @index: Filter index
 906  * @type: MAC address filter type (source or destination)
 907  * @addr: MAC address
 908  * @queue: If non-negative, queue assignment feature is enabled and frames
 909  *         matching the filter are enqueued onto 'queue'. Otherwise, queue
 910  *         assignment is disabled.
 911  */
 912 static void igc_set_mac_filter_hw(struct igc_adapter *adapter, int index,
 913                                   enum igc_mac_filter_type type,
 914                                   const u8 *addr, int queue)
 915 {
 916         struct net_device *dev = adapter->netdev;
 917         struct igc_hw *hw = &adapter->hw;
 918         u32 ral, rah;
 919
 920         if (WARN_ON(index >= hw->mac.rar_entry_count))
 921                 return;
 922
 923         ral = le32_to_cpup((__le32 *)(addr));
 924         rah = le16_to_cpup((__le16 *)(addr + 4));
 925
 926         if (type == IGC_MAC_FILTER_TYPE_SRC) {
 927                 rah &= ~IGC_RAH_ASEL_MASK;
 928                 rah |= IGC_RAH_ASEL_SRC_ADDR;
 929         }
 930
 931         if (queue >= 0) {
 932                 rah &= ~IGC_RAH_QSEL_MASK;
 933                 rah |= (queue << IGC_RAH_QSEL_SHIFT);
 934                 rah |= IGC_RAH_QSEL_ENABLE;
 935         }
 936
 937         rah |= IGC_RAH_AV;
 938
 939         wr32(IGC_RAL(index), ral);
 940         wr32(IGC_RAH(index), rah);
 941
 942         netdev_dbg(dev, "MAC address filter set in HW: index %d", index);
 943 }
 944
 945 /**
 946  * igc_clear_mac_filter_hw() - Clear MAC address filter in hardware
 947  * @adapter: Pointer to adapter where the filter should be cleared
 948  * @index: Filter index
 949  */
 950 static void igc_clear_mac_filter_hw(struct igc_adapter *adapter, int index)
 951 {
 952         struct net_device *dev = adapter->netdev;
 953         struct igc_hw *hw = &adapter->hw;
 954
 955         if (WARN_ON(index >= hw->mac.rar_entry_count))
 956                 return;
 957
 958         wr32(IGC_RAL(index), 0);
 959         wr32(IGC_RAH(index), 0);
 960
 961         netdev_dbg(dev, "MAC address filter cleared in HW: index %d", index);
 962 }
 963
 964 /* Set default MAC address for the PF in the first RAR entry */
 965 static void igc_set_default_mac_filter(struct igc_adapter *adapter)
 966 {
 967         struct net_device *dev = adapter->netdev;
 968         u8 *addr = adapter->hw.mac.addr;
 969
 970         netdev_dbg(dev, "Set default MAC address filter: address %pM", addr);
 971
 972         igc_set_mac_filter_hw(adapter, 0, IGC_MAC_FILTER_TYPE_DST, addr, -1);
 973 }
 974
 975 /**
 976  * igc_set_mac - Change the Ethernet Address of the NIC
 977  * @netdev: network interface device structure
 978  * @p: pointer to an address structure
 979  *
 980  * Returns 0 on success, negative on failure
 981  */
 982 static int igc_set_mac(struct net_device *netdev, void *p)
 983 {
 984         struct igc_adapter *adapter = netdev_priv(netdev);
 985         struct igc_hw *hw = &adapter->hw;
 986         struct sockaddr *addr = p;
 987
 988         if (!is_valid_ether_addr(addr->sa_data))
 989                 return -EADDRNOTAVAIL;
 990
 991         eth_hw_addr_set(netdev, addr->sa_data);
 992         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
 993
 994         /* set the correct pool for the new PF MAC address in entry 0 */
 995         igc_set_default_mac_filter(adapter);
 996
 997         return 0;
 998 }
 999
1000 /**
1001  *  igc_write_mc_addr_list - write multicast addresses to MTA
1002  *  @netdev: network interface device structure
1003  *
1004  *  Writes multicast address list to the MTA hash table.
1005  *  Returns: -ENOMEM on failure
1006  *           0 on no addresses written
1007  *           X on writing X addresses to MTA
1008  **/
1009 static int igc_write_mc_addr_list(struct net_device *netdev)
1010 {
1011         struct igc_adapter *adapter = netdev_priv(netdev);
1012         struct igc_hw *hw = &adapter->hw;
1013         struct netdev_hw_addr *ha;
1014         u8  *mta_list;
1015         int i;
1016
1017         if (netdev_mc_empty(netdev)) {
1018                 /* nothing to program, so clear mc list */
1019                 igc_update_mc_addr_list(hw, NULL, 0);
1020                 return 0;
1021         }
1022
1023         mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
1024         if (!mta_list)
1025                 return -ENOMEM;
1026
1027         /* The shared function expects a packed array of only addresses. */
1028         i = 0;
1029         netdev_for_each_mc_addr(ha, netdev)
1030                 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
1031
1032         igc_update_mc_addr_list(hw, mta_list, i);
1033         kfree(mta_list);
1034
1035         return netdev_mc_count(netdev);
1036 }
1037
1038 static __le32 igc_tx_launchtime(struct igc_ring *ring, ktime_t txtime,
1039                                 bool *first_flag, bool *insert_empty)
1040 {
1041         struct igc_adapter *adapter = netdev_priv(ring->netdev);
1042         ktime_t cycle_time = adapter->cycle_time;
1043         ktime_t base_time = adapter->base_time;
1044         ktime_t now = ktime_get_clocktai();
1045         ktime_t baset_est, end_of_cycle;
1046         s32 launchtime;
1047         s64 n;
1048
1049         n = div64_s64(ktime_sub_ns(now, base_time), cycle_time);
1050
1051         baset_est = ktime_add_ns(base_time, cycle_time * (n));
1052         end_of_cycle = ktime_add_ns(baset_est, cycle_time);
1053
1054         if (ktime_compare(txtime, end_of_cycle) >= 0) {
1055                 if (baset_est != ring->last_ff_cycle) {
1056                         *first_flag = true;
1057                         ring->last_ff_cycle = baset_est;
1058
1059                         if (ktime_compare(end_of_cycle, ring->last_tx_cycle) > 0)
1060                                 *insert_empty = true;
1061                 }
1062         }
1063
1064         /* Introducing a window at end of cycle on which packets
1065          * potentially not honor launchtime. Window of 5us chosen
1066          * considering software update the tail pointer and packets
1067          * are dma'ed to packet buffer.
1068          */
1069         if ((ktime_sub_ns(end_of_cycle, now) < 5 * NSEC_PER_USEC))
1070                 netdev_warn(ring->netdev, "Packet with txtime=%llu may not be honoured\n",
1071                             txtime);
1072
1073         ring->last_tx_cycle = end_of_cycle;
1074
1075         launchtime = ktime_sub_ns(txtime, baset_est);
1076         if (launchtime > 0)
1077                 div_s64_rem(launchtime, cycle_time, &launchtime);
1078         else
1079                 launchtime = 0;
1080
1081         return cpu_to_le32(launchtime);
1082 }
1083
1084 static int igc_init_empty_frame(struct igc_ring *ring,
1085                                 struct igc_tx_buffer *buffer,
1086                                 struct sk_buff *skb)
1087 {
1088         unsigned int size;
1089         dma_addr_t dma;
1090
1091         size = skb_headlen(skb);
1092
1093         dma = dma_map_single(ring->dev, skb->data, size, DMA_TO_DEVICE);
1094         if (dma_mapping_error(ring->dev, dma)) {
1095                 netdev_err_once(ring->netdev, "Failed to map DMA for TX\n");
1096                 return -ENOMEM;
1097         }
1098
1099         buffer->skb = skb;
1100         buffer->protocol = 0;
1101         buffer->bytecount = skb->len;
1102         buffer->gso_segs = 1;
1103         buffer->time_stamp = jiffies;
1104         dma_unmap_len_set(buffer, len, skb->len);
1105         dma_unmap_addr_set(buffer, dma, dma);
1106
1107         return 0;
1108 }
1109
1110 static int igc_init_tx_empty_descriptor(struct igc_ring *ring,
1111                                         struct sk_buff *skb,
1112                                         struct igc_tx_buffer *first)
1113 {
1114         union igc_adv_tx_desc *desc;
1115         u32 cmd_type, olinfo_status;
1116         int err;
1117
1118         if (!igc_desc_unused(ring))
1119                 return -EBUSY;
1120
1121         err = igc_init_empty_frame(ring, first, skb);
1122         if (err)
1123                 return err;
1124
1125         cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT |
1126                    IGC_ADVTXD_DCMD_IFCS | IGC_TXD_DCMD |
1127                    first->bytecount;
1128         olinfo_status = first->bytecount << IGC_ADVTXD_PAYLEN_SHIFT;
1129
1130         desc = IGC_TX_DESC(ring, ring->next_to_use);
1131         desc->read.cmd_type_len = cpu_to_le32(cmd_type);
1132         desc->read.olinfo_status = cpu_to_le32(olinfo_status);
1133         desc->read.buffer_addr = cpu_to_le64(dma_unmap_addr(first, dma));
1134
1135         netdev_tx_sent_queue(txring_txq(ring), skb->len);
1136
1137         first->next_to_watch = desc;
1138
1139         ring->next_to_use++;
1140         if (ring->next_to_use == ring->count)
1141                 ring->next_to_use = 0;
1142
1143         return 0;
1144 }
1145
1146 #define IGC_EMPTY_FRAME_SIZE 60
1147
1148 static void igc_tx_ctxtdesc(struct igc_ring *tx_ring,
1149                             __le32 launch_time, bool first_flag,
1150                             u32 vlan_macip_lens, u32 type_tucmd,
1151                             u32 mss_l4len_idx)
1152 {
1153         struct igc_adv_tx_context_desc *context_desc;
1154         u16 i = tx_ring->next_to_use;
1155
1156         context_desc = IGC_TX_CTXTDESC(tx_ring, i);
1157
1158         i++;
1159         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1160
1161         /* set bits to identify this as an advanced context descriptor */
1162         type_tucmd |= IGC_TXD_CMD_DEXT | IGC_ADVTXD_DTYP_CTXT;
1163
1164         /* For i225, context index must be unique per ring. */
1165         if (test_bit(IGC_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
1166                 mss_l4len_idx |= tx_ring->reg_idx << 4;
1167
1168         if (first_flag)
1169                 mss_l4len_idx |= IGC_ADVTXD_TSN_CNTX_FIRST;
1170
1171         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
1172         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
1173         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
1174         context_desc->launch_time       = launch_time;
1175 }
1176
1177 static void igc_tx_csum(struct igc_ring *tx_ring, struct igc_tx_buffer *first,
1178                         __le32 launch_time, bool first_flag)
1179 {
1180         struct sk_buff *skb = first->skb;
1181         u32 vlan_macip_lens = 0;
1182         u32 type_tucmd = 0;
1183
1184         if (skb->ip_summed != CHECKSUM_PARTIAL) {
1185 csum_failed:
1186                 if (!(first->tx_flags & IGC_TX_FLAGS_VLAN) &&
1187                     !tx_ring->launchtime_enable)
1188                         return;
1189                 goto no_csum;
1190         }
1191
1192         switch (skb->csum_offset) {
1193         case offsetof(struct tcphdr, check):
1194                 type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP;
1195                 fallthrough;
1196         case offsetof(struct udphdr, check):
1197                 break;
1198         case offsetof(struct sctphdr, checksum):
1199                 /* validate that this is actually an SCTP request */
1200                 if (skb_csum_is_sctp(skb)) {
1201                         type_tucmd = IGC_ADVTXD_TUCMD_L4T_SCTP;
1202                         break;
1203                 }
1204                 fallthrough;
1205         default:
1206                 skb_checksum_help(skb);
1207                 goto csum_failed;
1208         }
1209
1210         /* update TX checksum flag */
1211         first->tx_flags |= IGC_TX_FLAGS_CSUM;
1212         vlan_macip_lens = skb_checksum_start_offset(skb) -
1213                           skb_network_offset(skb);
1214 no_csum:
1215         vlan_macip_lens |= skb_network_offset(skb) << IGC_ADVTXD_MACLEN_SHIFT;
1216         vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK;
1217
1218         igc_tx_ctxtdesc(tx_ring, launch_time, first_flag,
1219                         vlan_macip_lens, type_tucmd, 0);
1220 }
1221
1222 static int __igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size)
1223 {
1224         struct net_device *netdev = tx_ring->netdev;
1225
1226         netif_stop_subqueue(netdev, tx_ring->queue_index);
1227
1228         /* memory barriier comment */
1229         smp_mb();
1230
1231         /* We need to check again in a case another CPU has just
1232          * made room available.
1233          */
1234         if (igc_desc_unused(tx_ring) < size)
1235                 return -EBUSY;
1236
1237         /* A reprieve! */
1238         netif_wake_subqueue(netdev, tx_ring->queue_index);
1239
1240         u64_stats_update_begin(&tx_ring->tx_syncp2);
1241         tx_ring->tx_stats.restart_queue2++;
1242         u64_stats_update_end(&tx_ring->tx_syncp2);
1243
1244         return 0;
1245 }
1246
1247 static inline int igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size)
1248 {
1249         if (igc_desc_unused(tx_ring) >= size)
1250                 return 0;
1251         return __igc_maybe_stop_tx(tx_ring, size);
1252 }
1253
1254 #define IGC_SET_FLAG(_input, _flag, _result) \
1255         (((_flag) <= (_result)) ?                               \
1256          ((u32)((_input) & (_flag)) * ((_result) / (_flag))) :  \
1257          ((u32)((_input) & (_flag)) / ((_flag) / (_result))))
1258
1259 static u32 igc_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
1260 {
1261         /* set type for advanced descriptor with frame checksum insertion */
1262         u32 cmd_type = IGC_ADVTXD_DTYP_DATA |
1263                        IGC_ADVTXD_DCMD_DEXT |
1264                        IGC_ADVTXD_DCMD_IFCS;
1265
1266         /* set HW vlan bit if vlan is present */
1267         cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_VLAN,
1268                                  IGC_ADVTXD_DCMD_VLE);
1269
1270         /* set segmentation bits for TSO */
1271         cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSO,
1272                                  (IGC_ADVTXD_DCMD_TSE));
1273
1274         /* set timestamp bit if present, will select the register set
1275          * based on the _TSTAMP(_X) bit.
1276          */
1277         cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP,
1278                                  (IGC_ADVTXD_MAC_TSTAMP));
1279
1280         cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_1,
1281                                  (IGC_ADVTXD_TSTAMP_REG_1));
1282
1283         cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_2,
1284                                  (IGC_ADVTXD_TSTAMP_REG_2));
1285
1286         cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_3,
1287                                  (IGC_ADVTXD_TSTAMP_REG_3));
1288
1289         /* insert frame checksum */
1290         cmd_type ^= IGC_SET_FLAG(skb->no_fcs, 1, IGC_ADVTXD_DCMD_IFCS);
1291
1292         return cmd_type;
1293 }
1294
1295 static void igc_tx_olinfo_status(struct igc_ring *tx_ring,
1296                                  union igc_adv_tx_desc *tx_desc,
1297                                  u32 tx_flags, unsigned int paylen)
1298 {
1299         u32 olinfo_status = paylen << IGC_ADVTXD_PAYLEN_SHIFT;
1300
1301         /* insert L4 checksum */
1302         olinfo_status |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_CSUM,
1303                                       (IGC_TXD_POPTS_TXSM << 8));
1304
1305         /* insert IPv4 checksum */
1306         olinfo_status |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_IPV4,
1307                                       (IGC_TXD_POPTS_IXSM << 8));
1308
1309         /* Use the second timer (free running, in general) for the timestamp */
1310         olinfo_status |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_TIMER_1,
1311                                       IGC_TXD_PTP2_TIMER_1);
1312
1313         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
1314 }
1315
1316 static int igc_tx_map(struct igc_ring *tx_ring,
1317                       struct igc_tx_buffer *first,
1318                       const u8 hdr_len)
1319 {
1320         struct sk_buff *skb = first->skb;
1321         struct igc_tx_buffer *tx_buffer;
1322         union igc_adv_tx_desc *tx_desc;
1323         u32 tx_flags = first->tx_flags;
1324         skb_frag_t *frag;
1325         u16 i = tx_ring->next_to_use;
1326         unsigned int data_len, size;
1327         dma_addr_t dma;
1328         u32 cmd_type;
1329
1330         cmd_type = igc_tx_cmd_type(skb, tx_flags);
1331         tx_desc = IGC_TX_DESC(tx_ring, i);
1332
1333         igc_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
1334
1335         size = skb_headlen(skb);
1336         data_len = skb->data_len;
1337
1338         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1339
1340         tx_buffer = first;
1341
1342         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1343                 if (dma_mapping_error(tx_ring->dev, dma))
1344                         goto dma_error;
1345
1346                 /* record length, and DMA address */
1347                 dma_unmap_len_set(tx_buffer, len, size);
1348                 dma_unmap_addr_set(tx_buffer, dma, dma);
1349
1350                 tx_desc->read.buffer_addr = cpu_to_le64(dma);
1351
1352                 while (unlikely(size > IGC_MAX_DATA_PER_TXD)) {
1353                         tx_desc->read.cmd_type_len =
1354                                 cpu_to_le32(cmd_type ^ IGC_MAX_DATA_PER_TXD);
1355
1356                         i++;
1357                         tx_desc++;
1358                         if (i == tx_ring->count) {
1359                                 tx_desc = IGC_TX_DESC(tx_ring, 0);
1360                                 i = 0;
1361                         }
1362                         tx_desc->read.olinfo_status = 0;
1363
1364                         dma += IGC_MAX_DATA_PER_TXD;
1365                         size -= IGC_MAX_DATA_PER_TXD;
1366
1367                         tx_desc->read.buffer_addr = cpu_to_le64(dma);
1368                 }
1369
1370                 if (likely(!data_len))
1371                         break;
1372
1373                 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
1374
1375                 i++;
1376                 tx_desc++;
1377                 if (i == tx_ring->count) {
1378                         tx_desc = IGC_TX_DESC(tx_ring, 0);
1379                         i = 0;
1380                 }
1381                 tx_desc->read.olinfo_status = 0;
1382
1383                 size = skb_frag_size(frag);
1384                 data_len -= size;
1385
1386                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
1387                                        size, DMA_TO_DEVICE);
1388
1389                 tx_buffer = &tx_ring->tx_buffer_info[i];
1390         }
1391
1392         /* write last descriptor with RS and EOP bits */
1393         cmd_type |= size | IGC_TXD_DCMD;
1394         tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
1395
1396         netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
1397
1398         /* set the timestamp */
1399         first->time_stamp = jiffies;
1400
1401         skb_tx_timestamp(skb);
1402
1403         /* Force memory writes to complete before letting h/w know there
1404          * are new descriptors to fetch.  (Only applicable for weak-ordered
1405          * memory model archs, such as IA-64).
1406          *
1407          * We also need this memory barrier to make certain all of the
1408          * status bits have been updated before next_to_watch is written.
1409          */
1410         wmb();
1411
1412         /* set next_to_watch value indicating a packet is present */
1413         first->next_to_watch = tx_desc;
1414
1415         i++;
1416         if (i == tx_ring->count)
1417                 i = 0;
1418
1419         tx_ring->next_to_use = i;
1420
1421         /* Make sure there is space in the ring for the next send. */
1422         igc_maybe_stop_tx(tx_ring, DESC_NEEDED);
1423
1424         if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
1425                 writel(i, tx_ring->tail);
1426         }
1427
1428         return 0;
1429 dma_error:
1430         netdev_err(tx_ring->netdev, "TX DMA map failed\n");
1431         tx_buffer = &tx_ring->tx_buffer_info[i];
1432
1433         /* clear dma mappings for failed tx_buffer_info map */
1434         while (tx_buffer != first) {
1435                 if (dma_unmap_len(tx_buffer, len))
1436                         igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
1437
1438                 if (i-- == 0)
1439                         i += tx_ring->count;
1440                 tx_buffer = &tx_ring->tx_buffer_info[i];
1441         }
1442
1443         if (dma_unmap_len(tx_buffer, len))
1444                 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
1445
1446         dev_kfree_skb_any(tx_buffer->skb);
1447         tx_buffer->skb = NULL;
1448
1449         tx_ring->next_to_use = i;
1450
1451         return -1;
1452 }
1453
1454 static int igc_tso(struct igc_ring *tx_ring,
1455                    struct igc_tx_buffer *first,
1456                    __le32 launch_time, bool first_flag,
1457                    u8 *hdr_len)
1458 {
1459         u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
1460         struct sk_buff *skb = first->skb;
1461         union {
1462                 struct iphdr *v4;
1463                 struct ipv6hdr *v6;
1464                 unsigned char *hdr;
1465         } ip;
1466         union {
1467                 struct tcphdr *tcp;
1468                 struct udphdr *udp;
1469                 unsigned char *hdr;
1470         } l4;
1471         u32 paylen, l4_offset;
1472         int err;
1473
1474         if (skb->ip_summed != CHECKSUM_PARTIAL)
1475                 return 0;
1476
1477         if (!skb_is_gso(skb))
1478                 return 0;
1479
1480         err = skb_cow_head(skb, 0);
1481         if (err < 0)
1482                 return err;
1483
1484         ip.hdr = skb_network_header(skb);
1485         l4.hdr = skb_checksum_start(skb);
1486
1487         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
1488         type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP;
1489
1490         /* initialize outer IP header fields */
1491         if (ip.v4->version == 4) {
1492                 unsigned char *csum_start = skb_checksum_start(skb);
1493                 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
1494
1495                 /* IP header will have to cancel out any data that
1496                  * is not a part of the outer IP header
1497                  */
1498                 ip.v4->check = csum_fold(csum_partial(trans_start,
1499                                                       csum_start - trans_start,
1500                                                       0));
1501                 type_tucmd |= IGC_ADVTXD_TUCMD_IPV4;
1502
1503                 ip.v4->tot_len = 0;
1504                 first->tx_flags |= IGC_TX_FLAGS_TSO |
1505                                    IGC_TX_FLAGS_CSUM |
1506                                    IGC_TX_FLAGS_IPV4;
1507         } else {
1508                 ip.v6->payload_len = 0;
1509                 first->tx_flags |= IGC_TX_FLAGS_TSO |
1510                                    IGC_TX_FLAGS_CSUM;
1511         }
1512
1513         /* determine offset of inner transport header */
1514         l4_offset = l4.hdr - skb->data;
1515
1516         /* remove payload length from inner checksum */
1517         paylen = skb->len - l4_offset;
1518         if (type_tucmd & IGC_ADVTXD_TUCMD_L4T_TCP) {
1519                 /* compute length of segmentation header */
1520                 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
1521                 csum_replace_by_diff(&l4.tcp->check,
1522                                      (__force __wsum)htonl(paylen));
1523         } else {
1524                 /* compute length of segmentation header */
1525                 *hdr_len = sizeof(*l4.udp) + l4_offset;
1526                 csum_replace_by_diff(&l4.udp->check,
1527                                      (__force __wsum)htonl(paylen));
1528         }
1529
1530         /* update gso size and bytecount with header size */
1531         first->gso_segs = skb_shinfo(skb)->gso_segs;
1532         first->bytecount += (first->gso_segs - 1) * *hdr_len;
1533
1534         /* MSS L4LEN IDX */
1535         mss_l4len_idx = (*hdr_len - l4_offset) << IGC_ADVTXD_L4LEN_SHIFT;
1536         mss_l4len_idx |= skb_shinfo(skb)->gso_size << IGC_ADVTXD_MSS_SHIFT;
1537
1538         /* VLAN MACLEN IPLEN */
1539         vlan_macip_lens = l4.hdr - ip.hdr;
1540         vlan_macip_lens |= (ip.hdr - skb->data) << IGC_ADVTXD_MACLEN_SHIFT;
1541         vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK;
1542
1543         igc_tx_ctxtdesc(tx_ring, launch_time, first_flag,
1544                         vlan_macip_lens, type_tucmd, mss_l4len_idx);
1545
1546         return 1;
1547 }
1548
1549 static bool igc_request_tx_tstamp(struct igc_adapter *adapter, struct sk_buff *skb, u32 *flags)
1550 {
1551         int i;
1552
1553         for (i = 0; i < IGC_MAX_TX_TSTAMP_REGS; i++) {
1554                 struct igc_tx_timestamp_request *tstamp = &adapter->tx_tstamp[i];
1555
1556                 if (tstamp->skb)
1557                         continue;
1558
1559                 tstamp->skb = skb_get(skb);
1560                 tstamp->start = jiffies;
1561                 *flags = tstamp->flags;
1562
1563                 return true;
1564         }
1565
1566         return false;
1567 }
1568
1569 static netdev_tx_t igc_xmit_frame_ring(struct sk_buff *skb,
1570                                        struct igc_ring *tx_ring)
1571 {
1572         struct igc_adapter *adapter = netdev_priv(tx_ring->netdev);
1573         bool first_flag = false, insert_empty = false;
1574         u16 count = TXD_USE_COUNT(skb_headlen(skb));
1575         __be16 protocol = vlan_get_protocol(skb);
1576         struct igc_tx_buffer *first;
1577         __le32 launch_time = 0;
1578         u32 tx_flags = 0;
1579         unsigned short f;
1580         ktime_t txtime;
1581         u8 hdr_len = 0;
1582         int tso = 0;
1583
1584         /* need: 1 descriptor per page * PAGE_SIZE/IGC_MAX_DATA_PER_TXD,
1585          *      + 1 desc for skb_headlen/IGC_MAX_DATA_PER_TXD,
1586          *      + 2 desc gap to keep tail from touching head,
1587          *      + 1 desc for context descriptor,
1588          * otherwise try next time
1589          */
1590         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1591                 count += TXD_USE_COUNT(skb_frag_size(
1592                                                 &skb_shinfo(skb)->frags[f]));
1593
1594         if (igc_maybe_stop_tx(tx_ring, count + 5)) {
1595                 /* this is a hard error */
1596                 return NETDEV_TX_BUSY;
1597         }
1598
1599         if (!tx_ring->launchtime_enable)
1600                 goto done;
1601
1602         txtime = skb->tstamp;
1603         skb->tstamp = ktime_set(0, 0);
1604         launch_time = igc_tx_launchtime(tx_ring, txtime, &first_flag, &insert_empty);
1605
1606         if (insert_empty) {
1607                 struct igc_tx_buffer *empty_info;
1608                 struct sk_buff *empty;
1609                 void *data;
1610
1611                 empty_info = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
1612                 empty = alloc_skb(IGC_EMPTY_FRAME_SIZE, GFP_ATOMIC);
1613                 if (!empty)
1614                         goto done;
1615
1616                 data = skb_put(empty, IGC_EMPTY_FRAME_SIZE);
1617                 memset(data, 0, IGC_EMPTY_FRAME_SIZE);
1618
1619                 igc_tx_ctxtdesc(tx_ring, 0, false, 0, 0, 0);
1620
1621                 if (igc_init_tx_empty_descriptor(tx_ring,
1622                                                  empty,
1623                                                  empty_info) < 0)
1624                         dev_kfree_skb_any(empty);
1625         }
1626
1627 done:
1628         /* record the location of the first descriptor for this packet */
1629         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
1630         first->type = IGC_TX_BUFFER_TYPE_SKB;
1631         first->skb = skb;
1632         first->bytecount = skb->len;
1633         first->gso_segs = 1;
1634
1635         if (adapter->qbv_transition || tx_ring->oper_gate_closed)
1636                 goto out_drop;
1637
1638         if (tx_ring->max_sdu > 0 && first->bytecount > tx_ring->max_sdu) {
1639                 adapter->stats.txdrop++;
1640                 goto out_drop;
1641         }
1642
1643         if (unlikely(test_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags) &&
1644                      skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
1645                 unsigned long flags;
1646                 u32 tstamp_flags;
1647
1648                 spin_lock_irqsave(&adapter->ptp_tx_lock, flags);
1649                 if (igc_request_tx_tstamp(adapter, skb, &tstamp_flags)) {
1650                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1651                         tx_flags |= IGC_TX_FLAGS_TSTAMP | tstamp_flags;
1652                         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP_USE_CYCLES)
1653                                 tx_flags |= IGC_TX_FLAGS_TSTAMP_TIMER_1;
1654                 } else {
1655                         adapter->tx_hwtstamp_skipped++;
1656                 }
1657
1658                 spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags);
1659         }
1660
1661         if (skb_vlan_tag_present(skb)) {
1662                 tx_flags |= IGC_TX_FLAGS_VLAN;
1663                 tx_flags |= (skb_vlan_tag_get(skb) << IGC_TX_FLAGS_VLAN_SHIFT);
1664         }
1665
1666         /* record initial flags and protocol */
1667         first->tx_flags = tx_flags;
1668         first->protocol = protocol;
1669
1670         tso = igc_tso(tx_ring, first, launch_time, first_flag, &hdr_len);
1671         if (tso < 0)
1672                 goto out_drop;
1673         else if (!tso)
1674                 igc_tx_csum(tx_ring, first, launch_time, first_flag);
1675
1676         igc_tx_map(tx_ring, first, hdr_len);
1677
1678         return NETDEV_TX_OK;
1679
1680 out_drop:
1681         dev_kfree_skb_any(first->skb);
1682         first->skb = NULL;
1683
1684         return NETDEV_TX_OK;
1685 }
1686
1687 static inline struct igc_ring *igc_tx_queue_mapping(struct igc_adapter *adapter,
1688                                                     struct sk_buff *skb)
1689 {
1690         unsigned int r_idx = skb->queue_mapping;
1691
1692         if (r_idx >= adapter->num_tx_queues)
1693                 r_idx = r_idx % adapter->num_tx_queues;
1694
1695         return adapter->tx_ring[r_idx];
1696 }
1697
1698 static netdev_tx_t igc_xmit_frame(struct sk_buff *skb,
1699                                   struct net_device *netdev)
1700 {
1701         struct igc_adapter *adapter = netdev_priv(netdev);
1702
1703         /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1704          * in order to meet this minimum size requirement.
1705          */
1706         if (skb->len < 17) {
1707                 if (skb_padto(skb, 17))
1708                         return NETDEV_TX_OK;
1709                 skb->len = 17;
1710         }
1711
1712         return igc_xmit_frame_ring(skb, igc_tx_queue_mapping(adapter, skb));
1713 }
1714
1715 static void igc_rx_checksum(struct igc_ring *ring,
1716                             union igc_adv_rx_desc *rx_desc,
1717                             struct sk_buff *skb)
1718 {
1719         skb_checksum_none_assert(skb);
1720
1721         /* Ignore Checksum bit is set */
1722         if (igc_test_staterr(rx_desc, IGC_RXD_STAT_IXSM))
1723                 return;
1724
1725         /* Rx checksum disabled via ethtool */
1726         if (!(ring->netdev->features & NETIF_F_RXCSUM))
1727                 return;
1728
1729         /* TCP/UDP checksum error bit is set */
1730         if (igc_test_staterr(rx_desc,
1731                              IGC_RXDEXT_STATERR_L4E |
1732                              IGC_RXDEXT_STATERR_IPE)) {
1733                 /* work around errata with sctp packets where the TCPE aka
1734                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
1735                  * packets (aka let the stack check the crc32c)
1736                  */
1737                 if (!(skb->len == 60 &&
1738                       test_bit(IGC_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
1739                         u64_stats_update_begin(&ring->rx_syncp);
1740                         ring->rx_stats.csum_err++;
1741                         u64_stats_update_end(&ring->rx_syncp);
1742                 }
1743                 /* let the stack verify checksum errors */
1744                 return;
1745         }
1746         /* It must be a TCP or UDP packet with a valid checksum */
1747         if (igc_test_staterr(rx_desc, IGC_RXD_STAT_TCPCS |
1748                                       IGC_RXD_STAT_UDPCS))
1749                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1750
1751         netdev_dbg(ring->netdev, "cksum success: bits %08X\n",
1752                    le32_to_cpu(rx_desc->wb.upper.status_error));
1753 }
1754
1755 /* Mapping HW RSS Type to enum pkt_hash_types */
1756 static const enum pkt_hash_types igc_rss_type_table[IGC_RSS_TYPE_MAX_TABLE] = {
1757         [IGC_RSS_TYPE_NO_HASH]          = PKT_HASH_TYPE_L2,
1758         [IGC_RSS_TYPE_HASH_TCP_IPV4]    = PKT_HASH_TYPE_L4,
1759         [IGC_RSS_TYPE_HASH_IPV4]        = PKT_HASH_TYPE_L3,
1760         [IGC_RSS_TYPE_HASH_TCP_IPV6]    = PKT_HASH_TYPE_L4,
1761         [IGC_RSS_TYPE_HASH_IPV6_EX]     = PKT_HASH_TYPE_L3,
1762         [IGC_RSS_TYPE_HASH_IPV6]        = PKT_HASH_TYPE_L3,
1763         [IGC_RSS_TYPE_HASH_TCP_IPV6_EX] = PKT_HASH_TYPE_L4,
1764         [IGC_RSS_TYPE_HASH_UDP_IPV4]    = PKT_HASH_TYPE_L4,
1765         [IGC_RSS_TYPE_HASH_UDP_IPV6]    = PKT_HASH_TYPE_L4,
1766         [IGC_RSS_TYPE_HASH_UDP_IPV6_EX] = PKT_HASH_TYPE_L4,
1767         [10] = PKT_HASH_TYPE_NONE, /* RSS Type above 9 "Reserved" by HW  */
1768         [11] = PKT_HASH_TYPE_NONE, /* keep array sized for SW bit-mask   */
1769         [12] = PKT_HASH_TYPE_NONE, /* to handle future HW revisons       */
1770         [13] = PKT_HASH_TYPE_NONE,
1771         [14] = PKT_HASH_TYPE_NONE,
1772         [15] = PKT_HASH_TYPE_NONE,
1773 };
1774
1775 static inline void igc_rx_hash(struct igc_ring *ring,
1776                                union igc_adv_rx_desc *rx_desc,
1777                                struct sk_buff *skb)
1778 {
1779         if (ring->netdev->features & NETIF_F_RXHASH) {
1780                 u32 rss_hash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1781                 u32 rss_type = igc_rss_type(rx_desc);
1782
1783                 skb_set_hash(skb, rss_hash, igc_rss_type_table[rss_type]);
1784         }
1785 }
1786
1787 static void igc_rx_vlan(struct igc_ring *rx_ring,
1788                         union igc_adv_rx_desc *rx_desc,
1789                         struct sk_buff *skb)
1790 {
1791         struct net_device *dev = rx_ring->netdev;
1792         u16 vid;
1793
1794         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1795             igc_test_staterr(rx_desc, IGC_RXD_STAT_VP)) {
1796                 if (igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_LB) &&
1797                     test_bit(IGC_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
1798                         vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan);
1799                 else
1800                         vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1801
1802                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1803         }
1804 }
1805
1806 /**
1807  * igc_process_skb_fields - Populate skb header fields from Rx descriptor
1808  * @rx_ring: rx descriptor ring packet is being transacted on
1809  * @rx_desc: pointer to the EOP Rx descriptor
1810  * @skb: pointer to current skb being populated
1811  *
1812  * This function checks the ring, descriptor, and packet information in order
1813  * to populate the hash, checksum, VLAN, protocol, and other fields within the
1814  * skb.
1815  */
1816 static void igc_process_skb_fields(struct igc_ring *rx_ring,
1817                                    union igc_adv_rx_desc *rx_desc,
1818                                    struct sk_buff *skb)
1819 {
1820         igc_rx_hash(rx_ring, rx_desc, skb);
1821
1822         igc_rx_checksum(rx_ring, rx_desc, skb);
1823
1824         igc_rx_vlan(rx_ring, rx_desc, skb);
1825
1826         skb_record_rx_queue(skb, rx_ring->queue_index);
1827
1828         skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1829 }
1830
1831 static void igc_vlan_mode(struct net_device *netdev, netdev_features_t features)
1832 {
1833         bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1834         struct igc_adapter *adapter = netdev_priv(netdev);
1835         struct igc_hw *hw = &adapter->hw;
1836         u32 ctrl;
1837
1838         ctrl = rd32(IGC_CTRL);
1839
1840         if (enable) {
1841                 /* enable VLAN tag insert/strip */
1842                 ctrl |= IGC_CTRL_VME;
1843         } else {
1844                 /* disable VLAN tag insert/strip */
1845                 ctrl &= ~IGC_CTRL_VME;
1846         }
1847         wr32(IGC_CTRL, ctrl);
1848 }
1849
1850 static void igc_restore_vlan(struct igc_adapter *adapter)
1851 {
1852         igc_vlan_mode(adapter->netdev, adapter->netdev->features);
1853 }
1854
1855 static struct igc_rx_buffer *igc_get_rx_buffer(struct igc_ring *rx_ring,
1856                                                const unsigned int size,
1857                                                int *rx_buffer_pgcnt)
1858 {
1859         struct igc_rx_buffer *rx_buffer;
1860
1861         rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1862         *rx_buffer_pgcnt =
1863 #if (PAGE_SIZE < 8192)
1864                 page_count(rx_buffer->page);
1865 #else
1866                 0;
1867 #endif
1868         prefetchw(rx_buffer->page);
1869
1870         /* we are reusing so sync this buffer for CPU use */
1871         dma_sync_single_range_for_cpu(rx_ring->dev,
1872                                       rx_buffer->dma,
1873                                       rx_buffer->page_offset,
1874                                       size,
1875                                       DMA_FROM_DEVICE);
1876
1877         rx_buffer->pagecnt_bias--;
1878
1879         return rx_buffer;
1880 }
1881
1882 static void igc_rx_buffer_flip(struct igc_rx_buffer *buffer,
1883                                unsigned int truesize)
1884 {
1885 #if (PAGE_SIZE < 8192)
1886         buffer->page_offset ^= truesize;
1887 #else
1888         buffer->page_offset += truesize;
1889 #endif
1890 }
1891
1892 static unsigned int igc_get_rx_frame_truesize(struct igc_ring *ring,
1893                                               unsigned int size)
1894 {
1895         unsigned int truesize;
1896
1897 #if (PAGE_SIZE < 8192)
1898         truesize = igc_rx_pg_size(ring) / 2;
1899 #else
1900         truesize = ring_uses_build_skb(ring) ?
1901                    SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1902                    SKB_DATA_ALIGN(IGC_SKB_PAD + size) :
1903                    SKB_DATA_ALIGN(size);
1904 #endif
1905         return truesize;
1906 }
1907
1908 /**
1909  * igc_add_rx_frag - Add contents of Rx buffer to sk_buff
1910  * @rx_ring: rx descriptor ring to transact packets on
1911  * @rx_buffer: buffer containing page to add
1912  * @skb: sk_buff to place the data into
1913  * @size: size of buffer to be added
1914  *
1915  * This function will add the data contained in rx_buffer->page to the skb.
1916  */
1917 static void igc_add_rx_frag(struct igc_ring *rx_ring,
1918                             struct igc_rx_buffer *rx_buffer,
1919                             struct sk_buff *skb,
1920                             unsigned int size)
1921 {
1922         unsigned int truesize;
1923
1924 #if (PAGE_SIZE < 8192)
1925         truesize = igc_rx_pg_size(rx_ring) / 2;
1926 #else
1927         truesize = ring_uses_build_skb(rx_ring) ?
1928                    SKB_DATA_ALIGN(IGC_SKB_PAD + size) :
1929                    SKB_DATA_ALIGN(size);
1930 #endif
1931         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
1932                         rx_buffer->page_offset, size, truesize);
1933
1934         igc_rx_buffer_flip(rx_buffer, truesize);
1935 }
1936
1937 static struct sk_buff *igc_build_skb(struct igc_ring *rx_ring,
1938                                      struct igc_rx_buffer *rx_buffer,
1939                                      struct xdp_buff *xdp)
1940 {
1941         unsigned int size = xdp->data_end - xdp->data;
1942         unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size);
1943         unsigned int metasize = xdp->data - xdp->data_meta;
1944         struct sk_buff *skb;
1945
1946         /* prefetch first cache line of first page */
1947         net_prefetch(xdp->data_meta);
1948
1949         /* build an skb around the page buffer */
1950         skb = napi_build_skb(xdp->data_hard_start, truesize);
1951         if (unlikely(!skb))
1952                 return NULL;
1953
1954         /* update pointers within the skb to store the data */
1955         skb_reserve(skb, xdp->data - xdp->data_hard_start);
1956         __skb_put(skb, size);
1957         if (metasize)
1958                 skb_metadata_set(skb, metasize);
1959
1960         igc_rx_buffer_flip(rx_buffer, truesize);
1961         return skb;
1962 }
1963
1964 static struct sk_buff *igc_construct_skb(struct igc_ring *rx_ring,
1965                                          struct igc_rx_buffer *rx_buffer,
1966                                          struct igc_xdp_buff *ctx)
1967 {
1968         struct xdp_buff *xdp = &ctx->xdp;
1969         unsigned int metasize = xdp->data - xdp->data_meta;
1970         unsigned int size = xdp->data_end - xdp->data;
1971         unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size);
1972         void *va = xdp->data;
1973         unsigned int headlen;
1974         struct sk_buff *skb;
1975
1976         /* prefetch first cache line of first page */
1977         net_prefetch(xdp->data_meta);
1978
1979         /* allocate a skb to store the frags */
1980         skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1981                              IGC_RX_HDR_LEN + metasize);
1982         if (unlikely(!skb))
1983                 return NULL;
1984
1985         if (ctx->rx_ts) {
1986                 skb_shinfo(skb)->tx_flags |= SKBTX_HW_TSTAMP_NETDEV;
1987                 skb_hwtstamps(skb)->netdev_data = ctx->rx_ts;
1988         }
1989
1990         /* Determine available headroom for copy */
1991         headlen = size;
1992         if (headlen > IGC_RX_HDR_LEN)
1993                 headlen = eth_get_headlen(skb->dev, va, IGC_RX_HDR_LEN);
1994
1995         /* align pull length to size of long to optimize memcpy performance */
1996         memcpy(__skb_put(skb, headlen + metasize), xdp->data_meta,
1997                ALIGN(headlen + metasize, sizeof(long)));
1998
1999         if (metasize) {
2000                 skb_metadata_set(skb, metasize);
2001                 __skb_pull(skb, metasize);
2002         }
2003
2004         /* update all of the pointers */
2005         size -= headlen;
2006         if (size) {
2007                 skb_add_rx_frag(skb, 0, rx_buffer->page,
2008                                 (va + headlen) - page_address(rx_buffer->page),
2009                                 size, truesize);
2010                 igc_rx_buffer_flip(rx_buffer, truesize);
2011         } else {
2012                 rx_buffer->pagecnt_bias++;
2013         }
2014
2015         return skb;
2016 }
2017
2018 /**
2019  * igc_reuse_rx_page - page flip buffer and store it back on the ring
2020  * @rx_ring: rx descriptor ring to store buffers on
2021  * @old_buff: donor buffer to have page reused
2022  *
2023  * Synchronizes page for reuse by the adapter
2024  */
2025 static void igc_reuse_rx_page(struct igc_ring *rx_ring,
2026                               struct igc_rx_buffer *old_buff)
2027 {
2028         u16 nta = rx_ring->next_to_alloc;
2029         struct igc_rx_buffer *new_buff;
2030
2031         new_buff = &rx_ring->rx_buffer_info[nta];
2032
2033         /* update, and store next to alloc */
2034         nta++;
2035         rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
2036
2037         /* Transfer page from old buffer to new buffer.
2038          * Move each member individually to avoid possible store
2039          * forwarding stalls.
2040          */
2041         new_buff->dma           = old_buff->dma;
2042         new_buff->page          = old_buff->page;
2043         new_buff->page_offset   = old_buff->page_offset;
2044         new_buff->pagecnt_bias  = old_buff->pagecnt_bias;
2045 }
2046
2047 static bool igc_can_reuse_rx_page(struct igc_rx_buffer *rx_buffer,
2048                                   int rx_buffer_pgcnt)
2049 {
2050         unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
2051         struct page *page = rx_buffer->page;
2052
2053         /* avoid re-using remote and pfmemalloc pages */
2054         if (!dev_page_is_reusable(page))
2055                 return false;
2056
2057 #if (PAGE_SIZE < 8192)
2058         /* if we are only owner of page we can reuse it */
2059         if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1))
2060                 return false;
2061 #else
2062 #define IGC_LAST_OFFSET \
2063         (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGC_RXBUFFER_2048)
2064
2065         if (rx_buffer->page_offset > IGC_LAST_OFFSET)
2066                 return false;
2067 #endif
2068
2069         /* If we have drained the page fragment pool we need to update
2070          * the pagecnt_bias and page count so that we fully restock the
2071          * number of references the driver holds.
2072          */
2073         if (unlikely(pagecnt_bias == 1)) {
2074                 page_ref_add(page, USHRT_MAX - 1);
2075                 rx_buffer->pagecnt_bias = USHRT_MAX;
2076         }
2077
2078         return true;
2079 }
2080
2081 /**
2082  * igc_is_non_eop - process handling of non-EOP buffers
2083  * @rx_ring: Rx ring being processed
2084  * @rx_desc: Rx descriptor for current buffer
2085  *
2086  * This function updates next to clean.  If the buffer is an EOP buffer
2087  * this function exits returning false, otherwise it will place the
2088  * sk_buff in the next buffer to be chained and return true indicating
2089  * that this is in fact a non-EOP buffer.
2090  */
2091 static bool igc_is_non_eop(struct igc_ring *rx_ring,
2092                            union igc_adv_rx_desc *rx_desc)
2093 {
2094         u32 ntc = rx_ring->next_to_clean + 1;
2095
2096         /* fetch, update, and store next to clean */
2097         ntc = (ntc < rx_ring->count) ? ntc : 0;
2098         rx_ring->next_to_clean = ntc;
2099
2100         prefetch(IGC_RX_DESC(rx_ring, ntc));
2101
2102         if (likely(igc_test_staterr(rx_desc, IGC_RXD_STAT_EOP)))
2103                 return false;
2104
2105         return true;
2106 }
2107
2108 /**
2109  * igc_cleanup_headers - Correct corrupted or empty headers
2110  * @rx_ring: rx descriptor ring packet is being transacted on
2111  * @rx_desc: pointer to the EOP Rx descriptor
2112  * @skb: pointer to current skb being fixed
2113  *
2114  * Address the case where we are pulling data in on pages only
2115  * and as such no data is present in the skb header.
2116  *
2117  * In addition if skb is not at least 60 bytes we need to pad it so that
2118  * it is large enough to qualify as a valid Ethernet frame.
2119  *
2120  * Returns true if an error was encountered and skb was freed.
2121  */
2122 static bool igc_cleanup_headers(struct igc_ring *rx_ring,
2123                                 union igc_adv_rx_desc *rx_desc,
2124                                 struct sk_buff *skb)
2125 {
2126         /* XDP packets use error pointer so abort at this point */
2127         if (IS_ERR(skb))
2128                 return true;
2129
2130         if (unlikely(igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_RXE))) {
2131                 struct net_device *netdev = rx_ring->netdev;
2132
2133                 if (!(netdev->features & NETIF_F_RXALL)) {
2134                         dev_kfree_skb_any(skb);
2135                         return true;
2136                 }
2137         }
2138
2139         /* if eth_skb_pad returns an error the skb was freed */
2140         if (eth_skb_pad(skb))
2141                 return true;
2142
2143         return false;
2144 }
2145
2146 static void igc_put_rx_buffer(struct igc_ring *rx_ring,
2147                               struct igc_rx_buffer *rx_buffer,
2148                               int rx_buffer_pgcnt)
2149 {
2150         if (igc_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) {
2151                 /* hand second half of page back to the ring */
2152                 igc_reuse_rx_page(rx_ring, rx_buffer);
2153         } else {
2154                 /* We are not reusing the buffer so unmap it and free
2155                  * any references we are holding to it
2156                  */
2157                 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2158                                      igc_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
2159                                      IGC_RX_DMA_ATTR);
2160                 __page_frag_cache_drain(rx_buffer->page,
2161                                         rx_buffer->pagecnt_bias);
2162         }
2163
2164         /* clear contents of rx_buffer */
2165         rx_buffer->page = NULL;
2166 }
2167
2168 static inline unsigned int igc_rx_offset(struct igc_ring *rx_ring)
2169 {
2170         struct igc_adapter *adapter = rx_ring->q_vector->adapter;
2171
2172         if (ring_uses_build_skb(rx_ring))
2173                 return IGC_SKB_PAD;
2174         if (igc_xdp_is_enabled(adapter))
2175                 return XDP_PACKET_HEADROOM;
2176
2177         return 0;
2178 }
2179
2180 static bool igc_alloc_mapped_page(struct igc_ring *rx_ring,
2181                                   struct igc_rx_buffer *bi)
2182 {
2183         struct page *page = bi->page;
2184         dma_addr_t dma;
2185
2186         /* since we are recycling buffers we should seldom need to alloc */
2187         if (likely(page))
2188                 return true;
2189
2190         /* alloc new page for storage */
2191         page = dev_alloc_pages(igc_rx_pg_order(rx_ring));
2192         if (unlikely(!page)) {
2193                 rx_ring->rx_stats.alloc_failed++;
2194                 return false;
2195         }
2196
2197         /* map page for use */
2198         dma = dma_map_page_attrs(rx_ring->dev, page, 0,
2199                                  igc_rx_pg_size(rx_ring),
2200                                  DMA_FROM_DEVICE,
2201                                  IGC_RX_DMA_ATTR);
2202
2203         /* if mapping failed free memory back to system since
2204          * there isn't much point in holding memory we can't use
2205          */
2206         if (dma_mapping_error(rx_ring->dev, dma)) {
2207                 __free_page(page);
2208
2209                 rx_ring->rx_stats.alloc_failed++;
2210                 return false;
2211         }
2212
2213         bi->dma = dma;
2214         bi->page = page;
2215         bi->page_offset = igc_rx_offset(rx_ring);
2216         page_ref_add(page, USHRT_MAX - 1);
2217         bi->pagecnt_bias = USHRT_MAX;
2218
2219         return true;
2220 }
2221
2222 /**
2223  * igc_alloc_rx_buffers - Replace used receive buffers; packet split
2224  * @rx_ring: rx descriptor ring
2225  * @cleaned_count: number of buffers to clean
2226  */
2227 static void igc_alloc_rx_buffers(struct igc_ring *rx_ring, u16 cleaned_count)
2228 {
2229         union igc_adv_rx_desc *rx_desc;
2230         u16 i = rx_ring->next_to_use;
2231         struct igc_rx_buffer *bi;
2232         u16 bufsz;
2233
2234         /* nothing to do */
2235         if (!cleaned_count)
2236                 return;
2237
2238         rx_desc = IGC_RX_DESC(rx_ring, i);
2239         bi = &rx_ring->rx_buffer_info[i];
2240         i -= rx_ring->count;
2241
2242         bufsz = igc_rx_bufsz(rx_ring);
2243
2244         do {
2245                 if (!igc_alloc_mapped_page(rx_ring, bi))
2246                         break;
2247
2248                 /* sync the buffer for use by the device */
2249                 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
2250                                                  bi->page_offset, bufsz,
2251                                                  DMA_FROM_DEVICE);
2252
2253                 /* Refresh the desc even if buffer_addrs didn't change
2254                  * because each write-back erases this info.
2255                  */
2256                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
2257
2258                 rx_desc++;
2259                 bi++;
2260                 i++;
2261                 if (unlikely(!i)) {
2262                         rx_desc = IGC_RX_DESC(rx_ring, 0);
2263                         bi = rx_ring->rx_buffer_info;
2264                         i -= rx_ring->count;
2265                 }
2266
2267                 /* clear the length for the next_to_use descriptor */
2268                 rx_desc->wb.upper.length = 0;
2269
2270                 cleaned_count--;
2271         } while (cleaned_count);
2272
2273         i += rx_ring->count;
2274
2275         if (rx_ring->next_to_use != i) {
2276                 /* record the next descriptor to use */
2277                 rx_ring->next_to_use = i;
2278
2279                 /* update next to alloc since we have filled the ring */
2280                 rx_ring->next_to_alloc = i;
2281
2282                 /* Force memory writes to complete before letting h/w
2283                  * know there are new descriptors to fetch.  (Only
2284                  * applicable for weak-ordered memory model archs,
2285                  * such as IA-64).
2286                  */
2287                 wmb();
2288                 writel(i, rx_ring->tail);
2289         }
2290 }
2291
2292 static bool igc_alloc_rx_buffers_zc(struct igc_ring *ring, u16 count)
2293 {
2294         union igc_adv_rx_desc *desc;
2295         u16 i = ring->next_to_use;
2296         struct igc_rx_buffer *bi;
2297         dma_addr_t dma;
2298         bool ok = true;
2299
2300         if (!count)
2301                 return ok;
2302
2303         XSK_CHECK_PRIV_TYPE(struct igc_xdp_buff);
2304
2305         desc = IGC_RX_DESC(ring, i);
2306         bi = &ring->rx_buffer_info[i];
2307         i -= ring->count;
2308
2309         do {
2310                 bi->xdp = xsk_buff_alloc(ring->xsk_pool);
2311                 if (!bi->xdp) {
2312                         ok = false;
2313                         break;
2314                 }
2315
2316                 dma = xsk_buff_xdp_get_dma(bi->xdp);
2317                 desc->read.pkt_addr = cpu_to_le64(dma);
2318
2319                 desc++;
2320                 bi++;
2321                 i++;
2322                 if (unlikely(!i)) {
2323                         desc = IGC_RX_DESC(ring, 0);
2324                         bi = ring->rx_buffer_info;
2325                         i -= ring->count;
2326                 }
2327
2328                 /* Clear the length for the next_to_use descriptor. */
2329                 desc->wb.upper.length = 0;
2330
2331                 count--;
2332         } while (count);
2333
2334         i += ring->count;
2335
2336         if (ring->next_to_use != i) {
2337                 ring->next_to_use = i;
2338
2339                 /* Force memory writes to complete before letting h/w
2340                  * know there are new descriptors to fetch.  (Only
2341                  * applicable for weak-ordered memory model archs,
2342                  * such as IA-64).
2343                  */
2344                 wmb();
2345                 writel(i, ring->tail);
2346         }
2347
2348         return ok;
2349 }
2350
2351 /* This function requires __netif_tx_lock is held by the caller. */
2352 static int igc_xdp_init_tx_descriptor(struct igc_ring *ring,
2353                                       struct xdp_frame *xdpf)
2354 {
2355         struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
2356         u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
2357         u16 count, index = ring->next_to_use;
2358         struct igc_tx_buffer *head = &ring->tx_buffer_info[index];
2359         struct igc_tx_buffer *buffer = head;
2360         union igc_adv_tx_desc *desc = IGC_TX_DESC(ring, index);
2361         u32 olinfo_status, len = xdpf->len, cmd_type;
2362         void *data = xdpf->data;
2363         u16 i;
2364
2365         count = TXD_USE_COUNT(len);
2366         for (i = 0; i < nr_frags; i++)
2367                 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i]));
2368
2369         if (igc_maybe_stop_tx(ring, count + 3)) {
2370                 /* this is a hard error */
2371                 return -EBUSY;
2372         }
2373
2374         i = 0;
2375         head->bytecount = xdp_get_frame_len(xdpf);
2376         head->type = IGC_TX_BUFFER_TYPE_XDP;
2377         head->gso_segs = 1;
2378         head->xdpf = xdpf;
2379
2380         olinfo_status = head->bytecount << IGC_ADVTXD_PAYLEN_SHIFT;
2381         desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2382
2383         for (;;) {
2384                 dma_addr_t dma;
2385
2386                 dma = dma_map_single(ring->dev, data, len, DMA_TO_DEVICE);
2387                 if (dma_mapping_error(ring->dev, dma)) {
2388                         netdev_err_once(ring->netdev,
2389                                         "Failed to map DMA for TX\n");
2390                         goto unmap;
2391                 }
2392
2393                 dma_unmap_len_set(buffer, len, len);
2394                 dma_unmap_addr_set(buffer, dma, dma);
2395
2396                 cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT |
2397                            IGC_ADVTXD_DCMD_IFCS | len;
2398
2399                 desc->read.cmd_type_len = cpu_to_le32(cmd_type);
2400                 desc->read.buffer_addr = cpu_to_le64(dma);
2401
2402                 buffer->protocol = 0;
2403
2404                 if (++index == ring->count)
2405                         index = 0;
2406
2407                 if (i == nr_frags)
2408                         break;
2409
2410                 buffer = &ring->tx_buffer_info[index];
2411                 desc = IGC_TX_DESC(ring, index);
2412                 desc->read.olinfo_status = 0;
2413
2414                 data = skb_frag_address(&sinfo->frags[i]);
2415                 len = skb_frag_size(&sinfo->frags[i]);
2416                 i++;
2417         }
2418         desc->read.cmd_type_len |= cpu_to_le32(IGC_TXD_DCMD);
2419
2420         netdev_tx_sent_queue(txring_txq(ring), head->bytecount);
2421         /* set the timestamp */
2422         head->time_stamp = jiffies;
2423         /* set next_to_watch value indicating a packet is present */
2424         head->next_to_watch = desc;
2425         ring->next_to_use = index;
2426
2427         return 0;
2428
2429 unmap:
2430         for (;;) {
2431                 buffer = &ring->tx_buffer_info[index];
2432                 if (dma_unmap_len(buffer, len))
2433                         dma_unmap_page(ring->dev,
2434                                        dma_unmap_addr(buffer, dma),
2435                                        dma_unmap_len(buffer, len),
2436                                        DMA_TO_DEVICE);
2437                 dma_unmap_len_set(buffer, len, 0);
2438                 if (buffer == head)
2439                         break;
2440
2441                 if (!index)
2442                         index += ring->count;
2443                 index--;
2444         }
2445
2446         return -ENOMEM;
2447 }
2448
2449 static struct igc_ring *igc_xdp_get_tx_ring(struct igc_adapter *adapter,
2450                                             int cpu)
2451 {
2452         int index = cpu;
2453
2454         if (unlikely(index < 0))
2455                 index = 0;
2456
2457         while (index >= adapter->num_tx_queues)
2458                 index -= adapter->num_tx_queues;
2459
2460         return adapter->tx_ring[index];
2461 }
2462
2463 static int igc_xdp_xmit_back(struct igc_adapter *adapter, struct xdp_buff *xdp)
2464 {
2465         struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2466         int cpu = smp_processor_id();
2467         struct netdev_queue *nq;
2468         struct igc_ring *ring;
2469         int res;
2470
2471         if (unlikely(!xdpf))
2472                 return -EFAULT;
2473
2474         ring = igc_xdp_get_tx_ring(adapter, cpu);
2475         nq = txring_txq(ring);
2476
2477         __netif_tx_lock(nq, cpu);
2478         /* Avoid transmit queue timeout since we share it with the slow path */
2479         txq_trans_cond_update(nq);
2480         res = igc_xdp_init_tx_descriptor(ring, xdpf);
2481         __netif_tx_unlock(nq);
2482         return res;
2483 }
2484
2485 /* This function assumes rcu_read_lock() is held by the caller. */
2486 static int __igc_xdp_run_prog(struct igc_adapter *adapter,
2487                               struct bpf_prog *prog,
2488                               struct xdp_buff *xdp)
2489 {
2490         u32 act = bpf_prog_run_xdp(prog, xdp);
2491
2492         switch (act) {
2493         case XDP_PASS:
2494                 return IGC_XDP_PASS;
2495         case XDP_TX:
2496                 if (igc_xdp_xmit_back(adapter, xdp) < 0)
2497                         goto out_failure;
2498                 return IGC_XDP_TX;
2499         case XDP_REDIRECT:
2500                 if (xdp_do_redirect(adapter->netdev, xdp, prog) < 0)
2501                         goto out_failure;
2502                 return IGC_XDP_REDIRECT;
2503                 break;
2504         default:
2505                 bpf_warn_invalid_xdp_action(adapter->netdev, prog, act);
2506                 fallthrough;
2507         case XDP_ABORTED:
2508 out_failure:
2509                 trace_xdp_exception(adapter->netdev, prog, act);
2510                 fallthrough;
2511         case XDP_DROP:
2512                 return IGC_XDP_CONSUMED;
2513         }
2514 }
2515
2516 static struct sk_buff *igc_xdp_run_prog(struct igc_adapter *adapter,
2517                                         struct xdp_buff *xdp)
2518 {
2519         struct bpf_prog *prog;
2520         int res;
2521
2522         prog = READ_ONCE(adapter->xdp_prog);
2523         if (!prog) {
2524                 res = IGC_XDP_PASS;
2525                 goto out;
2526         }
2527
2528         res = __igc_xdp_run_prog(adapter, prog, xdp);
2529
2530 out:
2531         return ERR_PTR(-res);
2532 }
2533
2534 /* This function assumes __netif_tx_lock is held by the caller. */
2535 static void igc_flush_tx_descriptors(struct igc_ring *ring)
2536 {
2537         /* Once tail pointer is updated, hardware can fetch the descriptors
2538          * any time so we issue a write membar here to ensure all memory
2539          * writes are complete before the tail pointer is updated.
2540          */
2541         wmb();
2542         writel(ring->next_to_use, ring->tail);
2543 }
2544
2545 static void igc_finalize_xdp(struct igc_adapter *adapter, int status)
2546 {
2547         int cpu = smp_processor_id();
2548         struct netdev_queue *nq;
2549         struct igc_ring *ring;
2550
2551         if (status & IGC_XDP_TX) {
2552                 ring = igc_xdp_get_tx_ring(adapter, cpu);
2553                 nq = txring_txq(ring);
2554
2555                 __netif_tx_lock(nq, cpu);
2556                 igc_flush_tx_descriptors(ring);
2557                 __netif_tx_unlock(nq);
2558         }
2559
2560         if (status & IGC_XDP_REDIRECT)
2561                 xdp_do_flush();
2562 }
2563
2564 static void igc_update_rx_stats(struct igc_q_vector *q_vector,
2565                                 unsigned int packets, unsigned int bytes)
2566 {
2567         struct igc_ring *ring = q_vector->rx.ring;
2568
2569         u64_stats_update_begin(&ring->rx_syncp);
2570         ring->rx_stats.packets += packets;
2571         ring->rx_stats.bytes += bytes;
2572         u64_stats_update_end(&ring->rx_syncp);
2573
2574         q_vector->rx.total_packets += packets;
2575         q_vector->rx.total_bytes += bytes;
2576 }
2577
2578 static int igc_clean_rx_irq(struct igc_q_vector *q_vector, const int budget)
2579 {
2580         unsigned int total_bytes = 0, total_packets = 0;
2581         struct igc_adapter *adapter = q_vector->adapter;
2582         struct igc_ring *rx_ring = q_vector->rx.ring;
2583         struct sk_buff *skb = rx_ring->skb;
2584         u16 cleaned_count = igc_desc_unused(rx_ring);
2585         int xdp_status = 0, rx_buffer_pgcnt;
2586
2587         while (likely(total_packets < budget)) {
2588                 struct igc_xdp_buff ctx = { .rx_ts = NULL };
2589                 struct igc_rx_buffer *rx_buffer;
2590                 union igc_adv_rx_desc *rx_desc;
2591                 unsigned int size, truesize;
2592                 int pkt_offset = 0;
2593                 void *pktbuf;
2594
2595                 /* return some buffers to hardware, one at a time is too slow */
2596                 if (cleaned_count >= IGC_RX_BUFFER_WRITE) {
2597                         igc_alloc_rx_buffers(rx_ring, cleaned_count);
2598                         cleaned_count = 0;
2599                 }
2600
2601                 rx_desc = IGC_RX_DESC(rx_ring, rx_ring->next_to_clean);
2602                 size = le16_to_cpu(rx_desc->wb.upper.length);
2603                 if (!size)
2604                         break;
2605
2606                 /* This memory barrier is needed to keep us from reading
2607                  * any other fields out of the rx_desc until we know the
2608                  * descriptor has been written back
2609                  */
2610                 dma_rmb();
2611
2612                 rx_buffer = igc_get_rx_buffer(rx_ring, size, &rx_buffer_pgcnt);
2613                 truesize = igc_get_rx_frame_truesize(rx_ring, size);
2614
2615                 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset;
2616
2617                 if (igc_test_staterr(rx_desc, IGC_RXDADV_STAT_TSIP)) {
2618                         ctx.rx_ts = pktbuf;
2619                         pkt_offset = IGC_TS_HDR_LEN;
2620                         size -= IGC_TS_HDR_LEN;
2621                 }
2622
2623                 if (!skb) {
2624                         xdp_init_buff(&ctx.xdp, truesize, &rx_ring->xdp_rxq);
2625                         xdp_prepare_buff(&ctx.xdp, pktbuf - igc_rx_offset(rx_ring),
2626                                          igc_rx_offset(rx_ring) + pkt_offset,
2627                                          size, true);
2628                         xdp_buff_clear_frags_flag(&ctx.xdp);
2629                         ctx.rx_desc = rx_desc;
2630
2631                         skb = igc_xdp_run_prog(adapter, &ctx.xdp);
2632                 }
2633
2634                 if (IS_ERR(skb)) {
2635                         unsigned int xdp_res = -PTR_ERR(skb);
2636
2637                         switch (xdp_res) {
2638                         case IGC_XDP_CONSUMED:
2639                                 rx_buffer->pagecnt_bias++;
2640                                 break;
2641                         case IGC_XDP_TX:
2642                         case IGC_XDP_REDIRECT:
2643                                 igc_rx_buffer_flip(rx_buffer, truesize);
2644                                 xdp_status |= xdp_res;
2645                                 break;
2646                         }
2647
2648                         total_packets++;
2649                         total_bytes += size;
2650                 } else if (skb)
2651                         igc_add_rx_frag(rx_ring, rx_buffer, skb, size);
2652                 else if (ring_uses_build_skb(rx_ring))
2653                         skb = igc_build_skb(rx_ring, rx_buffer, &ctx.xdp);
2654                 else
2655                         skb = igc_construct_skb(rx_ring, rx_buffer, &ctx);
2656
2657                 /* exit if we failed to retrieve a buffer */
2658                 if (!skb) {
2659                         rx_ring->rx_stats.alloc_failed++;
2660                         rx_buffer->pagecnt_bias++;
2661                         break;
2662                 }
2663
2664                 igc_put_rx_buffer(rx_ring, rx_buffer, rx_buffer_pgcnt);
2665                 cleaned_count++;
2666
2667                 /* fetch next buffer in frame if non-eop */
2668                 if (igc_is_non_eop(rx_ring, rx_desc))
2669                         continue;
2670
2671                 /* verify the packet layout is correct */
2672                 if (igc_cleanup_headers(rx_ring, rx_desc, skb)) {
2673                         skb = NULL;
2674                         continue;
2675                 }
2676
2677                 /* probably a little skewed due to removing CRC */
2678                 total_bytes += skb->len;
2679
2680                 /* populate checksum, VLAN, and protocol */
2681                 igc_process_skb_fields(rx_ring, rx_desc, skb);
2682
2683                 napi_gro_receive(&q_vector->napi, skb);
2684
2685                 /* reset skb pointer */
2686                 skb = NULL;
2687
2688                 /* update budget accounting */
2689                 total_packets++;
2690         }
2691
2692         if (xdp_status)
2693                 igc_finalize_xdp(adapter, xdp_status);
2694
2695         /* place incomplete frames back on ring for completion */
2696         rx_ring->skb = skb;
2697
2698         igc_update_rx_stats(q_vector, total_packets, total_bytes);
2699
2700         if (cleaned_count)
2701                 igc_alloc_rx_buffers(rx_ring, cleaned_count);
2702
2703         return total_packets;
2704 }
2705
2706 static struct sk_buff *igc_construct_skb_zc(struct igc_ring *ring,
2707                                             struct xdp_buff *xdp)
2708 {
2709         unsigned int totalsize = xdp->data_end - xdp->data_meta;
2710         unsigned int metasize = xdp->data - xdp->data_meta;
2711         struct sk_buff *skb;
2712
2713         net_prefetch(xdp->data_meta);
2714
2715         skb = napi_alloc_skb(&ring->q_vector->napi, totalsize);
2716         if (unlikely(!skb))
2717                 return NULL;
2718
2719         memcpy(__skb_put(skb, totalsize), xdp->data_meta,
2720                ALIGN(totalsize, sizeof(long)));
2721
2722         if (metasize) {
2723                 skb_metadata_set(skb, metasize);
2724                 __skb_pull(skb, metasize);
2725         }
2726
2727         return skb;
2728 }
2729
2730 static void igc_dispatch_skb_zc(struct igc_q_vector *q_vector,
2731                                 union igc_adv_rx_desc *desc,
2732                                 struct xdp_buff *xdp,
2733                                 ktime_t timestamp)
2734 {
2735         struct igc_ring *ring = q_vector->rx.ring;
2736         struct sk_buff *skb;
2737
2738         skb = igc_construct_skb_zc(ring, xdp);
2739         if (!skb) {
2740                 ring->rx_stats.alloc_failed++;
2741                 return;
2742         }
2743
2744         if (timestamp)
2745                 skb_hwtstamps(skb)->hwtstamp = timestamp;
2746
2747         if (igc_cleanup_headers(ring, desc, skb))
2748                 return;
2749
2750         igc_process_skb_fields(ring, desc, skb);
2751         napi_gro_receive(&q_vector->napi, skb);
2752 }
2753
2754 static struct igc_xdp_buff *xsk_buff_to_igc_ctx(struct xdp_buff *xdp)
2755 {
2756         /* xdp_buff pointer used by ZC code path is alloc as xdp_buff_xsk. The
2757          * igc_xdp_buff shares its layout with xdp_buff_xsk and private
2758          * igc_xdp_buff fields fall into xdp_buff_xsk->cb
2759          */
2760        return (struct igc_xdp_buff *)xdp;
2761 }
2762
2763 static int igc_clean_rx_irq_zc(struct igc_q_vector *q_vector, const int budget)
2764 {
2765         struct igc_adapter *adapter = q_vector->adapter;
2766         struct igc_ring *ring = q_vector->rx.ring;
2767         u16 cleaned_count = igc_desc_unused(ring);
2768         int total_bytes = 0, total_packets = 0;
2769         u16 ntc = ring->next_to_clean;
2770         struct bpf_prog *prog;
2771         bool failure = false;
2772         int xdp_status = 0;
2773
2774         rcu_read_lock();
2775
2776         prog = READ_ONCE(adapter->xdp_prog);
2777
2778         while (likely(total_packets < budget)) {
2779                 union igc_adv_rx_desc *desc;
2780                 struct igc_rx_buffer *bi;
2781                 struct igc_xdp_buff *ctx;
2782                 ktime_t timestamp = 0;
2783                 unsigned int size;
2784                 int res;
2785
2786                 desc = IGC_RX_DESC(ring, ntc);
2787                 size = le16_to_cpu(desc->wb.upper.length);
2788                 if (!size)
2789                         break;
2790
2791                 /* This memory barrier is needed to keep us from reading
2792                  * any other fields out of the rx_desc until we know the
2793                  * descriptor has been written back
2794                  */
2795                 dma_rmb();
2796
2797                 bi = &ring->rx_buffer_info[ntc];
2798
2799                 ctx = xsk_buff_to_igc_ctx(bi->xdp);
2800                 ctx->rx_desc = desc;
2801
2802                 if (igc_test_staterr(desc, IGC_RXDADV_STAT_TSIP)) {
2803                         ctx->rx_ts = bi->xdp->data;
2804
2805                         bi->xdp->data += IGC_TS_HDR_LEN;
2806
2807                         /* HW timestamp has been copied into local variable. Metadata
2808                          * length when XDP program is called should be 0.
2809                          */
2810                         bi->xdp->data_meta += IGC_TS_HDR_LEN;
2811                         size -= IGC_TS_HDR_LEN;
2812                 }
2813
2814                 bi->xdp->data_end = bi->xdp->data + size;
2815                 xsk_buff_dma_sync_for_cpu(bi->xdp);
2816
2817                 res = __igc_xdp_run_prog(adapter, prog, bi->xdp);
2818                 switch (res) {
2819                 case IGC_XDP_PASS:
2820                         igc_dispatch_skb_zc(q_vector, desc, bi->xdp, timestamp);
2821                         fallthrough;
2822                 case IGC_XDP_CONSUMED:
2823                         xsk_buff_free(bi->xdp);
2824                         break;
2825                 case IGC_XDP_TX:
2826                 case IGC_XDP_REDIRECT:
2827                         xdp_status |= res;
2828                         break;
2829                 }
2830
2831                 bi->xdp = NULL;
2832                 total_bytes += size;
2833                 total_packets++;
2834                 cleaned_count++;
2835                 ntc++;
2836                 if (ntc == ring->count)
2837                         ntc = 0;
2838         }
2839
2840         ring->next_to_clean = ntc;
2841         rcu_read_unlock();
2842
2843         if (cleaned_count >= IGC_RX_BUFFER_WRITE)
2844                 failure = !igc_alloc_rx_buffers_zc(ring, cleaned_count);
2845
2846         if (xdp_status)
2847                 igc_finalize_xdp(adapter, xdp_status);
2848
2849         igc_update_rx_stats(q_vector, total_packets, total_bytes);
2850
2851         if (xsk_uses_need_wakeup(ring->xsk_pool)) {
2852                 if (failure || ring->next_to_clean == ring->next_to_use)
2853                         xsk_set_rx_need_wakeup(ring->xsk_pool);
2854                 else
2855                         xsk_clear_rx_need_wakeup(ring->xsk_pool);
2856                 return total_packets;
2857         }
2858
2859         return failure ? budget : total_packets;
2860 }
2861
2862 static void igc_update_tx_stats(struct igc_q_vector *q_vector,
2863                                 unsigned int packets, unsigned int bytes)
2864 {
2865         struct igc_ring *ring = q_vector->tx.ring;
2866
2867         u64_stats_update_begin(&ring->tx_syncp);
2868         ring->tx_stats.bytes += bytes;
2869         ring->tx_stats.packets += packets;
2870         u64_stats_update_end(&ring->tx_syncp);
2871
2872         q_vector->tx.total_bytes += bytes;
2873         q_vector->tx.total_packets += packets;
2874 }
2875
2876 static void igc_xsk_request_timestamp(void *_priv)
2877 {
2878         struct igc_metadata_request *meta_req = _priv;
2879         struct igc_ring *tx_ring = meta_req->tx_ring;
2880         struct igc_tx_timestamp_request *tstamp;
2881         u32 tx_flags = IGC_TX_FLAGS_TSTAMP;
2882         struct igc_adapter *adapter;
2883         unsigned long lock_flags;
2884         bool found = false;
2885         int i;
2886
2887         if (test_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags)) {
2888                 adapter = netdev_priv(tx_ring->netdev);
2889
2890                 spin_lock_irqsave(&adapter->ptp_tx_lock, lock_flags);
2891
2892                 /* Search for available tstamp regs */
2893                 for (i = 0; i < IGC_MAX_TX_TSTAMP_REGS; i++) {
2894                         tstamp = &adapter->tx_tstamp[i];
2895
2896                         /* tstamp->skb and tstamp->xsk_tx_buffer are in union.
2897                          * When tstamp->skb is equal to NULL,
2898                          * tstamp->xsk_tx_buffer is equal to NULL as well.
2899                          * This condition means that the particular tstamp reg
2900                          * is not occupied by other packet.
2901                          */
2902                         if (!tstamp->skb) {
2903                                 found = true;
2904                                 break;
2905                         }
2906                 }
2907
2908                 /* Return if no available tstamp regs */
2909                 if (!found) {
2910                         adapter->tx_hwtstamp_skipped++;
2911                         spin_unlock_irqrestore(&adapter->ptp_tx_lock,
2912                                                lock_flags);
2913                         return;
2914                 }
2915
2916                 tstamp->start = jiffies;
2917                 tstamp->xsk_queue_index = tx_ring->queue_index;
2918                 tstamp->xsk_tx_buffer = meta_req->tx_buffer;
2919                 tstamp->buffer_type = IGC_TX_BUFFER_TYPE_XSK;
2920
2921                 /* Hold the transmit completion until timestamp is ready */
2922                 meta_req->tx_buffer->xsk_pending_ts = true;
2923
2924                 /* Keep the pointer to tx_timestamp, which is located in XDP
2925                  * metadata area. It is the location to store the value of
2926                  * tx hardware timestamp.
2927                  */
2928                 xsk_tx_metadata_to_compl(meta_req->meta, &tstamp->xsk_meta);
2929
2930                 /* Set timestamp bit based on the _TSTAMP(_X) bit. */
2931                 tx_flags |= tstamp->flags;
2932                 meta_req->cmd_type |= IGC_SET_FLAG(tx_flags,
2933                                                    IGC_TX_FLAGS_TSTAMP,
2934                                                    (IGC_ADVTXD_MAC_TSTAMP));
2935                 meta_req->cmd_type |= IGC_SET_FLAG(tx_flags,
2936                                                    IGC_TX_FLAGS_TSTAMP_1,
2937                                                    (IGC_ADVTXD_TSTAMP_REG_1));
2938                 meta_req->cmd_type |= IGC_SET_FLAG(tx_flags,
2939                                                    IGC_TX_FLAGS_TSTAMP_2,
2940                                                    (IGC_ADVTXD_TSTAMP_REG_2));
2941                 meta_req->cmd_type |= IGC_SET_FLAG(tx_flags,
2942                                                    IGC_TX_FLAGS_TSTAMP_3,
2943                                                    (IGC_ADVTXD_TSTAMP_REG_3));
2944
2945                 spin_unlock_irqrestore(&adapter->ptp_tx_lock, lock_flags);
2946         }
2947 }
2948
2949 static u64 igc_xsk_fill_timestamp(void *_priv)
2950 {
2951         return *(u64 *)_priv;
2952 }
2953
2954 const struct xsk_tx_metadata_ops igc_xsk_tx_metadata_ops = {
2955         .tmo_request_timestamp          = igc_xsk_request_timestamp,
2956         .tmo_fill_timestamp             = igc_xsk_fill_timestamp,
2957 };
2958
2959 static void igc_xdp_xmit_zc(struct igc_ring *ring)
2960 {
2961         struct xsk_buff_pool *pool = ring->xsk_pool;
2962         struct netdev_queue *nq = txring_txq(ring);
2963         union igc_adv_tx_desc *tx_desc = NULL;
2964         int cpu = smp_processor_id();
2965         struct xdp_desc xdp_desc;
2966         u16 budget, ntu;
2967
2968         if (!netif_carrier_ok(ring->netdev))
2969                 return;
2970
2971         __netif_tx_lock(nq, cpu);
2972
2973         /* Avoid transmit queue timeout since we share it with the slow path */
2974         txq_trans_cond_update(nq);
2975
2976         ntu = ring->next_to_use;
2977         budget = igc_desc_unused(ring);
2978
2979         while (xsk_tx_peek_desc(pool, &xdp_desc) && budget--) {
2980                 struct igc_metadata_request meta_req;
2981                 struct xsk_tx_metadata *meta = NULL;
2982                 struct igc_tx_buffer *bi;
2983                 u32 olinfo_status;
2984                 dma_addr_t dma;
2985
2986                 meta_req.cmd_type = IGC_ADVTXD_DTYP_DATA |
2987                                     IGC_ADVTXD_DCMD_DEXT |
2988                                     IGC_ADVTXD_DCMD_IFCS |
2989                                     IGC_TXD_DCMD | xdp_desc.len;
2990                 olinfo_status = xdp_desc.len << IGC_ADVTXD_PAYLEN_SHIFT;
2991
2992                 dma = xsk_buff_raw_get_dma(pool, xdp_desc.addr);
2993                 meta = xsk_buff_get_metadata(pool, xdp_desc.addr);
2994                 xsk_buff_raw_dma_sync_for_device(pool, dma, xdp_desc.len);
2995                 bi = &ring->tx_buffer_info[ntu];
2996
2997                 meta_req.tx_ring = ring;
2998                 meta_req.tx_buffer = bi;
2999                 meta_req.meta = meta;
3000                 xsk_tx_metadata_request(meta, &igc_xsk_tx_metadata_ops,
3001                                         &meta_req);
3002
3003                 tx_desc = IGC_TX_DESC(ring, ntu);
3004                 tx_desc->read.cmd_type_len = cpu_to_le32(meta_req.cmd_type);
3005                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3006                 tx_desc->read.buffer_addr = cpu_to_le64(dma);
3007
3008                 bi->type = IGC_TX_BUFFER_TYPE_XSK;
3009                 bi->protocol = 0;
3010                 bi->bytecount = xdp_desc.len;
3011                 bi->gso_segs = 1;
3012                 bi->time_stamp = jiffies;
3013                 bi->next_to_watch = tx_desc;
3014
3015                 netdev_tx_sent_queue(txring_txq(ring), xdp_desc.len);
3016
3017                 ntu++;
3018                 if (ntu == ring->count)
3019                         ntu = 0;
3020         }
3021
3022         ring->next_to_use = ntu;
3023         if (tx_desc) {
3024                 igc_flush_tx_descriptors(ring);
3025                 xsk_tx_release(pool);
3026         }
3027
3028         __netif_tx_unlock(nq);
3029 }
3030
3031 /**
3032  * igc_clean_tx_irq - Reclaim resources after transmit completes
3033  * @q_vector: pointer to q_vector containing needed info
3034  * @napi_budget: Used to determine if we are in netpoll
3035  *
3036  * returns true if ring is completely cleaned
3037  */
3038 static bool igc_clean_tx_irq(struct igc_q_vector *q_vector, int napi_budget)
3039 {
3040         struct igc_adapter *adapter = q_vector->adapter;
3041         unsigned int total_bytes = 0, total_packets = 0;
3042         unsigned int budget = q_vector->tx.work_limit;
3043         struct igc_ring *tx_ring = q_vector->tx.ring;
3044         unsigned int i = tx_ring->next_to_clean;
3045         struct igc_tx_buffer *tx_buffer;
3046         union igc_adv_tx_desc *tx_desc;
3047         u32 xsk_frames = 0;
3048
3049         if (test_bit(__IGC_DOWN, &adapter->state))
3050                 return true;
3051
3052         tx_buffer = &tx_ring->tx_buffer_info[i];
3053         tx_desc = IGC_TX_DESC(tx_ring, i);
3054         i -= tx_ring->count;
3055
3056         do {
3057                 union igc_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
3058
3059                 /* if next_to_watch is not set then there is no work pending */
3060                 if (!eop_desc)
3061                         break;
3062
3063                 /* prevent any other reads prior to eop_desc */
3064                 smp_rmb();
3065
3066                 /* if DD is not set pending work has not been completed */
3067                 if (!(eop_desc->wb.status & cpu_to_le32(IGC_TXD_STAT_DD)))
3068                         break;
3069
3070                 /* Hold the completions while there's a pending tx hardware
3071                  * timestamp request from XDP Tx metadata.
3072                  */
3073                 if (tx_buffer->type == IGC_TX_BUFFER_TYPE_XSK &&
3074                     tx_buffer->xsk_pending_ts)
3075                         break;
3076
3077                 /* clear next_to_watch to prevent false hangs */
3078                 tx_buffer->next_to_watch = NULL;
3079
3080                 /* update the statistics for this packet */
3081                 total_bytes += tx_buffer->bytecount;
3082                 total_packets += tx_buffer->gso_segs;
3083
3084                 switch (tx_buffer->type) {
3085                 case IGC_TX_BUFFER_TYPE_XSK:
3086                         xsk_frames++;
3087                         break;
3088                 case IGC_TX_BUFFER_TYPE_XDP:
3089                         xdp_return_frame(tx_buffer->xdpf);
3090                         igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
3091                         break;
3092                 case IGC_TX_BUFFER_TYPE_SKB:
3093                         napi_consume_skb(tx_buffer->skb, napi_budget);
3094                         igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
3095                         break;
3096                 default:
3097                         netdev_warn_once(tx_ring->netdev, "Unknown Tx buffer type\n");
3098                         break;
3099                 }
3100
3101                 /* clear last DMA location and unmap remaining buffers */
3102                 while (tx_desc != eop_desc) {
3103                         tx_buffer++;
3104                         tx_desc++;
3105                         i++;
3106                         if (unlikely(!i)) {
3107                                 i -= tx_ring->count;
3108                                 tx_buffer = tx_ring->tx_buffer_info;
3109                                 tx_desc = IGC_TX_DESC(tx_ring, 0);
3110                         }
3111
3112                         /* unmap any remaining paged data */
3113                         if (dma_unmap_len(tx_buffer, len))
3114                                 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
3115                 }
3116
3117                 /* move us one more past the eop_desc for start of next pkt */
3118                 tx_buffer++;
3119                 tx_desc++;
3120                 i++;
3121                 if (unlikely(!i)) {
3122                         i -= tx_ring->count;
3123                         tx_buffer = tx_ring->tx_buffer_info;
3124                         tx_desc = IGC_TX_DESC(tx_ring, 0);
3125                 }
3126
3127                 /* issue prefetch for next Tx descriptor */
3128                 prefetch(tx_desc);
3129
3130                 /* update budget accounting */
3131                 budget--;
3132         } while (likely(budget));
3133
3134         netdev_tx_completed_queue(txring_txq(tx_ring),
3135                                   total_packets, total_bytes);
3136
3137         i += tx_ring->count;
3138         tx_ring->next_to_clean = i;
3139
3140         igc_update_tx_stats(q_vector, total_packets, total_bytes);
3141
3142         if (tx_ring->xsk_pool) {
3143                 if (xsk_frames)
3144                         xsk_tx_completed(tx_ring->xsk_pool, xsk_frames);
3145                 if (xsk_uses_need_wakeup(tx_ring->xsk_pool))
3146                         xsk_set_tx_need_wakeup(tx_ring->xsk_pool);
3147                 igc_xdp_xmit_zc(tx_ring);
3148         }
3149
3150         if (test_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
3151                 struct igc_hw *hw = &adapter->hw;
3152
3153                 /* Detect a transmit hang in hardware, this serializes the
3154                  * check with the clearing of time_stamp and movement of i
3155                  */
3156                 clear_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
3157                 if (tx_buffer->next_to_watch &&
3158                     time_after(jiffies, tx_buffer->time_stamp +
3159                     (adapter->tx_timeout_factor * HZ)) &&
3160                     !(rd32(IGC_STATUS) & IGC_STATUS_TXOFF) &&
3161                     (rd32(IGC_TDH(tx_ring->reg_idx)) != readl(tx_ring->tail)) &&
3162                     !tx_ring->oper_gate_closed) {
3163                         /* detected Tx unit hang */
3164                         netdev_err(tx_ring->netdev,
3165                                    "Detected Tx Unit Hang\n"
3166                                    "  Tx Queue             <%d>\n"
3167                                    "  TDH                  <%x>\n"
3168                                    "  TDT                  <%x>\n"
3169                                    "  next_to_use          <%x>\n"
3170                                    "  next_to_clean        <%x>\n"
3171                                    "buffer_info[next_to_clean]\n"
3172                                    "  time_stamp           <%lx>\n"
3173                                    "  next_to_watch        <%p>\n"
3174                                    "  jiffies              <%lx>\n"
3175                                    "  desc.status          <%x>\n",
3176                                    tx_ring->queue_index,
3177                                    rd32(IGC_TDH(tx_ring->reg_idx)),
3178                                    readl(tx_ring->tail),
3179                                    tx_ring->next_to_use,
3180                                    tx_ring->next_to_clean,
3181                                    tx_buffer->time_stamp,
3182                                    tx_buffer->next_to_watch,
3183                                    jiffies,
3184                                    tx_buffer->next_to_watch->wb.status);
3185                         netif_stop_subqueue(tx_ring->netdev,
3186                                             tx_ring->queue_index);
3187
3188                         /* we are about to reset, no point in enabling stuff */
3189                         return true;
3190                 }
3191         }
3192
3193 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
3194         if (unlikely(total_packets &&
3195                      netif_carrier_ok(tx_ring->netdev) &&
3196                      igc_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
3197                 /* Make sure that anybody stopping the queue after this
3198                  * sees the new next_to_clean.
3199                  */
3200                 smp_mb();
3201                 if (__netif_subqueue_stopped(tx_ring->netdev,
3202                                              tx_ring->queue_index) &&
3203                     !(test_bit(__IGC_DOWN, &adapter->state))) {
3204                         netif_wake_subqueue(tx_ring->netdev,
3205                                             tx_ring->queue_index);
3206
3207                         u64_stats_update_begin(&tx_ring->tx_syncp);
3208                         tx_ring->tx_stats.restart_queue++;
3209                         u64_stats_update_end(&tx_ring->tx_syncp);
3210                 }
3211         }
3212
3213         return !!budget;
3214 }
3215
3216 static int igc_find_mac_filter(struct igc_adapter *adapter,
3217                                enum igc_mac_filter_type type, const u8 *addr)
3218 {
3219         struct igc_hw *hw = &adapter->hw;
3220         int max_entries = hw->mac.rar_entry_count;
3221         u32 ral, rah;
3222         int i;
3223
3224         for (i = 0; i < max_entries; i++) {
3225                 ral = rd32(IGC_RAL(i));
3226                 rah = rd32(IGC_RAH(i));
3227
3228                 if (!(rah & IGC_RAH_AV))
3229                         continue;
3230                 if (!!(rah & IGC_RAH_ASEL_SRC_ADDR) != type)
3231                         continue;
3232                 if ((rah & IGC_RAH_RAH_MASK) !=
3233                     le16_to_cpup((__le16 *)(addr + 4)))
3234                         continue;
3235                 if (ral != le32_to_cpup((__le32 *)(addr)))
3236                         continue;
3237
3238                 return i;
3239         }
3240
3241         return -1;
3242 }
3243
3244 static int igc_get_avail_mac_filter_slot(struct igc_adapter *adapter)
3245 {
3246         struct igc_hw *hw = &adapter->hw;
3247         int max_entries = hw->mac.rar_entry_count;
3248         u32 rah;
3249         int i;
3250
3251         for (i = 0; i < max_entries; i++) {
3252                 rah = rd32(IGC_RAH(i));
3253
3254                 if (!(rah & IGC_RAH_AV))
3255                         return i;
3256         }
3257
3258         return -1;
3259 }
3260
3261 /**
3262  * igc_add_mac_filter() - Add MAC address filter
3263  * @adapter: Pointer to adapter where the filter should be added
3264  * @type: MAC address filter type (source or destination)
3265  * @addr: MAC address
3266  * @queue: If non-negative, queue assignment feature is enabled and frames
3267  *         matching the filter are enqueued onto 'queue'. Otherwise, queue
3268  *         assignment is disabled.
3269  *
3270  * Return: 0 in case of success, negative errno code otherwise.
3271  */
3272 static int igc_add_mac_filter(struct igc_adapter *adapter,
3273                               enum igc_mac_filter_type type, const u8 *addr,
3274                               int queue)
3275 {
3276         struct net_device *dev = adapter->netdev;
3277         int index;
3278
3279         index = igc_find_mac_filter(adapter, type, addr);
3280         if (index >= 0)
3281                 goto update_filter;
3282
3283         index = igc_get_avail_mac_filter_slot(adapter);
3284         if (index < 0)
3285                 return -ENOSPC;
3286
3287         netdev_dbg(dev, "Add MAC address filter: index %d type %s address %pM queue %d\n",
3288                    index, type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src",
3289                    addr, queue);
3290
3291 update_filter:
3292         igc_set_mac_filter_hw(adapter, index, type, addr, queue);
3293         return 0;
3294 }
3295
3296 /**
3297  * igc_del_mac_filter() - Delete MAC address filter
3298  * @adapter: Pointer to adapter where the filter should be deleted from
3299  * @type: MAC address filter type (source or destination)
3300  * @addr: MAC address
3301  */
3302 static void igc_del_mac_filter(struct igc_adapter *adapter,
3303                                enum igc_mac_filter_type type, const u8 *addr)
3304 {
3305         struct net_device *dev = adapter->netdev;
3306         int index;
3307
3308         index = igc_find_mac_filter(adapter, type, addr);
3309         if (index < 0)
3310                 return;
3311
3312         if (index == 0) {
3313                 /* If this is the default filter, we don't actually delete it.
3314                  * We just reset to its default value i.e. disable queue
3315                  * assignment.
3316                  */
3317                 netdev_dbg(dev, "Disable default MAC filter queue assignment");
3318
3319                 igc_set_mac_filter_hw(adapter, 0, type, addr, -1);
3320         } else {
3321                 netdev_dbg(dev, "Delete MAC address filter: index %d type %s address %pM\n",
3322                            index,
3323                            type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src",
3324                            addr);
3325
3326                 igc_clear_mac_filter_hw(adapter, index);
3327         }
3328 }
3329
3330 /**
3331  * igc_add_vlan_prio_filter() - Add VLAN priority filter
3332  * @adapter: Pointer to adapter where the filter should be added
3333  * @prio: VLAN priority value
3334  * @queue: Queue number which matching frames are assigned to
3335  *
3336  * Return: 0 in case of success, negative errno code otherwise.
3337  */
3338 static int igc_add_vlan_prio_filter(struct igc_adapter *adapter, int prio,
3339                                     int queue)
3340 {
3341         struct net_device *dev = adapter->netdev;
3342         struct igc_hw *hw = &adapter->hw;
3343         u32 vlanpqf;
3344
3345         vlanpqf = rd32(IGC_VLANPQF);
3346
3347         if (vlanpqf & IGC_VLANPQF_VALID(prio)) {
3348                 netdev_dbg(dev, "VLAN priority filter already in use\n");
3349                 return -EEXIST;
3350         }
3351
3352         vlanpqf |= IGC_VLANPQF_QSEL(prio, queue);
3353         vlanpqf |= IGC_VLANPQF_VALID(prio);
3354
3355         wr32(IGC_VLANPQF, vlanpqf);
3356
3357         netdev_dbg(dev, "Add VLAN priority filter: prio %d queue %d\n",
3358                    prio, queue);
3359         return 0;
3360 }
3361
3362 /**
3363  * igc_del_vlan_prio_filter() - Delete VLAN priority filter
3364  * @adapter: Pointer to adapter where the filter should be deleted from
3365  * @prio: VLAN priority value
3366  */
3367 static void igc_del_vlan_prio_filter(struct igc_adapter *adapter, int prio)
3368 {
3369         struct igc_hw *hw = &adapter->hw;
3370         u32 vlanpqf;
3371
3372         vlanpqf = rd32(IGC_VLANPQF);
3373
3374         vlanpqf &= ~IGC_VLANPQF_VALID(prio);
3375         vlanpqf &= ~IGC_VLANPQF_QSEL(prio, IGC_VLANPQF_QUEUE_MASK);
3376
3377         wr32(IGC_VLANPQF, vlanpqf);
3378
3379         netdev_dbg(adapter->netdev, "Delete VLAN priority filter: prio %d\n",
3380                    prio);
3381 }
3382
3383 static int igc_get_avail_etype_filter_slot(struct igc_adapter *adapter)
3384 {
3385         struct igc_hw *hw = &adapter->hw;
3386         int i;
3387
3388         for (i = 0; i < MAX_ETYPE_FILTER; i++) {
3389                 u32 etqf = rd32(IGC_ETQF(i));
3390
3391                 if (!(etqf & IGC_ETQF_FILTER_ENABLE))
3392                         return i;
3393         }
3394
3395         return -1;
3396 }
3397
3398 /**
3399  * igc_add_etype_filter() - Add ethertype filter
3400  * @adapter: Pointer to adapter where the filter should be added
3401  * @etype: Ethertype value
3402  * @queue: If non-negative, queue assignment feature is enabled and frames
3403  *         matching the filter are enqueued onto 'queue'. Otherwise, queue
3404  *         assignment is disabled.
3405  *
3406  * Return: 0 in case of success, negative errno code otherwise.
3407  */
3408 static int igc_add_etype_filter(struct igc_adapter *adapter, u16 etype,
3409                                 int queue)
3410 {
3411         struct igc_hw *hw = &adapter->hw;
3412         int index;
3413         u32 etqf;
3414
3415         index = igc_get_avail_etype_filter_slot(adapter);
3416         if (index < 0)
3417                 return -ENOSPC;
3418
3419         etqf = rd32(IGC_ETQF(index));
3420
3421         etqf &= ~IGC_ETQF_ETYPE_MASK;
3422         etqf |= etype;
3423
3424         if (queue >= 0) {
3425                 etqf &= ~IGC_ETQF_QUEUE_MASK;
3426                 etqf |= (queue << IGC_ETQF_QUEUE_SHIFT);
3427                 etqf |= IGC_ETQF_QUEUE_ENABLE;
3428         }
3429
3430         etqf |= IGC_ETQF_FILTER_ENABLE;
3431
3432         wr32(IGC_ETQF(index), etqf);
3433
3434         netdev_dbg(adapter->netdev, "Add ethertype filter: etype %04x queue %d\n",
3435                    etype, queue);
3436         return 0;
3437 }
3438
3439 static int igc_find_etype_filter(struct igc_adapter *adapter, u16 etype)
3440 {
3441         struct igc_hw *hw = &adapter->hw;
3442         int i;
3443
3444         for (i = 0; i < MAX_ETYPE_FILTER; i++) {
3445                 u32 etqf = rd32(IGC_ETQF(i));
3446
3447                 if ((etqf & IGC_ETQF_ETYPE_MASK) == etype)
3448                         return i;
3449         }
3450
3451         return -1;
3452 }
3453
3454 /**
3455  * igc_del_etype_filter() - Delete ethertype filter
3456  * @adapter: Pointer to adapter where the filter should be deleted from
3457  * @etype: Ethertype value
3458  */
3459 static void igc_del_etype_filter(struct igc_adapter *adapter, u16 etype)
3460 {
3461         struct igc_hw *hw = &adapter->hw;
3462         int index;
3463
3464         index = igc_find_etype_filter(adapter, etype);
3465         if (index < 0)
3466                 return;
3467
3468         wr32(IGC_ETQF(index), 0);
3469
3470         netdev_dbg(adapter->netdev, "Delete ethertype filter: etype %04x\n",
3471                    etype);
3472 }
3473
3474 static int igc_flex_filter_select(struct igc_adapter *adapter,
3475                                   struct igc_flex_filter *input,
3476                                   u32 *fhft)
3477 {
3478         struct igc_hw *hw = &adapter->hw;
3479         u8 fhft_index;
3480         u32 fhftsl;
3481
3482         if (input->index >= MAX_FLEX_FILTER) {
3483                 netdev_err(adapter->netdev, "Wrong Flex Filter index selected!\n");
3484                 return -EINVAL;
3485         }
3486
3487         /* Indirect table select register */
3488         fhftsl = rd32(IGC_FHFTSL);
3489         fhftsl &= ~IGC_FHFTSL_FTSL_MASK;
3490         switch (input->index) {
3491         case 0 ... 7:
3492                 fhftsl |= 0x00;
3493                 break;
3494         case 8 ... 15:
3495                 fhftsl |= 0x01;
3496                 break;
3497         case 16 ... 23:
3498                 fhftsl |= 0x02;
3499                 break;
3500         case 24 ... 31:
3501                 fhftsl |= 0x03;
3502                 break;
3503         }
3504         wr32(IGC_FHFTSL, fhftsl);
3505
3506         /* Normalize index down to host table register */
3507         fhft_index = input->index % 8;
3508
3509         *fhft = (fhft_index < 4) ? IGC_FHFT(fhft_index) :
3510                 IGC_FHFT_EXT(fhft_index - 4);
3511
3512         return 0;
3513 }
3514
3515 static int igc_write_flex_filter_ll(struct igc_adapter *adapter,
3516                                     struct igc_flex_filter *input)
3517 {
3518         struct igc_hw *hw = &adapter->hw;
3519         u8 *data = input->data;
3520         u8 *mask = input->mask;
3521         u32 queuing;
3522         u32 fhft;
3523         u32 wufc;
3524         int ret;
3525         int i;
3526
3527         /* Length has to be aligned to 8. Otherwise the filter will fail. Bail
3528          * out early to avoid surprises later.
3529          */
3530         if (input->length % 8 != 0) {
3531                 netdev_err(adapter->netdev, "The length of a flex filter has to be 8 byte aligned!\n");
3532                 return -EINVAL;
3533         }
3534
3535         /* Select corresponding flex filter register and get base for host table. */
3536         ret = igc_flex_filter_select(adapter, input, &fhft);
3537         if (ret)
3538                 return ret;
3539
3540         /* When adding a filter globally disable flex filter feature. That is
3541          * recommended within the datasheet.
3542          */
3543         wufc = rd32(IGC_WUFC);
3544         wufc &= ~IGC_WUFC_FLEX_HQ;
3545         wr32(IGC_WUFC, wufc);
3546
3547         /* Configure filter */
3548         queuing = input->length & IGC_FHFT_LENGTH_MASK;
3549         queuing |= FIELD_PREP(IGC_FHFT_QUEUE_MASK, input->rx_queue);
3550         queuing |= FIELD_PREP(IGC_FHFT_PRIO_MASK, input->prio);
3551
3552         if (input->immediate_irq)
3553                 queuing |= IGC_FHFT_IMM_INT;
3554
3555         if (input->drop)
3556                 queuing |= IGC_FHFT_DROP;
3557
3558         wr32(fhft + 0xFC, queuing);
3559
3560         /* Write data (128 byte) and mask (128 bit) */
3561         for (i = 0; i < 16; ++i) {
3562                 const size_t data_idx = i * 8;
3563                 const size_t row_idx = i * 16;
3564                 u32 dw0 =
3565                         (data[data_idx + 0] << 0) |
3566                         (data[data_idx + 1] << 8) |
3567                         (data[data_idx + 2] << 16) |
3568                         (data[data_idx + 3] << 24);
3569                 u32 dw1 =
3570                         (data[data_idx + 4] << 0) |
3571                         (data[data_idx + 5] << 8) |
3572                         (data[data_idx + 6] << 16) |
3573                         (data[data_idx + 7] << 24);
3574                 u32 tmp;
3575
3576                 /* Write row: dw0, dw1 and mask */
3577                 wr32(fhft + row_idx, dw0);
3578                 wr32(fhft + row_idx + 4, dw1);
3579
3580                 /* mask is only valid for MASK(7, 0) */
3581                 tmp = rd32(fhft + row_idx + 8);
3582                 tmp &= ~GENMASK(7, 0);
3583                 tmp |= mask[i];
3584                 wr32(fhft + row_idx + 8, tmp);
3585         }
3586
3587         /* Enable filter. */
3588         wufc |= IGC_WUFC_FLEX_HQ;
3589         if (input->index > 8) {
3590                 /* Filter 0-7 are enabled via WUFC. The other 24 filters are not. */
3591                 u32 wufc_ext = rd32(IGC_WUFC_EXT);
3592
3593                 wufc_ext |= (IGC_WUFC_EXT_FLX8 << (input->index - 8));
3594
3595                 wr32(IGC_WUFC_EXT, wufc_ext);
3596         } else {
3597                 wufc |= (IGC_WUFC_FLX0 << input->index);
3598         }
3599         wr32(IGC_WUFC, wufc);
3600
3601         netdev_dbg(adapter->netdev, "Added flex filter %u to HW.\n",
3602                    input->index);
3603
3604         return 0;
3605 }
3606
3607 static void igc_flex_filter_add_field(struct igc_flex_filter *flex,
3608                                       const void *src, unsigned int offset,
3609                                       size_t len, const void *mask)
3610 {
3611         int i;
3612
3613         /* data */
3614         memcpy(&flex->data[offset], src, len);
3615
3616         /* mask */
3617         for (i = 0; i < len; ++i) {
3618                 const unsigned int idx = i + offset;
3619                 const u8 *ptr = mask;
3620
3621                 if (mask) {
3622                         if (ptr[i] & 0xff)
3623                                 flex->mask[idx / 8] |= BIT(idx % 8);
3624
3625                         continue;
3626                 }
3627
3628                 flex->mask[idx / 8] |= BIT(idx % 8);
3629         }
3630 }
3631
3632 static int igc_find_avail_flex_filter_slot(struct igc_adapter *adapter)
3633 {
3634         struct igc_hw *hw = &adapter->hw;
3635         u32 wufc, wufc_ext;
3636         int i;
3637
3638         wufc = rd32(IGC_WUFC);
3639         wufc_ext = rd32(IGC_WUFC_EXT);
3640
3641         for (i = 0; i < MAX_FLEX_FILTER; i++) {
3642                 if (i < 8) {
3643                         if (!(wufc & (IGC_WUFC_FLX0 << i)))
3644                                 return i;
3645                 } else {
3646                         if (!(wufc_ext & (IGC_WUFC_EXT_FLX8 << (i - 8))))
3647                                 return i;
3648                 }
3649         }
3650
3651         return -ENOSPC;
3652 }
3653
3654 static bool igc_flex_filter_in_use(struct igc_adapter *adapter)
3655 {
3656         struct igc_hw *hw = &adapter->hw;
3657         u32 wufc, wufc_ext;
3658
3659         wufc = rd32(IGC_WUFC);
3660         wufc_ext = rd32(IGC_WUFC_EXT);
3661
3662         if (wufc & IGC_WUFC_FILTER_MASK)
3663                 return true;
3664
3665         if (wufc_ext & IGC_WUFC_EXT_FILTER_MASK)
3666                 return true;
3667
3668         return false;
3669 }
3670
3671 static int igc_add_flex_filter(struct igc_adapter *adapter,
3672                                struct igc_nfc_rule *rule)
3673 {
3674         struct igc_nfc_filter *filter = &rule->filter;
3675         unsigned int eth_offset, user_offset;
3676         struct igc_flex_filter flex = { };
3677         int ret, index;
3678         bool vlan;
3679
3680         index = igc_find_avail_flex_filter_slot(adapter);
3681         if (index < 0)
3682                 return -ENOSPC;
3683
3684         /* Construct the flex filter:
3685          *  -> dest_mac [6]
3686          *  -> src_mac [6]
3687          *  -> tpid [2]
3688          *  -> vlan tci [2]
3689          *  -> ether type [2]
3690          *  -> user data [8]
3691          *  -> = 26 bytes => 32 length
3692          */
3693         flex.index    = index;
3694         flex.length   = 32;
3695         flex.rx_queue = rule->action;
3696
3697         vlan = rule->filter.vlan_tci || rule->filter.vlan_etype;
3698         eth_offset = vlan ? 16 : 12;
3699         user_offset = vlan ? 18 : 14;
3700
3701         /* Add destination MAC  */
3702         if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR)
3703                 igc_flex_filter_add_field(&flex, &filter->dst_addr, 0,
3704                                           ETH_ALEN, NULL);
3705
3706         /* Add source MAC */
3707         if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR)
3708                 igc_flex_filter_add_field(&flex, &filter->src_addr, 6,
3709                                           ETH_ALEN, NULL);
3710
3711         /* Add VLAN etype */
3712         if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_ETYPE) {
3713                 __be16 vlan_etype = cpu_to_be16(filter->vlan_etype);
3714
3715                 igc_flex_filter_add_field(&flex, &vlan_etype, 12,
3716                                           sizeof(vlan_etype), NULL);
3717         }
3718
3719         /* Add VLAN TCI */
3720         if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI)
3721                 igc_flex_filter_add_field(&flex, &filter->vlan_tci, 14,
3722                                           sizeof(filter->vlan_tci), NULL);
3723
3724         /* Add Ether type */
3725         if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) {
3726                 __be16 etype = cpu_to_be16(filter->etype);
3727
3728                 igc_flex_filter_add_field(&flex, &etype, eth_offset,
3729                                           sizeof(etype), NULL);
3730         }
3731
3732         /* Add user data */
3733         if (rule->filter.match_flags & IGC_FILTER_FLAG_USER_DATA)
3734                 igc_flex_filter_add_field(&flex, &filter->user_data,
3735                                           user_offset,
3736                                           sizeof(filter->user_data),
3737                                           filter->user_mask);
3738
3739         /* Add it down to the hardware and enable it. */
3740         ret = igc_write_flex_filter_ll(adapter, &flex);
3741         if (ret)
3742                 return ret;
3743
3744         filter->flex_index = index;
3745
3746         return 0;
3747 }
3748
3749 static void igc_del_flex_filter(struct igc_adapter *adapter,
3750                                 u16 reg_index)
3751 {
3752         struct igc_hw *hw = &adapter->hw;
3753         u32 wufc;
3754
3755         /* Just disable the filter. The filter table itself is kept
3756          * intact. Another flex_filter_add() should override the "old" data
3757          * then.
3758          */
3759         if (reg_index > 8) {
3760                 u32 wufc_ext = rd32(IGC_WUFC_EXT);
3761
3762                 wufc_ext &= ~(IGC_WUFC_EXT_FLX8 << (reg_index - 8));
3763                 wr32(IGC_WUFC_EXT, wufc_ext);
3764         } else {
3765                 wufc = rd32(IGC_WUFC);
3766
3767                 wufc &= ~(IGC_WUFC_FLX0 << reg_index);
3768                 wr32(IGC_WUFC, wufc);
3769         }
3770
3771         if (igc_flex_filter_in_use(adapter))
3772                 return;
3773
3774         /* No filters are in use, we may disable flex filters */
3775         wufc = rd32(IGC_WUFC);
3776         wufc &= ~IGC_WUFC_FLEX_HQ;
3777         wr32(IGC_WUFC, wufc);
3778 }
3779
3780 static int igc_enable_nfc_rule(struct igc_adapter *adapter,
3781                                struct igc_nfc_rule *rule)
3782 {
3783         int err;
3784
3785         if (rule->flex) {
3786                 return igc_add_flex_filter(adapter, rule);
3787         }
3788
3789         if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) {
3790                 err = igc_add_etype_filter(adapter, rule->filter.etype,
3791                                            rule->action);
3792                 if (err)
3793                         return err;
3794         }
3795
3796         if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR) {
3797                 err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC,
3798                                          rule->filter.src_addr, rule->action);
3799                 if (err)
3800                         return err;
3801         }
3802
3803         if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR) {
3804                 err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST,
3805                                          rule->filter.dst_addr, rule->action);
3806                 if (err)
3807                         return err;
3808         }
3809
3810         if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) {
3811                 int prio = FIELD_GET(VLAN_PRIO_MASK, rule->filter.vlan_tci);
3812
3813                 err = igc_add_vlan_prio_filter(adapter, prio, rule->action);
3814                 if (err)
3815                         return err;
3816         }
3817
3818         return 0;
3819 }
3820
3821 static void igc_disable_nfc_rule(struct igc_adapter *adapter,
3822                                  const struct igc_nfc_rule *rule)
3823 {
3824         if (rule->flex) {
3825                 igc_del_flex_filter(adapter, rule->filter.flex_index);
3826                 return;
3827         }
3828
3829         if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE)
3830                 igc_del_etype_filter(adapter, rule->filter.etype);
3831
3832         if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) {
3833                 int prio = FIELD_GET(VLAN_PRIO_MASK, rule->filter.vlan_tci);
3834
3835                 igc_del_vlan_prio_filter(adapter, prio);
3836         }
3837
3838         if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR)
3839                 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC,
3840                                    rule->filter.src_addr);
3841
3842         if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR)
3843                 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST,
3844                                    rule->filter.dst_addr);
3845 }
3846
3847 /**
3848  * igc_get_nfc_rule() - Get NFC rule
3849  * @adapter: Pointer to adapter
3850  * @location: Rule location
3851  *
3852  * Context: Expects adapter->nfc_rule_lock to be held by caller.
3853  *
3854  * Return: Pointer to NFC rule at @location. If not found, NULL.
3855  */
3856 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
3857                                       u32 location)
3858 {
3859         struct igc_nfc_rule *rule;
3860
3861         list_for_each_entry(rule, &adapter->nfc_rule_list, list) {
3862                 if (rule->location == location)
3863                         return rule;
3864                 if (rule->location > location)
3865                         break;
3866         }
3867
3868         return NULL;
3869 }
3870
3871 /**
3872  * igc_del_nfc_rule() - Delete NFC rule
3873  * @adapter: Pointer to adapter
3874  * @rule: Pointer to rule to be deleted
3875  *
3876  * Disable NFC rule in hardware and delete it from adapter.
3877  *
3878  * Context: Expects adapter->nfc_rule_lock to be held by caller.
3879  */
3880 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule)
3881 {
3882         igc_disable_nfc_rule(adapter, rule);
3883
3884         list_del(&rule->list);
3885         adapter->nfc_rule_count--;
3886
3887         kfree(rule);
3888 }
3889
3890 static void igc_flush_nfc_rules(struct igc_adapter *adapter)
3891 {
3892         struct igc_nfc_rule *rule, *tmp;
3893
3894         mutex_lock(&adapter->nfc_rule_lock);
3895
3896         list_for_each_entry_safe(rule, tmp, &adapter->nfc_rule_list, list)
3897                 igc_del_nfc_rule(adapter, rule);
3898
3899         mutex_unlock(&adapter->nfc_rule_lock);
3900 }
3901
3902 /**
3903  * igc_add_nfc_rule() - Add NFC rule
3904  * @adapter: Pointer to adapter
3905  * @rule: Pointer to rule to be added
3906  *
3907  * Enable NFC rule in hardware and add it to adapter.
3908  *
3909  * Context: Expects adapter->nfc_rule_lock to be held by caller.
3910  *
3911  * Return: 0 on success, negative errno on failure.
3912  */
3913 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule)
3914 {
3915         struct igc_nfc_rule *pred, *cur;
3916         int err;
3917
3918         err = igc_enable_nfc_rule(adapter, rule);
3919         if (err)
3920                 return err;
3921
3922         pred = NULL;
3923         list_for_each_entry(cur, &adapter->nfc_rule_list, list) {
3924                 if (cur->location >= rule->location)
3925                         break;
3926                 pred = cur;
3927         }
3928
3929         list_add(&rule->list, pred ? &pred->list : &adapter->nfc_rule_list);
3930         adapter->nfc_rule_count++;
3931         return 0;
3932 }
3933
3934 static void igc_restore_nfc_rules(struct igc_adapter *adapter)
3935 {
3936         struct igc_nfc_rule *rule;
3937
3938         mutex_lock(&adapter->nfc_rule_lock);
3939
3940         list_for_each_entry_reverse(rule, &adapter->nfc_rule_list, list)
3941                 igc_enable_nfc_rule(adapter, rule);
3942
3943         mutex_unlock(&adapter->nfc_rule_lock);
3944 }
3945
3946 static int igc_uc_sync(struct net_device *netdev, const unsigned char *addr)
3947 {
3948         struct igc_adapter *adapter = netdev_priv(netdev);
3949
3950         return igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr, -1);
3951 }
3952
3953 static int igc_uc_unsync(struct net_device *netdev, const unsigned char *addr)
3954 {
3955         struct igc_adapter *adapter = netdev_priv(netdev);
3956
3957         igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr);
3958         return 0;
3959 }
3960
3961 /**
3962  * igc_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3963  * @netdev: network interface device structure
3964  *
3965  * The set_rx_mode entry point is called whenever the unicast or multicast
3966  * address lists or the network interface flags are updated.  This routine is
3967  * responsible for configuring the hardware for proper unicast, multicast,
3968  * promiscuous mode, and all-multi behavior.
3969  */
3970 static void igc_set_rx_mode(struct net_device *netdev)
3971 {
3972         struct igc_adapter *adapter = netdev_priv(netdev);
3973         struct igc_hw *hw = &adapter->hw;
3974         u32 rctl = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
3975         int count;
3976
3977         /* Check for Promiscuous and All Multicast modes */
3978         if (netdev->flags & IFF_PROMISC) {
3979                 rctl |= IGC_RCTL_UPE | IGC_RCTL_MPE;
3980         } else {
3981                 if (netdev->flags & IFF_ALLMULTI) {
3982                         rctl |= IGC_RCTL_MPE;
3983                 } else {
3984                         /* Write addresses to the MTA, if the attempt fails
3985                          * then we should just turn on promiscuous mode so
3986                          * that we can at least receive multicast traffic
3987                          */
3988                         count = igc_write_mc_addr_list(netdev);
3989                         if (count < 0)
3990                                 rctl |= IGC_RCTL_MPE;
3991                 }
3992         }
3993
3994         /* Write addresses to available RAR registers, if there is not
3995          * sufficient space to store all the addresses then enable
3996          * unicast promiscuous mode
3997          */
3998         if (__dev_uc_sync(netdev, igc_uc_sync, igc_uc_unsync))
3999                 rctl |= IGC_RCTL_UPE;
4000
4001         /* update state of unicast and multicast */
4002         rctl |= rd32(IGC_RCTL) & ~(IGC_RCTL_UPE | IGC_RCTL_MPE);
4003         wr32(IGC_RCTL, rctl);
4004
4005 #if (PAGE_SIZE < 8192)
4006         if (adapter->max_frame_size <= IGC_MAX_FRAME_BUILD_SKB)
4007                 rlpml = IGC_MAX_FRAME_BUILD_SKB;
4008 #endif
4009         wr32(IGC_RLPML, rlpml);
4010 }
4011
4012 /**
4013  * igc_configure - configure the hardware for RX and TX
4014  * @adapter: private board structure
4015  */
4016 static void igc_configure(struct igc_adapter *adapter)
4017 {
4018         struct net_device *netdev = adapter->netdev;
4019         int i = 0;
4020
4021         igc_get_hw_control(adapter);
4022         igc_set_rx_mode(netdev);
4023
4024         igc_restore_vlan(adapter);
4025
4026         igc_setup_tctl(adapter);
4027         igc_setup_mrqc(adapter);
4028         igc_setup_rctl(adapter);
4029
4030         igc_set_default_mac_filter(adapter);
4031         igc_restore_nfc_rules(adapter);
4032
4033         igc_configure_tx(adapter);
4034         igc_configure_rx(adapter);
4035
4036         igc_rx_fifo_flush_base(&adapter->hw);
4037
4038         /* call igc_desc_unused which always leaves
4039          * at least 1 descriptor unused to make sure
4040          * next_to_use != next_to_clean
4041          */
4042         for (i = 0; i < adapter->num_rx_queues; i++) {
4043                 struct igc_ring *ring = adapter->rx_ring[i];
4044
4045                 if (ring->xsk_pool)
4046                         igc_alloc_rx_buffers_zc(ring, igc_desc_unused(ring));
4047                 else
4048                         igc_alloc_rx_buffers(ring, igc_desc_unused(ring));
4049         }
4050 }
4051
4052 /**
4053  * igc_write_ivar - configure ivar for given MSI-X vector
4054  * @hw: pointer to the HW structure
4055  * @msix_vector: vector number we are allocating to a given ring
4056  * @index: row index of IVAR register to write within IVAR table
4057  * @offset: column offset of in IVAR, should be multiple of 8
4058  *
4059  * The IVAR table consists of 2 columns,
4060  * each containing an cause allocation for an Rx and Tx ring, and a
4061  * variable number of rows depending on the number of queues supported.
4062  */
4063 static void igc_write_ivar(struct igc_hw *hw, int msix_vector,
4064                            int index, int offset)
4065 {
4066         u32 ivar = array_rd32(IGC_IVAR0, index);
4067
4068         /* clear any bits that are currently set */
4069         ivar &= ~((u32)0xFF << offset);
4070
4071         /* write vector and valid bit */
4072         ivar |= (msix_vector | IGC_IVAR_VALID) << offset;
4073
4074         array_wr32(IGC_IVAR0, index, ivar);
4075 }
4076
4077 static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector)
4078 {
4079         struct igc_adapter *adapter = q_vector->adapter;
4080         struct igc_hw *hw = &adapter->hw;
4081         int rx_queue = IGC_N0_QUEUE;
4082         int tx_queue = IGC_N0_QUEUE;
4083
4084         if (q_vector->rx.ring)
4085                 rx_queue = q_vector->rx.ring->reg_idx;
4086         if (q_vector->tx.ring)
4087                 tx_queue = q_vector->tx.ring->reg_idx;
4088
4089         switch (hw->mac.type) {
4090         case igc_i225:
4091                 if (rx_queue > IGC_N0_QUEUE)
4092                         igc_write_ivar(hw, msix_vector,
4093                                        rx_queue >> 1,
4094                                        (rx_queue & 0x1) << 4);
4095                 if (tx_queue > IGC_N0_QUEUE)
4096                         igc_write_ivar(hw, msix_vector,
4097                                        tx_queue >> 1,
4098                                        ((tx_queue & 0x1) << 4) + 8);
4099                 q_vector->eims_value = BIT(msix_vector);
4100                 break;
4101         default:
4102                 WARN_ONCE(hw->mac.type != igc_i225, "Wrong MAC type\n");
4103                 break;
4104         }
4105
4106         /* add q_vector eims value to global eims_enable_mask */
4107         adapter->eims_enable_mask |= q_vector->eims_value;
4108
4109         /* configure q_vector to set itr on first interrupt */
4110         q_vector->set_itr = 1;
4111 }
4112
4113 /**
4114  * igc_configure_msix - Configure MSI-X hardware
4115  * @adapter: Pointer to adapter structure
4116  *
4117  * igc_configure_msix sets up the hardware to properly
4118  * generate MSI-X interrupts.
4119  */
4120 static void igc_configure_msix(struct igc_adapter *adapter)
4121 {
4122         struct igc_hw *hw = &adapter->hw;
4123         int i, vector = 0;
4124         u32 tmp;
4125
4126         adapter->eims_enable_mask = 0;
4127
4128         /* set vector for other causes, i.e. link changes */
4129         switch (hw->mac.type) {
4130         case igc_i225:
4131                 /* Turn on MSI-X capability first, or our settings
4132                  * won't stick.  And it will take days to debug.
4133                  */
4134                 wr32(IGC_GPIE, IGC_GPIE_MSIX_MODE |
4135                      IGC_GPIE_PBA | IGC_GPIE_EIAME |
4136                      IGC_GPIE_NSICR);
4137
4138                 /* enable msix_other interrupt */
4139                 adapter->eims_other = BIT(vector);
4140                 tmp = (vector++ | IGC_IVAR_VALID) << 8;
4141
4142                 wr32(IGC_IVAR_MISC, tmp);
4143                 break;
4144         default:
4145                 /* do nothing, since nothing else supports MSI-X */
4146                 break;
4147         } /* switch (hw->mac.type) */
4148
4149         adapter->eims_enable_mask |= adapter->eims_other;
4150
4151         for (i = 0; i < adapter->num_q_vectors; i++)
4152                 igc_assign_vector(adapter->q_vector[i], vector++);
4153
4154         wrfl();
4155 }
4156
4157 /**
4158  * igc_irq_enable - Enable default interrupt generation settings
4159  * @adapter: board private structure
4160  */
4161 static void igc_irq_enable(struct igc_adapter *adapter)
4162 {
4163         struct igc_hw *hw = &adapter->hw;
4164
4165         if (adapter->msix_entries) {
4166                 u32 ims = IGC_IMS_LSC | IGC_IMS_DOUTSYNC | IGC_IMS_DRSTA;
4167                 u32 regval = rd32(IGC_EIAC);
4168
4169                 wr32(IGC_EIAC, regval | adapter->eims_enable_mask);
4170                 regval = rd32(IGC_EIAM);
4171                 wr32(IGC_EIAM, regval | adapter->eims_enable_mask);
4172                 wr32(IGC_EIMS, adapter->eims_enable_mask);
4173                 wr32(IGC_IMS, ims);
4174         } else {
4175                 wr32(IGC_IMS, IMS_ENABLE_MASK | IGC_IMS_DRSTA);
4176                 wr32(IGC_IAM, IMS_ENABLE_MASK | IGC_IMS_DRSTA);
4177         }
4178 }
4179
4180 /**
4181  * igc_irq_disable - Mask off interrupt generation on the NIC
4182  * @adapter: board private structure
4183  */
4184 static void igc_irq_disable(struct igc_adapter *adapter)
4185 {
4186         struct igc_hw *hw = &adapter->hw;
4187
4188         if (adapter->msix_entries) {
4189                 u32 regval = rd32(IGC_EIAM);
4190
4191                 wr32(IGC_EIAM, regval & ~adapter->eims_enable_mask);
4192                 wr32(IGC_EIMC, adapter->eims_enable_mask);
4193                 regval = rd32(IGC_EIAC);
4194                 wr32(IGC_EIAC, regval & ~adapter->eims_enable_mask);
4195         }
4196
4197         wr32(IGC_IAM, 0);
4198         wr32(IGC_IMC, ~0);
4199         wrfl();
4200
4201         if (adapter->msix_entries) {
4202                 int vector = 0, i;
4203
4204                 synchronize_irq(adapter->msix_entries[vector++].vector);
4205
4206                 for (i = 0; i < adapter->num_q_vectors; i++)
4207                         synchronize_irq(adapter->msix_entries[vector++].vector);
4208         } else {
4209                 synchronize_irq(adapter->pdev->irq);
4210         }
4211 }
4212
4213 void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
4214                               const u32 max_rss_queues)
4215 {
4216         /* Determine if we need to pair queues. */
4217         /* If rss_queues > half of max_rss_queues, pair the queues in
4218          * order to conserve interrupts due to limited supply.
4219          */
4220         if (adapter->rss_queues > (max_rss_queues / 2))
4221                 adapter->flags |= IGC_FLAG_QUEUE_PAIRS;
4222         else
4223                 adapter->flags &= ~IGC_FLAG_QUEUE_PAIRS;
4224 }
4225
4226 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter)
4227 {
4228         return IGC_MAX_RX_QUEUES;
4229 }
4230
4231 static void igc_init_queue_configuration(struct igc_adapter *adapter)
4232 {
4233         u32 max_rss_queues;
4234
4235         max_rss_queues = igc_get_max_rss_queues(adapter);
4236         adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
4237
4238         igc_set_flag_queue_pairs(adapter, max_rss_queues);
4239 }
4240
4241 /**
4242  * igc_reset_q_vector - Reset config for interrupt vector
4243  * @adapter: board private structure to initialize
4244  * @v_idx: Index of vector to be reset
4245  *
4246  * If NAPI is enabled it will delete any references to the
4247  * NAPI struct. This is preparation for igc_free_q_vector.
4248  */
4249 static void igc_reset_q_vector(struct igc_adapter *adapter, int v_idx)
4250 {
4251         struct igc_q_vector *q_vector = adapter->q_vector[v_idx];
4252
4253         /* if we're coming from igc_set_interrupt_capability, the vectors are
4254          * not yet allocated
4255          */
4256         if (!q_vector)
4257                 return;
4258
4259         if (q_vector->tx.ring)
4260                 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
4261
4262         if (q_vector->rx.ring)
4263                 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
4264
4265         netif_napi_del(&q_vector->napi);
4266 }
4267
4268 /**
4269  * igc_free_q_vector - Free memory allocated for specific interrupt vector
4270  * @adapter: board private structure to initialize
4271  * @v_idx: Index of vector to be freed
4272  *
4273  * This function frees the memory allocated to the q_vector.
4274  */
4275 static void igc_free_q_vector(struct igc_adapter *adapter, int v_idx)
4276 {
4277         struct igc_q_vector *q_vector = adapter->q_vector[v_idx];
4278
4279         adapter->q_vector[v_idx] = NULL;
4280
4281         /* igc_get_stats64() might access the rings on this vector,
4282          * we must wait a grace period before freeing it.
4283          */
4284         if (q_vector)
4285                 kfree_rcu(q_vector, rcu);
4286 }
4287
4288 /**
4289  * igc_free_q_vectors - Free memory allocated for interrupt vectors
4290  * @adapter: board private structure to initialize
4291  *
4292  * This function frees the memory allocated to the q_vectors.  In addition if
4293  * NAPI is enabled it will delete any references to the NAPI struct prior
4294  * to freeing the q_vector.
4295  */
4296 static void igc_free_q_vectors(struct igc_adapter *adapter)
4297 {
4298         int v_idx = adapter->num_q_vectors;
4299
4300         adapter->num_tx_queues = 0;
4301         adapter->num_rx_queues = 0;
4302         adapter->num_q_vectors = 0;
4303
4304         while (v_idx--) {
4305                 igc_reset_q_vector(adapter, v_idx);
4306                 igc_free_q_vector(adapter, v_idx);
4307         }
4308 }
4309
4310 /**
4311  * igc_update_itr - update the dynamic ITR value based on statistics
4312  * @q_vector: pointer to q_vector
4313  * @ring_container: ring info to update the itr for
4314  *
4315  * Stores a new ITR value based on packets and byte
4316  * counts during the last interrupt.  The advantage of per interrupt
4317  * computation is faster updates and more accurate ITR for the current
4318  * traffic pattern.  Constants in this function were computed
4319  * based on theoretical maximum wire speed and thresholds were set based
4320  * on testing data as well as attempting to minimize response time
4321  * while increasing bulk throughput.
4322  * NOTE: These calculations are only valid when operating in a single-
4323  * queue environment.
4324  */
4325 static void igc_update_itr(struct igc_q_vector *q_vector,
4326                            struct igc_ring_container *ring_container)
4327 {
4328         unsigned int packets = ring_container->total_packets;
4329         unsigned int bytes = ring_container->total_bytes;
4330         u8 itrval = ring_container->itr;
4331
4332         /* no packets, exit with status unchanged */
4333         if (packets == 0)
4334                 return;
4335
4336         switch (itrval) {
4337         case lowest_latency:
4338                 /* handle TSO and jumbo frames */
4339                 if (bytes / packets > 8000)
4340                         itrval = bulk_latency;
4341                 else if ((packets < 5) && (bytes > 512))
4342                         itrval = low_latency;
4343                 break;
4344         case low_latency:  /* 50 usec aka 20000 ints/s */
4345                 if (bytes > 10000) {
4346                         /* this if handles the TSO accounting */
4347                         if (bytes / packets > 8000)
4348                                 itrval = bulk_latency;
4349                         else if ((packets < 10) || ((bytes / packets) > 1200))
4350                                 itrval = bulk_latency;
4351                         else if ((packets > 35))
4352                                 itrval = lowest_latency;
4353                 } else if (bytes / packets > 2000) {
4354                         itrval = bulk_latency;
4355                 } else if (packets <= 2 && bytes < 512) {
4356                         itrval = lowest_latency;
4357                 }
4358                 break;
4359         case bulk_latency: /* 250 usec aka 4000 ints/s */
4360                 if (bytes > 25000) {
4361                         if (packets > 35)
4362                                 itrval = low_latency;
4363                 } else if (bytes < 1500) {
4364                         itrval = low_latency;
4365                 }
4366                 break;
4367         }
4368
4369         /* clear work counters since we have the values we need */
4370         ring_container->total_bytes = 0;
4371         ring_container->total_packets = 0;
4372
4373         /* write updated itr to ring container */
4374         ring_container->itr = itrval;
4375 }
4376
4377 static void igc_set_itr(struct igc_q_vector *q_vector)
4378 {
4379         struct igc_adapter *adapter = q_vector->adapter;
4380         u32 new_itr = q_vector->itr_val;
4381         u8 current_itr = 0;
4382
4383         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4384         switch (adapter->link_speed) {
4385         case SPEED_10:
4386         case SPEED_100:
4387                 current_itr = 0;
4388                 new_itr = IGC_4K_ITR;
4389                 goto set_itr_now;
4390         default:
4391                 break;
4392         }
4393
4394         igc_update_itr(q_vector, &q_vector->tx);
4395         igc_update_itr(q_vector, &q_vector->rx);
4396
4397         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4398
4399         /* conservative mode (itr 3) eliminates the lowest_latency setting */
4400         if (current_itr == lowest_latency &&
4401             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4402             (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4403                 current_itr = low_latency;
4404
4405         switch (current_itr) {
4406         /* counts and packets in update_itr are dependent on these numbers */
4407         case lowest_latency:
4408                 new_itr = IGC_70K_ITR; /* 70,000 ints/sec */
4409                 break;
4410         case low_latency:
4411                 new_itr = IGC_20K_ITR; /* 20,000 ints/sec */
4412                 break;
4413         case bulk_latency:
4414                 new_itr = IGC_4K_ITR;  /* 4,000 ints/sec */
4415                 break;
4416         default:
4417                 break;
4418         }
4419
4420 set_itr_now:
4421         if (new_itr != q_vector->itr_val) {
4422                 /* this attempts to bias the interrupt rate towards Bulk
4423                  * by adding intermediate steps when interrupt rate is
4424                  * increasing
4425                  */
4426                 new_itr = new_itr > q_vector->itr_val ?
4427                           max((new_itr * q_vector->itr_val) /
4428                           (new_itr + (q_vector->itr_val >> 2)),
4429                           new_itr) : new_itr;
4430                 /* Don't write the value here; it resets the adapter's
4431                  * internal timer, and causes us to delay far longer than
4432                  * we should between interrupts.  Instead, we write the ITR
4433                  * value at the beginning of the next interrupt so the timing
4434                  * ends up being correct.
4435                  */
4436                 q_vector->itr_val = new_itr;
4437                 q_vector->set_itr = 1;
4438         }
4439 }
4440
4441 static void igc_reset_interrupt_capability(struct igc_adapter *adapter)
4442 {
4443         int v_idx = adapter->num_q_vectors;
4444
4445         if (adapter->msix_entries) {
4446                 pci_disable_msix(adapter->pdev);
4447                 kfree(adapter->msix_entries);
4448                 adapter->msix_entries = NULL;
4449         } else if (adapter->flags & IGC_FLAG_HAS_MSI) {
4450                 pci_disable_msi(adapter->pdev);
4451         }
4452
4453         while (v_idx--)
4454                 igc_reset_q_vector(adapter, v_idx);
4455 }
4456
4457 /**
4458  * igc_set_interrupt_capability - set MSI or MSI-X if supported
4459  * @adapter: Pointer to adapter structure
4460  * @msix: boolean value for MSI-X capability
4461  *
4462  * Attempt to configure interrupts using the best available
4463  * capabilities of the hardware and kernel.
4464  */
4465 static void igc_set_interrupt_capability(struct igc_adapter *adapter,
4466                                          bool msix)
4467 {
4468         int numvecs, i;
4469         int err;
4470
4471         if (!msix)
4472                 goto msi_only;
4473         adapter->flags |= IGC_FLAG_HAS_MSIX;
4474
4475         /* Number of supported queues. */
4476         adapter->num_rx_queues = adapter->rss_queues;
4477
4478         adapter->num_tx_queues = adapter->rss_queues;
4479
4480         /* start with one vector for every Rx queue */
4481         numvecs = adapter->num_rx_queues;
4482
4483         /* if Tx handler is separate add 1 for every Tx queue */
4484         if (!(adapter->flags & IGC_FLAG_QUEUE_PAIRS))
4485                 numvecs += adapter->num_tx_queues;
4486
4487         /* store the number of vectors reserved for queues */
4488         adapter->num_q_vectors = numvecs;
4489
4490         /* add 1 vector for link status interrupts */
4491         numvecs++;
4492
4493         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
4494                                         GFP_KERNEL);
4495
4496         if (!adapter->msix_entries)
4497                 return;
4498
4499         /* populate entry values */
4500         for (i = 0; i < numvecs; i++)
4501                 adapter->msix_entries[i].entry = i;
4502
4503         err = pci_enable_msix_range(adapter->pdev,
4504                                     adapter->msix_entries,
4505                                     numvecs,
4506                                     numvecs);
4507         if (err > 0)
4508                 return;
4509
4510         kfree(adapter->msix_entries);
4511         adapter->msix_entries = NULL;
4512
4513         igc_reset_interrupt_capability(adapter);
4514
4515 msi_only:
4516         adapter->flags &= ~IGC_FLAG_HAS_MSIX;
4517
4518         adapter->rss_queues = 1;
4519         adapter->flags |= IGC_FLAG_QUEUE_PAIRS;
4520         adapter->num_rx_queues = 1;
4521         adapter->num_tx_queues = 1;
4522         adapter->num_q_vectors = 1;
4523         if (!pci_enable_msi(adapter->pdev))
4524                 adapter->flags |= IGC_FLAG_HAS_MSI;
4525 }
4526
4527 /**
4528  * igc_update_ring_itr - update the dynamic ITR value based on packet size
4529  * @q_vector: pointer to q_vector
4530  *
4531  * Stores a new ITR value based on strictly on packet size.  This
4532  * algorithm is less sophisticated than that used in igc_update_itr,
4533  * due to the difficulty of synchronizing statistics across multiple
4534  * receive rings.  The divisors and thresholds used by this function
4535  * were determined based on theoretical maximum wire speed and testing
4536  * data, in order to minimize response time while increasing bulk
4537  * throughput.
4538  * NOTE: This function is called only when operating in a multiqueue
4539  * receive environment.
4540  */
4541 static void igc_update_ring_itr(struct igc_q_vector *q_vector)
4542 {
4543         struct igc_adapter *adapter = q_vector->adapter;
4544         int new_val = q_vector->itr_val;
4545         int avg_wire_size = 0;
4546         unsigned int packets;
4547
4548         /* For non-gigabit speeds, just fix the interrupt rate at 4000
4549          * ints/sec - ITR timer value of 120 ticks.
4550          */
4551         switch (adapter->link_speed) {
4552         case SPEED_10:
4553         case SPEED_100:
4554                 new_val = IGC_4K_ITR;
4555                 goto set_itr_val;
4556         default:
4557                 break;
4558         }
4559
4560         packets = q_vector->rx.total_packets;
4561         if (packets)
4562                 avg_wire_size = q_vector->rx.total_bytes / packets;
4563
4564         packets = q_vector->tx.total_packets;
4565         if (packets)
4566                 avg_wire_size = max_t(u32, avg_wire_size,
4567                                       q_vector->tx.total_bytes / packets);
4568
4569         /* if avg_wire_size isn't set no work was done */
4570         if (!avg_wire_size)
4571                 goto clear_counts;
4572
4573         /* Add 24 bytes to size to account for CRC, preamble, and gap */
4574         avg_wire_size += 24;
4575
4576         /* Don't starve jumbo frames */
4577         avg_wire_size = min(avg_wire_size, 3000);
4578
4579         /* Give a little boost to mid-size frames */
4580         if (avg_wire_size > 300 && avg_wire_size < 1200)
4581                 new_val = avg_wire_size / 3;
4582         else
4583                 new_val = avg_wire_size / 2;
4584
4585         /* conservative mode (itr 3) eliminates the lowest_latency setting */
4586         if (new_val < IGC_20K_ITR &&
4587             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4588             (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4589                 new_val = IGC_20K_ITR;
4590
4591 set_itr_val:
4592         if (new_val != q_vector->itr_val) {
4593                 q_vector->itr_val = new_val;
4594                 q_vector->set_itr = 1;
4595         }
4596 clear_counts:
4597         q_vector->rx.total_bytes = 0;
4598         q_vector->rx.total_packets = 0;
4599         q_vector->tx.total_bytes = 0;
4600         q_vector->tx.total_packets = 0;
4601 }
4602
4603 static void igc_ring_irq_enable(struct igc_q_vector *q_vector)
4604 {
4605         struct igc_adapter *adapter = q_vector->adapter;
4606         struct igc_hw *hw = &adapter->hw;
4607
4608         if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
4609             (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
4610                 if (adapter->num_q_vectors == 1)
4611                         igc_set_itr(q_vector);
4612                 else
4613                         igc_update_ring_itr(q_vector);
4614         }
4615
4616         if (!test_bit(__IGC_DOWN, &adapter->state)) {
4617                 if (adapter->msix_entries)
4618                         wr32(IGC_EIMS, q_vector->eims_value);
4619                 else
4620                         igc_irq_enable(adapter);
4621         }
4622 }
4623
4624 static void igc_add_ring(struct igc_ring *ring,
4625                          struct igc_ring_container *head)
4626 {
4627         head->ring = ring;
4628         head->count++;
4629 }
4630
4631 /**
4632  * igc_cache_ring_register - Descriptor ring to register mapping
4633  * @adapter: board private structure to initialize
4634  *
4635  * Once we know the feature-set enabled for the device, we'll cache
4636  * the register offset the descriptor ring is assigned to.
4637  */
4638 static void igc_cache_ring_register(struct igc_adapter *adapter)
4639 {
4640         int i = 0, j = 0;
4641
4642         switch (adapter->hw.mac.type) {
4643         case igc_i225:
4644         default:
4645                 for (; i < adapter->num_rx_queues; i++)
4646                         adapter->rx_ring[i]->reg_idx = i;
4647                 for (; j < adapter->num_tx_queues; j++)
4648                         adapter->tx_ring[j]->reg_idx = j;
4649                 break;
4650         }
4651 }
4652
4653 /**
4654  * igc_poll - NAPI Rx polling callback
4655  * @napi: napi polling structure
4656  * @budget: count of how many packets we should handle
4657  */
4658 static int igc_poll(struct napi_struct *napi, int budget)
4659 {
4660         struct igc_q_vector *q_vector = container_of(napi,
4661                                                      struct igc_q_vector,
4662                                                      napi);
4663         struct igc_ring *rx_ring = q_vector->rx.ring;
4664         bool clean_complete = true;
4665         int work_done = 0;
4666
4667         if (q_vector->tx.ring)
4668                 clean_complete = igc_clean_tx_irq(q_vector, budget);
4669
4670         if (rx_ring) {
4671                 int cleaned = rx_ring->xsk_pool ?
4672                               igc_clean_rx_irq_zc(q_vector, budget) :
4673                               igc_clean_rx_irq(q_vector, budget);
4674
4675                 work_done += cleaned;
4676                 if (cleaned >= budget)
4677                         clean_complete = false;
4678         }
4679
4680         /* If all work not completed, return budget and keep polling */
4681         if (!clean_complete)
4682                 return budget;
4683
4684         /* Exit the polling mode, but don't re-enable interrupts if stack might
4685          * poll us due to busy-polling
4686          */
4687         if (likely(napi_complete_done(napi, work_done)))
4688                 igc_ring_irq_enable(q_vector);
4689
4690         return min(work_done, budget - 1);
4691 }
4692
4693 /**
4694  * igc_alloc_q_vector - Allocate memory for a single interrupt vector
4695  * @adapter: board private structure to initialize
4696  * @v_count: q_vectors allocated on adapter, used for ring interleaving
4697  * @v_idx: index of vector in adapter struct
4698  * @txr_count: total number of Tx rings to allocate
4699  * @txr_idx: index of first Tx ring to allocate
4700  * @rxr_count: total number of Rx rings to allocate
4701  * @rxr_idx: index of first Rx ring to allocate
4702  *
4703  * We allocate one q_vector.  If allocation fails we return -ENOMEM.
4704  */
4705 static int igc_alloc_q_vector(struct igc_adapter *adapter,
4706                               unsigned int v_count, unsigned int v_idx,
4707                               unsigned int txr_count, unsigned int txr_idx,
4708                               unsigned int rxr_count, unsigned int rxr_idx)
4709 {
4710         struct igc_q_vector *q_vector;
4711         struct igc_ring *ring;
4712         int ring_count;
4713
4714         /* igc only supports 1 Tx and/or 1 Rx queue per vector */
4715         if (txr_count > 1 || rxr_count > 1)
4716                 return -ENOMEM;
4717
4718         ring_count = txr_count + rxr_count;
4719
4720         /* allocate q_vector and rings */
4721         q_vector = adapter->q_vector[v_idx];
4722         if (!q_vector)
4723                 q_vector = kzalloc(struct_size(q_vector, ring, ring_count),
4724                                    GFP_KERNEL);
4725         else
4726                 memset(q_vector, 0, struct_size(q_vector, ring, ring_count));
4727         if (!q_vector)
4728                 return -ENOMEM;
4729
4730         /* initialize NAPI */
4731         netif_napi_add(adapter->netdev, &q_vector->napi, igc_poll);
4732
4733         /* tie q_vector and adapter together */
4734         adapter->q_vector[v_idx] = q_vector;
4735         q_vector->adapter = adapter;
4736
4737         /* initialize work limits */
4738         q_vector->tx.work_limit = adapter->tx_work_limit;
4739
4740         /* initialize ITR configuration */
4741         q_vector->itr_register = adapter->io_addr + IGC_EITR(0);
4742         q_vector->itr_val = IGC_START_ITR;
4743
4744         /* initialize pointer to rings */
4745         ring = q_vector->ring;
4746
4747         /* initialize ITR */
4748         if (rxr_count) {
4749                 /* rx or rx/tx vector */
4750                 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
4751                         q_vector->itr_val = adapter->rx_itr_setting;
4752         } else {
4753                 /* tx only vector */
4754                 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
4755                         q_vector->itr_val = adapter->tx_itr_setting;
4756         }
4757
4758         if (txr_count) {
4759                 /* assign generic ring traits */
4760                 ring->dev = &adapter->pdev->dev;
4761                 ring->netdev = adapter->netdev;
4762
4763                 /* configure backlink on ring */
4764                 ring->q_vector = q_vector;
4765
4766                 /* update q_vector Tx values */
4767                 igc_add_ring(ring, &q_vector->tx);
4768
4769                 /* apply Tx specific ring traits */
4770                 ring->count = adapter->tx_ring_count;
4771                 ring->queue_index = txr_idx;
4772
4773                 /* assign ring to adapter */
4774                 adapter->tx_ring[txr_idx] = ring;
4775
4776                 /* push pointer to next ring */
4777                 ring++;
4778         }
4779
4780         if (rxr_count) {
4781                 /* assign generic ring traits */
4782                 ring->dev = &adapter->pdev->dev;
4783                 ring->netdev = adapter->netdev;
4784
4785                 /* configure backlink on ring */
4786                 ring->q_vector = q_vector;
4787
4788                 /* update q_vector Rx values */
4789                 igc_add_ring(ring, &q_vector->rx);
4790
4791                 /* apply Rx specific ring traits */
4792                 ring->count = adapter->rx_ring_count;
4793                 ring->queue_index = rxr_idx;
4794
4795                 /* assign ring to adapter */
4796                 adapter->rx_ring[rxr_idx] = ring;
4797         }
4798
4799         return 0;
4800 }
4801
4802 /**
4803  * igc_alloc_q_vectors - Allocate memory for interrupt vectors
4804  * @adapter: board private structure to initialize
4805  *
4806  * We allocate one q_vector per queue interrupt.  If allocation fails we
4807  * return -ENOMEM.
4808  */
4809 static int igc_alloc_q_vectors(struct igc_adapter *adapter)
4810 {
4811         int rxr_remaining = adapter->num_rx_queues;
4812         int txr_remaining = adapter->num_tx_queues;
4813         int rxr_idx = 0, txr_idx = 0, v_idx = 0;
4814         int q_vectors = adapter->num_q_vectors;
4815         int err;
4816
4817         if (q_vectors >= (rxr_remaining + txr_remaining)) {
4818                 for (; rxr_remaining; v_idx++) {
4819                         err = igc_alloc_q_vector(adapter, q_vectors, v_idx,
4820                                                  0, 0, 1, rxr_idx);
4821
4822                         if (err)
4823                                 goto err_out;
4824
4825                         /* update counts and index */
4826                         rxr_remaining--;
4827                         rxr_idx++;
4828                 }
4829         }
4830
4831         for (; v_idx < q_vectors; v_idx++) {
4832                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
4833                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
4834
4835                 err = igc_alloc_q_vector(adapter, q_vectors, v_idx,
4836                                          tqpv, txr_idx, rqpv, rxr_idx);
4837
4838                 if (err)
4839                         goto err_out;
4840
4841                 /* update counts and index */
4842                 rxr_remaining -= rqpv;
4843                 txr_remaining -= tqpv;
4844                 rxr_idx++;
4845                 txr_idx++;
4846         }
4847
4848         return 0;
4849
4850 err_out:
4851         adapter->num_tx_queues = 0;
4852         adapter->num_rx_queues = 0;
4853         adapter->num_q_vectors = 0;
4854
4855         while (v_idx--)
4856                 igc_free_q_vector(adapter, v_idx);
4857
4858         return -ENOMEM;
4859 }
4860
4861 /**
4862  * igc_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
4863  * @adapter: Pointer to adapter structure
4864  * @msix: boolean for MSI-X capability
4865  *
4866  * This function initializes the interrupts and allocates all of the queues.
4867  */
4868 static int igc_init_interrupt_scheme(struct igc_adapter *adapter, bool msix)
4869 {
4870         struct net_device *dev = adapter->netdev;
4871         int err = 0;
4872
4873         igc_set_interrupt_capability(adapter, msix);
4874
4875         err = igc_alloc_q_vectors(adapter);
4876         if (err) {
4877                 netdev_err(dev, "Unable to allocate memory for vectors\n");
4878                 goto err_alloc_q_vectors;
4879         }
4880
4881         igc_cache_ring_register(adapter);
4882
4883         return 0;
4884
4885 err_alloc_q_vectors:
4886         igc_reset_interrupt_capability(adapter);
4887         return err;
4888 }
4889
4890 /**
4891  * igc_sw_init - Initialize general software structures (struct igc_adapter)
4892  * @adapter: board private structure to initialize
4893  *
4894  * igc_sw_init initializes the Adapter private data structure.
4895  * Fields are initialized based on PCI device information and
4896  * OS network device settings (MTU size).
4897  */
4898 static int igc_sw_init(struct igc_adapter *adapter)
4899 {
4900         struct net_device *netdev = adapter->netdev;
4901         struct pci_dev *pdev = adapter->pdev;
4902         struct igc_hw *hw = &adapter->hw;
4903
4904         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
4905
4906         /* set default ring sizes */
4907         adapter->tx_ring_count = IGC_DEFAULT_TXD;
4908         adapter->rx_ring_count = IGC_DEFAULT_RXD;
4909
4910         /* set default ITR values */
4911         adapter->rx_itr_setting = IGC_DEFAULT_ITR;
4912         adapter->tx_itr_setting = IGC_DEFAULT_ITR;
4913
4914         /* set default work limits */
4915         adapter->tx_work_limit = IGC_DEFAULT_TX_WORK;
4916
4917         /* adjust max frame to be at least the size of a standard frame */
4918         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
4919                                 VLAN_HLEN;
4920         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4921
4922         mutex_init(&adapter->nfc_rule_lock);
4923         INIT_LIST_HEAD(&adapter->nfc_rule_list);
4924         adapter->nfc_rule_count = 0;
4925
4926         spin_lock_init(&adapter->stats64_lock);
4927         spin_lock_init(&adapter->qbv_tx_lock);
4928         /* Assume MSI-X interrupts, will be checked during IRQ allocation */
4929         adapter->flags |= IGC_FLAG_HAS_MSIX;
4930
4931         igc_init_queue_configuration(adapter);
4932
4933         /* This call may decrease the number of queues */
4934         if (igc_init_interrupt_scheme(adapter, true)) {
4935                 netdev_err(netdev, "Unable to allocate memory for queues\n");
4936                 return -ENOMEM;
4937         }
4938
4939         /* Explicitly disable IRQ since the NIC can be in any state. */
4940         igc_irq_disable(adapter);
4941
4942         set_bit(__IGC_DOWN, &adapter->state);
4943
4944         return 0;
4945 }
4946
4947 /**
4948  * igc_up - Open the interface and prepare it to handle traffic
4949  * @adapter: board private structure
4950  */
4951 void igc_up(struct igc_adapter *adapter)
4952 {
4953         struct igc_hw *hw = &adapter->hw;
4954         int i = 0;
4955
4956         /* hardware has been reset, we need to reload some things */
4957         igc_configure(adapter);
4958
4959         clear_bit(__IGC_DOWN, &adapter->state);
4960
4961         for (i = 0; i < adapter->num_q_vectors; i++)
4962                 napi_enable(&adapter->q_vector[i]->napi);
4963
4964         if (adapter->msix_entries)
4965                 igc_configure_msix(adapter);
4966         else
4967                 igc_assign_vector(adapter->q_vector[0], 0);
4968
4969         /* Clear any pending interrupts. */
4970         rd32(IGC_ICR);
4971         igc_irq_enable(adapter);
4972
4973         netif_tx_start_all_queues(adapter->netdev);
4974
4975         /* start the watchdog. */
4976         hw->mac.get_link_status = true;
4977         schedule_work(&adapter->watchdog_task);
4978 }
4979
4980 /**
4981  * igc_update_stats - Update the board statistics counters
4982  * @adapter: board private structure
4983  */
4984 void igc_update_stats(struct igc_adapter *adapter)
4985 {
4986         struct rtnl_link_stats64 *net_stats = &adapter->stats64;
4987         struct pci_dev *pdev = adapter->pdev;
4988         struct igc_hw *hw = &adapter->hw;
4989         u64 _bytes, _packets;
4990         u64 bytes, packets;
4991         unsigned int start;
4992         u32 mpc;
4993         int i;
4994
4995         /* Prevent stats update while adapter is being reset, or if the pci
4996          * connection is down.
4997          */
4998         if (adapter->link_speed == 0)
4999                 return;
5000         if (pci_channel_offline(pdev))
5001                 return;
5002
5003         packets = 0;
5004         bytes = 0;
5005
5006         rcu_read_lock();
5007         for (i = 0; i < adapter->num_rx_queues; i++) {
5008                 struct igc_ring *ring = adapter->rx_ring[i];
5009                 u32 rqdpc = rd32(IGC_RQDPC(i));
5010
5011                 if (hw->mac.type >= igc_i225)
5012                         wr32(IGC_RQDPC(i), 0);
5013
5014                 if (rqdpc) {
5015                         ring->rx_stats.drops += rqdpc;
5016                         net_stats->rx_fifo_errors += rqdpc;
5017                 }
5018
5019                 do {
5020                         start = u64_stats_fetch_begin(&ring->rx_syncp);
5021                         _bytes = ring->rx_stats.bytes;
5022                         _packets = ring->rx_stats.packets;
5023                 } while (u64_stats_fetch_retry(&ring->rx_syncp, start));
5024                 bytes += _bytes;
5025                 packets += _packets;
5026         }
5027
5028         net_stats->rx_bytes = bytes;
5029         net_stats->rx_packets = packets;
5030
5031         packets = 0;
5032         bytes = 0;
5033         for (i = 0; i < adapter->num_tx_queues; i++) {
5034                 struct igc_ring *ring = adapter->tx_ring[i];
5035
5036                 do {
5037                         start = u64_stats_fetch_begin(&ring->tx_syncp);
5038                         _bytes = ring->tx_stats.bytes;
5039                         _packets = ring->tx_stats.packets;
5040                 } while (u64_stats_fetch_retry(&ring->tx_syncp, start));
5041                 bytes += _bytes;
5042                 packets += _packets;
5043         }
5044         net_stats->tx_bytes = bytes;
5045         net_stats->tx_packets = packets;
5046         rcu_read_unlock();
5047
5048         /* read stats registers */
5049         adapter->stats.crcerrs += rd32(IGC_CRCERRS);
5050         adapter->stats.gprc += rd32(IGC_GPRC);
5051         adapter->stats.gorc += rd32(IGC_GORCL);
5052         rd32(IGC_GORCH); /* clear GORCL */
5053         adapter->stats.bprc += rd32(IGC_BPRC);
5054         adapter->stats.mprc += rd32(IGC_MPRC);
5055         adapter->stats.roc += rd32(IGC_ROC);
5056
5057         adapter->stats.prc64 += rd32(IGC_PRC64);
5058         adapter->stats.prc127 += rd32(IGC_PRC127);
5059         adapter->stats.prc255 += rd32(IGC_PRC255);
5060         adapter->stats.prc511 += rd32(IGC_PRC511);
5061         adapter->stats.prc1023 += rd32(IGC_PRC1023);
5062         adapter->stats.prc1522 += rd32(IGC_PRC1522);
5063         adapter->stats.tlpic += rd32(IGC_TLPIC);
5064         adapter->stats.rlpic += rd32(IGC_RLPIC);
5065         adapter->stats.hgptc += rd32(IGC_HGPTC);
5066
5067         mpc = rd32(IGC_MPC);
5068         adapter->stats.mpc += mpc;
5069         net_stats->rx_fifo_errors += mpc;
5070         adapter->stats.scc += rd32(IGC_SCC);
5071         adapter->stats.ecol += rd32(IGC_ECOL);
5072         adapter->stats.mcc += rd32(IGC_MCC);
5073         adapter->stats.latecol += rd32(IGC_LATECOL);
5074         adapter->stats.dc += rd32(IGC_DC);
5075         adapter->stats.rlec += rd32(IGC_RLEC);
5076         adapter->stats.xonrxc += rd32(IGC_XONRXC);
5077         adapter->stats.xontxc += rd32(IGC_XONTXC);
5078         adapter->stats.xoffrxc += rd32(IGC_XOFFRXC);
5079         adapter->stats.xofftxc += rd32(IGC_XOFFTXC);
5080         adapter->stats.fcruc += rd32(IGC_FCRUC);
5081         adapter->stats.gptc += rd32(IGC_GPTC);
5082         adapter->stats.gotc += rd32(IGC_GOTCL);
5083         rd32(IGC_GOTCH); /* clear GOTCL */
5084         adapter->stats.rnbc += rd32(IGC_RNBC);
5085         adapter->stats.ruc += rd32(IGC_RUC);
5086         adapter->stats.rfc += rd32(IGC_RFC);
5087         adapter->stats.rjc += rd32(IGC_RJC);
5088         adapter->stats.tor += rd32(IGC_TORH);
5089         adapter->stats.tot += rd32(IGC_TOTH);
5090         adapter->stats.tpr += rd32(IGC_TPR);
5091
5092         adapter->stats.ptc64 += rd32(IGC_PTC64);
5093         adapter->stats.ptc127 += rd32(IGC_PTC127);
5094         adapter->stats.ptc255 += rd32(IGC_PTC255);
5095         adapter->stats.ptc511 += rd32(IGC_PTC511);
5096         adapter->stats.ptc1023 += rd32(IGC_PTC1023);
5097         adapter->stats.ptc1522 += rd32(IGC_PTC1522);
5098
5099         adapter->stats.mptc += rd32(IGC_MPTC);
5100         adapter->stats.bptc += rd32(IGC_BPTC);
5101
5102         adapter->stats.tpt += rd32(IGC_TPT);
5103         adapter->stats.colc += rd32(IGC_COLC);
5104         adapter->stats.colc += rd32(IGC_RERC);
5105
5106         adapter->stats.algnerrc += rd32(IGC_ALGNERRC);
5107
5108         adapter->stats.tsctc += rd32(IGC_TSCTC);
5109
5110         adapter->stats.iac += rd32(IGC_IAC);
5111
5112         /* Fill out the OS statistics structure */
5113         net_stats->multicast = adapter->stats.mprc;
5114         net_stats->collisions = adapter->stats.colc;
5115
5116         /* Rx Errors */
5117
5118         /* RLEC on some newer hardware can be incorrect so build
5119          * our own version based on RUC and ROC
5120          */
5121         net_stats->rx_errors = adapter->stats.rxerrc +
5122                 adapter->stats.crcerrs + adapter->stats.algnerrc +
5123                 adapter->stats.ruc + adapter->stats.roc +
5124                 adapter->stats.cexterr;
5125         net_stats->rx_length_errors = adapter->stats.ruc +
5126                                       adapter->stats.roc;
5127         net_stats->rx_crc_errors = adapter->stats.crcerrs;
5128         net_stats->rx_frame_errors = adapter->stats.algnerrc;
5129         net_stats->rx_missed_errors = adapter->stats.mpc;
5130
5131         /* Tx Errors */
5132         net_stats->tx_errors = adapter->stats.ecol +
5133                                adapter->stats.latecol;
5134         net_stats->tx_aborted_errors = adapter->stats.ecol;
5135         net_stats->tx_window_errors = adapter->stats.latecol;
5136         net_stats->tx_carrier_errors = adapter->stats.tncrs;
5137
5138         /* Tx Dropped */
5139         net_stats->tx_dropped = adapter->stats.txdrop;
5140
5141         /* Management Stats */
5142         adapter->stats.mgptc += rd32(IGC_MGTPTC);
5143         adapter->stats.mgprc += rd32(IGC_MGTPRC);
5144         adapter->stats.mgpdc += rd32(IGC_MGTPDC);
5145 }
5146
5147 /**
5148  * igc_down - Close the interface
5149  * @adapter: board private structure
5150  */
5151 void igc_down(struct igc_adapter *adapter)
5152 {
5153         struct net_device *netdev = adapter->netdev;
5154         struct igc_hw *hw = &adapter->hw;
5155         u32 tctl, rctl;
5156         int i = 0;
5157
5158         set_bit(__IGC_DOWN, &adapter->state);
5159
5160         igc_ptp_suspend(adapter);
5161
5162         if (pci_device_is_present(adapter->pdev)) {
5163                 /* disable receives in the hardware */
5164                 rctl = rd32(IGC_RCTL);
5165                 wr32(IGC_RCTL, rctl & ~IGC_RCTL_EN);
5166                 /* flush and sleep below */
5167         }
5168         /* set trans_start so we don't get spurious watchdogs during reset */
5169         netif_trans_update(netdev);
5170
5171         netif_carrier_off(netdev);
5172         netif_tx_stop_all_queues(netdev);
5173
5174         if (pci_device_is_present(adapter->pdev)) {
5175                 /* disable transmits in the hardware */
5176                 tctl = rd32(IGC_TCTL);
5177                 tctl &= ~IGC_TCTL_EN;
5178                 wr32(IGC_TCTL, tctl);
5179                 /* flush both disables and wait for them to finish */
5180                 wrfl();
5181                 usleep_range(10000, 20000);
5182
5183                 igc_irq_disable(adapter);
5184         }
5185
5186         adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
5187
5188         for (i = 0; i < adapter->num_q_vectors; i++) {
5189                 if (adapter->q_vector[i]) {
5190                         napi_synchronize(&adapter->q_vector[i]->napi);
5191                         napi_disable(&adapter->q_vector[i]->napi);
5192                 }
5193         }
5194
5195         del_timer_sync(&adapter->watchdog_timer);
5196         del_timer_sync(&adapter->phy_info_timer);
5197
5198         /* record the stats before reset*/
5199         spin_lock(&adapter->stats64_lock);
5200         igc_update_stats(adapter);
5201         spin_unlock(&adapter->stats64_lock);
5202
5203         adapter->link_speed = 0;
5204         adapter->link_duplex = 0;
5205
5206         if (!pci_channel_offline(adapter->pdev))
5207                 igc_reset(adapter);
5208
5209         /* clear VLAN promisc flag so VFTA will be updated if necessary */
5210         adapter->flags &= ~IGC_FLAG_VLAN_PROMISC;
5211
5212         igc_disable_all_tx_rings_hw(adapter);
5213         igc_clean_all_tx_rings(adapter);
5214         igc_clean_all_rx_rings(adapter);
5215 }
5216
5217 void igc_reinit_locked(struct igc_adapter *adapter)
5218 {
5219         while (test_and_set_bit(__IGC_RESETTING, &adapter->state))
5220                 usleep_range(1000, 2000);
5221         igc_down(adapter);
5222         igc_up(adapter);
5223         clear_bit(__IGC_RESETTING, &adapter->state);
5224 }
5225
5226 static void igc_reset_task(struct work_struct *work)
5227 {
5228         struct igc_adapter *adapter;
5229
5230         adapter = container_of(work, struct igc_adapter, reset_task);
5231
5232         rtnl_lock();
5233         /* If we're already down or resetting, just bail */
5234         if (test_bit(__IGC_DOWN, &adapter->state) ||
5235             test_bit(__IGC_RESETTING, &adapter->state)) {
5236                 rtnl_unlock();
5237                 return;
5238         }
5239
5240         igc_rings_dump(adapter);
5241         igc_regs_dump(adapter);
5242         netdev_err(adapter->netdev, "Reset adapter\n");
5243         igc_reinit_locked(adapter);
5244         rtnl_unlock();
5245 }
5246
5247 /**
5248  * igc_change_mtu - Change the Maximum Transfer Unit
5249  * @netdev: network interface device structure
5250  * @new_mtu: new value for maximum frame size
5251  *
5252  * Returns 0 on success, negative on failure
5253  */
5254 static int igc_change_mtu(struct net_device *netdev, int new_mtu)
5255 {
5256         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5257         struct igc_adapter *adapter = netdev_priv(netdev);
5258
5259         if (igc_xdp_is_enabled(adapter) && new_mtu > ETH_DATA_LEN) {
5260                 netdev_dbg(netdev, "Jumbo frames not supported with XDP");
5261                 return -EINVAL;
5262         }
5263
5264         /* adjust max frame to be at least the size of a standard frame */
5265         if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5266                 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5267
5268         while (test_and_set_bit(__IGC_RESETTING, &adapter->state))
5269                 usleep_range(1000, 2000);
5270
5271         /* igc_down has a dependency on max_frame_size */
5272         adapter->max_frame_size = max_frame;
5273
5274         if (netif_running(netdev))
5275                 igc_down(adapter);
5276
5277         netdev_dbg(netdev, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5278         WRITE_ONCE(netdev->mtu, new_mtu);
5279
5280         if (netif_running(netdev))
5281                 igc_up(adapter);
5282         else
5283                 igc_reset(adapter);
5284
5285         clear_bit(__IGC_RESETTING, &adapter->state);
5286
5287         return 0;
5288 }
5289
5290 /**
5291  * igc_tx_timeout - Respond to a Tx Hang
5292  * @netdev: network interface device structure
5293  * @txqueue: queue number that timed out
5294  **/
5295 static void igc_tx_timeout(struct net_device *netdev,
5296                            unsigned int __always_unused txqueue)
5297 {
5298         struct igc_adapter *adapter = netdev_priv(netdev);
5299         struct igc_hw *hw = &adapter->hw;
5300
5301         /* Do the reset outside of interrupt context */
5302         adapter->tx_timeout_count++;
5303         schedule_work(&adapter->reset_task);
5304         wr32(IGC_EICS,
5305              (adapter->eims_enable_mask & ~adapter->eims_other));
5306 }
5307
5308 /**
5309  * igc_get_stats64 - Get System Network Statistics
5310  * @netdev: network interface device structure
5311  * @stats: rtnl_link_stats64 pointer
5312  *
5313  * Returns the address of the device statistics structure.
5314  * The statistics are updated here and also from the timer callback.
5315  */
5316 static void igc_get_stats64(struct net_device *netdev,
5317                             struct rtnl_link_stats64 *stats)
5318 {
5319         struct igc_adapter *adapter = netdev_priv(netdev);
5320
5321         spin_lock(&adapter->stats64_lock);
5322         if (!test_bit(__IGC_RESETTING, &adapter->state))
5323                 igc_update_stats(adapter);
5324         memcpy(stats, &adapter->stats64, sizeof(*stats));
5325         spin_unlock(&adapter->stats64_lock);
5326 }
5327
5328 static netdev_features_t igc_fix_features(struct net_device *netdev,
5329                                           netdev_features_t features)
5330 {
5331         /* Since there is no support for separate Rx/Tx vlan accel
5332          * enable/disable make sure Tx flag is always in same state as Rx.
5333          */
5334         if (features & NETIF_F_HW_VLAN_CTAG_RX)
5335                 features |= NETIF_F_HW_VLAN_CTAG_TX;
5336         else
5337                 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
5338
5339         return features;
5340 }
5341
5342 static int igc_set_features(struct net_device *netdev,
5343                             netdev_features_t features)
5344 {
5345         netdev_features_t changed = netdev->features ^ features;
5346         struct igc_adapter *adapter = netdev_priv(netdev);
5347
5348         if (changed & NETIF_F_HW_VLAN_CTAG_RX)
5349                 igc_vlan_mode(netdev, features);
5350
5351         /* Add VLAN support */
5352         if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
5353                 return 0;
5354
5355         if (!(features & NETIF_F_NTUPLE))
5356                 igc_flush_nfc_rules(adapter);
5357
5358         netdev->features = features;
5359
5360         if (netif_running(netdev))
5361                 igc_reinit_locked(adapter);
5362         else
5363                 igc_reset(adapter);
5364
5365         return 1;
5366 }
5367
5368 static netdev_features_t
5369 igc_features_check(struct sk_buff *skb, struct net_device *dev,
5370                    netdev_features_t features)
5371 {
5372         unsigned int network_hdr_len, mac_hdr_len;
5373
5374         /* Make certain the headers can be described by a context descriptor */
5375         mac_hdr_len = skb_network_offset(skb);
5376         if (unlikely(mac_hdr_len > IGC_MAX_MAC_HDR_LEN))
5377                 return features & ~(NETIF_F_HW_CSUM |
5378                                     NETIF_F_SCTP_CRC |
5379                                     NETIF_F_HW_VLAN_CTAG_TX |
5380                                     NETIF_F_TSO |
5381                                     NETIF_F_TSO6);
5382
5383         network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
5384         if (unlikely(network_hdr_len >  IGC_MAX_NETWORK_HDR_LEN))
5385                 return features & ~(NETIF_F_HW_CSUM |
5386                                     NETIF_F_SCTP_CRC |
5387                                     NETIF_F_TSO |
5388                                     NETIF_F_TSO6);
5389
5390         /* We can only support IPv4 TSO in tunnels if we can mangle the
5391          * inner IP ID field, so strip TSO if MANGLEID is not supported.
5392          */
5393         if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
5394                 features &= ~NETIF_F_TSO;
5395
5396         return features;
5397 }
5398
5399 static void igc_tsync_interrupt(struct igc_adapter *adapter)
5400 {
5401         struct igc_hw *hw = &adapter->hw;
5402         u32 tsauxc, sec, nsec, tsicr;
5403         struct ptp_clock_event event;
5404         struct timespec64 ts;
5405
5406         tsicr = rd32(IGC_TSICR);
5407
5408         if (tsicr & IGC_TSICR_SYS_WRAP) {
5409                 event.type = PTP_CLOCK_PPS;
5410                 if (adapter->ptp_caps.pps)
5411                         ptp_clock_event(adapter->ptp_clock, &event);
5412         }
5413
5414         if (tsicr & IGC_TSICR_TXTS) {
5415                 /* retrieve hardware timestamp */
5416                 igc_ptp_tx_tstamp_event(adapter);
5417         }
5418
5419         if (tsicr & IGC_TSICR_TT0) {
5420                 spin_lock(&adapter->tmreg_lock);
5421                 ts = timespec64_add(adapter->perout[0].start,
5422                                     adapter->perout[0].period);
5423                 wr32(IGC_TRGTTIML0, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);
5424                 wr32(IGC_TRGTTIMH0, (u32)ts.tv_sec);
5425                 tsauxc = rd32(IGC_TSAUXC);
5426                 tsauxc |= IGC_TSAUXC_EN_TT0;
5427                 wr32(IGC_TSAUXC, tsauxc);
5428                 adapter->perout[0].start = ts;
5429                 spin_unlock(&adapter->tmreg_lock);
5430         }
5431
5432         if (tsicr & IGC_TSICR_TT1) {
5433                 spin_lock(&adapter->tmreg_lock);
5434                 ts = timespec64_add(adapter->perout[1].start,
5435                                     adapter->perout[1].period);
5436                 wr32(IGC_TRGTTIML1, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);
5437                 wr32(IGC_TRGTTIMH1, (u32)ts.tv_sec);
5438                 tsauxc = rd32(IGC_TSAUXC);
5439                 tsauxc |= IGC_TSAUXC_EN_TT1;
5440                 wr32(IGC_TSAUXC, tsauxc);
5441                 adapter->perout[1].start = ts;
5442                 spin_unlock(&adapter->tmreg_lock);
5443         }
5444
5445         if (tsicr & IGC_TSICR_AUTT0) {
5446                 nsec = rd32(IGC_AUXSTMPL0);
5447                 sec  = rd32(IGC_AUXSTMPH0);
5448                 event.type = PTP_CLOCK_EXTTS;
5449                 event.index = 0;
5450                 event.timestamp = sec * NSEC_PER_SEC + nsec;
5451                 ptp_clock_event(adapter->ptp_clock, &event);
5452         }
5453
5454         if (tsicr & IGC_TSICR_AUTT1) {
5455                 nsec = rd32(IGC_AUXSTMPL1);
5456                 sec  = rd32(IGC_AUXSTMPH1);
5457                 event.type = PTP_CLOCK_EXTTS;
5458                 event.index = 1;
5459                 event.timestamp = sec * NSEC_PER_SEC + nsec;
5460                 ptp_clock_event(adapter->ptp_clock, &event);
5461         }
5462 }
5463
5464 /**
5465  * igc_msix_other - msix other interrupt handler
5466  * @irq: interrupt number
5467  * @data: pointer to a q_vector
5468  */
5469 static irqreturn_t igc_msix_other(int irq, void *data)
5470 {
5471         struct igc_adapter *adapter = data;
5472         struct igc_hw *hw = &adapter->hw;
5473         u32 icr = rd32(IGC_ICR);
5474
5475         /* reading ICR causes bit 31 of EICR to be cleared */
5476         if (icr & IGC_ICR_DRSTA)
5477                 schedule_work(&adapter->reset_task);
5478
5479         if (icr & IGC_ICR_DOUTSYNC) {
5480                 /* HW is reporting DMA is out of sync */
5481                 adapter->stats.doosync++;
5482         }
5483
5484         if (icr & IGC_ICR_LSC) {
5485                 hw->mac.get_link_status = true;
5486                 /* guard against interrupt when we're going down */
5487                 if (!test_bit(__IGC_DOWN, &adapter->state))
5488                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5489         }
5490
5491         if (icr & IGC_ICR_TS)
5492                 igc_tsync_interrupt(adapter);
5493
5494         wr32(IGC_EIMS, adapter->eims_other);
5495
5496         return IRQ_HANDLED;
5497 }
5498
5499 static void igc_write_itr(struct igc_q_vector *q_vector)
5500 {
5501         u32 itr_val = q_vector->itr_val & IGC_QVECTOR_MASK;
5502
5503         if (!q_vector->set_itr)
5504                 return;
5505
5506         if (!itr_val)
5507                 itr_val = IGC_ITR_VAL_MASK;
5508
5509         itr_val |= IGC_EITR_CNT_IGNR;
5510
5511         writel(itr_val, q_vector->itr_register);
5512         q_vector->set_itr = 0;
5513 }
5514
5515 static irqreturn_t igc_msix_ring(int irq, void *data)
5516 {
5517         struct igc_q_vector *q_vector = data;
5518
5519         /* Write the ITR value calculated from the previous interrupt. */
5520         igc_write_itr(q_vector);
5521
5522         napi_schedule(&q_vector->napi);
5523
5524         return IRQ_HANDLED;
5525 }
5526
5527 /**
5528  * igc_request_msix - Initialize MSI-X interrupts
5529  * @adapter: Pointer to adapter structure
5530  *
5531  * igc_request_msix allocates MSI-X vectors and requests interrupts from the
5532  * kernel.
5533  */
5534 static int igc_request_msix(struct igc_adapter *adapter)
5535 {
5536         unsigned int num_q_vectors = adapter->num_q_vectors;
5537         int i = 0, err = 0, vector = 0, free_vector = 0;
5538         struct net_device *netdev = adapter->netdev;
5539
5540         err = request_irq(adapter->msix_entries[vector].vector,
5541                           &igc_msix_other, 0, netdev->name, adapter);
5542         if (err)
5543                 goto err_out;
5544
5545         if (num_q_vectors > MAX_Q_VECTORS) {
5546                 num_q_vectors = MAX_Q_VECTORS;
5547                 dev_warn(&adapter->pdev->dev,
5548                          "The number of queue vectors (%d) is higher than max allowed (%d)\n",
5549                          adapter->num_q_vectors, MAX_Q_VECTORS);
5550         }
5551         for (i = 0; i < num_q_vectors; i++) {
5552                 struct igc_q_vector *q_vector = adapter->q_vector[i];
5553
5554                 vector++;
5555
5556                 q_vector->itr_register = adapter->io_addr + IGC_EITR(vector);
5557
5558                 if (q_vector->rx.ring && q_vector->tx.ring)
5559                         sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
5560                                 q_vector->rx.ring->queue_index);
5561                 else if (q_vector->tx.ring)
5562                         sprintf(q_vector->name, "%s-tx-%u", netdev->name,
5563                                 q_vector->tx.ring->queue_index);
5564                 else if (q_vector->rx.ring)
5565                         sprintf(q_vector->name, "%s-rx-%u", netdev->name,
5566                                 q_vector->rx.ring->queue_index);
5567                 else
5568                         sprintf(q_vector->name, "%s-unused", netdev->name);
5569
5570                 err = request_irq(adapter->msix_entries[vector].vector,
5571                                   igc_msix_ring, 0, q_vector->name,
5572                                   q_vector);
5573                 if (err)
5574                         goto err_free;
5575         }
5576
5577         igc_configure_msix(adapter);
5578         return 0;
5579
5580 err_free:
5581         /* free already assigned IRQs */
5582         free_irq(adapter->msix_entries[free_vector++].vector, adapter);
5583
5584         vector--;
5585         for (i = 0; i < vector; i++) {
5586                 free_irq(adapter->msix_entries[free_vector++].vector,
5587                          adapter->q_vector[i]);
5588         }
5589 err_out:
5590         return err;
5591 }
5592
5593 /**
5594  * igc_clear_interrupt_scheme - reset the device to a state of no interrupts
5595  * @adapter: Pointer to adapter structure
5596  *
5597  * This function resets the device so that it has 0 rx queues, tx queues, and
5598  * MSI-X interrupts allocated.
5599  */
5600 static void igc_clear_interrupt_scheme(struct igc_adapter *adapter)
5601 {
5602         igc_free_q_vectors(adapter);
5603         igc_reset_interrupt_capability(adapter);
5604 }
5605
5606 /* Need to wait a few seconds after link up to get diagnostic information from
5607  * the phy
5608  */
5609 static void igc_update_phy_info(struct timer_list *t)
5610 {
5611         struct igc_adapter *adapter = from_timer(adapter, t, phy_info_timer);
5612
5613         igc_get_phy_info(&adapter->hw);
5614 }
5615
5616 /**
5617  * igc_has_link - check shared code for link and determine up/down
5618  * @adapter: pointer to driver private info
5619  */
5620 bool igc_has_link(struct igc_adapter *adapter)
5621 {
5622         struct igc_hw *hw = &adapter->hw;
5623         bool link_active = false;
5624
5625         /* get_link_status is set on LSC (link status) interrupt or
5626          * rx sequence error interrupt.  get_link_status will stay
5627          * false until the igc_check_for_link establishes link
5628          * for copper adapters ONLY
5629          */
5630         if (!hw->mac.get_link_status)
5631                 return true;
5632         hw->mac.ops.check_for_link(hw);
5633         link_active = !hw->mac.get_link_status;
5634
5635         if (hw->mac.type == igc_i225) {
5636                 if (!netif_carrier_ok(adapter->netdev)) {
5637                         adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
5638                 } else if (!(adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)) {
5639                         adapter->flags |= IGC_FLAG_NEED_LINK_UPDATE;
5640                         adapter->link_check_timeout = jiffies;
5641                 }
5642         }
5643
5644         return link_active;
5645 }
5646
5647 /**
5648  * igc_watchdog - Timer Call-back
5649  * @t: timer for the watchdog
5650  */
5651 static void igc_watchdog(struct timer_list *t)
5652 {
5653         struct igc_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5654         /* Do the rest outside of interrupt context */
5655         schedule_work(&adapter->watchdog_task);
5656 }
5657
5658 static void igc_watchdog_task(struct work_struct *work)
5659 {
5660         struct igc_adapter *adapter = container_of(work,
5661                                                    struct igc_adapter,
5662                                                    watchdog_task);
5663         struct net_device *netdev = adapter->netdev;
5664         struct igc_hw *hw = &adapter->hw;
5665         struct igc_phy_info *phy = &hw->phy;
5666         u16 phy_data, retry_count = 20;
5667         u32 link;
5668         int i;
5669
5670         link = igc_has_link(adapter);
5671
5672         if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) {
5673                 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
5674                         adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
5675                 else
5676                         link = false;
5677         }
5678
5679         if (link) {
5680                 /* Cancel scheduled suspend requests. */
5681                 pm_runtime_resume(netdev->dev.parent);
5682
5683                 if (!netif_carrier_ok(netdev)) {
5684                         u32 ctrl;
5685
5686                         hw->mac.ops.get_speed_and_duplex(hw,
5687                                                          &adapter->link_speed,
5688                                                          &adapter->link_duplex);
5689
5690                         ctrl = rd32(IGC_CTRL);
5691                         /* Link status message must follow this format */
5692                         netdev_info(netdev,
5693                                     "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5694                                     adapter->link_speed,
5695                                     adapter->link_duplex == FULL_DUPLEX ?
5696                                     "Full" : "Half",
5697                                     (ctrl & IGC_CTRL_TFCE) &&
5698                                     (ctrl & IGC_CTRL_RFCE) ? "RX/TX" :
5699                                     (ctrl & IGC_CTRL_RFCE) ?  "RX" :
5700                                     (ctrl & IGC_CTRL_TFCE) ?  "TX" : "None");
5701
5702                         /* disable EEE if enabled */
5703                         if ((adapter->flags & IGC_FLAG_EEE) &&
5704                             adapter->link_duplex == HALF_DUPLEX) {
5705                                 netdev_info(netdev,
5706                                             "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex\n");
5707                                 adapter->hw.dev_spec._base.eee_enable = false;
5708                                 adapter->flags &= ~IGC_FLAG_EEE;
5709                         }
5710
5711                         /* check if SmartSpeed worked */
5712                         igc_check_downshift(hw);
5713                         if (phy->speed_downgraded)
5714                                 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
5715
5716                         /* adjust timeout factor according to speed/duplex */
5717                         adapter->tx_timeout_factor = 1;
5718                         switch (adapter->link_speed) {
5719                         case SPEED_10:
5720                                 adapter->tx_timeout_factor = 14;
5721                                 break;
5722                         case SPEED_100:
5723                         case SPEED_1000:
5724                         case SPEED_2500:
5725                                 adapter->tx_timeout_factor = 1;
5726                                 break;
5727                         }
5728
5729                         /* Once the launch time has been set on the wire, there
5730                          * is a delay before the link speed can be determined
5731                          * based on link-up activity. Write into the register
5732                          * as soon as we know the correct link speed.
5733                          */
5734                         igc_tsn_adjust_txtime_offset(adapter);
5735
5736                         if (adapter->link_speed != SPEED_1000)
5737                                 goto no_wait;
5738
5739                         /* wait for Remote receiver status OK */
5740 retry_read_status:
5741                         if (!igc_read_phy_reg(hw, PHY_1000T_STATUS,
5742                                               &phy_data)) {
5743                                 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
5744                                     retry_count) {
5745                                         msleep(100);
5746                                         retry_count--;
5747                                         goto retry_read_status;
5748                                 } else if (!retry_count) {
5749                                         netdev_err(netdev, "exceed max 2 second\n");
5750                                 }
5751                         } else {
5752                                 netdev_err(netdev, "read 1000Base-T Status Reg\n");
5753                         }
5754 no_wait:
5755                         netif_carrier_on(netdev);
5756
5757                         /* link state has changed, schedule phy info update */
5758                         if (!test_bit(__IGC_DOWN, &adapter->state))
5759                                 mod_timer(&adapter->phy_info_timer,
5760                                           round_jiffies(jiffies + 2 * HZ));
5761                 }
5762         } else {
5763                 if (netif_carrier_ok(netdev)) {
5764                         adapter->link_speed = 0;
5765                         adapter->link_duplex = 0;
5766
5767                         /* Links status message must follow this format */
5768                         netdev_info(netdev, "NIC Link is Down\n");
5769                         netif_carrier_off(netdev);
5770
5771                         /* link state has changed, schedule phy info update */
5772                         if (!test_bit(__IGC_DOWN, &adapter->state))
5773                                 mod_timer(&adapter->phy_info_timer,
5774                                           round_jiffies(jiffies + 2 * HZ));
5775
5776                         pm_schedule_suspend(netdev->dev.parent,
5777                                             MSEC_PER_SEC * 5);
5778                 }
5779         }
5780
5781         spin_lock(&adapter->stats64_lock);
5782         igc_update_stats(adapter);
5783         spin_unlock(&adapter->stats64_lock);
5784
5785         for (i = 0; i < adapter->num_tx_queues; i++) {
5786                 struct igc_ring *tx_ring = adapter->tx_ring[i];
5787
5788                 if (!netif_carrier_ok(netdev)) {
5789                         /* We've lost link, so the controller stops DMA,
5790                          * but we've got queued Tx work that's never going
5791                          * to get done, so reset controller to flush Tx.
5792                          * (Do the reset outside of interrupt context).
5793                          */
5794                         if (igc_desc_unused(tx_ring) + 1 < tx_ring->count) {
5795                                 adapter->tx_timeout_count++;
5796                                 schedule_work(&adapter->reset_task);
5797                                 /* return immediately since reset is imminent */
5798                                 return;
5799                         }
5800                 }
5801
5802                 /* Force detection of hung controller every watchdog period */
5803                 set_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5804         }
5805
5806         /* Cause software interrupt to ensure Rx ring is cleaned */
5807         if (adapter->flags & IGC_FLAG_HAS_MSIX) {
5808                 u32 eics = 0;
5809
5810                 for (i = 0; i < adapter->num_q_vectors; i++)
5811                         eics |= adapter->q_vector[i]->eims_value;
5812                 wr32(IGC_EICS, eics);
5813         } else {
5814                 wr32(IGC_ICS, IGC_ICS_RXDMT0);
5815         }
5816
5817         igc_ptp_tx_hang(adapter);
5818
5819         /* Reset the timer */
5820         if (!test_bit(__IGC_DOWN, &adapter->state)) {
5821                 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)
5822                         mod_timer(&adapter->watchdog_timer,
5823                                   round_jiffies(jiffies +  HZ));
5824                 else
5825                         mod_timer(&adapter->watchdog_timer,
5826                                   round_jiffies(jiffies + 2 * HZ));
5827         }
5828 }
5829
5830 /**
5831  * igc_intr_msi - Interrupt Handler
5832  * @irq: interrupt number
5833  * @data: pointer to a network interface device structure
5834  */
5835 static irqreturn_t igc_intr_msi(int irq, void *data)
5836 {
5837         struct igc_adapter *adapter = data;
5838         struct igc_q_vector *q_vector = adapter->q_vector[0];
5839         struct igc_hw *hw = &adapter->hw;
5840         /* read ICR disables interrupts using IAM */
5841         u32 icr = rd32(IGC_ICR);
5842
5843         igc_write_itr(q_vector);
5844
5845         if (icr & IGC_ICR_DRSTA)
5846                 schedule_work(&adapter->reset_task);
5847
5848         if (icr & IGC_ICR_DOUTSYNC) {
5849                 /* HW is reporting DMA is out of sync */
5850                 adapter->stats.doosync++;
5851         }
5852
5853         if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) {
5854                 hw->mac.get_link_status = true;
5855                 if (!test_bit(__IGC_DOWN, &adapter->state))
5856                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5857         }
5858
5859         if (icr & IGC_ICR_TS)
5860                 igc_tsync_interrupt(adapter);
5861
5862         napi_schedule(&q_vector->napi);
5863
5864         return IRQ_HANDLED;
5865 }
5866
5867 /**
5868  * igc_intr - Legacy Interrupt Handler
5869  * @irq: interrupt number
5870  * @data: pointer to a network interface device structure
5871  */
5872 static irqreturn_t igc_intr(int irq, void *data)
5873 {
5874         struct igc_adapter *adapter = data;
5875         struct igc_q_vector *q_vector = adapter->q_vector[0];
5876         struct igc_hw *hw = &adapter->hw;
5877         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
5878          * need for the IMC write
5879          */
5880         u32 icr = rd32(IGC_ICR);
5881
5882         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5883          * not set, then the adapter didn't send an interrupt
5884          */
5885         if (!(icr & IGC_ICR_INT_ASSERTED))
5886                 return IRQ_NONE;
5887
5888         igc_write_itr(q_vector);
5889
5890         if (icr & IGC_ICR_DRSTA)
5891                 schedule_work(&adapter->reset_task);
5892
5893         if (icr & IGC_ICR_DOUTSYNC) {
5894                 /* HW is reporting DMA is out of sync */
5895                 adapter->stats.doosync++;
5896         }
5897
5898         if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) {
5899                 hw->mac.get_link_status = true;
5900                 /* guard against interrupt when we're going down */
5901                 if (!test_bit(__IGC_DOWN, &adapter->state))
5902                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5903         }
5904
5905         if (icr & IGC_ICR_TS)
5906                 igc_tsync_interrupt(adapter);
5907
5908         napi_schedule(&q_vector->napi);
5909
5910         return IRQ_HANDLED;
5911 }
5912
5913 static void igc_free_irq(struct igc_adapter *adapter)
5914 {
5915         if (adapter->msix_entries) {
5916                 int vector = 0, i;
5917
5918                 free_irq(adapter->msix_entries[vector++].vector, adapter);
5919
5920                 for (i = 0; i < adapter->num_q_vectors; i++)
5921                         free_irq(adapter->msix_entries[vector++].vector,
5922                                  adapter->q_vector[i]);
5923         } else {
5924                 free_irq(adapter->pdev->irq, adapter);
5925         }
5926 }
5927
5928 /**
5929  * igc_request_irq - initialize interrupts
5930  * @adapter: Pointer to adapter structure
5931  *
5932  * Attempts to configure interrupts using the best available
5933  * capabilities of the hardware and kernel.
5934  */
5935 static int igc_request_irq(struct igc_adapter *adapter)
5936 {
5937         struct net_device *netdev = adapter->netdev;
5938         struct pci_dev *pdev = adapter->pdev;
5939         int err = 0;
5940
5941         if (adapter->flags & IGC_FLAG_HAS_MSIX) {
5942                 err = igc_request_msix(adapter);
5943                 if (!err)
5944                         goto request_done;
5945                 /* fall back to MSI */
5946                 igc_free_all_tx_resources(adapter);
5947                 igc_free_all_rx_resources(adapter);
5948
5949                 igc_clear_interrupt_scheme(adapter);
5950                 err = igc_init_interrupt_scheme(adapter, false);
5951                 if (err)
5952                         goto request_done;
5953                 igc_setup_all_tx_resources(adapter);
5954                 igc_setup_all_rx_resources(adapter);
5955                 igc_configure(adapter);
5956         }
5957
5958         igc_assign_vector(adapter->q_vector[0], 0);
5959
5960         if (adapter->flags & IGC_FLAG_HAS_MSI) {
5961                 err = request_irq(pdev->irq, &igc_intr_msi, 0,
5962                                   netdev->name, adapter);
5963                 if (!err)
5964                         goto request_done;
5965
5966                 /* fall back to legacy interrupts */
5967                 igc_reset_interrupt_capability(adapter);
5968                 adapter->flags &= ~IGC_FLAG_HAS_MSI;
5969         }
5970
5971         err = request_irq(pdev->irq, &igc_intr, IRQF_SHARED,
5972                           netdev->name, adapter);
5973
5974         if (err)
5975                 netdev_err(netdev, "Error %d getting interrupt\n", err);
5976
5977 request_done:
5978         return err;
5979 }
5980
5981 /**
5982  * __igc_open - Called when a network interface is made active
5983  * @netdev: network interface device structure
5984  * @resuming: boolean indicating if the device is resuming
5985  *
5986  * Returns 0 on success, negative value on failure
5987  *
5988  * The open entry point is called when a network interface is made
5989  * active by the system (IFF_UP).  At this point all resources needed
5990  * for transmit and receive operations are allocated, the interrupt
5991  * handler is registered with the OS, the watchdog timer is started,
5992  * and the stack is notified that the interface is ready.
5993  */
5994 static int __igc_open(struct net_device *netdev, bool resuming)
5995 {
5996         struct igc_adapter *adapter = netdev_priv(netdev);
5997         struct pci_dev *pdev = adapter->pdev;
5998         struct igc_hw *hw = &adapter->hw;
5999         int err = 0;
6000         int i = 0;
6001
6002         /* disallow open during test */
6003
6004         if (test_bit(__IGC_TESTING, &adapter->state)) {
6005                 WARN_ON(resuming);
6006                 return -EBUSY;
6007         }
6008
6009         if (!resuming)
6010                 pm_runtime_get_sync(&pdev->dev);
6011
6012         netif_carrier_off(netdev);
6013
6014         /* allocate transmit descriptors */
6015         err = igc_setup_all_tx_resources(adapter);
6016         if (err)
6017                 goto err_setup_tx;
6018
6019         /* allocate receive descriptors */
6020         err = igc_setup_all_rx_resources(adapter);
6021         if (err)
6022                 goto err_setup_rx;
6023
6024         igc_power_up_link(adapter);
6025
6026         igc_configure(adapter);
6027
6028         err = igc_request_irq(adapter);
6029         if (err)
6030                 goto err_req_irq;
6031
6032         clear_bit(__IGC_DOWN, &adapter->state);
6033
6034         for (i = 0; i < adapter->num_q_vectors; i++)
6035                 napi_enable(&adapter->q_vector[i]->napi);
6036
6037         /* Clear any pending interrupts. */
6038         rd32(IGC_ICR);
6039         igc_irq_enable(adapter);
6040
6041         if (!resuming)
6042                 pm_runtime_put(&pdev->dev);
6043
6044         netif_tx_start_all_queues(netdev);
6045
6046         /* start the watchdog. */
6047         hw->mac.get_link_status = true;
6048         schedule_work(&adapter->watchdog_task);
6049
6050         return IGC_SUCCESS;
6051
6052 err_req_irq:
6053         igc_release_hw_control(adapter);
6054         igc_power_down_phy_copper_base(&adapter->hw);
6055         igc_free_all_rx_resources(adapter);
6056 err_setup_rx:
6057         igc_free_all_tx_resources(adapter);
6058 err_setup_tx:
6059         igc_reset(adapter);
6060         if (!resuming)
6061                 pm_runtime_put(&pdev->dev);
6062
6063         return err;
6064 }
6065
6066 int igc_open(struct net_device *netdev)
6067 {
6068         struct igc_adapter *adapter = netdev_priv(netdev);
6069         int err;
6070
6071         /* Notify the stack of the actual queue counts. */
6072         err = netif_set_real_num_queues(netdev, adapter->num_tx_queues,
6073                                         adapter->num_rx_queues);
6074         if (err) {
6075                 netdev_err(netdev, "error setting real queue count\n");
6076                 return err;
6077         }
6078
6079         return __igc_open(netdev, false);
6080 }
6081
6082 /**
6083  * __igc_close - Disables a network interface
6084  * @netdev: network interface device structure
6085  * @suspending: boolean indicating the device is suspending
6086  *
6087  * Returns 0, this is not allowed to fail
6088  *
6089  * The close entry point is called when an interface is de-activated
6090  * by the OS.  The hardware is still under the driver's control, but
6091  * needs to be disabled.  A global MAC reset is issued to stop the
6092  * hardware, and all transmit and receive resources are freed.
6093  */
6094 static int __igc_close(struct net_device *netdev, bool suspending)
6095 {
6096         struct igc_adapter *adapter = netdev_priv(netdev);
6097         struct pci_dev *pdev = adapter->pdev;
6098
6099         WARN_ON(test_bit(__IGC_RESETTING, &adapter->state));
6100
6101         if (!suspending)
6102                 pm_runtime_get_sync(&pdev->dev);
6103
6104         igc_down(adapter);
6105
6106         igc_release_hw_control(adapter);
6107
6108         igc_free_irq(adapter);
6109
6110         igc_free_all_tx_resources(adapter);
6111         igc_free_all_rx_resources(adapter);
6112
6113         if (!suspending)
6114                 pm_runtime_put_sync(&pdev->dev);
6115
6116         return 0;
6117 }
6118
6119 int igc_close(struct net_device *netdev)
6120 {
6121         if (netif_device_present(netdev) || netdev->dismantle)
6122                 return __igc_close(netdev, false);
6123         return 0;
6124 }
6125
6126 /**
6127  * igc_ioctl - Access the hwtstamp interface
6128  * @netdev: network interface device structure
6129  * @ifr: interface request data
6130  * @cmd: ioctl command
6131  **/
6132 static int igc_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6133 {
6134         switch (cmd) {
6135         case SIOCGHWTSTAMP:
6136                 return igc_ptp_get_ts_config(netdev, ifr);
6137         case SIOCSHWTSTAMP:
6138                 return igc_ptp_set_ts_config(netdev, ifr);
6139         default:
6140                 return -EOPNOTSUPP;
6141         }
6142 }
6143
6144 static int igc_save_launchtime_params(struct igc_adapter *adapter, int queue,
6145                                       bool enable)
6146 {
6147         struct igc_ring *ring;
6148
6149         if (queue < 0 || queue >= adapter->num_tx_queues)
6150                 return -EINVAL;
6151
6152         ring = adapter->tx_ring[queue];
6153         ring->launchtime_enable = enable;
6154
6155         return 0;
6156 }
6157
6158 static bool is_base_time_past(ktime_t base_time, const struct timespec64 *now)
6159 {
6160         struct timespec64 b;
6161
6162         b = ktime_to_timespec64(base_time);
6163
6164         return timespec64_compare(now, &b) > 0;
6165 }
6166
6167 static bool validate_schedule(struct igc_adapter *adapter,
6168                               const struct tc_taprio_qopt_offload *qopt)
6169 {
6170         int queue_uses[IGC_MAX_TX_QUEUES] = { };
6171         struct igc_hw *hw = &adapter->hw;
6172         struct timespec64 now;
6173         size_t n;
6174
6175         if (qopt->cycle_time_extension)
6176                 return false;
6177
6178         igc_ptp_read(adapter, &now);
6179
6180         /* If we program the controller's BASET registers with a time
6181          * in the future, it will hold all the packets until that
6182          * time, causing a lot of TX Hangs, so to avoid that, we
6183          * reject schedules that would start in the future.
6184          * Note: Limitation above is no longer in i226.
6185          */
6186         if (!is_base_time_past(qopt->base_time, &now) &&
6187             igc_is_device_id_i225(hw))
6188                 return false;
6189
6190         for (n = 0; n < qopt->num_entries; n++) {
6191                 const struct tc_taprio_sched_entry *e, *prev;
6192                 int i;
6193
6194                 prev = n ? &qopt->entries[n - 1] : NULL;
6195                 e = &qopt->entries[n];
6196
6197                 /* i225 only supports "global" frame preemption
6198                  * settings.
6199                  */
6200                 if (e->command != TC_TAPRIO_CMD_SET_GATES)
6201                         return false;
6202
6203                 for (i = 0; i < adapter->num_tx_queues; i++)
6204                         if (e->gate_mask & BIT(i)) {
6205                                 queue_uses[i]++;
6206
6207                                 /* There are limitations: A single queue cannot
6208                                  * be opened and closed multiple times per cycle
6209                                  * unless the gate stays open. Check for it.
6210                                  */
6211                                 if (queue_uses[i] > 1 &&
6212                                     !(prev->gate_mask & BIT(i)))
6213                                         return false;
6214                         }
6215         }
6216
6217         return true;
6218 }
6219
6220 static int igc_tsn_enable_launchtime(struct igc_adapter *adapter,
6221                                      struct tc_etf_qopt_offload *qopt)
6222 {
6223         struct igc_hw *hw = &adapter->hw;
6224         int err;
6225
6226         if (hw->mac.type != igc_i225)
6227                 return -EOPNOTSUPP;
6228
6229         err = igc_save_launchtime_params(adapter, qopt->queue, qopt->enable);
6230         if (err)
6231                 return err;
6232
6233         return igc_tsn_offload_apply(adapter);
6234 }
6235
6236 static int igc_qbv_clear_schedule(struct igc_adapter *adapter)
6237 {
6238         unsigned long flags;
6239         int i;
6240
6241         adapter->base_time = 0;
6242         adapter->cycle_time = NSEC_PER_SEC;
6243         adapter->taprio_offload_enable = false;
6244         adapter->qbv_config_change_errors = 0;
6245         adapter->qbv_count = 0;
6246
6247         for (i = 0; i < adapter->num_tx_queues; i++) {
6248                 struct igc_ring *ring = adapter->tx_ring[i];
6249
6250                 ring->start_time = 0;
6251                 ring->end_time = NSEC_PER_SEC;
6252                 ring->max_sdu = 0;
6253         }
6254
6255         spin_lock_irqsave(&adapter->qbv_tx_lock, flags);
6256
6257         adapter->qbv_transition = false;
6258
6259         for (i = 0; i < adapter->num_tx_queues; i++) {
6260                 struct igc_ring *ring = adapter->tx_ring[i];
6261
6262                 ring->oper_gate_closed = false;
6263                 ring->admin_gate_closed = false;
6264         }
6265
6266         spin_unlock_irqrestore(&adapter->qbv_tx_lock, flags);
6267
6268         return 0;
6269 }
6270
6271 static int igc_tsn_clear_schedule(struct igc_adapter *adapter)
6272 {
6273         igc_qbv_clear_schedule(adapter);
6274
6275         return 0;
6276 }
6277
6278 static void igc_taprio_stats(struct net_device *dev,
6279                              struct tc_taprio_qopt_stats *stats)
6280 {
6281         /* When Strict_End is enabled, the tx_overruns counter
6282          * will always be zero.
6283          */
6284         stats->tx_overruns = 0;
6285 }
6286
6287 static void igc_taprio_queue_stats(struct net_device *dev,
6288                                    struct tc_taprio_qopt_queue_stats *queue_stats)
6289 {
6290         struct tc_taprio_qopt_stats *stats = &queue_stats->stats;
6291
6292         /* When Strict_End is enabled, the tx_overruns counter
6293          * will always be zero.
6294          */
6295         stats->tx_overruns = 0;
6296 }
6297
6298 static int igc_save_qbv_schedule(struct igc_adapter *adapter,
6299                                  struct tc_taprio_qopt_offload *qopt)
6300 {
6301         bool queue_configured[IGC_MAX_TX_QUEUES] = { };
6302         struct igc_hw *hw = &adapter->hw;
6303         u32 start_time = 0, end_time = 0;
6304         struct timespec64 now;
6305         unsigned long flags;
6306         size_t n;
6307         int i;
6308
6309         if (qopt->base_time < 0)
6310                 return -ERANGE;
6311
6312         if (igc_is_device_id_i225(hw) && adapter->taprio_offload_enable)
6313                 return -EALREADY;
6314
6315         if (!validate_schedule(adapter, qopt))
6316                 return -EINVAL;
6317
6318         adapter->cycle_time = qopt->cycle_time;
6319         adapter->base_time = qopt->base_time;
6320         adapter->taprio_offload_enable = true;
6321
6322         igc_ptp_read(adapter, &now);
6323
6324         for (n = 0; n < qopt->num_entries; n++) {
6325                 struct tc_taprio_sched_entry *e = &qopt->entries[n];
6326
6327                 end_time += e->interval;
6328
6329                 /* If any of the conditions below are true, we need to manually
6330                  * control the end time of the cycle.
6331                  * 1. Qbv users can specify a cycle time that is not equal
6332                  * to the total GCL intervals. Hence, recalculation is
6333                  * necessary here to exclude the time interval that
6334                  * exceeds the cycle time.
6335                  * 2. According to IEEE Std. 802.1Q-2018 section 8.6.9.2,
6336                  * once the end of the list is reached, it will switch
6337                  * to the END_OF_CYCLE state and leave the gates in the
6338                  * same state until the next cycle is started.
6339                  */
6340                 if (end_time > adapter->cycle_time ||
6341                     n + 1 == qopt->num_entries)
6342                         end_time = adapter->cycle_time;
6343
6344                 for (i = 0; i < adapter->num_tx_queues; i++) {
6345                         struct igc_ring *ring = adapter->tx_ring[i];
6346
6347                         if (!(e->gate_mask & BIT(i)))
6348                                 continue;
6349
6350                         /* Check whether a queue stays open for more than one
6351                          * entry. If so, keep the start and advance the end
6352                          * time.
6353                          */
6354                         if (!queue_configured[i])
6355                                 ring->start_time = start_time;
6356                         ring->end_time = end_time;
6357
6358                         if (ring->start_time >= adapter->cycle_time)
6359                                 queue_configured[i] = false;
6360                         else
6361                                 queue_configured[i] = true;
6362                 }
6363
6364                 start_time += e->interval;
6365         }
6366
6367         spin_lock_irqsave(&adapter->qbv_tx_lock, flags);
6368
6369         /* Check whether a queue gets configured.
6370          * If not, set the start and end time to be end time.
6371          */
6372         for (i = 0; i < adapter->num_tx_queues; i++) {
6373                 struct igc_ring *ring = adapter->tx_ring[i];
6374
6375                 if (!is_base_time_past(qopt->base_time, &now)) {
6376                         ring->admin_gate_closed = false;
6377                 } else {
6378                         ring->oper_gate_closed = false;
6379                         ring->admin_gate_closed = false;
6380                 }
6381
6382                 if (!queue_configured[i]) {
6383                         if (!is_base_time_past(qopt->base_time, &now))
6384                                 ring->admin_gate_closed = true;
6385                         else
6386                                 ring->oper_gate_closed = true;
6387
6388                         ring->start_time = end_time;
6389                         ring->end_time = end_time;
6390                 }
6391         }
6392
6393         spin_unlock_irqrestore(&adapter->qbv_tx_lock, flags);
6394
6395         for (i = 0; i < adapter->num_tx_queues; i++) {
6396                 struct igc_ring *ring = adapter->tx_ring[i];
6397                 struct net_device *dev = adapter->netdev;
6398
6399                 if (qopt->max_sdu[i])
6400                         ring->max_sdu = qopt->max_sdu[i] + dev->hard_header_len - ETH_TLEN;
6401                 else
6402                         ring->max_sdu = 0;
6403         }
6404
6405         return 0;
6406 }
6407
6408 static int igc_tsn_enable_qbv_scheduling(struct igc_adapter *adapter,
6409                                          struct tc_taprio_qopt_offload *qopt)
6410 {
6411         struct igc_hw *hw = &adapter->hw;
6412         int err;
6413
6414         if (hw->mac.type != igc_i225)
6415                 return -EOPNOTSUPP;
6416
6417         switch (qopt->cmd) {
6418         case TAPRIO_CMD_REPLACE:
6419                 err = igc_save_qbv_schedule(adapter, qopt);
6420                 break;
6421         case TAPRIO_CMD_DESTROY:
6422                 err = igc_tsn_clear_schedule(adapter);
6423                 break;
6424         case TAPRIO_CMD_STATS:
6425                 igc_taprio_stats(adapter->netdev, &qopt->stats);
6426                 return 0;
6427         case TAPRIO_CMD_QUEUE_STATS:
6428                 igc_taprio_queue_stats(adapter->netdev, &qopt->queue_stats);
6429                 return 0;
6430         default:
6431                 return -EOPNOTSUPP;
6432         }
6433
6434         if (err)
6435                 return err;
6436
6437         return igc_tsn_offload_apply(adapter);
6438 }
6439
6440 static int igc_save_cbs_params(struct igc_adapter *adapter, int queue,
6441                                bool enable, int idleslope, int sendslope,
6442                                int hicredit, int locredit)
6443 {
6444         bool cbs_status[IGC_MAX_SR_QUEUES] = { false };
6445         struct net_device *netdev = adapter->netdev;
6446         struct igc_ring *ring;
6447         int i;
6448
6449         /* i225 has two sets of credit-based shaper logic.
6450          * Supporting it only on the top two priority queues
6451          */
6452         if (queue < 0 || queue > 1)
6453                 return -EINVAL;
6454
6455         ring = adapter->tx_ring[queue];
6456
6457         for (i = 0; i < IGC_MAX_SR_QUEUES; i++)
6458                 if (adapter->tx_ring[i])
6459                         cbs_status[i] = adapter->tx_ring[i]->cbs_enable;
6460
6461         /* CBS should be enabled on the highest priority queue first in order
6462          * for the CBS algorithm to operate as intended.
6463          */
6464         if (enable) {
6465                 if (queue == 1 && !cbs_status[0]) {
6466                         netdev_err(netdev,
6467                                    "Enabling CBS on queue1 before queue0\n");
6468                         return -EINVAL;
6469                 }
6470         } else {
6471                 if (queue == 0 && cbs_status[1]) {
6472                         netdev_err(netdev,
6473                                    "Disabling CBS on queue0 before queue1\n");
6474                         return -EINVAL;
6475                 }
6476         }
6477
6478         ring->cbs_enable = enable;
6479         ring->idleslope = idleslope;
6480         ring->sendslope = sendslope;
6481         ring->hicredit = hicredit;
6482         ring->locredit = locredit;
6483
6484         return 0;
6485 }
6486
6487 static int igc_tsn_enable_cbs(struct igc_adapter *adapter,
6488                               struct tc_cbs_qopt_offload *qopt)
6489 {
6490         struct igc_hw *hw = &adapter->hw;
6491         int err;
6492
6493         if (hw->mac.type != igc_i225)
6494                 return -EOPNOTSUPP;
6495
6496         if (qopt->queue < 0 || qopt->queue > 1)
6497                 return -EINVAL;
6498
6499         err = igc_save_cbs_params(adapter, qopt->queue, qopt->enable,
6500                                   qopt->idleslope, qopt->sendslope,
6501                                   qopt->hicredit, qopt->locredit);
6502         if (err)
6503                 return err;
6504
6505         return igc_tsn_offload_apply(adapter);
6506 }
6507
6508 static int igc_tc_query_caps(struct igc_adapter *adapter,
6509                              struct tc_query_caps_base *base)
6510 {
6511         struct igc_hw *hw = &adapter->hw;
6512
6513         switch (base->type) {
6514         case TC_SETUP_QDISC_TAPRIO: {
6515                 struct tc_taprio_caps *caps = base->caps;
6516
6517                 caps->broken_mqprio = true;
6518
6519                 if (hw->mac.type == igc_i225) {
6520                         caps->supports_queue_max_sdu = true;
6521                         caps->gate_mask_per_txq = true;
6522                 }
6523
6524                 return 0;
6525         }
6526         default:
6527                 return -EOPNOTSUPP;
6528         }
6529 }
6530
6531 static int igc_setup_tc(struct net_device *dev, enum tc_setup_type type,
6532                         void *type_data)
6533 {
6534         struct igc_adapter *adapter = netdev_priv(dev);
6535
6536         adapter->tc_setup_type = type;
6537
6538         switch (type) {
6539         case TC_QUERY_CAPS:
6540                 return igc_tc_query_caps(adapter, type_data);
6541         case TC_SETUP_QDISC_TAPRIO:
6542                 return igc_tsn_enable_qbv_scheduling(adapter, type_data);
6543
6544         case TC_SETUP_QDISC_ETF:
6545                 return igc_tsn_enable_launchtime(adapter, type_data);
6546
6547         case TC_SETUP_QDISC_CBS:
6548                 return igc_tsn_enable_cbs(adapter, type_data);
6549
6550         default:
6551                 return -EOPNOTSUPP;
6552         }
6553 }
6554
6555 static int igc_bpf(struct net_device *dev, struct netdev_bpf *bpf)
6556 {
6557         struct igc_adapter *adapter = netdev_priv(dev);
6558
6559         switch (bpf->command) {
6560         case XDP_SETUP_PROG:
6561                 return igc_xdp_set_prog(adapter, bpf->prog, bpf->extack);
6562         case XDP_SETUP_XSK_POOL:
6563                 return igc_xdp_setup_pool(adapter, bpf->xsk.pool,
6564                                           bpf->xsk.queue_id);
6565         default:
6566                 return -EOPNOTSUPP;
6567         }
6568 }
6569
6570 static int igc_xdp_xmit(struct net_device *dev, int num_frames,
6571                         struct xdp_frame **frames, u32 flags)
6572 {
6573         struct igc_adapter *adapter = netdev_priv(dev);
6574         int cpu = smp_processor_id();
6575         struct netdev_queue *nq;
6576         struct igc_ring *ring;
6577         int i, nxmit;
6578
6579         if (unlikely(!netif_carrier_ok(dev)))
6580                 return -ENETDOWN;
6581
6582         if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
6583                 return -EINVAL;
6584
6585         ring = igc_xdp_get_tx_ring(adapter, cpu);
6586         nq = txring_txq(ring);
6587
6588         __netif_tx_lock(nq, cpu);
6589
6590         /* Avoid transmit queue timeout since we share it with the slow path */
6591         txq_trans_cond_update(nq);
6592
6593         nxmit = 0;
6594         for (i = 0; i < num_frames; i++) {
6595                 int err;
6596                 struct xdp_frame *xdpf = frames[i];
6597
6598                 err = igc_xdp_init_tx_descriptor(ring, xdpf);
6599                 if (err)
6600                         break;
6601                 nxmit++;
6602         }
6603
6604         if (flags & XDP_XMIT_FLUSH)
6605                 igc_flush_tx_descriptors(ring);
6606
6607         __netif_tx_unlock(nq);
6608
6609         return nxmit;
6610 }
6611
6612 static void igc_trigger_rxtxq_interrupt(struct igc_adapter *adapter,
6613                                         struct igc_q_vector *q_vector)
6614 {
6615         struct igc_hw *hw = &adapter->hw;
6616         u32 eics = 0;
6617
6618         eics |= q_vector->eims_value;
6619         wr32(IGC_EICS, eics);
6620 }
6621
6622 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags)
6623 {
6624         struct igc_adapter *adapter = netdev_priv(dev);
6625         struct igc_q_vector *q_vector;
6626         struct igc_ring *ring;
6627
6628         if (test_bit(__IGC_DOWN, &adapter->state))
6629                 return -ENETDOWN;
6630
6631         if (!igc_xdp_is_enabled(adapter))
6632                 return -ENXIO;
6633
6634         if (queue_id >= adapter->num_rx_queues)
6635                 return -EINVAL;
6636
6637         ring = adapter->rx_ring[queue_id];
6638
6639         if (!ring->xsk_pool)
6640                 return -ENXIO;
6641
6642         q_vector = adapter->q_vector[queue_id];
6643         if (!napi_if_scheduled_mark_missed(&q_vector->napi))
6644                 igc_trigger_rxtxq_interrupt(adapter, q_vector);
6645
6646         return 0;
6647 }
6648
6649 static ktime_t igc_get_tstamp(struct net_device *dev,
6650                               const struct skb_shared_hwtstamps *hwtstamps,
6651                               bool cycles)
6652 {
6653         struct igc_adapter *adapter = netdev_priv(dev);
6654         struct igc_inline_rx_tstamps *tstamp;
6655         ktime_t timestamp;
6656
6657         tstamp = hwtstamps->netdev_data;
6658
6659         if (cycles)
6660                 timestamp = igc_ptp_rx_pktstamp(adapter, tstamp->timer1);
6661         else
6662                 timestamp = igc_ptp_rx_pktstamp(adapter, tstamp->timer0);
6663
6664         return timestamp;
6665 }
6666
6667 static const struct net_device_ops igc_netdev_ops = {
6668         .ndo_open               = igc_open,
6669         .ndo_stop               = igc_close,
6670         .ndo_start_xmit         = igc_xmit_frame,
6671         .ndo_set_rx_mode        = igc_set_rx_mode,
6672         .ndo_set_mac_address    = igc_set_mac,
6673         .ndo_change_mtu         = igc_change_mtu,
6674         .ndo_tx_timeout         = igc_tx_timeout,
6675         .ndo_get_stats64        = igc_get_stats64,
6676         .ndo_fix_features       = igc_fix_features,
6677         .ndo_set_features       = igc_set_features,
6678         .ndo_features_check     = igc_features_check,
6679         .ndo_eth_ioctl          = igc_ioctl,
6680         .ndo_setup_tc           = igc_setup_tc,
6681         .ndo_bpf                = igc_bpf,
6682         .ndo_xdp_xmit           = igc_xdp_xmit,
6683         .ndo_xsk_wakeup         = igc_xsk_wakeup,
6684         .ndo_get_tstamp         = igc_get_tstamp,
6685 };
6686
6687 /* PCIe configuration access */
6688 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)
6689 {
6690         struct igc_adapter *adapter = hw->back;
6691
6692         pci_read_config_word(adapter->pdev, reg, value);
6693 }
6694
6695 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)
6696 {
6697         struct igc_adapter *adapter = hw->back;
6698
6699         pci_write_config_word(adapter->pdev, reg, *value);
6700 }
6701
6702 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)
6703 {
6704         struct igc_adapter *adapter = hw->back;
6705
6706         if (!pci_is_pcie(adapter->pdev))
6707                 return -IGC_ERR_CONFIG;
6708
6709         pcie_capability_read_word(adapter->pdev, reg, value);
6710
6711         return IGC_SUCCESS;
6712 }
6713
6714 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)
6715 {
6716         struct igc_adapter *adapter = hw->back;
6717
6718         if (!pci_is_pcie(adapter->pdev))
6719                 return -IGC_ERR_CONFIG;
6720
6721         pcie_capability_write_word(adapter->pdev, reg, *value);
6722
6723         return IGC_SUCCESS;
6724 }
6725
6726 u32 igc_rd32(struct igc_hw *hw, u32 reg)
6727 {
6728         struct igc_adapter *igc = container_of(hw, struct igc_adapter, hw);
6729         u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
6730         u32 value = 0;
6731
6732         if (IGC_REMOVED(hw_addr))
6733                 return ~value;
6734
6735         value = readl(&hw_addr[reg]);
6736
6737         /* reads should not return all F's */
6738         if (!(~value) && (!reg || !(~readl(hw_addr)))) {
6739                 struct net_device *netdev = igc->netdev;
6740
6741                 hw->hw_addr = NULL;
6742                 netif_device_detach(netdev);
6743                 netdev_err(netdev, "PCIe link lost, device now detached\n");
6744                 WARN(pci_device_is_present(igc->pdev),
6745                      "igc: Failed to read reg 0x%x!\n", reg);
6746         }
6747
6748         return value;
6749 }
6750
6751 /* Mapping HW RSS Type to enum xdp_rss_hash_type */
6752 static enum xdp_rss_hash_type igc_xdp_rss_type[IGC_RSS_TYPE_MAX_TABLE] = {
6753         [IGC_RSS_TYPE_NO_HASH]          = XDP_RSS_TYPE_L2,
6754         [IGC_RSS_TYPE_HASH_TCP_IPV4]    = XDP_RSS_TYPE_L4_IPV4_TCP,
6755         [IGC_RSS_TYPE_HASH_IPV4]        = XDP_RSS_TYPE_L3_IPV4,
6756         [IGC_RSS_TYPE_HASH_TCP_IPV6]    = XDP_RSS_TYPE_L4_IPV6_TCP,
6757         [IGC_RSS_TYPE_HASH_IPV6_EX]     = XDP_RSS_TYPE_L3_IPV6_EX,
6758         [IGC_RSS_TYPE_HASH_IPV6]        = XDP_RSS_TYPE_L3_IPV6,
6759         [IGC_RSS_TYPE_HASH_TCP_IPV6_EX] = XDP_RSS_TYPE_L4_IPV6_TCP_EX,
6760         [IGC_RSS_TYPE_HASH_UDP_IPV4]    = XDP_RSS_TYPE_L4_IPV4_UDP,
6761         [IGC_RSS_TYPE_HASH_UDP_IPV6]    = XDP_RSS_TYPE_L4_IPV6_UDP,
6762         [IGC_RSS_TYPE_HASH_UDP_IPV6_EX] = XDP_RSS_TYPE_L4_IPV6_UDP_EX,
6763         [10] = XDP_RSS_TYPE_NONE, /* RSS Type above 9 "Reserved" by HW  */
6764         [11] = XDP_RSS_TYPE_NONE, /* keep array sized for SW bit-mask   */
6765         [12] = XDP_RSS_TYPE_NONE, /* to handle future HW revisons       */
6766         [13] = XDP_RSS_TYPE_NONE,
6767         [14] = XDP_RSS_TYPE_NONE,
6768         [15] = XDP_RSS_TYPE_NONE,
6769 };
6770
6771 static int igc_xdp_rx_hash(const struct xdp_md *_ctx, u32 *hash,
6772                            enum xdp_rss_hash_type *rss_type)
6773 {
6774         const struct igc_xdp_buff *ctx = (void *)_ctx;
6775
6776         if (!(ctx->xdp.rxq->dev->features & NETIF_F_RXHASH))
6777                 return -ENODATA;
6778
6779         *hash = le32_to_cpu(ctx->rx_desc->wb.lower.hi_dword.rss);
6780         *rss_type = igc_xdp_rss_type[igc_rss_type(ctx->rx_desc)];
6781
6782         return 0;
6783 }
6784
6785 static int igc_xdp_rx_timestamp(const struct xdp_md *_ctx, u64 *timestamp)
6786 {
6787         const struct igc_xdp_buff *ctx = (void *)_ctx;
6788         struct igc_adapter *adapter = netdev_priv(ctx->xdp.rxq->dev);
6789         struct igc_inline_rx_tstamps *tstamp = ctx->rx_ts;
6790
6791         if (igc_test_staterr(ctx->rx_desc, IGC_RXDADV_STAT_TSIP)) {
6792                 *timestamp = igc_ptp_rx_pktstamp(adapter, tstamp->timer0);
6793
6794                 return 0;
6795         }
6796
6797         return -ENODATA;
6798 }
6799
6800 static const struct xdp_metadata_ops igc_xdp_metadata_ops = {
6801         .xmo_rx_hash                    = igc_xdp_rx_hash,
6802         .xmo_rx_timestamp               = igc_xdp_rx_timestamp,
6803 };
6804
6805 static enum hrtimer_restart igc_qbv_scheduling_timer(struct hrtimer *timer)
6806 {
6807         struct igc_adapter *adapter = container_of(timer, struct igc_adapter,
6808                                                    hrtimer);
6809         unsigned long flags;
6810         unsigned int i;
6811
6812         spin_lock_irqsave(&adapter->qbv_tx_lock, flags);
6813
6814         adapter->qbv_transition = true;
6815         for (i = 0; i < adapter->num_tx_queues; i++) {
6816                 struct igc_ring *tx_ring = adapter->tx_ring[i];
6817
6818                 if (tx_ring->admin_gate_closed) {
6819                         tx_ring->admin_gate_closed = false;
6820                         tx_ring->oper_gate_closed = true;
6821                 } else {
6822                         tx_ring->oper_gate_closed = false;
6823                 }
6824         }
6825         adapter->qbv_transition = false;
6826
6827         spin_unlock_irqrestore(&adapter->qbv_tx_lock, flags);
6828
6829         return HRTIMER_NORESTART;
6830 }
6831
6832 /**
6833  * igc_probe - Device Initialization Routine
6834  * @pdev: PCI device information struct
6835  * @ent: entry in igc_pci_tbl
6836  *
6837  * Returns 0 on success, negative on failure
6838  *
6839  * igc_probe initializes an adapter identified by a pci_dev structure.
6840  * The OS initialization, configuring the adapter private structure,
6841  * and a hardware reset occur.
6842  */
6843 static int igc_probe(struct pci_dev *pdev,
6844                      const struct pci_device_id *ent)
6845 {
6846         struct igc_adapter *adapter;
6847         struct net_device *netdev;
6848         struct igc_hw *hw;
6849         const struct igc_info *ei = igc_info_tbl[ent->driver_data];
6850         int err;
6851
6852         err = pci_enable_device_mem(pdev);
6853         if (err)
6854                 return err;
6855
6856         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6857         if (err) {
6858                 dev_err(&pdev->dev,
6859                         "No usable DMA configuration, aborting\n");
6860                 goto err_dma;
6861         }
6862
6863         err = pci_request_mem_regions(pdev, igc_driver_name);
6864         if (err)
6865                 goto err_pci_reg;
6866
6867         err = pci_enable_ptm(pdev, NULL);
6868         if (err < 0)
6869                 dev_info(&pdev->dev, "PCIe PTM not supported by PCIe bus/controller\n");
6870
6871         pci_set_master(pdev);
6872
6873         err = -ENOMEM;
6874         netdev = alloc_etherdev_mq(sizeof(struct igc_adapter),
6875                                    IGC_MAX_TX_QUEUES);
6876
6877         if (!netdev)
6878                 goto err_alloc_etherdev;
6879
6880         SET_NETDEV_DEV(netdev, &pdev->dev);
6881
6882         pci_set_drvdata(pdev, netdev);
6883         adapter = netdev_priv(netdev);
6884         adapter->netdev = netdev;
6885         adapter->pdev = pdev;
6886         hw = &adapter->hw;
6887         hw->back = adapter;
6888         adapter->port_num = hw->bus.func;
6889         adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
6890
6891         err = pci_save_state(pdev);
6892         if (err)
6893                 goto err_ioremap;
6894
6895         err = -EIO;
6896         adapter->io_addr = ioremap(pci_resource_start(pdev, 0),
6897                                    pci_resource_len(pdev, 0));
6898         if (!adapter->io_addr)
6899                 goto err_ioremap;
6900
6901         /* hw->hw_addr can be zeroed, so use adapter->io_addr for unmap */
6902         hw->hw_addr = adapter->io_addr;
6903
6904         netdev->netdev_ops = &igc_netdev_ops;
6905         netdev->xdp_metadata_ops = &igc_xdp_metadata_ops;
6906         netdev->xsk_tx_metadata_ops = &igc_xsk_tx_metadata_ops;
6907         igc_ethtool_set_ops(netdev);
6908         netdev->watchdog_timeo = 5 * HZ;
6909
6910         netdev->mem_start = pci_resource_start(pdev, 0);
6911         netdev->mem_end = pci_resource_end(pdev, 0);
6912
6913         /* PCI config space info */
6914         hw->vendor_id = pdev->vendor;
6915         hw->device_id = pdev->device;
6916         hw->revision_id = pdev->revision;
6917         hw->subsystem_vendor_id = pdev->subsystem_vendor;
6918         hw->subsystem_device_id = pdev->subsystem_device;
6919
6920         /* Copy the default MAC and PHY function pointers */
6921         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6922         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6923
6924         /* Initialize skew-specific constants */
6925         err = ei->get_invariants(hw);
6926         if (err)
6927                 goto err_sw_init;
6928
6929         /* Add supported features to the features list*/
6930         netdev->features |= NETIF_F_SG;
6931         netdev->features |= NETIF_F_TSO;
6932         netdev->features |= NETIF_F_TSO6;
6933         netdev->features |= NETIF_F_TSO_ECN;
6934         netdev->features |= NETIF_F_RXHASH;
6935         netdev->features |= NETIF_F_RXCSUM;
6936         netdev->features |= NETIF_F_HW_CSUM;
6937         netdev->features |= NETIF_F_SCTP_CRC;
6938         netdev->features |= NETIF_F_HW_TC;
6939
6940 #define IGC_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
6941                                   NETIF_F_GSO_GRE_CSUM | \
6942                                   NETIF_F_GSO_IPXIP4 | \
6943                                   NETIF_F_GSO_IPXIP6 | \
6944                                   NETIF_F_GSO_UDP_TUNNEL | \
6945                                   NETIF_F_GSO_UDP_TUNNEL_CSUM)
6946
6947         netdev->gso_partial_features = IGC_GSO_PARTIAL_FEATURES;
6948         netdev->features |= NETIF_F_GSO_PARTIAL | IGC_GSO_PARTIAL_FEATURES;
6949
6950         /* setup the private structure */
6951         err = igc_sw_init(adapter);
6952         if (err)
6953                 goto err_sw_init;
6954
6955         /* copy netdev features into list of user selectable features */
6956         netdev->hw_features |= NETIF_F_NTUPLE;
6957         netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
6958         netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
6959         netdev->hw_features |= netdev->features;
6960
6961         netdev->features |= NETIF_F_HIGHDMA;
6962
6963         netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
6964         netdev->mpls_features |= NETIF_F_HW_CSUM;
6965         netdev->hw_enc_features |= netdev->vlan_features;
6966
6967         netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
6968                                NETDEV_XDP_ACT_XSK_ZEROCOPY;
6969
6970         /* MTU range: 68 - 9216 */
6971         netdev->min_mtu = ETH_MIN_MTU;
6972         netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
6973
6974         /* before reading the NVM, reset the controller to put the device in a
6975          * known good starting state
6976          */
6977         hw->mac.ops.reset_hw(hw);
6978
6979         if (igc_get_flash_presence_i225(hw)) {
6980                 if (hw->nvm.ops.validate(hw) < 0) {
6981                         dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
6982                         err = -EIO;
6983                         goto err_eeprom;
6984                 }
6985         }
6986
6987         if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
6988                 /* copy the MAC address out of the NVM */
6989                 if (hw->mac.ops.read_mac_addr(hw))
6990                         dev_err(&pdev->dev, "NVM Read Error\n");
6991         }
6992
6993         eth_hw_addr_set(netdev, hw->mac.addr);
6994
6995         if (!is_valid_ether_addr(netdev->dev_addr)) {
6996                 dev_err(&pdev->dev, "Invalid MAC Address\n");
6997                 err = -EIO;
6998                 goto err_eeprom;
6999         }
7000
7001         /* configure RXPBSIZE and TXPBSIZE */
7002         wr32(IGC_RXPBS, I225_RXPBSIZE_DEFAULT);
7003         wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT);
7004
7005         timer_setup(&adapter->watchdog_timer, igc_watchdog, 0);
7006         timer_setup(&adapter->phy_info_timer, igc_update_phy_info, 0);
7007
7008         INIT_WORK(&adapter->reset_task, igc_reset_task);
7009         INIT_WORK(&adapter->watchdog_task, igc_watchdog_task);
7010
7011         hrtimer_init(&adapter->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
7012         adapter->hrtimer.function = &igc_qbv_scheduling_timer;
7013
7014         /* Initialize link properties that are user-changeable */
7015         adapter->fc_autoneg = true;
7016         hw->mac.autoneg = true;
7017         hw->phy.autoneg_advertised = 0xaf;
7018
7019         hw->fc.requested_mode = igc_fc_default;
7020         hw->fc.current_mode = igc_fc_default;
7021
7022         /* By default, support wake on port A */
7023         adapter->flags |= IGC_FLAG_WOL_SUPPORTED;
7024
7025         /* initialize the wol settings based on the eeprom settings */
7026         if (adapter->flags & IGC_FLAG_WOL_SUPPORTED)
7027                 adapter->wol |= IGC_WUFC_MAG;
7028
7029         device_set_wakeup_enable(&adapter->pdev->dev,
7030                                  adapter->flags & IGC_FLAG_WOL_SUPPORTED);
7031
7032         igc_ptp_init(adapter);
7033
7034         igc_tsn_clear_schedule(adapter);
7035
7036         /* reset the hardware with the new settings */
7037         igc_reset(adapter);
7038
7039         /* let the f/w know that the h/w is now under the control of the
7040          * driver.
7041          */
7042         igc_get_hw_control(adapter);
7043
7044         strscpy(netdev->name, "eth%d", sizeof(netdev->name));
7045         err = register_netdev(netdev);
7046         if (err)
7047                 goto err_register;
7048
7049          /* carrier off reporting is important to ethtool even BEFORE open */
7050         netif_carrier_off(netdev);
7051
7052         /* Check if Media Autosense is enabled */
7053         adapter->ei = *ei;
7054
7055         /* print pcie link status and MAC address */
7056         pcie_print_link_status(pdev);
7057         netdev_info(netdev, "MAC: %pM\n", netdev->dev_addr);
7058
7059         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
7060         /* Disable EEE for internal PHY devices */
7061         hw->dev_spec._base.eee_enable = false;
7062         adapter->flags &= ~IGC_FLAG_EEE;
7063         igc_set_eee_i225(hw, false, false, false);
7064
7065         pm_runtime_put_noidle(&pdev->dev);
7066
7067         if (IS_ENABLED(CONFIG_IGC_LEDS)) {
7068                 err = igc_led_setup(adapter);
7069                 if (err)
7070                         goto err_register;
7071         }
7072
7073         return 0;
7074
7075 err_register:
7076         igc_release_hw_control(adapter);
7077 err_eeprom:
7078         if (!igc_check_reset_block(hw))
7079                 igc_reset_phy(hw);
7080 err_sw_init:
7081         igc_clear_interrupt_scheme(adapter);
7082         iounmap(adapter->io_addr);
7083 err_ioremap:
7084         free_netdev(netdev);
7085 err_alloc_etherdev:
7086         pci_release_mem_regions(pdev);
7087 err_pci_reg:
7088 err_dma:
7089         pci_disable_device(pdev);
7090         return err;
7091 }
7092
7093 /**
7094  * igc_remove - Device Removal Routine
7095  * @pdev: PCI device information struct
7096  *
7097  * igc_remove is called by the PCI subsystem to alert the driver
7098  * that it should release a PCI device.  This could be caused by a
7099  * Hot-Plug event, or because the driver is going to be removed from
7100  * memory.
7101  */
7102 static void igc_remove(struct pci_dev *pdev)
7103 {
7104         struct net_device *netdev = pci_get_drvdata(pdev);
7105         struct igc_adapter *adapter = netdev_priv(netdev);
7106
7107         pm_runtime_get_noresume(&pdev->dev);
7108
7109         igc_flush_nfc_rules(adapter);
7110
7111         igc_ptp_stop(adapter);
7112
7113         pci_disable_ptm(pdev);
7114         pci_clear_master(pdev);
7115
7116         set_bit(__IGC_DOWN, &adapter->state);
7117
7118         del_timer_sync(&adapter->watchdog_timer);
7119         del_timer_sync(&adapter->phy_info_timer);
7120
7121         cancel_work_sync(&adapter->reset_task);
7122         cancel_work_sync(&adapter->watchdog_task);
7123         hrtimer_cancel(&adapter->hrtimer);
7124
7125         if (IS_ENABLED(CONFIG_IGC_LEDS))
7126                 igc_led_free(adapter);
7127
7128         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
7129          * would have already happened in close and is redundant.
7130          */
7131         igc_release_hw_control(adapter);
7132         unregister_netdev(netdev);
7133
7134         igc_clear_interrupt_scheme(adapter);
7135         pci_iounmap(pdev, adapter->io_addr);
7136         pci_release_mem_regions(pdev);
7137
7138         free_netdev(netdev);
7139
7140         pci_disable_device(pdev);
7141 }
7142
7143 static int __igc_shutdown(struct pci_dev *pdev, bool *enable_wake,
7144                           bool runtime)
7145 {
7146         struct net_device *netdev = pci_get_drvdata(pdev);
7147         struct igc_adapter *adapter = netdev_priv(netdev);
7148         u32 wufc = runtime ? IGC_WUFC_LNKC : adapter->wol;
7149         struct igc_hw *hw = &adapter->hw;
7150         u32 ctrl, rctl, status;
7151         bool wake;
7152
7153         rtnl_lock();
7154         netif_device_detach(netdev);
7155
7156         if (netif_running(netdev))
7157                 __igc_close(netdev, true);
7158
7159         igc_ptp_suspend(adapter);
7160
7161         igc_clear_interrupt_scheme(adapter);
7162         rtnl_unlock();
7163
7164         status = rd32(IGC_STATUS);
7165         if (status & IGC_STATUS_LU)
7166                 wufc &= ~IGC_WUFC_LNKC;
7167
7168         if (wufc) {
7169                 igc_setup_rctl(adapter);
7170                 igc_set_rx_mode(netdev);
7171
7172                 /* turn on all-multi mode if wake on multicast is enabled */
7173                 if (wufc & IGC_WUFC_MC) {
7174                         rctl = rd32(IGC_RCTL);
7175                         rctl |= IGC_RCTL_MPE;
7176                         wr32(IGC_RCTL, rctl);
7177                 }
7178
7179                 ctrl = rd32(IGC_CTRL);
7180                 ctrl |= IGC_CTRL_ADVD3WUC;
7181                 wr32(IGC_CTRL, ctrl);
7182
7183                 /* Allow time for pending master requests to run */
7184                 igc_disable_pcie_master(hw);
7185
7186                 wr32(IGC_WUC, IGC_WUC_PME_EN);
7187                 wr32(IGC_WUFC, wufc);
7188         } else {
7189                 wr32(IGC_WUC, 0);
7190                 wr32(IGC_WUFC, 0);
7191         }
7192
7193         wake = wufc || adapter->en_mng_pt;
7194         if (!wake)
7195                 igc_power_down_phy_copper_base(&adapter->hw);
7196         else
7197                 igc_power_up_link(adapter);
7198
7199         if (enable_wake)
7200                 *enable_wake = wake;
7201
7202         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
7203          * would have already happened in close and is redundant.
7204          */
7205         igc_release_hw_control(adapter);
7206
7207         pci_disable_device(pdev);
7208
7209         return 0;
7210 }
7211
7212 static int igc_runtime_suspend(struct device *dev)
7213 {
7214         return __igc_shutdown(to_pci_dev(dev), NULL, 1);
7215 }
7216
7217 static void igc_deliver_wake_packet(struct net_device *netdev)
7218 {
7219         struct igc_adapter *adapter = netdev_priv(netdev);
7220         struct igc_hw *hw = &adapter->hw;
7221         struct sk_buff *skb;
7222         u32 wupl;
7223
7224         wupl = rd32(IGC_WUPL) & IGC_WUPL_MASK;
7225
7226         /* WUPM stores only the first 128 bytes of the wake packet.
7227          * Read the packet only if we have the whole thing.
7228          */
7229         if (wupl == 0 || wupl > IGC_WUPM_BYTES)
7230                 return;
7231
7232         skb = netdev_alloc_skb_ip_align(netdev, IGC_WUPM_BYTES);
7233         if (!skb)
7234                 return;
7235
7236         skb_put(skb, wupl);
7237
7238         /* Ensure reads are 32-bit aligned */
7239         wupl = roundup(wupl, 4);
7240
7241         memcpy_fromio(skb->data, hw->hw_addr + IGC_WUPM_REG(0), wupl);
7242
7243         skb->protocol = eth_type_trans(skb, netdev);
7244         netif_rx(skb);
7245 }
7246
7247 static int igc_resume(struct device *dev)
7248 {
7249         struct pci_dev *pdev = to_pci_dev(dev);
7250         struct net_device *netdev = pci_get_drvdata(pdev);
7251         struct igc_adapter *adapter = netdev_priv(netdev);
7252         struct igc_hw *hw = &adapter->hw;
7253         u32 err, val;
7254
7255         pci_set_power_state(pdev, PCI_D0);
7256         pci_restore_state(pdev);
7257         pci_save_state(pdev);
7258
7259         if (!pci_device_is_present(pdev))
7260                 return -ENODEV;
7261         err = pci_enable_device_mem(pdev);
7262         if (err) {
7263                 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
7264                 return err;
7265         }
7266         pci_set_master(pdev);
7267
7268         pci_enable_wake(pdev, PCI_D3hot, 0);
7269         pci_enable_wake(pdev, PCI_D3cold, 0);
7270
7271         if (igc_init_interrupt_scheme(adapter, true)) {
7272                 netdev_err(netdev, "Unable to allocate memory for queues\n");
7273                 return -ENOMEM;
7274         }
7275
7276         igc_reset(adapter);
7277
7278         /* let the f/w know that the h/w is now under the control of the
7279          * driver.
7280          */
7281         igc_get_hw_control(adapter);
7282
7283         val = rd32(IGC_WUS);
7284         if (val & WAKE_PKT_WUS)
7285                 igc_deliver_wake_packet(netdev);
7286
7287         wr32(IGC_WUS, ~0);
7288
7289         if (netif_running(netdev)) {
7290                 err = __igc_open(netdev, true);
7291                 if (!err)
7292                         netif_device_attach(netdev);
7293         }
7294
7295         return err;
7296 }
7297
7298 static int igc_runtime_resume(struct device *dev)
7299 {
7300         return igc_resume(dev);
7301 }
7302
7303 static int igc_suspend(struct device *dev)
7304 {
7305         return __igc_shutdown(to_pci_dev(dev), NULL, 0);
7306 }
7307
7308 static int __maybe_unused igc_runtime_idle(struct device *dev)
7309 {
7310         struct net_device *netdev = dev_get_drvdata(dev);
7311         struct igc_adapter *adapter = netdev_priv(netdev);
7312
7313         if (!igc_has_link(adapter))
7314                 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7315
7316         return -EBUSY;
7317 }
7318
7319 static void igc_shutdown(struct pci_dev *pdev)
7320 {
7321         bool wake;
7322
7323         __igc_shutdown(pdev, &wake, 0);
7324
7325         if (system_state == SYSTEM_POWER_OFF) {
7326                 pci_wake_from_d3(pdev, wake);
7327                 pci_set_power_state(pdev, PCI_D3hot);
7328         }
7329 }
7330
7331 /**
7332  *  igc_io_error_detected - called when PCI error is detected
7333  *  @pdev: Pointer to PCI device
7334  *  @state: The current PCI connection state
7335  *
7336  *  This function is called after a PCI bus error affecting
7337  *  this device has been detected.
7338  **/
7339 static pci_ers_result_t igc_io_error_detected(struct pci_dev *pdev,
7340                                               pci_channel_state_t state)
7341 {
7342         struct net_device *netdev = pci_get_drvdata(pdev);
7343         struct igc_adapter *adapter = netdev_priv(netdev);
7344
7345         netif_device_detach(netdev);
7346
7347         if (state == pci_channel_io_perm_failure)
7348                 return PCI_ERS_RESULT_DISCONNECT;
7349
7350         if (netif_running(netdev))
7351                 igc_down(adapter);
7352         pci_disable_device(pdev);
7353
7354         /* Request a slot reset. */
7355         return PCI_ERS_RESULT_NEED_RESET;
7356 }
7357
7358 /**
7359  *  igc_io_slot_reset - called after the PCI bus has been reset.
7360  *  @pdev: Pointer to PCI device
7361  *
7362  *  Restart the card from scratch, as if from a cold-boot. Implementation
7363  *  resembles the first-half of the igc_resume routine.
7364  **/
7365 static pci_ers_result_t igc_io_slot_reset(struct pci_dev *pdev)
7366 {
7367         struct net_device *netdev = pci_get_drvdata(pdev);
7368         struct igc_adapter *adapter = netdev_priv(netdev);
7369         struct igc_hw *hw = &adapter->hw;
7370         pci_ers_result_t result;
7371
7372         if (pci_enable_device_mem(pdev)) {
7373                 netdev_err(netdev, "Could not re-enable PCI device after reset\n");
7374                 result = PCI_ERS_RESULT_DISCONNECT;
7375         } else {
7376                 pci_set_master(pdev);
7377                 pci_restore_state(pdev);
7378                 pci_save_state(pdev);
7379
7380                 pci_enable_wake(pdev, PCI_D3hot, 0);
7381                 pci_enable_wake(pdev, PCI_D3cold, 0);
7382
7383                 /* In case of PCI error, adapter loses its HW address
7384                  * so we should re-assign it here.
7385                  */
7386                 hw->hw_addr = adapter->io_addr;
7387
7388                 igc_reset(adapter);
7389                 wr32(IGC_WUS, ~0);
7390                 result = PCI_ERS_RESULT_RECOVERED;
7391         }
7392
7393         return result;
7394 }
7395
7396 /**
7397  *  igc_io_resume - called when traffic can start to flow again.
7398  *  @pdev: Pointer to PCI device
7399  *
7400  *  This callback is called when the error recovery driver tells us that
7401  *  its OK to resume normal operation. Implementation resembles the
7402  *  second-half of the igc_resume routine.
7403  */
7404 static void igc_io_resume(struct pci_dev *pdev)
7405 {
7406         struct net_device *netdev = pci_get_drvdata(pdev);
7407         struct igc_adapter *adapter = netdev_priv(netdev);
7408
7409         rtnl_lock();
7410         if (netif_running(netdev)) {
7411                 if (igc_open(netdev)) {
7412                         netdev_err(netdev, "igc_open failed after reset\n");
7413                         return;
7414                 }
7415         }
7416
7417         netif_device_attach(netdev);
7418
7419         /* let the f/w know that the h/w is now under the control of the
7420          * driver.
7421          */
7422         igc_get_hw_control(adapter);
7423         rtnl_unlock();
7424 }
7425
7426 static const struct pci_error_handlers igc_err_handler = {
7427         .error_detected = igc_io_error_detected,
7428         .slot_reset = igc_io_slot_reset,
7429         .resume = igc_io_resume,
7430 };
7431
7432 static _DEFINE_DEV_PM_OPS(igc_pm_ops, igc_suspend, igc_resume,
7433                           igc_runtime_suspend, igc_runtime_resume,
7434                           igc_runtime_idle);
7435
7436 static struct pci_driver igc_driver = {
7437         .name     = igc_driver_name,
7438         .id_table = igc_pci_tbl,
7439         .probe    = igc_probe,
7440         .remove   = igc_remove,
7441         .driver.pm = pm_ptr(&igc_pm_ops),
7442         .shutdown = igc_shutdown,
7443         .err_handler = &igc_err_handler,
7444 };
7445
7446 /**
7447  * igc_reinit_queues - return error
7448  * @adapter: pointer to adapter structure
7449  */
7450 int igc_reinit_queues(struct igc_adapter *adapter)
7451 {
7452         struct net_device *netdev = adapter->netdev;
7453         int err = 0;
7454
7455         if (netif_running(netdev))
7456                 igc_close(netdev);
7457
7458         igc_reset_interrupt_capability(adapter);
7459
7460         if (igc_init_interrupt_scheme(adapter, true)) {
7461                 netdev_err(netdev, "Unable to allocate memory for queues\n");
7462                 return -ENOMEM;
7463         }
7464
7465         if (netif_running(netdev))
7466                 err = igc_open(netdev);
7467
7468         return err;
7469 }
7470
7471 /**
7472  * igc_get_hw_dev - return device
7473  * @hw: pointer to hardware structure
7474  *
7475  * used by hardware layer to print debugging information
7476  */
7477 struct net_device *igc_get_hw_dev(struct igc_hw *hw)
7478 {
7479         struct igc_adapter *adapter = hw->back;
7480
7481         return adapter->netdev;
7482 }
7483
7484 static void igc_disable_rx_ring_hw(struct igc_ring *ring)
7485 {
7486         struct igc_hw *hw = &ring->q_vector->adapter->hw;
7487         u8 idx = ring->reg_idx;
7488         u32 rxdctl;
7489
7490         rxdctl = rd32(IGC_RXDCTL(idx));
7491         rxdctl &= ~IGC_RXDCTL_QUEUE_ENABLE;
7492         rxdctl |= IGC_RXDCTL_SWFLUSH;
7493         wr32(IGC_RXDCTL(idx), rxdctl);
7494 }
7495
7496 void igc_disable_rx_ring(struct igc_ring *ring)
7497 {
7498         igc_disable_rx_ring_hw(ring);
7499         igc_clean_rx_ring(ring);
7500 }
7501
7502 void igc_enable_rx_ring(struct igc_ring *ring)
7503 {
7504         struct igc_adapter *adapter = ring->q_vector->adapter;
7505
7506         igc_configure_rx_ring(adapter, ring);
7507
7508         if (ring->xsk_pool)
7509                 igc_alloc_rx_buffers_zc(ring, igc_desc_unused(ring));
7510         else
7511                 igc_alloc_rx_buffers(ring, igc_desc_unused(ring));
7512 }
7513
7514 void igc_disable_tx_ring(struct igc_ring *ring)
7515 {
7516         igc_disable_tx_ring_hw(ring);
7517         igc_clean_tx_ring(ring);
7518 }
7519
7520 void igc_enable_tx_ring(struct igc_ring *ring)
7521 {
7522         struct igc_adapter *adapter = ring->q_vector->adapter;
7523
7524         igc_configure_tx_ring(adapter, ring);
7525 }
7526
7527 /**
7528  * igc_init_module - Driver Registration Routine
7529  *
7530  * igc_init_module is the first routine called when the driver is
7531  * loaded. All it does is register with the PCI subsystem.
7532  */
7533 static int __init igc_init_module(void)
7534 {
7535         int ret;
7536
7537         pr_info("%s\n", igc_driver_string);
7538         pr_info("%s\n", igc_copyright);
7539
7540         ret = pci_register_driver(&igc_driver);
7541         return ret;
7542 }
7543
7544 module_init(igc_init_module);
7545
7546 /**
7547  * igc_exit_module - Driver Exit Cleanup Routine
7548  *
7549  * igc_exit_module is called just before the driver is removed
7550  * from memory.
7551  */
7552 static void __exit igc_exit_module(void)
7553 {
7554         pci_unregister_driver(&igc_driver);
7555 }
7556
7557 module_exit(igc_exit_module);
7558 /* igc_main.c */