drivers/net/dsa/microchip/ksz_common.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Microchip switch driver main logic
   4  *
   5  * Copyright (C) 2017-2019 Microchip Technology Inc.
   6  */
   7
   8 #include <linux/delay.h>
   9 #include <linux/dsa/ksz_common.h>
  10 #include <linux/export.h>
  11 #include <linux/gpio/consumer.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_data/microchip-ksz.h>
  15 #include <linux/phy.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/if_bridge.h>
  18 #include <linux/if_vlan.h>
  19 #include <linux/if_hsr.h>
  20 #include <linux/irq.h>
  21 #include <linux/irqdomain.h>
  22 #include <linux/of.h>
  23 #include <linux/of_mdio.h>
  24 #include <linux/of_net.h>
  25 #include <linux/micrel_phy.h>
  26 #include <net/dsa.h>
  27 #include <net/ieee8021q.h>
  28 #include <net/pkt_cls.h>
  29 #include <net/switchdev.h>
  30
  31 #include "ksz_common.h"
  32 #include "ksz_dcb.h"
  33 #include "ksz_ptp.h"
  34 #include "ksz8.h"
  35 #include "ksz9477.h"
  36 #include "lan937x.h"
  37
  38 #define MIB_COUNTER_NUM 0x20
  39
  40 struct ksz_stats_raw {
  41         u64 rx_hi;
  42         u64 rx_undersize;
  43         u64 rx_fragments;
  44         u64 rx_oversize;
  45         u64 rx_jabbers;
  46         u64 rx_symbol_err;
  47         u64 rx_crc_err;
  48         u64 rx_align_err;
  49         u64 rx_mac_ctrl;
  50         u64 rx_pause;
  51         u64 rx_bcast;
  52         u64 rx_mcast;
  53         u64 rx_ucast;
  54         u64 rx_64_or_less;
  55         u64 rx_65_127;
  56         u64 rx_128_255;
  57         u64 rx_256_511;
  58         u64 rx_512_1023;
  59         u64 rx_1024_1522;
  60         u64 rx_1523_2000;
  61         u64 rx_2001;
  62         u64 tx_hi;
  63         u64 tx_late_col;
  64         u64 tx_pause;
  65         u64 tx_bcast;
  66         u64 tx_mcast;
  67         u64 tx_ucast;
  68         u64 tx_deferred;
  69         u64 tx_total_col;
  70         u64 tx_exc_col;
  71         u64 tx_single_col;
  72         u64 tx_mult_col;
  73         u64 rx_total;
  74         u64 tx_total;
  75         u64 rx_discards;
  76         u64 tx_discards;
  77 };
  78
  79 struct ksz88xx_stats_raw {
  80         u64 rx;
  81         u64 rx_hi;
  82         u64 rx_undersize;
  83         u64 rx_fragments;
  84         u64 rx_oversize;
  85         u64 rx_jabbers;
  86         u64 rx_symbol_err;
  87         u64 rx_crc_err;
  88         u64 rx_align_err;
  89         u64 rx_mac_ctrl;
  90         u64 rx_pause;
  91         u64 rx_bcast;
  92         u64 rx_mcast;
  93         u64 rx_ucast;
  94         u64 rx_64_or_less;
  95         u64 rx_65_127;
  96         u64 rx_128_255;
  97         u64 rx_256_511;
  98         u64 rx_512_1023;
  99         u64 rx_1024_1522;
 100         u64 tx;
 101         u64 tx_hi;
 102         u64 tx_late_col;
 103         u64 tx_pause;
 104         u64 tx_bcast;
 105         u64 tx_mcast;
 106         u64 tx_ucast;
 107         u64 tx_deferred;
 108         u64 tx_total_col;
 109         u64 tx_exc_col;
 110         u64 tx_single_col;
 111         u64 tx_mult_col;
 112         u64 rx_discards;
 113         u64 tx_discards;
 114 };
 115
 116 static const struct ksz_mib_names ksz88xx_mib_names[] = {
 117         { 0x00, "rx" },
 118         { 0x01, "rx_hi" },
 119         { 0x02, "rx_undersize" },
 120         { 0x03, "rx_fragments" },
 121         { 0x04, "rx_oversize" },
 122         { 0x05, "rx_jabbers" },
 123         { 0x06, "rx_symbol_err" },
 124         { 0x07, "rx_crc_err" },
 125         { 0x08, "rx_align_err" },
 126         { 0x09, "rx_mac_ctrl" },
 127         { 0x0a, "rx_pause" },
 128         { 0x0b, "rx_bcast" },
 129         { 0x0c, "rx_mcast" },
 130         { 0x0d, "rx_ucast" },
 131         { 0x0e, "rx_64_or_less" },
 132         { 0x0f, "rx_65_127" },
 133         { 0x10, "rx_128_255" },
 134         { 0x11, "rx_256_511" },
 135         { 0x12, "rx_512_1023" },
 136         { 0x13, "rx_1024_1522" },
 137         { 0x14, "tx" },
 138         { 0x15, "tx_hi" },
 139         { 0x16, "tx_late_col" },
 140         { 0x17, "tx_pause" },
 141         { 0x18, "tx_bcast" },
 142         { 0x19, "tx_mcast" },
 143         { 0x1a, "tx_ucast" },
 144         { 0x1b, "tx_deferred" },
 145         { 0x1c, "tx_total_col" },
 146         { 0x1d, "tx_exc_col" },
 147         { 0x1e, "tx_single_col" },
 148         { 0x1f, "tx_mult_col" },
 149         { 0x100, "rx_discards" },
 150         { 0x101, "tx_discards" },
 151 };
 152
 153 static const struct ksz_mib_names ksz9477_mib_names[] = {
 154         { 0x00, "rx_hi" },
 155         { 0x01, "rx_undersize" },
 156         { 0x02, "rx_fragments" },
 157         { 0x03, "rx_oversize" },
 158         { 0x04, "rx_jabbers" },
 159         { 0x05, "rx_symbol_err" },
 160         { 0x06, "rx_crc_err" },
 161         { 0x07, "rx_align_err" },
 162         { 0x08, "rx_mac_ctrl" },
 163         { 0x09, "rx_pause" },
 164         { 0x0A, "rx_bcast" },
 165         { 0x0B, "rx_mcast" },
 166         { 0x0C, "rx_ucast" },
 167         { 0x0D, "rx_64_or_less" },
 168         { 0x0E, "rx_65_127" },
 169         { 0x0F, "rx_128_255" },
 170         { 0x10, "rx_256_511" },
 171         { 0x11, "rx_512_1023" },
 172         { 0x12, "rx_1024_1522" },
 173         { 0x13, "rx_1523_2000" },
 174         { 0x14, "rx_2001" },
 175         { 0x15, "tx_hi" },
 176         { 0x16, "tx_late_col" },
 177         { 0x17, "tx_pause" },
 178         { 0x18, "tx_bcast" },
 179         { 0x19, "tx_mcast" },
 180         { 0x1A, "tx_ucast" },
 181         { 0x1B, "tx_deferred" },
 182         { 0x1C, "tx_total_col" },
 183         { 0x1D, "tx_exc_col" },
 184         { 0x1E, "tx_single_col" },
 185         { 0x1F, "tx_mult_col" },
 186         { 0x80, "rx_total" },
 187         { 0x81, "tx_total" },
 188         { 0x82, "rx_discards" },
 189         { 0x83, "tx_discards" },
 190 };
 191
 192 struct ksz_driver_strength_prop {
 193         const char *name;
 194         int offset;
 195         int value;
 196 };
 197
 198 enum ksz_driver_strength_type {
 199         KSZ_DRIVER_STRENGTH_HI,
 200         KSZ_DRIVER_STRENGTH_LO,
 201         KSZ_DRIVER_STRENGTH_IO,
 202 };
 203
 204 /**
 205  * struct ksz_drive_strength - drive strength mapping
 206  * @reg_val:    register value
 207  * @microamp:   microamp value
 208  */
 209 struct ksz_drive_strength {
 210         u32 reg_val;
 211         u32 microamp;
 212 };
 213
 214 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants
 215  *
 216  * This values are not documented in KSZ9477 variants but confirmed by
 217  * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893
 218  * and KSZ8563 are using same register (drive strength) settings like KSZ8795.
 219  *
 220  * Documentation in KSZ8795CLX provides more information with some
 221  * recommendations:
 222  * - for high speed signals
 223  *   1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using
 224  *      2.5V or 3.3V VDDIO.
 225  *   2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with
 226  *      using 1.8V VDDIO.
 227  *   3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V
 228  *      or 3.3V VDDIO.
 229  *   4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO.
 230  *   5. In same interface, the heavy loading should use higher one of the
 231  *      drive current strength.
 232  * - for low speed signals
 233  *   1. 3.3V VDDIO, use either 4 mA or 8 mA.
 234  *   2. 2.5V VDDIO, use either 8 mA or 12 mA.
 235  *   3. 1.8V VDDIO, use either 12 mA or 16 mA.
 236  *   4. If it is heavy loading, can use higher drive current strength.
 237  */
 238 static const struct ksz_drive_strength ksz9477_drive_strengths[] = {
 239         { SW_DRIVE_STRENGTH_2MA,  2000 },
 240         { SW_DRIVE_STRENGTH_4MA,  4000 },
 241         { SW_DRIVE_STRENGTH_8MA,  8000 },
 242         { SW_DRIVE_STRENGTH_12MA, 12000 },
 243         { SW_DRIVE_STRENGTH_16MA, 16000 },
 244         { SW_DRIVE_STRENGTH_20MA, 20000 },
 245         { SW_DRIVE_STRENGTH_24MA, 24000 },
 246         { SW_DRIVE_STRENGTH_28MA, 28000 },
 247 };
 248
 249 /* ksz8830_drive_strengths - Drive strength mapping for KSZ8830, KSZ8873, ..
 250  *                           variants.
 251  * This values are documented in KSZ8873 and KSZ8863 datasheets.
 252  */
 253 static const struct ksz_drive_strength ksz8830_drive_strengths[] = {
 254         { 0,  8000 },
 255         { KSZ8873_DRIVE_STRENGTH_16MA, 16000 },
 256 };
 257
 258 static void ksz8830_phylink_mac_config(struct phylink_config *config,
 259                                        unsigned int mode,
 260                                        const struct phylink_link_state *state);
 261 static void ksz_phylink_mac_config(struct phylink_config *config,
 262                                    unsigned int mode,
 263                                    const struct phylink_link_state *state);
 264 static void ksz_phylink_mac_link_down(struct phylink_config *config,
 265                                       unsigned int mode,
 266                                       phy_interface_t interface);
 267
 268 static const struct phylink_mac_ops ksz8830_phylink_mac_ops = {
 269         .mac_config     = ksz8830_phylink_mac_config,
 270         .mac_link_down  = ksz_phylink_mac_link_down,
 271         .mac_link_up    = ksz8_phylink_mac_link_up,
 272 };
 273
 274 static const struct phylink_mac_ops ksz8_phylink_mac_ops = {
 275         .mac_config     = ksz_phylink_mac_config,
 276         .mac_link_down  = ksz_phylink_mac_link_down,
 277         .mac_link_up    = ksz8_phylink_mac_link_up,
 278 };
 279
 280 static const struct ksz_dev_ops ksz8_dev_ops = {
 281         .setup = ksz8_setup,
 282         .get_port_addr = ksz8_get_port_addr,
 283         .cfg_port_member = ksz8_cfg_port_member,
 284         .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
 285         .port_setup = ksz8_port_setup,
 286         .r_phy = ksz8_r_phy,
 287         .w_phy = ksz8_w_phy,
 288         .r_mib_cnt = ksz8_r_mib_cnt,
 289         .r_mib_pkt = ksz8_r_mib_pkt,
 290         .r_mib_stat64 = ksz88xx_r_mib_stats64,
 291         .freeze_mib = ksz8_freeze_mib,
 292         .port_init_cnt = ksz8_port_init_cnt,
 293         .fdb_dump = ksz8_fdb_dump,
 294         .fdb_add = ksz8_fdb_add,
 295         .fdb_del = ksz8_fdb_del,
 296         .mdb_add = ksz8_mdb_add,
 297         .mdb_del = ksz8_mdb_del,
 298         .vlan_filtering = ksz8_port_vlan_filtering,
 299         .vlan_add = ksz8_port_vlan_add,
 300         .vlan_del = ksz8_port_vlan_del,
 301         .mirror_add = ksz8_port_mirror_add,
 302         .mirror_del = ksz8_port_mirror_del,
 303         .get_caps = ksz8_get_caps,
 304         .config_cpu_port = ksz8_config_cpu_port,
 305         .enable_stp_addr = ksz8_enable_stp_addr,
 306         .reset = ksz8_reset_switch,
 307         .init = ksz8_switch_init,
 308         .exit = ksz8_switch_exit,
 309         .change_mtu = ksz8_change_mtu,
 310 };
 311
 312 static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
 313                                         struct phy_device *phydev,
 314                                         unsigned int mode,
 315                                         phy_interface_t interface,
 316                                         int speed, int duplex, bool tx_pause,
 317                                         bool rx_pause);
 318
 319 static const struct phylink_mac_ops ksz9477_phylink_mac_ops = {
 320         .mac_config     = ksz_phylink_mac_config,
 321         .mac_link_down  = ksz_phylink_mac_link_down,
 322         .mac_link_up    = ksz9477_phylink_mac_link_up,
 323 };
 324
 325 static const struct ksz_dev_ops ksz9477_dev_ops = {
 326         .setup = ksz9477_setup,
 327         .get_port_addr = ksz9477_get_port_addr,
 328         .cfg_port_member = ksz9477_cfg_port_member,
 329         .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
 330         .port_setup = ksz9477_port_setup,
 331         .set_ageing_time = ksz9477_set_ageing_time,
 332         .r_phy = ksz9477_r_phy,
 333         .w_phy = ksz9477_w_phy,
 334         .r_mib_cnt = ksz9477_r_mib_cnt,
 335         .r_mib_pkt = ksz9477_r_mib_pkt,
 336         .r_mib_stat64 = ksz_r_mib_stats64,
 337         .freeze_mib = ksz9477_freeze_mib,
 338         .port_init_cnt = ksz9477_port_init_cnt,
 339         .vlan_filtering = ksz9477_port_vlan_filtering,
 340         .vlan_add = ksz9477_port_vlan_add,
 341         .vlan_del = ksz9477_port_vlan_del,
 342         .mirror_add = ksz9477_port_mirror_add,
 343         .mirror_del = ksz9477_port_mirror_del,
 344         .get_caps = ksz9477_get_caps,
 345         .fdb_dump = ksz9477_fdb_dump,
 346         .fdb_add = ksz9477_fdb_add,
 347         .fdb_del = ksz9477_fdb_del,
 348         .mdb_add = ksz9477_mdb_add,
 349         .mdb_del = ksz9477_mdb_del,
 350         .change_mtu = ksz9477_change_mtu,
 351         .get_wol = ksz9477_get_wol,
 352         .set_wol = ksz9477_set_wol,
 353         .wol_pre_shutdown = ksz9477_wol_pre_shutdown,
 354         .config_cpu_port = ksz9477_config_cpu_port,
 355         .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc,
 356         .enable_stp_addr = ksz9477_enable_stp_addr,
 357         .reset = ksz9477_reset_switch,
 358         .init = ksz9477_switch_init,
 359         .exit = ksz9477_switch_exit,
 360 };
 361
 362 static const struct phylink_mac_ops lan937x_phylink_mac_ops = {
 363         .mac_config     = ksz_phylink_mac_config,
 364         .mac_link_down  = ksz_phylink_mac_link_down,
 365         .mac_link_up    = ksz9477_phylink_mac_link_up,
 366 };
 367
 368 static const struct ksz_dev_ops lan937x_dev_ops = {
 369         .setup = lan937x_setup,
 370         .teardown = lan937x_teardown,
 371         .get_port_addr = ksz9477_get_port_addr,
 372         .cfg_port_member = ksz9477_cfg_port_member,
 373         .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
 374         .port_setup = lan937x_port_setup,
 375         .set_ageing_time = lan937x_set_ageing_time,
 376         .r_phy = lan937x_r_phy,
 377         .w_phy = lan937x_w_phy,
 378         .r_mib_cnt = ksz9477_r_mib_cnt,
 379         .r_mib_pkt = ksz9477_r_mib_pkt,
 380         .r_mib_stat64 = ksz_r_mib_stats64,
 381         .freeze_mib = ksz9477_freeze_mib,
 382         .port_init_cnt = ksz9477_port_init_cnt,
 383         .vlan_filtering = ksz9477_port_vlan_filtering,
 384         .vlan_add = ksz9477_port_vlan_add,
 385         .vlan_del = ksz9477_port_vlan_del,
 386         .mirror_add = ksz9477_port_mirror_add,
 387         .mirror_del = ksz9477_port_mirror_del,
 388         .get_caps = lan937x_phylink_get_caps,
 389         .setup_rgmii_delay = lan937x_setup_rgmii_delay,
 390         .fdb_dump = ksz9477_fdb_dump,
 391         .fdb_add = ksz9477_fdb_add,
 392         .fdb_del = ksz9477_fdb_del,
 393         .mdb_add = ksz9477_mdb_add,
 394         .mdb_del = ksz9477_mdb_del,
 395         .change_mtu = lan937x_change_mtu,
 396         .config_cpu_port = lan937x_config_cpu_port,
 397         .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc,
 398         .enable_stp_addr = ksz9477_enable_stp_addr,
 399         .reset = lan937x_reset_switch,
 400         .init = lan937x_switch_init,
 401         .exit = lan937x_switch_exit,
 402 };
 403
 404 static const u16 ksz8795_regs[] = {
 405         [REG_SW_MAC_ADDR]               = 0x68,
 406         [REG_IND_CTRL_0]                = 0x6E,
 407         [REG_IND_DATA_8]                = 0x70,
 408         [REG_IND_DATA_CHECK]            = 0x72,
 409         [REG_IND_DATA_HI]               = 0x71,
 410         [REG_IND_DATA_LO]               = 0x75,
 411         [REG_IND_MIB_CHECK]             = 0x74,
 412         [REG_IND_BYTE]                  = 0xA0,
 413         [P_FORCE_CTRL]                  = 0x0C,
 414         [P_LINK_STATUS]                 = 0x0E,
 415         [P_LOCAL_CTRL]                  = 0x07,
 416         [P_NEG_RESTART_CTRL]            = 0x0D,
 417         [P_REMOTE_STATUS]               = 0x08,
 418         [P_SPEED_STATUS]                = 0x09,
 419         [S_TAIL_TAG_CTRL]               = 0x0C,
 420         [P_STP_CTRL]                    = 0x02,
 421         [S_START_CTRL]                  = 0x01,
 422         [S_BROADCAST_CTRL]              = 0x06,
 423         [S_MULTICAST_CTRL]              = 0x04,
 424         [P_XMII_CTRL_0]                 = 0x06,
 425         [P_XMII_CTRL_1]                 = 0x06,
 426 };
 427
 428 static const u32 ksz8795_masks[] = {
 429         [PORT_802_1P_REMAPPING]         = BIT(7),
 430         [SW_TAIL_TAG_ENABLE]            = BIT(1),
 431         [MIB_COUNTER_OVERFLOW]          = BIT(6),
 432         [MIB_COUNTER_VALID]             = BIT(5),
 433         [VLAN_TABLE_FID]                = GENMASK(6, 0),
 434         [VLAN_TABLE_MEMBERSHIP]         = GENMASK(11, 7),
 435         [VLAN_TABLE_VALID]              = BIT(12),
 436         [STATIC_MAC_TABLE_VALID]        = BIT(21),
 437         [STATIC_MAC_TABLE_USE_FID]      = BIT(23),
 438         [STATIC_MAC_TABLE_FID]          = GENMASK(30, 24),
 439         [STATIC_MAC_TABLE_OVERRIDE]     = BIT(22),
 440         [STATIC_MAC_TABLE_FWD_PORTS]    = GENMASK(20, 16),
 441         [DYNAMIC_MAC_TABLE_ENTRIES_H]   = GENMASK(6, 0),
 442         [DYNAMIC_MAC_TABLE_MAC_EMPTY]   = BIT(7),
 443         [DYNAMIC_MAC_TABLE_NOT_READY]   = BIT(7),
 444         [DYNAMIC_MAC_TABLE_ENTRIES]     = GENMASK(31, 29),
 445         [DYNAMIC_MAC_TABLE_FID]         = GENMASK(22, 16),
 446         [DYNAMIC_MAC_TABLE_SRC_PORT]    = GENMASK(26, 24),
 447         [DYNAMIC_MAC_TABLE_TIMESTAMP]   = GENMASK(28, 27),
 448         [P_MII_TX_FLOW_CTRL]            = BIT(5),
 449         [P_MII_RX_FLOW_CTRL]            = BIT(5),
 450 };
 451
 452 static const u8 ksz8795_xmii_ctrl0[] = {
 453         [P_MII_100MBIT]                 = 0,
 454         [P_MII_10MBIT]                  = 1,
 455         [P_MII_FULL_DUPLEX]             = 0,
 456         [P_MII_HALF_DUPLEX]             = 1,
 457 };
 458
 459 static const u8 ksz8795_xmii_ctrl1[] = {
 460         [P_RGMII_SEL]                   = 3,
 461         [P_GMII_SEL]                    = 2,
 462         [P_RMII_SEL]                    = 1,
 463         [P_MII_SEL]                     = 0,
 464         [P_GMII_1GBIT]                  = 1,
 465         [P_GMII_NOT_1GBIT]              = 0,
 466 };
 467
 468 static const u8 ksz8795_shifts[] = {
 469         [VLAN_TABLE_MEMBERSHIP_S]       = 7,
 470         [VLAN_TABLE]                    = 16,
 471         [STATIC_MAC_FWD_PORTS]          = 16,
 472         [STATIC_MAC_FID]                = 24,
 473         [DYNAMIC_MAC_ENTRIES_H]         = 3,
 474         [DYNAMIC_MAC_ENTRIES]           = 29,
 475         [DYNAMIC_MAC_FID]               = 16,
 476         [DYNAMIC_MAC_TIMESTAMP]         = 27,
 477         [DYNAMIC_MAC_SRC_PORT]          = 24,
 478 };
 479
 480 static const u16 ksz8863_regs[] = {
 481         [REG_SW_MAC_ADDR]               = 0x70,
 482         [REG_IND_CTRL_0]                = 0x79,
 483         [REG_IND_DATA_8]                = 0x7B,
 484         [REG_IND_DATA_CHECK]            = 0x7B,
 485         [REG_IND_DATA_HI]               = 0x7C,
 486         [REG_IND_DATA_LO]               = 0x80,
 487         [REG_IND_MIB_CHECK]             = 0x80,
 488         [P_FORCE_CTRL]                  = 0x0C,
 489         [P_LINK_STATUS]                 = 0x0E,
 490         [P_LOCAL_CTRL]                  = 0x0C,
 491         [P_NEG_RESTART_CTRL]            = 0x0D,
 492         [P_REMOTE_STATUS]               = 0x0E,
 493         [P_SPEED_STATUS]                = 0x0F,
 494         [S_TAIL_TAG_CTRL]               = 0x03,
 495         [P_STP_CTRL]                    = 0x02,
 496         [S_START_CTRL]                  = 0x01,
 497         [S_BROADCAST_CTRL]              = 0x06,
 498         [S_MULTICAST_CTRL]              = 0x04,
 499 };
 500
 501 static const u32 ksz8863_masks[] = {
 502         [PORT_802_1P_REMAPPING]         = BIT(3),
 503         [SW_TAIL_TAG_ENABLE]            = BIT(6),
 504         [MIB_COUNTER_OVERFLOW]          = BIT(7),
 505         [MIB_COUNTER_VALID]             = BIT(6),
 506         [VLAN_TABLE_FID]                = GENMASK(15, 12),
 507         [VLAN_TABLE_MEMBERSHIP]         = GENMASK(18, 16),
 508         [VLAN_TABLE_VALID]              = BIT(19),
 509         [STATIC_MAC_TABLE_VALID]        = BIT(19),
 510         [STATIC_MAC_TABLE_USE_FID]      = BIT(21),
 511         [STATIC_MAC_TABLE_FID]          = GENMASK(25, 22),
 512         [STATIC_MAC_TABLE_OVERRIDE]     = BIT(20),
 513         [STATIC_MAC_TABLE_FWD_PORTS]    = GENMASK(18, 16),
 514         [DYNAMIC_MAC_TABLE_ENTRIES_H]   = GENMASK(1, 0),
 515         [DYNAMIC_MAC_TABLE_MAC_EMPTY]   = BIT(2),
 516         [DYNAMIC_MAC_TABLE_NOT_READY]   = BIT(7),
 517         [DYNAMIC_MAC_TABLE_ENTRIES]     = GENMASK(31, 24),
 518         [DYNAMIC_MAC_TABLE_FID]         = GENMASK(19, 16),
 519         [DYNAMIC_MAC_TABLE_SRC_PORT]    = GENMASK(21, 20),
 520         [DYNAMIC_MAC_TABLE_TIMESTAMP]   = GENMASK(23, 22),
 521 };
 522
 523 static u8 ksz8863_shifts[] = {
 524         [VLAN_TABLE_MEMBERSHIP_S]       = 16,
 525         [STATIC_MAC_FWD_PORTS]          = 16,
 526         [STATIC_MAC_FID]                = 22,
 527         [DYNAMIC_MAC_ENTRIES_H]         = 8,
 528         [DYNAMIC_MAC_ENTRIES]           = 24,
 529         [DYNAMIC_MAC_FID]               = 16,
 530         [DYNAMIC_MAC_TIMESTAMP]         = 22,
 531         [DYNAMIC_MAC_SRC_PORT]          = 20,
 532 };
 533
 534 static const u16 ksz9477_regs[] = {
 535         [REG_SW_MAC_ADDR]               = 0x0302,
 536         [P_STP_CTRL]                    = 0x0B04,
 537         [S_START_CTRL]                  = 0x0300,
 538         [S_BROADCAST_CTRL]              = 0x0332,
 539         [S_MULTICAST_CTRL]              = 0x0331,
 540         [P_XMII_CTRL_0]                 = 0x0300,
 541         [P_XMII_CTRL_1]                 = 0x0301,
 542 };
 543
 544 static const u32 ksz9477_masks[] = {
 545         [ALU_STAT_WRITE]                = 0,
 546         [ALU_STAT_READ]                 = 1,
 547         [P_MII_TX_FLOW_CTRL]            = BIT(5),
 548         [P_MII_RX_FLOW_CTRL]            = BIT(3),
 549 };
 550
 551 static const u8 ksz9477_shifts[] = {
 552         [ALU_STAT_INDEX]                = 16,
 553 };
 554
 555 static const u8 ksz9477_xmii_ctrl0[] = {
 556         [P_MII_100MBIT]                 = 1,
 557         [P_MII_10MBIT]                  = 0,
 558         [P_MII_FULL_DUPLEX]             = 1,
 559         [P_MII_HALF_DUPLEX]             = 0,
 560 };
 561
 562 static const u8 ksz9477_xmii_ctrl1[] = {
 563         [P_RGMII_SEL]                   = 0,
 564         [P_RMII_SEL]                    = 1,
 565         [P_GMII_SEL]                    = 2,
 566         [P_MII_SEL]                     = 3,
 567         [P_GMII_1GBIT]                  = 0,
 568         [P_GMII_NOT_1GBIT]              = 1,
 569 };
 570
 571 static const u32 lan937x_masks[] = {
 572         [ALU_STAT_WRITE]                = 1,
 573         [ALU_STAT_READ]                 = 2,
 574         [P_MII_TX_FLOW_CTRL]            = BIT(5),
 575         [P_MII_RX_FLOW_CTRL]            = BIT(3),
 576 };
 577
 578 static const u8 lan937x_shifts[] = {
 579         [ALU_STAT_INDEX]                = 8,
 580 };
 581
 582 static const struct regmap_range ksz8563_valid_regs[] = {
 583         regmap_reg_range(0x0000, 0x0003),
 584         regmap_reg_range(0x0006, 0x0006),
 585         regmap_reg_range(0x000f, 0x001f),
 586         regmap_reg_range(0x0100, 0x0100),
 587         regmap_reg_range(0x0104, 0x0107),
 588         regmap_reg_range(0x010d, 0x010d),
 589         regmap_reg_range(0x0110, 0x0113),
 590         regmap_reg_range(0x0120, 0x012b),
 591         regmap_reg_range(0x0201, 0x0201),
 592         regmap_reg_range(0x0210, 0x0213),
 593         regmap_reg_range(0x0300, 0x0300),
 594         regmap_reg_range(0x0302, 0x031b),
 595         regmap_reg_range(0x0320, 0x032b),
 596         regmap_reg_range(0x0330, 0x0336),
 597         regmap_reg_range(0x0338, 0x033e),
 598         regmap_reg_range(0x0340, 0x035f),
 599         regmap_reg_range(0x0370, 0x0370),
 600         regmap_reg_range(0x0378, 0x0378),
 601         regmap_reg_range(0x037c, 0x037d),
 602         regmap_reg_range(0x0390, 0x0393),
 603         regmap_reg_range(0x0400, 0x040e),
 604         regmap_reg_range(0x0410, 0x042f),
 605         regmap_reg_range(0x0500, 0x0519),
 606         regmap_reg_range(0x0520, 0x054b),
 607         regmap_reg_range(0x0550, 0x05b3),
 608
 609         /* port 1 */
 610         regmap_reg_range(0x1000, 0x1001),
 611         regmap_reg_range(0x1004, 0x100b),
 612         regmap_reg_range(0x1013, 0x1013),
 613         regmap_reg_range(0x1017, 0x1017),
 614         regmap_reg_range(0x101b, 0x101b),
 615         regmap_reg_range(0x101f, 0x1021),
 616         regmap_reg_range(0x1030, 0x1030),
 617         regmap_reg_range(0x1100, 0x1111),
 618         regmap_reg_range(0x111a, 0x111d),
 619         regmap_reg_range(0x1122, 0x1127),
 620         regmap_reg_range(0x112a, 0x112b),
 621         regmap_reg_range(0x1136, 0x1139),
 622         regmap_reg_range(0x113e, 0x113f),
 623         regmap_reg_range(0x1400, 0x1401),
 624         regmap_reg_range(0x1403, 0x1403),
 625         regmap_reg_range(0x1410, 0x1417),
 626         regmap_reg_range(0x1420, 0x1423),
 627         regmap_reg_range(0x1500, 0x1507),
 628         regmap_reg_range(0x1600, 0x1612),
 629         regmap_reg_range(0x1800, 0x180f),
 630         regmap_reg_range(0x1900, 0x1907),
 631         regmap_reg_range(0x1914, 0x191b),
 632         regmap_reg_range(0x1a00, 0x1a03),
 633         regmap_reg_range(0x1a04, 0x1a08),
 634         regmap_reg_range(0x1b00, 0x1b01),
 635         regmap_reg_range(0x1b04, 0x1b04),
 636         regmap_reg_range(0x1c00, 0x1c05),
 637         regmap_reg_range(0x1c08, 0x1c1b),
 638
 639         /* port 2 */
 640         regmap_reg_range(0x2000, 0x2001),
 641         regmap_reg_range(0x2004, 0x200b),
 642         regmap_reg_range(0x2013, 0x2013),
 643         regmap_reg_range(0x2017, 0x2017),
 644         regmap_reg_range(0x201b, 0x201b),
 645         regmap_reg_range(0x201f, 0x2021),
 646         regmap_reg_range(0x2030, 0x2030),
 647         regmap_reg_range(0x2100, 0x2111),
 648         regmap_reg_range(0x211a, 0x211d),
 649         regmap_reg_range(0x2122, 0x2127),
 650         regmap_reg_range(0x212a, 0x212b),
 651         regmap_reg_range(0x2136, 0x2139),
 652         regmap_reg_range(0x213e, 0x213f),
 653         regmap_reg_range(0x2400, 0x2401),
 654         regmap_reg_range(0x2403, 0x2403),
 655         regmap_reg_range(0x2410, 0x2417),
 656         regmap_reg_range(0x2420, 0x2423),
 657         regmap_reg_range(0x2500, 0x2507),
 658         regmap_reg_range(0x2600, 0x2612),
 659         regmap_reg_range(0x2800, 0x280f),
 660         regmap_reg_range(0x2900, 0x2907),
 661         regmap_reg_range(0x2914, 0x291b),
 662         regmap_reg_range(0x2a00, 0x2a03),
 663         regmap_reg_range(0x2a04, 0x2a08),
 664         regmap_reg_range(0x2b00, 0x2b01),
 665         regmap_reg_range(0x2b04, 0x2b04),
 666         regmap_reg_range(0x2c00, 0x2c05),
 667         regmap_reg_range(0x2c08, 0x2c1b),
 668
 669         /* port 3 */
 670         regmap_reg_range(0x3000, 0x3001),
 671         regmap_reg_range(0x3004, 0x300b),
 672         regmap_reg_range(0x3013, 0x3013),
 673         regmap_reg_range(0x3017, 0x3017),
 674         regmap_reg_range(0x301b, 0x301b),
 675         regmap_reg_range(0x301f, 0x3021),
 676         regmap_reg_range(0x3030, 0x3030),
 677         regmap_reg_range(0x3300, 0x3301),
 678         regmap_reg_range(0x3303, 0x3303),
 679         regmap_reg_range(0x3400, 0x3401),
 680         regmap_reg_range(0x3403, 0x3403),
 681         regmap_reg_range(0x3410, 0x3417),
 682         regmap_reg_range(0x3420, 0x3423),
 683         regmap_reg_range(0x3500, 0x3507),
 684         regmap_reg_range(0x3600, 0x3612),
 685         regmap_reg_range(0x3800, 0x380f),
 686         regmap_reg_range(0x3900, 0x3907),
 687         regmap_reg_range(0x3914, 0x391b),
 688         regmap_reg_range(0x3a00, 0x3a03),
 689         regmap_reg_range(0x3a04, 0x3a08),
 690         regmap_reg_range(0x3b00, 0x3b01),
 691         regmap_reg_range(0x3b04, 0x3b04),
 692         regmap_reg_range(0x3c00, 0x3c05),
 693         regmap_reg_range(0x3c08, 0x3c1b),
 694 };
 695
 696 static const struct regmap_access_table ksz8563_register_set = {
 697         .yes_ranges = ksz8563_valid_regs,
 698         .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
 699 };
 700
 701 static const struct regmap_range ksz9477_valid_regs[] = {
 702         regmap_reg_range(0x0000, 0x0003),
 703         regmap_reg_range(0x0006, 0x0006),
 704         regmap_reg_range(0x0010, 0x001f),
 705         regmap_reg_range(0x0100, 0x0100),
 706         regmap_reg_range(0x0103, 0x0107),
 707         regmap_reg_range(0x010d, 0x010d),
 708         regmap_reg_range(0x0110, 0x0113),
 709         regmap_reg_range(0x0120, 0x012b),
 710         regmap_reg_range(0x0201, 0x0201),
 711         regmap_reg_range(0x0210, 0x0213),
 712         regmap_reg_range(0x0300, 0x0300),
 713         regmap_reg_range(0x0302, 0x031b),
 714         regmap_reg_range(0x0320, 0x032b),
 715         regmap_reg_range(0x0330, 0x0336),
 716         regmap_reg_range(0x0338, 0x033b),
 717         regmap_reg_range(0x033e, 0x033e),
 718         regmap_reg_range(0x0340, 0x035f),
 719         regmap_reg_range(0x0370, 0x0370),
 720         regmap_reg_range(0x0378, 0x0378),
 721         regmap_reg_range(0x037c, 0x037d),
 722         regmap_reg_range(0x0390, 0x0393),
 723         regmap_reg_range(0x0400, 0x040e),
 724         regmap_reg_range(0x0410, 0x042f),
 725         regmap_reg_range(0x0444, 0x044b),
 726         regmap_reg_range(0x0450, 0x046f),
 727         regmap_reg_range(0x0500, 0x0519),
 728         regmap_reg_range(0x0520, 0x054b),
 729         regmap_reg_range(0x0550, 0x05b3),
 730         regmap_reg_range(0x0604, 0x060b),
 731         regmap_reg_range(0x0610, 0x0612),
 732         regmap_reg_range(0x0614, 0x062c),
 733         regmap_reg_range(0x0640, 0x0645),
 734         regmap_reg_range(0x0648, 0x064d),
 735
 736         /* port 1 */
 737         regmap_reg_range(0x1000, 0x1001),
 738         regmap_reg_range(0x1013, 0x1013),
 739         regmap_reg_range(0x1017, 0x1017),
 740         regmap_reg_range(0x101b, 0x101b),
 741         regmap_reg_range(0x101f, 0x1020),
 742         regmap_reg_range(0x1030, 0x1030),
 743         regmap_reg_range(0x1100, 0x1115),
 744         regmap_reg_range(0x111a, 0x111f),
 745         regmap_reg_range(0x1120, 0x112b),
 746         regmap_reg_range(0x1134, 0x113b),
 747         regmap_reg_range(0x113c, 0x113f),
 748         regmap_reg_range(0x1400, 0x1401),
 749         regmap_reg_range(0x1403, 0x1403),
 750         regmap_reg_range(0x1410, 0x1417),
 751         regmap_reg_range(0x1420, 0x1423),
 752         regmap_reg_range(0x1500, 0x1507),
 753         regmap_reg_range(0x1600, 0x1613),
 754         regmap_reg_range(0x1800, 0x180f),
 755         regmap_reg_range(0x1820, 0x1827),
 756         regmap_reg_range(0x1830, 0x1837),
 757         regmap_reg_range(0x1840, 0x184b),
 758         regmap_reg_range(0x1900, 0x1907),
 759         regmap_reg_range(0x1914, 0x191b),
 760         regmap_reg_range(0x1920, 0x1920),
 761         regmap_reg_range(0x1923, 0x1927),
 762         regmap_reg_range(0x1a00, 0x1a03),
 763         regmap_reg_range(0x1a04, 0x1a07),
 764         regmap_reg_range(0x1b00, 0x1b01),
 765         regmap_reg_range(0x1b04, 0x1b04),
 766         regmap_reg_range(0x1c00, 0x1c05),
 767         regmap_reg_range(0x1c08, 0x1c1b),
 768
 769         /* port 2 */
 770         regmap_reg_range(0x2000, 0x2001),
 771         regmap_reg_range(0x2013, 0x2013),
 772         regmap_reg_range(0x2017, 0x2017),
 773         regmap_reg_range(0x201b, 0x201b),
 774         regmap_reg_range(0x201f, 0x2020),
 775         regmap_reg_range(0x2030, 0x2030),
 776         regmap_reg_range(0x2100, 0x2115),
 777         regmap_reg_range(0x211a, 0x211f),
 778         regmap_reg_range(0x2120, 0x212b),
 779         regmap_reg_range(0x2134, 0x213b),
 780         regmap_reg_range(0x213c, 0x213f),
 781         regmap_reg_range(0x2400, 0x2401),
 782         regmap_reg_range(0x2403, 0x2403),
 783         regmap_reg_range(0x2410, 0x2417),
 784         regmap_reg_range(0x2420, 0x2423),
 785         regmap_reg_range(0x2500, 0x2507),
 786         regmap_reg_range(0x2600, 0x2613),
 787         regmap_reg_range(0x2800, 0x280f),
 788         regmap_reg_range(0x2820, 0x2827),
 789         regmap_reg_range(0x2830, 0x2837),
 790         regmap_reg_range(0x2840, 0x284b),
 791         regmap_reg_range(0x2900, 0x2907),
 792         regmap_reg_range(0x2914, 0x291b),
 793         regmap_reg_range(0x2920, 0x2920),
 794         regmap_reg_range(0x2923, 0x2927),
 795         regmap_reg_range(0x2a00, 0x2a03),
 796         regmap_reg_range(0x2a04, 0x2a07),
 797         regmap_reg_range(0x2b00, 0x2b01),
 798         regmap_reg_range(0x2b04, 0x2b04),
 799         regmap_reg_range(0x2c00, 0x2c05),
 800         regmap_reg_range(0x2c08, 0x2c1b),
 801
 802         /* port 3 */
 803         regmap_reg_range(0x3000, 0x3001),
 804         regmap_reg_range(0x3013, 0x3013),
 805         regmap_reg_range(0x3017, 0x3017),
 806         regmap_reg_range(0x301b, 0x301b),
 807         regmap_reg_range(0x301f, 0x3020),
 808         regmap_reg_range(0x3030, 0x3030),
 809         regmap_reg_range(0x3100, 0x3115),
 810         regmap_reg_range(0x311a, 0x311f),
 811         regmap_reg_range(0x3120, 0x312b),
 812         regmap_reg_range(0x3134, 0x313b),
 813         regmap_reg_range(0x313c, 0x313f),
 814         regmap_reg_range(0x3400, 0x3401),
 815         regmap_reg_range(0x3403, 0x3403),
 816         regmap_reg_range(0x3410, 0x3417),
 817         regmap_reg_range(0x3420, 0x3423),
 818         regmap_reg_range(0x3500, 0x3507),
 819         regmap_reg_range(0x3600, 0x3613),
 820         regmap_reg_range(0x3800, 0x380f),
 821         regmap_reg_range(0x3820, 0x3827),
 822         regmap_reg_range(0x3830, 0x3837),
 823         regmap_reg_range(0x3840, 0x384b),
 824         regmap_reg_range(0x3900, 0x3907),
 825         regmap_reg_range(0x3914, 0x391b),
 826         regmap_reg_range(0x3920, 0x3920),
 827         regmap_reg_range(0x3923, 0x3927),
 828         regmap_reg_range(0x3a00, 0x3a03),
 829         regmap_reg_range(0x3a04, 0x3a07),
 830         regmap_reg_range(0x3b00, 0x3b01),
 831         regmap_reg_range(0x3b04, 0x3b04),
 832         regmap_reg_range(0x3c00, 0x3c05),
 833         regmap_reg_range(0x3c08, 0x3c1b),
 834
 835         /* port 4 */
 836         regmap_reg_range(0x4000, 0x4001),
 837         regmap_reg_range(0x4013, 0x4013),
 838         regmap_reg_range(0x4017, 0x4017),
 839         regmap_reg_range(0x401b, 0x401b),
 840         regmap_reg_range(0x401f, 0x4020),
 841         regmap_reg_range(0x4030, 0x4030),
 842         regmap_reg_range(0x4100, 0x4115),
 843         regmap_reg_range(0x411a, 0x411f),
 844         regmap_reg_range(0x4120, 0x412b),
 845         regmap_reg_range(0x4134, 0x413b),
 846         regmap_reg_range(0x413c, 0x413f),
 847         regmap_reg_range(0x4400, 0x4401),
 848         regmap_reg_range(0x4403, 0x4403),
 849         regmap_reg_range(0x4410, 0x4417),
 850         regmap_reg_range(0x4420, 0x4423),
 851         regmap_reg_range(0x4500, 0x4507),
 852         regmap_reg_range(0x4600, 0x4613),
 853         regmap_reg_range(0x4800, 0x480f),
 854         regmap_reg_range(0x4820, 0x4827),
 855         regmap_reg_range(0x4830, 0x4837),
 856         regmap_reg_range(0x4840, 0x484b),
 857         regmap_reg_range(0x4900, 0x4907),
 858         regmap_reg_range(0x4914, 0x491b),
 859         regmap_reg_range(0x4920, 0x4920),
 860         regmap_reg_range(0x4923, 0x4927),
 861         regmap_reg_range(0x4a00, 0x4a03),
 862         regmap_reg_range(0x4a04, 0x4a07),
 863         regmap_reg_range(0x4b00, 0x4b01),
 864         regmap_reg_range(0x4b04, 0x4b04),
 865         regmap_reg_range(0x4c00, 0x4c05),
 866         regmap_reg_range(0x4c08, 0x4c1b),
 867
 868         /* port 5 */
 869         regmap_reg_range(0x5000, 0x5001),
 870         regmap_reg_range(0x5013, 0x5013),
 871         regmap_reg_range(0x5017, 0x5017),
 872         regmap_reg_range(0x501b, 0x501b),
 873         regmap_reg_range(0x501f, 0x5020),
 874         regmap_reg_range(0x5030, 0x5030),
 875         regmap_reg_range(0x5100, 0x5115),
 876         regmap_reg_range(0x511a, 0x511f),
 877         regmap_reg_range(0x5120, 0x512b),
 878         regmap_reg_range(0x5134, 0x513b),
 879         regmap_reg_range(0x513c, 0x513f),
 880         regmap_reg_range(0x5400, 0x5401),
 881         regmap_reg_range(0x5403, 0x5403),
 882         regmap_reg_range(0x5410, 0x5417),
 883         regmap_reg_range(0x5420, 0x5423),
 884         regmap_reg_range(0x5500, 0x5507),
 885         regmap_reg_range(0x5600, 0x5613),
 886         regmap_reg_range(0x5800, 0x580f),
 887         regmap_reg_range(0x5820, 0x5827),
 888         regmap_reg_range(0x5830, 0x5837),
 889         regmap_reg_range(0x5840, 0x584b),
 890         regmap_reg_range(0x5900, 0x5907),
 891         regmap_reg_range(0x5914, 0x591b),
 892         regmap_reg_range(0x5920, 0x5920),
 893         regmap_reg_range(0x5923, 0x5927),
 894         regmap_reg_range(0x5a00, 0x5a03),
 895         regmap_reg_range(0x5a04, 0x5a07),
 896         regmap_reg_range(0x5b00, 0x5b01),
 897         regmap_reg_range(0x5b04, 0x5b04),
 898         regmap_reg_range(0x5c00, 0x5c05),
 899         regmap_reg_range(0x5c08, 0x5c1b),
 900
 901         /* port 6 */
 902         regmap_reg_range(0x6000, 0x6001),
 903         regmap_reg_range(0x6013, 0x6013),
 904         regmap_reg_range(0x6017, 0x6017),
 905         regmap_reg_range(0x601b, 0x601b),
 906         regmap_reg_range(0x601f, 0x6020),
 907         regmap_reg_range(0x6030, 0x6030),
 908         regmap_reg_range(0x6300, 0x6301),
 909         regmap_reg_range(0x6400, 0x6401),
 910         regmap_reg_range(0x6403, 0x6403),
 911         regmap_reg_range(0x6410, 0x6417),
 912         regmap_reg_range(0x6420, 0x6423),
 913         regmap_reg_range(0x6500, 0x6507),
 914         regmap_reg_range(0x6600, 0x6613),
 915         regmap_reg_range(0x6800, 0x680f),
 916         regmap_reg_range(0x6820, 0x6827),
 917         regmap_reg_range(0x6830, 0x6837),
 918         regmap_reg_range(0x6840, 0x684b),
 919         regmap_reg_range(0x6900, 0x6907),
 920         regmap_reg_range(0x6914, 0x691b),
 921         regmap_reg_range(0x6920, 0x6920),
 922         regmap_reg_range(0x6923, 0x6927),
 923         regmap_reg_range(0x6a00, 0x6a03),
 924         regmap_reg_range(0x6a04, 0x6a07),
 925         regmap_reg_range(0x6b00, 0x6b01),
 926         regmap_reg_range(0x6b04, 0x6b04),
 927         regmap_reg_range(0x6c00, 0x6c05),
 928         regmap_reg_range(0x6c08, 0x6c1b),
 929
 930         /* port 7 */
 931         regmap_reg_range(0x7000, 0x7001),
 932         regmap_reg_range(0x7013, 0x7013),
 933         regmap_reg_range(0x7017, 0x7017),
 934         regmap_reg_range(0x701b, 0x701b),
 935         regmap_reg_range(0x701f, 0x7020),
 936         regmap_reg_range(0x7030, 0x7030),
 937         regmap_reg_range(0x7200, 0x7203),
 938         regmap_reg_range(0x7206, 0x7207),
 939         regmap_reg_range(0x7300, 0x7301),
 940         regmap_reg_range(0x7400, 0x7401),
 941         regmap_reg_range(0x7403, 0x7403),
 942         regmap_reg_range(0x7410, 0x7417),
 943         regmap_reg_range(0x7420, 0x7423),
 944         regmap_reg_range(0x7500, 0x7507),
 945         regmap_reg_range(0x7600, 0x7613),
 946         regmap_reg_range(0x7800, 0x780f),
 947         regmap_reg_range(0x7820, 0x7827),
 948         regmap_reg_range(0x7830, 0x7837),
 949         regmap_reg_range(0x7840, 0x784b),
 950         regmap_reg_range(0x7900, 0x7907),
 951         regmap_reg_range(0x7914, 0x791b),
 952         regmap_reg_range(0x7920, 0x7920),
 953         regmap_reg_range(0x7923, 0x7927),
 954         regmap_reg_range(0x7a00, 0x7a03),
 955         regmap_reg_range(0x7a04, 0x7a07),
 956         regmap_reg_range(0x7b00, 0x7b01),
 957         regmap_reg_range(0x7b04, 0x7b04),
 958         regmap_reg_range(0x7c00, 0x7c05),
 959         regmap_reg_range(0x7c08, 0x7c1b),
 960 };
 961
 962 static const struct regmap_access_table ksz9477_register_set = {
 963         .yes_ranges = ksz9477_valid_regs,
 964         .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
 965 };
 966
 967 static const struct regmap_range ksz9896_valid_regs[] = {
 968         regmap_reg_range(0x0000, 0x0003),
 969         regmap_reg_range(0x0006, 0x0006),
 970         regmap_reg_range(0x0010, 0x001f),
 971         regmap_reg_range(0x0100, 0x0100),
 972         regmap_reg_range(0x0103, 0x0107),
 973         regmap_reg_range(0x010d, 0x010d),
 974         regmap_reg_range(0x0110, 0x0113),
 975         regmap_reg_range(0x0120, 0x0127),
 976         regmap_reg_range(0x0201, 0x0201),
 977         regmap_reg_range(0x0210, 0x0213),
 978         regmap_reg_range(0x0300, 0x0300),
 979         regmap_reg_range(0x0302, 0x030b),
 980         regmap_reg_range(0x0310, 0x031b),
 981         regmap_reg_range(0x0320, 0x032b),
 982         regmap_reg_range(0x0330, 0x0336),
 983         regmap_reg_range(0x0338, 0x033b),
 984         regmap_reg_range(0x033e, 0x033e),
 985         regmap_reg_range(0x0340, 0x035f),
 986         regmap_reg_range(0x0370, 0x0370),
 987         regmap_reg_range(0x0378, 0x0378),
 988         regmap_reg_range(0x037c, 0x037d),
 989         regmap_reg_range(0x0390, 0x0393),
 990         regmap_reg_range(0x0400, 0x040e),
 991         regmap_reg_range(0x0410, 0x042f),
 992
 993         /* port 1 */
 994         regmap_reg_range(0x1000, 0x1001),
 995         regmap_reg_range(0x1013, 0x1013),
 996         regmap_reg_range(0x1017, 0x1017),
 997         regmap_reg_range(0x101b, 0x101b),
 998         regmap_reg_range(0x101f, 0x1020),
 999         regmap_reg_range(0x1030, 0x1030),
1000         regmap_reg_range(0x1100, 0x1115),
1001         regmap_reg_range(0x111a, 0x111f),
1002         regmap_reg_range(0x1122, 0x1127),
1003         regmap_reg_range(0x112a, 0x112b),
1004         regmap_reg_range(0x1136, 0x1139),
1005         regmap_reg_range(0x113e, 0x113f),
1006         regmap_reg_range(0x1400, 0x1401),
1007         regmap_reg_range(0x1403, 0x1403),
1008         regmap_reg_range(0x1410, 0x1417),
1009         regmap_reg_range(0x1420, 0x1423),
1010         regmap_reg_range(0x1500, 0x1507),
1011         regmap_reg_range(0x1600, 0x1612),
1012         regmap_reg_range(0x1800, 0x180f),
1013         regmap_reg_range(0x1820, 0x1827),
1014         regmap_reg_range(0x1830, 0x1837),
1015         regmap_reg_range(0x1840, 0x184b),
1016         regmap_reg_range(0x1900, 0x1907),
1017         regmap_reg_range(0x1914, 0x1915),
1018         regmap_reg_range(0x1a00, 0x1a03),
1019         regmap_reg_range(0x1a04, 0x1a07),
1020         regmap_reg_range(0x1b00, 0x1b01),
1021         regmap_reg_range(0x1b04, 0x1b04),
1022
1023         /* port 2 */
1024         regmap_reg_range(0x2000, 0x2001),
1025         regmap_reg_range(0x2013, 0x2013),
1026         regmap_reg_range(0x2017, 0x2017),
1027         regmap_reg_range(0x201b, 0x201b),
1028         regmap_reg_range(0x201f, 0x2020),
1029         regmap_reg_range(0x2030, 0x2030),
1030         regmap_reg_range(0x2100, 0x2115),
1031         regmap_reg_range(0x211a, 0x211f),
1032         regmap_reg_range(0x2122, 0x2127),
1033         regmap_reg_range(0x212a, 0x212b),
1034         regmap_reg_range(0x2136, 0x2139),
1035         regmap_reg_range(0x213e, 0x213f),
1036         regmap_reg_range(0x2400, 0x2401),
1037         regmap_reg_range(0x2403, 0x2403),
1038         regmap_reg_range(0x2410, 0x2417),
1039         regmap_reg_range(0x2420, 0x2423),
1040         regmap_reg_range(0x2500, 0x2507),
1041         regmap_reg_range(0x2600, 0x2612),
1042         regmap_reg_range(0x2800, 0x280f),
1043         regmap_reg_range(0x2820, 0x2827),
1044         regmap_reg_range(0x2830, 0x2837),
1045         regmap_reg_range(0x2840, 0x284b),
1046         regmap_reg_range(0x2900, 0x2907),
1047         regmap_reg_range(0x2914, 0x2915),
1048         regmap_reg_range(0x2a00, 0x2a03),
1049         regmap_reg_range(0x2a04, 0x2a07),
1050         regmap_reg_range(0x2b00, 0x2b01),
1051         regmap_reg_range(0x2b04, 0x2b04),
1052
1053         /* port 3 */
1054         regmap_reg_range(0x3000, 0x3001),
1055         regmap_reg_range(0x3013, 0x3013),
1056         regmap_reg_range(0x3017, 0x3017),
1057         regmap_reg_range(0x301b, 0x301b),
1058         regmap_reg_range(0x301f, 0x3020),
1059         regmap_reg_range(0x3030, 0x3030),
1060         regmap_reg_range(0x3100, 0x3115),
1061         regmap_reg_range(0x311a, 0x311f),
1062         regmap_reg_range(0x3122, 0x3127),
1063         regmap_reg_range(0x312a, 0x312b),
1064         regmap_reg_range(0x3136, 0x3139),
1065         regmap_reg_range(0x313e, 0x313f),
1066         regmap_reg_range(0x3400, 0x3401),
1067         regmap_reg_range(0x3403, 0x3403),
1068         regmap_reg_range(0x3410, 0x3417),
1069         regmap_reg_range(0x3420, 0x3423),
1070         regmap_reg_range(0x3500, 0x3507),
1071         regmap_reg_range(0x3600, 0x3612),
1072         regmap_reg_range(0x3800, 0x380f),
1073         regmap_reg_range(0x3820, 0x3827),
1074         regmap_reg_range(0x3830, 0x3837),
1075         regmap_reg_range(0x3840, 0x384b),
1076         regmap_reg_range(0x3900, 0x3907),
1077         regmap_reg_range(0x3914, 0x3915),
1078         regmap_reg_range(0x3a00, 0x3a03),
1079         regmap_reg_range(0x3a04, 0x3a07),
1080         regmap_reg_range(0x3b00, 0x3b01),
1081         regmap_reg_range(0x3b04, 0x3b04),
1082
1083         /* port 4 */
1084         regmap_reg_range(0x4000, 0x4001),
1085         regmap_reg_range(0x4013, 0x4013),
1086         regmap_reg_range(0x4017, 0x4017),
1087         regmap_reg_range(0x401b, 0x401b),
1088         regmap_reg_range(0x401f, 0x4020),
1089         regmap_reg_range(0x4030, 0x4030),
1090         regmap_reg_range(0x4100, 0x4115),
1091         regmap_reg_range(0x411a, 0x411f),
1092         regmap_reg_range(0x4122, 0x4127),
1093         regmap_reg_range(0x412a, 0x412b),
1094         regmap_reg_range(0x4136, 0x4139),
1095         regmap_reg_range(0x413e, 0x413f),
1096         regmap_reg_range(0x4400, 0x4401),
1097         regmap_reg_range(0x4403, 0x4403),
1098         regmap_reg_range(0x4410, 0x4417),
1099         regmap_reg_range(0x4420, 0x4423),
1100         regmap_reg_range(0x4500, 0x4507),
1101         regmap_reg_range(0x4600, 0x4612),
1102         regmap_reg_range(0x4800, 0x480f),
1103         regmap_reg_range(0x4820, 0x4827),
1104         regmap_reg_range(0x4830, 0x4837),
1105         regmap_reg_range(0x4840, 0x484b),
1106         regmap_reg_range(0x4900, 0x4907),
1107         regmap_reg_range(0x4914, 0x4915),
1108         regmap_reg_range(0x4a00, 0x4a03),
1109         regmap_reg_range(0x4a04, 0x4a07),
1110         regmap_reg_range(0x4b00, 0x4b01),
1111         regmap_reg_range(0x4b04, 0x4b04),
1112
1113         /* port 5 */
1114         regmap_reg_range(0x5000, 0x5001),
1115         regmap_reg_range(0x5013, 0x5013),
1116         regmap_reg_range(0x5017, 0x5017),
1117         regmap_reg_range(0x501b, 0x501b),
1118         regmap_reg_range(0x501f, 0x5020),
1119         regmap_reg_range(0x5030, 0x5030),
1120         regmap_reg_range(0x5100, 0x5115),
1121         regmap_reg_range(0x511a, 0x511f),
1122         regmap_reg_range(0x5122, 0x5127),
1123         regmap_reg_range(0x512a, 0x512b),
1124         regmap_reg_range(0x5136, 0x5139),
1125         regmap_reg_range(0x513e, 0x513f),
1126         regmap_reg_range(0x5400, 0x5401),
1127         regmap_reg_range(0x5403, 0x5403),
1128         regmap_reg_range(0x5410, 0x5417),
1129         regmap_reg_range(0x5420, 0x5423),
1130         regmap_reg_range(0x5500, 0x5507),
1131         regmap_reg_range(0x5600, 0x5612),
1132         regmap_reg_range(0x5800, 0x580f),
1133         regmap_reg_range(0x5820, 0x5827),
1134         regmap_reg_range(0x5830, 0x5837),
1135         regmap_reg_range(0x5840, 0x584b),
1136         regmap_reg_range(0x5900, 0x5907),
1137         regmap_reg_range(0x5914, 0x5915),
1138         regmap_reg_range(0x5a00, 0x5a03),
1139         regmap_reg_range(0x5a04, 0x5a07),
1140         regmap_reg_range(0x5b00, 0x5b01),
1141         regmap_reg_range(0x5b04, 0x5b04),
1142
1143         /* port 6 */
1144         regmap_reg_range(0x6000, 0x6001),
1145         regmap_reg_range(0x6013, 0x6013),
1146         regmap_reg_range(0x6017, 0x6017),
1147         regmap_reg_range(0x601b, 0x601b),
1148         regmap_reg_range(0x601f, 0x6020),
1149         regmap_reg_range(0x6030, 0x6030),
1150         regmap_reg_range(0x6100, 0x6115),
1151         regmap_reg_range(0x611a, 0x611f),
1152         regmap_reg_range(0x6122, 0x6127),
1153         regmap_reg_range(0x612a, 0x612b),
1154         regmap_reg_range(0x6136, 0x6139),
1155         regmap_reg_range(0x613e, 0x613f),
1156         regmap_reg_range(0x6300, 0x6301),
1157         regmap_reg_range(0x6400, 0x6401),
1158         regmap_reg_range(0x6403, 0x6403),
1159         regmap_reg_range(0x6410, 0x6417),
1160         regmap_reg_range(0x6420, 0x6423),
1161         regmap_reg_range(0x6500, 0x6507),
1162         regmap_reg_range(0x6600, 0x6612),
1163         regmap_reg_range(0x6800, 0x680f),
1164         regmap_reg_range(0x6820, 0x6827),
1165         regmap_reg_range(0x6830, 0x6837),
1166         regmap_reg_range(0x6840, 0x684b),
1167         regmap_reg_range(0x6900, 0x6907),
1168         regmap_reg_range(0x6914, 0x6915),
1169         regmap_reg_range(0x6a00, 0x6a03),
1170         regmap_reg_range(0x6a04, 0x6a07),
1171         regmap_reg_range(0x6b00, 0x6b01),
1172         regmap_reg_range(0x6b04, 0x6b04),
1173 };
1174
1175 static const struct regmap_access_table ksz9896_register_set = {
1176         .yes_ranges = ksz9896_valid_regs,
1177         .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1178 };
1179
1180 static const struct regmap_range ksz8873_valid_regs[] = {
1181         regmap_reg_range(0x00, 0x01),
1182         /* global control register */
1183         regmap_reg_range(0x02, 0x0f),
1184
1185         /* port registers */
1186         regmap_reg_range(0x10, 0x1d),
1187         regmap_reg_range(0x1e, 0x1f),
1188         regmap_reg_range(0x20, 0x2d),
1189         regmap_reg_range(0x2e, 0x2f),
1190         regmap_reg_range(0x30, 0x39),
1191         regmap_reg_range(0x3f, 0x3f),
1192
1193         /* advanced control registers */
1194         regmap_reg_range(0x60, 0x6f),
1195         regmap_reg_range(0x70, 0x75),
1196         regmap_reg_range(0x76, 0x78),
1197         regmap_reg_range(0x79, 0x7a),
1198         regmap_reg_range(0x7b, 0x83),
1199         regmap_reg_range(0x8e, 0x99),
1200         regmap_reg_range(0x9a, 0xa5),
1201         regmap_reg_range(0xa6, 0xa6),
1202         regmap_reg_range(0xa7, 0xaa),
1203         regmap_reg_range(0xab, 0xae),
1204         regmap_reg_range(0xaf, 0xba),
1205         regmap_reg_range(0xbb, 0xbc),
1206         regmap_reg_range(0xbd, 0xbd),
1207         regmap_reg_range(0xc0, 0xc0),
1208         regmap_reg_range(0xc2, 0xc2),
1209         regmap_reg_range(0xc3, 0xc3),
1210         regmap_reg_range(0xc4, 0xc4),
1211         regmap_reg_range(0xc6, 0xc6),
1212 };
1213
1214 static const struct regmap_access_table ksz8873_register_set = {
1215         .yes_ranges = ksz8873_valid_regs,
1216         .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs),
1217 };
1218
1219 const struct ksz_chip_data ksz_switch_chips[] = {
1220         [KSZ8563] = {
1221                 .chip_id = KSZ8563_CHIP_ID,
1222                 .dev_name = "KSZ8563",
1223                 .num_vlans = 4096,
1224                 .num_alus = 4096,
1225                 .num_statics = 16,
1226                 .cpu_ports = 0x07,      /* can be configured as cpu port */
1227                 .port_cnt = 3,          /* total port count */
1228                 .port_nirqs = 3,
1229                 .num_tx_queues = 4,
1230                 .num_ipms = 8,
1231                 .tc_cbs_supported = true,
1232                 .ops = &ksz9477_dev_ops,
1233                 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1234                 .mib_names = ksz9477_mib_names,
1235                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1236                 .reg_mib_cnt = MIB_COUNTER_NUM,
1237                 .regs = ksz9477_regs,
1238                 .masks = ksz9477_masks,
1239                 .shifts = ksz9477_shifts,
1240                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1241                 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1242                 .supports_mii = {false, false, true},
1243                 .supports_rmii = {false, false, true},
1244                 .supports_rgmii = {false, false, true},
1245                 .internal_phy = {true, true, false},
1246                 .gbit_capable = {false, false, true},
1247                 .wr_table = &ksz8563_register_set,
1248                 .rd_table = &ksz8563_register_set,
1249         },
1250
1251         [KSZ8795] = {
1252                 .chip_id = KSZ8795_CHIP_ID,
1253                 .dev_name = "KSZ8795",
1254                 .num_vlans = 4096,
1255                 .num_alus = 0,
1256                 .num_statics = 8,
1257                 .cpu_ports = 0x10,      /* can be configured as cpu port */
1258                 .port_cnt = 5,          /* total cpu and user ports */
1259                 .num_tx_queues = 4,
1260                 .num_ipms = 4,
1261                 .ops = &ksz8_dev_ops,
1262                 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1263                 .ksz87xx_eee_link_erratum = true,
1264                 .mib_names = ksz9477_mib_names,
1265                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1266                 .reg_mib_cnt = MIB_COUNTER_NUM,
1267                 .regs = ksz8795_regs,
1268                 .masks = ksz8795_masks,
1269                 .shifts = ksz8795_shifts,
1270                 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1271                 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1272                 .supports_mii = {false, false, false, false, true},
1273                 .supports_rmii = {false, false, false, false, true},
1274                 .supports_rgmii = {false, false, false, false, true},
1275                 .internal_phy = {true, true, true, true, false},
1276         },
1277
1278         [KSZ8794] = {
1279                 /* WARNING
1280                  * =======
1281                  * KSZ8794 is similar to KSZ8795, except the port map
1282                  * contains a gap between external and CPU ports, the
1283                  * port map is NOT continuous. The per-port register
1284                  * map is shifted accordingly too, i.e. registers at
1285                  * offset 0x40 are NOT used on KSZ8794 and they ARE
1286                  * used on KSZ8795 for external port 3.
1287                  *           external  cpu
1288                  * KSZ8794   0,1,2      4
1289                  * KSZ8795   0,1,2,3    4
1290                  * KSZ8765   0,1,2,3    4
1291                  * port_cnt is configured as 5, even though it is 4
1292                  */
1293                 .chip_id = KSZ8794_CHIP_ID,
1294                 .dev_name = "KSZ8794",
1295                 .num_vlans = 4096,
1296                 .num_alus = 0,
1297                 .num_statics = 8,
1298                 .cpu_ports = 0x10,      /* can be configured as cpu port */
1299                 .port_cnt = 5,          /* total cpu and user ports */
1300                 .num_tx_queues = 4,
1301                 .num_ipms = 4,
1302                 .ops = &ksz8_dev_ops,
1303                 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1304                 .ksz87xx_eee_link_erratum = true,
1305                 .mib_names = ksz9477_mib_names,
1306                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1307                 .reg_mib_cnt = MIB_COUNTER_NUM,
1308                 .regs = ksz8795_regs,
1309                 .masks = ksz8795_masks,
1310                 .shifts = ksz8795_shifts,
1311                 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1312                 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1313                 .supports_mii = {false, false, false, false, true},
1314                 .supports_rmii = {false, false, false, false, true},
1315                 .supports_rgmii = {false, false, false, false, true},
1316                 .internal_phy = {true, true, true, false, false},
1317         },
1318
1319         [KSZ8765] = {
1320                 .chip_id = KSZ8765_CHIP_ID,
1321                 .dev_name = "KSZ8765",
1322                 .num_vlans = 4096,
1323                 .num_alus = 0,
1324                 .num_statics = 8,
1325                 .cpu_ports = 0x10,      /* can be configured as cpu port */
1326                 .port_cnt = 5,          /* total cpu and user ports */
1327                 .num_tx_queues = 4,
1328                 .num_ipms = 4,
1329                 .ops = &ksz8_dev_ops,
1330                 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1331                 .ksz87xx_eee_link_erratum = true,
1332                 .mib_names = ksz9477_mib_names,
1333                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1334                 .reg_mib_cnt = MIB_COUNTER_NUM,
1335                 .regs = ksz8795_regs,
1336                 .masks = ksz8795_masks,
1337                 .shifts = ksz8795_shifts,
1338                 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1339                 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1340                 .supports_mii = {false, false, false, false, true},
1341                 .supports_rmii = {false, false, false, false, true},
1342                 .supports_rgmii = {false, false, false, false, true},
1343                 .internal_phy = {true, true, true, true, false},
1344         },
1345
1346         [KSZ8830] = {
1347                 .chip_id = KSZ8830_CHIP_ID,
1348                 .dev_name = "KSZ8863/KSZ8873",
1349                 .num_vlans = 16,
1350                 .num_alus = 0,
1351                 .num_statics = 8,
1352                 .cpu_ports = 0x4,       /* can be configured as cpu port */
1353                 .port_cnt = 3,
1354                 .num_tx_queues = 4,
1355                 .num_ipms = 4,
1356                 .ops = &ksz8_dev_ops,
1357                 .phylink_mac_ops = &ksz8830_phylink_mac_ops,
1358                 .mib_names = ksz88xx_mib_names,
1359                 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1360                 .reg_mib_cnt = MIB_COUNTER_NUM,
1361                 .regs = ksz8863_regs,
1362                 .masks = ksz8863_masks,
1363                 .shifts = ksz8863_shifts,
1364                 .supports_mii = {false, false, true},
1365                 .supports_rmii = {false, false, true},
1366                 .internal_phy = {true, true, false},
1367                 .wr_table = &ksz8873_register_set,
1368                 .rd_table = &ksz8873_register_set,
1369         },
1370
1371         [KSZ9477] = {
1372                 .chip_id = KSZ9477_CHIP_ID,
1373                 .dev_name = "KSZ9477",
1374                 .num_vlans = 4096,
1375                 .num_alus = 4096,
1376                 .num_statics = 16,
1377                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1378                 .port_cnt = 7,          /* total physical port count */
1379                 .port_nirqs = 4,
1380                 .num_tx_queues = 4,
1381                 .num_ipms = 8,
1382                 .tc_cbs_supported = true,
1383                 .ops = &ksz9477_dev_ops,
1384                 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1385                 .phy_errata_9477 = true,
1386                 .mib_names = ksz9477_mib_names,
1387                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1388                 .reg_mib_cnt = MIB_COUNTER_NUM,
1389                 .regs = ksz9477_regs,
1390                 .masks = ksz9477_masks,
1391                 .shifts = ksz9477_shifts,
1392                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1393                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1394                 .supports_mii   = {false, false, false, false,
1395                                    false, true, false},
1396                 .supports_rmii  = {false, false, false, false,
1397                                    false, true, false},
1398                 .supports_rgmii = {false, false, false, false,
1399                                    false, true, false},
1400                 .internal_phy   = {true, true, true, true,
1401                                    true, false, false},
1402                 .gbit_capable   = {true, true, true, true, true, true, true},
1403                 .wr_table = &ksz9477_register_set,
1404                 .rd_table = &ksz9477_register_set,
1405         },
1406
1407         [KSZ9896] = {
1408                 .chip_id = KSZ9896_CHIP_ID,
1409                 .dev_name = "KSZ9896",
1410                 .num_vlans = 4096,
1411                 .num_alus = 4096,
1412                 .num_statics = 16,
1413                 .cpu_ports = 0x3F,      /* can be configured as cpu port */
1414                 .port_cnt = 6,          /* total physical port count */
1415                 .port_nirqs = 2,
1416                 .num_tx_queues = 4,
1417                 .num_ipms = 8,
1418                 .ops = &ksz9477_dev_ops,
1419                 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1420                 .phy_errata_9477 = true,
1421                 .mib_names = ksz9477_mib_names,
1422                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1423                 .reg_mib_cnt = MIB_COUNTER_NUM,
1424                 .regs = ksz9477_regs,
1425                 .masks = ksz9477_masks,
1426                 .shifts = ksz9477_shifts,
1427                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1428                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1429                 .supports_mii   = {false, false, false, false,
1430                                    false, true},
1431                 .supports_rmii  = {false, false, false, false,
1432                                    false, true},
1433                 .supports_rgmii = {false, false, false, false,
1434                                    false, true},
1435                 .internal_phy   = {true, true, true, true,
1436                                    true, false},
1437                 .gbit_capable   = {true, true, true, true, true, true},
1438                 .wr_table = &ksz9896_register_set,
1439                 .rd_table = &ksz9896_register_set,
1440         },
1441
1442         [KSZ9897] = {
1443                 .chip_id = KSZ9897_CHIP_ID,
1444                 .dev_name = "KSZ9897",
1445                 .num_vlans = 4096,
1446                 .num_alus = 4096,
1447                 .num_statics = 16,
1448                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1449                 .port_cnt = 7,          /* total physical port count */
1450                 .port_nirqs = 2,
1451                 .num_tx_queues = 4,
1452                 .num_ipms = 8,
1453                 .ops = &ksz9477_dev_ops,
1454                 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1455                 .phy_errata_9477 = true,
1456                 .mib_names = ksz9477_mib_names,
1457                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1458                 .reg_mib_cnt = MIB_COUNTER_NUM,
1459                 .regs = ksz9477_regs,
1460                 .masks = ksz9477_masks,
1461                 .shifts = ksz9477_shifts,
1462                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1463                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1464                 .supports_mii   = {false, false, false, false,
1465                                    false, true, true},
1466                 .supports_rmii  = {false, false, false, false,
1467                                    false, true, true},
1468                 .supports_rgmii = {false, false, false, false,
1469                                    false, true, true},
1470                 .internal_phy   = {true, true, true, true,
1471                                    true, false, false},
1472                 .gbit_capable   = {true, true, true, true, true, true, true},
1473         },
1474
1475         [KSZ9893] = {
1476                 .chip_id = KSZ9893_CHIP_ID,
1477                 .dev_name = "KSZ9893",
1478                 .num_vlans = 4096,
1479                 .num_alus = 4096,
1480                 .num_statics = 16,
1481                 .cpu_ports = 0x07,      /* can be configured as cpu port */
1482                 .port_cnt = 3,          /* total port count */
1483                 .port_nirqs = 2,
1484                 .num_tx_queues = 4,
1485                 .num_ipms = 8,
1486                 .ops = &ksz9477_dev_ops,
1487                 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1488                 .mib_names = ksz9477_mib_names,
1489                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1490                 .reg_mib_cnt = MIB_COUNTER_NUM,
1491                 .regs = ksz9477_regs,
1492                 .masks = ksz9477_masks,
1493                 .shifts = ksz9477_shifts,
1494                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1495                 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1496                 .supports_mii = {false, false, true},
1497                 .supports_rmii = {false, false, true},
1498                 .supports_rgmii = {false, false, true},
1499                 .internal_phy = {true, true, false},
1500                 .gbit_capable = {true, true, true},
1501         },
1502
1503         [KSZ9563] = {
1504                 .chip_id = KSZ9563_CHIP_ID,
1505                 .dev_name = "KSZ9563",
1506                 .num_vlans = 4096,
1507                 .num_alus = 4096,
1508                 .num_statics = 16,
1509                 .cpu_ports = 0x07,      /* can be configured as cpu port */
1510                 .port_cnt = 3,          /* total port count */
1511                 .port_nirqs = 3,
1512                 .num_tx_queues = 4,
1513                 .num_ipms = 8,
1514                 .tc_cbs_supported = true,
1515                 .ops = &ksz9477_dev_ops,
1516                 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1517                 .mib_names = ksz9477_mib_names,
1518                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1519                 .reg_mib_cnt = MIB_COUNTER_NUM,
1520                 .regs = ksz9477_regs,
1521                 .masks = ksz9477_masks,
1522                 .shifts = ksz9477_shifts,
1523                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1524                 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1525                 .supports_mii = {false, false, true},
1526                 .supports_rmii = {false, false, true},
1527                 .supports_rgmii = {false, false, true},
1528                 .internal_phy = {true, true, false},
1529                 .gbit_capable = {true, true, true},
1530         },
1531
1532         [KSZ8567] = {
1533                 .chip_id = KSZ8567_CHIP_ID,
1534                 .dev_name = "KSZ8567",
1535                 .num_vlans = 4096,
1536                 .num_alus = 4096,
1537                 .num_statics = 16,
1538                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1539                 .port_cnt = 7,          /* total port count */
1540                 .port_nirqs = 3,
1541                 .num_tx_queues = 4,
1542                 .num_ipms = 8,
1543                 .tc_cbs_supported = true,
1544                 .ops = &ksz9477_dev_ops,
1545                 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1546                 .phy_errata_9477 = true,
1547                 .mib_names = ksz9477_mib_names,
1548                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1549                 .reg_mib_cnt = MIB_COUNTER_NUM,
1550                 .regs = ksz9477_regs,
1551                 .masks = ksz9477_masks,
1552                 .shifts = ksz9477_shifts,
1553                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1554                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1555                 .supports_mii   = {false, false, false, false,
1556                                    false, true, true},
1557                 .supports_rmii  = {false, false, false, false,
1558                                    false, true, true},
1559                 .supports_rgmii = {false, false, false, false,
1560                                    false, true, true},
1561                 .internal_phy   = {true, true, true, true,
1562                                    true, false, false},
1563                 .gbit_capable   = {false, false, false, false, false,
1564                                    true, true},
1565         },
1566
1567         [KSZ9567] = {
1568                 .chip_id = KSZ9567_CHIP_ID,
1569                 .dev_name = "KSZ9567",
1570                 .num_vlans = 4096,
1571                 .num_alus = 4096,
1572                 .num_statics = 16,
1573                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1574                 .port_cnt = 7,          /* total physical port count */
1575                 .port_nirqs = 3,
1576                 .num_tx_queues = 4,
1577                 .num_ipms = 8,
1578                 .tc_cbs_supported = true,
1579                 .ops = &ksz9477_dev_ops,
1580                 .mib_names = ksz9477_mib_names,
1581                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1582                 .reg_mib_cnt = MIB_COUNTER_NUM,
1583                 .regs = ksz9477_regs,
1584                 .masks = ksz9477_masks,
1585                 .shifts = ksz9477_shifts,
1586                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1587                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1588                 .supports_mii   = {false, false, false, false,
1589                                    false, true, true},
1590                 .supports_rmii  = {false, false, false, false,
1591                                    false, true, true},
1592                 .supports_rgmii = {false, false, false, false,
1593                                    false, true, true},
1594                 .internal_phy   = {true, true, true, true,
1595                                    true, false, false},
1596                 .gbit_capable   = {true, true, true, true, true, true, true},
1597         },
1598
1599         [LAN9370] = {
1600                 .chip_id = LAN9370_CHIP_ID,
1601                 .dev_name = "LAN9370",
1602                 .num_vlans = 4096,
1603                 .num_alus = 1024,
1604                 .num_statics = 256,
1605                 .cpu_ports = 0x10,      /* can be configured as cpu port */
1606                 .port_cnt = 5,          /* total physical port count */
1607                 .port_nirqs = 6,
1608                 .num_tx_queues = 8,
1609                 .num_ipms = 8,
1610                 .tc_cbs_supported = true,
1611                 .ops = &lan937x_dev_ops,
1612                 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1613                 .mib_names = ksz9477_mib_names,
1614                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1615                 .reg_mib_cnt = MIB_COUNTER_NUM,
1616                 .regs = ksz9477_regs,
1617                 .masks = lan937x_masks,
1618                 .shifts = lan937x_shifts,
1619                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1620                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1621                 .supports_mii = {false, false, false, false, true},
1622                 .supports_rmii = {false, false, false, false, true},
1623                 .supports_rgmii = {false, false, false, false, true},
1624                 .internal_phy = {true, true, true, true, false},
1625         },
1626
1627         [LAN9371] = {
1628                 .chip_id = LAN9371_CHIP_ID,
1629                 .dev_name = "LAN9371",
1630                 .num_vlans = 4096,
1631                 .num_alus = 1024,
1632                 .num_statics = 256,
1633                 .cpu_ports = 0x30,      /* can be configured as cpu port */
1634                 .port_cnt = 6,          /* total physical port count */
1635                 .port_nirqs = 6,
1636                 .num_tx_queues = 8,
1637                 .num_ipms = 8,
1638                 .tc_cbs_supported = true,
1639                 .ops = &lan937x_dev_ops,
1640                 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1641                 .mib_names = ksz9477_mib_names,
1642                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1643                 .reg_mib_cnt = MIB_COUNTER_NUM,
1644                 .regs = ksz9477_regs,
1645                 .masks = lan937x_masks,
1646                 .shifts = lan937x_shifts,
1647                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1648                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1649                 .supports_mii = {false, false, false, false, true, true},
1650                 .supports_rmii = {false, false, false, false, true, true},
1651                 .supports_rgmii = {false, false, false, false, true, true},
1652                 .internal_phy = {true, true, true, true, false, false},
1653         },
1654
1655         [LAN9372] = {
1656                 .chip_id = LAN9372_CHIP_ID,
1657                 .dev_name = "LAN9372",
1658                 .num_vlans = 4096,
1659                 .num_alus = 1024,
1660                 .num_statics = 256,
1661                 .cpu_ports = 0x30,      /* can be configured as cpu port */
1662                 .port_cnt = 8,          /* total physical port count */
1663                 .port_nirqs = 6,
1664                 .num_tx_queues = 8,
1665                 .num_ipms = 8,
1666                 .tc_cbs_supported = true,
1667                 .ops = &lan937x_dev_ops,
1668                 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1669                 .mib_names = ksz9477_mib_names,
1670                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1671                 .reg_mib_cnt = MIB_COUNTER_NUM,
1672                 .regs = ksz9477_regs,
1673                 .masks = lan937x_masks,
1674                 .shifts = lan937x_shifts,
1675                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1676                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1677                 .supports_mii   = {false, false, false, false,
1678                                    true, true, false, false},
1679                 .supports_rmii  = {false, false, false, false,
1680                                    true, true, false, false},
1681                 .supports_rgmii = {false, false, false, false,
1682                                    true, true, false, false},
1683                 .internal_phy   = {true, true, true, true,
1684                                    false, false, true, true},
1685         },
1686
1687         [LAN9373] = {
1688                 .chip_id = LAN9373_CHIP_ID,
1689                 .dev_name = "LAN9373",
1690                 .num_vlans = 4096,
1691                 .num_alus = 1024,
1692                 .num_statics = 256,
1693                 .cpu_ports = 0x38,      /* can be configured as cpu port */
1694                 .port_cnt = 5,          /* total physical port count */
1695                 .port_nirqs = 6,
1696                 .num_tx_queues = 8,
1697                 .num_ipms = 8,
1698                 .tc_cbs_supported = true,
1699                 .ops = &lan937x_dev_ops,
1700                 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1701                 .mib_names = ksz9477_mib_names,
1702                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1703                 .reg_mib_cnt = MIB_COUNTER_NUM,
1704                 .regs = ksz9477_regs,
1705                 .masks = lan937x_masks,
1706                 .shifts = lan937x_shifts,
1707                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1708                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1709                 .supports_mii   = {false, false, false, false,
1710                                    true, true, false, false},
1711                 .supports_rmii  = {false, false, false, false,
1712                                    true, true, false, false},
1713                 .supports_rgmii = {false, false, false, false,
1714                                    true, true, false, false},
1715                 .internal_phy   = {true, true, true, false,
1716                                    false, false, true, true},
1717         },
1718
1719         [LAN9374] = {
1720                 .chip_id = LAN9374_CHIP_ID,
1721                 .dev_name = "LAN9374",
1722                 .num_vlans = 4096,
1723                 .num_alus = 1024,
1724                 .num_statics = 256,
1725                 .cpu_ports = 0x30,      /* can be configured as cpu port */
1726                 .port_cnt = 8,          /* total physical port count */
1727                 .port_nirqs = 6,
1728                 .num_tx_queues = 8,
1729                 .num_ipms = 8,
1730                 .tc_cbs_supported = true,
1731                 .ops = &lan937x_dev_ops,
1732                 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1733                 .mib_names = ksz9477_mib_names,
1734                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1735                 .reg_mib_cnt = MIB_COUNTER_NUM,
1736                 .regs = ksz9477_regs,
1737                 .masks = lan937x_masks,
1738                 .shifts = lan937x_shifts,
1739                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1740                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1741                 .supports_mii   = {false, false, false, false,
1742                                    true, true, false, false},
1743                 .supports_rmii  = {false, false, false, false,
1744                                    true, true, false, false},
1745                 .supports_rgmii = {false, false, false, false,
1746                                    true, true, false, false},
1747                 .internal_phy   = {true, true, true, true,
1748                                    false, false, true, true},
1749         },
1750 };
1751 EXPORT_SYMBOL_GPL(ksz_switch_chips);
1752
1753 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
1754 {
1755         int i;
1756
1757         for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1758                 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1759
1760                 if (chip->chip_id == prod_num)
1761                         return chip;
1762         }
1763
1764         return NULL;
1765 }
1766
1767 static int ksz_check_device_id(struct ksz_device *dev)
1768 {
1769         const struct ksz_chip_data *expected_chip_data;
1770         u32 expected_chip_id;
1771
1772         if (dev->pdata) {
1773                 expected_chip_id = dev->pdata->chip_id;
1774                 expected_chip_data = ksz_lookup_info(expected_chip_id);
1775                 if (WARN_ON(!expected_chip_data))
1776                         return -ENODEV;
1777         } else {
1778                 expected_chip_data = of_device_get_match_data(dev->dev);
1779                 expected_chip_id = expected_chip_data->chip_id;
1780         }
1781
1782         if (expected_chip_id != dev->chip_id) {
1783                 dev_err(dev->dev,
1784                         "Device tree specifies chip %s but found %s, please fix it!\n",
1785                         expected_chip_data->dev_name, dev->info->dev_name);
1786                 return -ENODEV;
1787         }
1788
1789         return 0;
1790 }
1791
1792 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
1793                                  struct phylink_config *config)
1794 {
1795         struct ksz_device *dev = ds->priv;
1796
1797         if (dev->info->supports_mii[port])
1798                 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1799
1800         if (dev->info->supports_rmii[port])
1801                 __set_bit(PHY_INTERFACE_MODE_RMII,
1802                           config->supported_interfaces);
1803
1804         if (dev->info->supports_rgmii[port])
1805                 phy_interface_set_rgmii(config->supported_interfaces);
1806
1807         if (dev->info->internal_phy[port]) {
1808                 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1809                           config->supported_interfaces);
1810                 /* Compatibility for phylib's default interface type when the
1811                  * phy-mode property is absent
1812                  */
1813                 __set_bit(PHY_INTERFACE_MODE_GMII,
1814                           config->supported_interfaces);
1815         }
1816
1817         if (dev->dev_ops->get_caps)
1818                 dev->dev_ops->get_caps(dev, port, config);
1819 }
1820
1821 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
1822 {
1823         struct ethtool_pause_stats *pstats;
1824         struct rtnl_link_stats64 *stats;
1825         struct ksz_stats_raw *raw;
1826         struct ksz_port_mib *mib;
1827         int ret;
1828
1829         mib = &dev->ports[port].mib;
1830         stats = &mib->stats64;
1831         pstats = &mib->pause_stats;
1832         raw = (struct ksz_stats_raw *)mib->counters;
1833
1834         spin_lock(&mib->stats64_lock);
1835
1836         stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1837                 raw->rx_pause;
1838         stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1839                 raw->tx_pause;
1840
1841         /* HW counters are counting bytes + FCS which is not acceptable
1842          * for rtnl_link_stats64 interface
1843          */
1844         stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
1845         stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
1846
1847         stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1848                 raw->rx_oversize;
1849
1850         stats->rx_crc_errors = raw->rx_crc_err;
1851         stats->rx_frame_errors = raw->rx_align_err;
1852         stats->rx_dropped = raw->rx_discards;
1853         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1854                 stats->rx_frame_errors  + stats->rx_dropped;
1855
1856         stats->tx_window_errors = raw->tx_late_col;
1857         stats->tx_fifo_errors = raw->tx_discards;
1858         stats->tx_aborted_errors = raw->tx_exc_col;
1859         stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1860                 stats->tx_aborted_errors;
1861
1862         stats->multicast = raw->rx_mcast;
1863         stats->collisions = raw->tx_total_col;
1864
1865         pstats->tx_pause_frames = raw->tx_pause;
1866         pstats->rx_pause_frames = raw->rx_pause;
1867
1868         spin_unlock(&mib->stats64_lock);
1869
1870         if (dev->info->phy_errata_9477) {
1871                 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col);
1872                 if (ret)
1873                         dev_err(dev->dev, "Failed to monitor transmission halt\n");
1874         }
1875 }
1876
1877 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
1878 {
1879         struct ethtool_pause_stats *pstats;
1880         struct rtnl_link_stats64 *stats;
1881         struct ksz88xx_stats_raw *raw;
1882         struct ksz_port_mib *mib;
1883
1884         mib = &dev->ports[port].mib;
1885         stats = &mib->stats64;
1886         pstats = &mib->pause_stats;
1887         raw = (struct ksz88xx_stats_raw *)mib->counters;
1888
1889         spin_lock(&mib->stats64_lock);
1890
1891         stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1892                 raw->rx_pause;
1893         stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1894                 raw->tx_pause;
1895
1896         /* HW counters are counting bytes + FCS which is not acceptable
1897          * for rtnl_link_stats64 interface
1898          */
1899         stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
1900         stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
1901
1902         stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1903                 raw->rx_oversize;
1904
1905         stats->rx_crc_errors = raw->rx_crc_err;
1906         stats->rx_frame_errors = raw->rx_align_err;
1907         stats->rx_dropped = raw->rx_discards;
1908         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1909                 stats->rx_frame_errors  + stats->rx_dropped;
1910
1911         stats->tx_window_errors = raw->tx_late_col;
1912         stats->tx_fifo_errors = raw->tx_discards;
1913         stats->tx_aborted_errors = raw->tx_exc_col;
1914         stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1915                 stats->tx_aborted_errors;
1916
1917         stats->multicast = raw->rx_mcast;
1918         stats->collisions = raw->tx_total_col;
1919
1920         pstats->tx_pause_frames = raw->tx_pause;
1921         pstats->rx_pause_frames = raw->rx_pause;
1922
1923         spin_unlock(&mib->stats64_lock);
1924 }
1925
1926 static void ksz_get_stats64(struct dsa_switch *ds, int port,
1927                             struct rtnl_link_stats64 *s)
1928 {
1929         struct ksz_device *dev = ds->priv;
1930         struct ksz_port_mib *mib;
1931
1932         mib = &dev->ports[port].mib;
1933
1934         spin_lock(&mib->stats64_lock);
1935         memcpy(s, &mib->stats64, sizeof(*s));
1936         spin_unlock(&mib->stats64_lock);
1937 }
1938
1939 static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
1940                                 struct ethtool_pause_stats *pause_stats)
1941 {
1942         struct ksz_device *dev = ds->priv;
1943         struct ksz_port_mib *mib;
1944
1945         mib = &dev->ports[port].mib;
1946
1947         spin_lock(&mib->stats64_lock);
1948         memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
1949         spin_unlock(&mib->stats64_lock);
1950 }
1951
1952 static void ksz_get_strings(struct dsa_switch *ds, int port,
1953                             u32 stringset, uint8_t *buf)
1954 {
1955         struct ksz_device *dev = ds->priv;
1956         int i;
1957
1958         if (stringset != ETH_SS_STATS)
1959                 return;
1960
1961         for (i = 0; i < dev->info->mib_cnt; i++) {
1962                 memcpy(buf + i * ETH_GSTRING_LEN,
1963                        dev->info->mib_names[i].string, ETH_GSTRING_LEN);
1964         }
1965 }
1966
1967 /**
1968  * ksz_update_port_member - Adjust port forwarding rules based on STP state and
1969  *                          isolation settings.
1970  * @dev: A pointer to the struct ksz_device representing the device.
1971  * @port: The port number to adjust.
1972  *
1973  * This function dynamically adjusts the port membership configuration for a
1974  * specified port and other device ports, based on Spanning Tree Protocol (STP)
1975  * states and port isolation settings. Each port, including the CPU port, has a
1976  * membership register, represented as a bitfield, where each bit corresponds
1977  * to a port number. A set bit indicates permission to forward frames to that
1978  * port. This function iterates over all ports, updating the membership register
1979  * to reflect current forwarding permissions:
1980  *
1981  * 1. Forwards frames only to ports that are part of the same bridge group and
1982  *    in the BR_STATE_FORWARDING state.
1983  * 2. Takes into account the isolation status of ports; ports in the
1984  *    BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward
1985  *    frames to each other, even if they are in the same bridge group.
1986  * 3. Ensures that the CPU port is included in the membership based on its
1987  *    upstream port configuration, allowing for management and control traffic
1988  *    to flow as required.
1989  */
1990 static void ksz_update_port_member(struct ksz_device *dev, int port)
1991 {
1992         struct ksz_port *p = &dev->ports[port];
1993         struct dsa_switch *ds = dev->ds;
1994         u8 port_member = 0, cpu_port;
1995         const struct dsa_port *dp;
1996         int i, j;
1997
1998         if (!dsa_is_user_port(ds, port))
1999                 return;
2000
2001         dp = dsa_to_port(ds, port);
2002         cpu_port = BIT(dsa_upstream_port(ds, port));
2003
2004         for (i = 0; i < ds->num_ports; i++) {
2005                 const struct dsa_port *other_dp = dsa_to_port(ds, i);
2006                 struct ksz_port *other_p = &dev->ports[i];
2007                 u8 val = 0;
2008
2009                 if (!dsa_is_user_port(ds, i))
2010                         continue;
2011                 if (port == i)
2012                         continue;
2013                 if (!dsa_port_bridge_same(dp, other_dp))
2014                         continue;
2015                 if (other_p->stp_state != BR_STATE_FORWARDING)
2016                         continue;
2017
2018                 /* At this point we know that "port" and "other" port [i] are in
2019                  * the same bridge group and that "other" port [i] is in
2020                  * forwarding stp state. If "port" is also in forwarding stp
2021                  * state, we can allow forwarding from port [port] to port [i].
2022                  * Except if both ports are isolated.
2023                  */
2024                 if (p->stp_state == BR_STATE_FORWARDING &&
2025                     !(p->isolated && other_p->isolated)) {
2026                         val |= BIT(port);
2027                         port_member |= BIT(i);
2028                 }
2029
2030                 /* Retain port [i]'s relationship to other ports than [port] */
2031                 for (j = 0; j < ds->num_ports; j++) {
2032                         const struct dsa_port *third_dp;
2033                         struct ksz_port *third_p;
2034
2035                         if (j == i)
2036                                 continue;
2037                         if (j == port)
2038                                 continue;
2039                         if (!dsa_is_user_port(ds, j))
2040                                 continue;
2041                         third_p = &dev->ports[j];
2042                         if (third_p->stp_state != BR_STATE_FORWARDING)
2043                                 continue;
2044
2045                         third_dp = dsa_to_port(ds, j);
2046
2047                         /* Now we updating relation of the "other" port [i] to
2048                          * the "third" port [j]. We already know that "other"
2049                          * port [i] is in forwarding stp state and that "third"
2050                          * port [j] is in forwarding stp state too.
2051                          * We need to check if "other" port [i] and "third" port
2052                          * [j] are in the same bridge group and not isolated
2053                          * before allowing forwarding from port [i] to port [j].
2054                          */
2055                         if (dsa_port_bridge_same(other_dp, third_dp) &&
2056                             !(other_p->isolated && third_p->isolated))
2057                                 val |= BIT(j);
2058                 }
2059
2060                 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
2061         }
2062
2063         dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
2064 }
2065
2066 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
2067 {
2068         struct ksz_device *dev = bus->priv;
2069         u16 val;
2070         int ret;
2071
2072         ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
2073         if (ret < 0)
2074                 return ret;
2075
2076         return val;
2077 }
2078
2079 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
2080                              u16 val)
2081 {
2082         struct ksz_device *dev = bus->priv;
2083
2084         return dev->dev_ops->w_phy(dev, addr, regnum, val);
2085 }
2086
2087 static int ksz_irq_phy_setup(struct ksz_device *dev)
2088 {
2089         struct dsa_switch *ds = dev->ds;
2090         int phy;
2091         int irq;
2092         int ret;
2093
2094         for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) {
2095                 if (BIT(phy) & ds->phys_mii_mask) {
2096                         irq = irq_find_mapping(dev->ports[phy].pirq.domain,
2097                                                PORT_SRC_PHY_INT);
2098                         if (irq < 0) {
2099                                 ret = irq;
2100                                 goto out;
2101                         }
2102                         ds->user_mii_bus->irq[phy] = irq;
2103                 }
2104         }
2105         return 0;
2106 out:
2107         while (phy--)
2108                 if (BIT(phy) & ds->phys_mii_mask)
2109                         irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
2110
2111         return ret;
2112 }
2113
2114 static void ksz_irq_phy_free(struct ksz_device *dev)
2115 {
2116         struct dsa_switch *ds = dev->ds;
2117         int phy;
2118
2119         for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++)
2120                 if (BIT(phy) & ds->phys_mii_mask)
2121                         irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
2122 }
2123
2124 static int ksz_mdio_register(struct ksz_device *dev)
2125 {
2126         struct dsa_switch *ds = dev->ds;
2127         struct device_node *mdio_np;
2128         struct mii_bus *bus;
2129         int ret;
2130
2131         mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
2132         if (!mdio_np)
2133                 return 0;
2134
2135         bus = devm_mdiobus_alloc(ds->dev);
2136         if (!bus) {
2137                 of_node_put(mdio_np);
2138                 return -ENOMEM;
2139         }
2140
2141         bus->priv = dev;
2142         bus->read = ksz_sw_mdio_read;
2143         bus->write = ksz_sw_mdio_write;
2144         bus->name = "ksz user smi";
2145         snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
2146         bus->parent = ds->dev;
2147         bus->phy_mask = ~ds->phys_mii_mask;
2148
2149         ds->user_mii_bus = bus;
2150
2151         if (dev->irq > 0) {
2152                 ret = ksz_irq_phy_setup(dev);
2153                 if (ret) {
2154                         of_node_put(mdio_np);
2155                         return ret;
2156                 }
2157         }
2158
2159         ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
2160         if (ret) {
2161                 dev_err(ds->dev, "unable to register MDIO bus %s\n",
2162                         bus->id);
2163                 if (dev->irq > 0)
2164                         ksz_irq_phy_free(dev);
2165         }
2166
2167         of_node_put(mdio_np);
2168
2169         return ret;
2170 }
2171
2172 static void ksz_irq_mask(struct irq_data *d)
2173 {
2174         struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2175
2176         kirq->masked |= BIT(d->hwirq);
2177 }
2178
2179 static void ksz_irq_unmask(struct irq_data *d)
2180 {
2181         struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2182
2183         kirq->masked &= ~BIT(d->hwirq);
2184 }
2185
2186 static void ksz_irq_bus_lock(struct irq_data *d)
2187 {
2188         struct ksz_irq *kirq  = irq_data_get_irq_chip_data(d);
2189
2190         mutex_lock(&kirq->dev->lock_irq);
2191 }
2192
2193 static void ksz_irq_bus_sync_unlock(struct irq_data *d)
2194 {
2195         struct ksz_irq *kirq  = irq_data_get_irq_chip_data(d);
2196         struct ksz_device *dev = kirq->dev;
2197         int ret;
2198
2199         ret = ksz_write8(dev, kirq->reg_mask, kirq->masked);
2200         if (ret)
2201                 dev_err(dev->dev, "failed to change IRQ mask\n");
2202
2203         mutex_unlock(&dev->lock_irq);
2204 }
2205
2206 static const struct irq_chip ksz_irq_chip = {
2207         .name                   = "ksz-irq",
2208         .irq_mask               = ksz_irq_mask,
2209         .irq_unmask             = ksz_irq_unmask,
2210         .irq_bus_lock           = ksz_irq_bus_lock,
2211         .irq_bus_sync_unlock    = ksz_irq_bus_sync_unlock,
2212 };
2213
2214 static int ksz_irq_domain_map(struct irq_domain *d,
2215                               unsigned int irq, irq_hw_number_t hwirq)
2216 {
2217         irq_set_chip_data(irq, d->host_data);
2218         irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq);
2219         irq_set_noprobe(irq);
2220
2221         return 0;
2222 }
2223
2224 static const struct irq_domain_ops ksz_irq_domain_ops = {
2225         .map    = ksz_irq_domain_map,
2226         .xlate  = irq_domain_xlate_twocell,
2227 };
2228
2229 static void ksz_irq_free(struct ksz_irq *kirq)
2230 {
2231         int irq, virq;
2232
2233         free_irq(kirq->irq_num, kirq);
2234
2235         for (irq = 0; irq < kirq->nirqs; irq++) {
2236                 virq = irq_find_mapping(kirq->domain, irq);
2237                 irq_dispose_mapping(virq);
2238         }
2239
2240         irq_domain_remove(kirq->domain);
2241 }
2242
2243 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
2244 {
2245         struct ksz_irq *kirq = dev_id;
2246         unsigned int nhandled = 0;
2247         struct ksz_device *dev;
2248         unsigned int sub_irq;
2249         u8 data;
2250         int ret;
2251         u8 n;
2252
2253         dev = kirq->dev;
2254
2255         /* Read interrupt status register */
2256         ret = ksz_read8(dev, kirq->reg_status, &data);
2257         if (ret)
2258                 goto out;
2259
2260         for (n = 0; n < kirq->nirqs; ++n) {
2261                 if (data & BIT(n)) {
2262                         sub_irq = irq_find_mapping(kirq->domain, n);
2263                         handle_nested_irq(sub_irq);
2264                         ++nhandled;
2265                 }
2266         }
2267 out:
2268         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
2269 }
2270
2271 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
2272 {
2273         int ret, n;
2274
2275         kirq->dev = dev;
2276         kirq->masked = ~0;
2277
2278         kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0,
2279                                              &ksz_irq_domain_ops, kirq);
2280         if (!kirq->domain)
2281                 return -ENOMEM;
2282
2283         for (n = 0; n < kirq->nirqs; n++)
2284                 irq_create_mapping(kirq->domain, n);
2285
2286         ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn,
2287                                    IRQF_ONESHOT, kirq->name, kirq);
2288         if (ret)
2289                 goto out;
2290
2291         return 0;
2292
2293 out:
2294         ksz_irq_free(kirq);
2295
2296         return ret;
2297 }
2298
2299 static int ksz_girq_setup(struct ksz_device *dev)
2300 {
2301         struct ksz_irq *girq = &dev->girq;
2302
2303         girq->nirqs = dev->info->port_cnt;
2304         girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2305         girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2306         snprintf(girq->name, sizeof(girq->name), "global_port_irq");
2307
2308         girq->irq_num = dev->irq;
2309
2310         return ksz_irq_common_setup(dev, girq);
2311 }
2312
2313 static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2314 {
2315         struct ksz_irq *pirq = &dev->ports[p].pirq;
2316
2317         pirq->nirqs = dev->info->port_nirqs;
2318         pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2319         pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2320         snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
2321
2322         pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
2323         if (pirq->irq_num < 0)
2324                 return pirq->irq_num;
2325
2326         return ksz_irq_common_setup(dev, pirq);
2327 }
2328
2329 static int ksz_parse_drive_strength(struct ksz_device *dev);
2330
2331 static int ksz_setup(struct dsa_switch *ds)
2332 {
2333         struct ksz_device *dev = ds->priv;
2334         struct dsa_port *dp;
2335         struct ksz_port *p;
2336         const u16 *regs;
2337         int ret;
2338
2339         regs = dev->info->regs;
2340
2341         dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
2342                                        dev->info->num_vlans, GFP_KERNEL);
2343         if (!dev->vlan_cache)
2344                 return -ENOMEM;
2345
2346         ret = dev->dev_ops->reset(dev);
2347         if (ret) {
2348                 dev_err(ds->dev, "failed to reset switch\n");
2349                 return ret;
2350         }
2351
2352         ret = ksz_parse_drive_strength(dev);
2353         if (ret)
2354                 return ret;
2355
2356         /* set broadcast storm protection 10% rate */
2357         regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL],
2358                            BROADCAST_STORM_RATE,
2359                            (BROADCAST_STORM_VALUE *
2360                            BROADCAST_STORM_PROT_RATE) / 100);
2361
2362         dev->dev_ops->config_cpu_port(ds);
2363
2364         dev->dev_ops->enable_stp_addr(dev);
2365
2366         ds->num_tx_queues = dev->info->num_tx_queues;
2367
2368         regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL],
2369                            MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
2370
2371         ksz_init_mib_timer(dev);
2372
2373         ds->configure_vlan_while_not_filtering = false;
2374         ds->dscp_prio_mapping_is_global = true;
2375
2376         if (dev->dev_ops->setup) {
2377                 ret = dev->dev_ops->setup(ds);
2378                 if (ret)
2379                         return ret;
2380         }
2381
2382         /* Start with learning disabled on standalone user ports, and enabled
2383          * on the CPU port. In lack of other finer mechanisms, learning on the
2384          * CPU port will avoid flooding bridge local addresses on the network
2385          * in some cases.
2386          */
2387         p = &dev->ports[dev->cpu_port];
2388         p->learning = true;
2389
2390         if (dev->irq > 0) {
2391                 ret = ksz_girq_setup(dev);
2392                 if (ret)
2393                         return ret;
2394
2395                 dsa_switch_for_each_user_port(dp, dev->ds) {
2396                         ret = ksz_pirq_setup(dev, dp->index);
2397                         if (ret)
2398                                 goto out_girq;
2399
2400                         ret = ksz_ptp_irq_setup(ds, dp->index);
2401                         if (ret)
2402                                 goto out_pirq;
2403                 }
2404         }
2405
2406         ret = ksz_ptp_clock_register(ds);
2407         if (ret) {
2408                 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret);
2409                 goto out_ptpirq;
2410         }
2411
2412         ret = ksz_mdio_register(dev);
2413         if (ret < 0) {
2414                 dev_err(dev->dev, "failed to register the mdio");
2415                 goto out_ptp_clock_unregister;
2416         }
2417
2418         ret = ksz_dcb_init(dev);
2419         if (ret)
2420                 goto out_ptp_clock_unregister;
2421
2422         /* start switch */
2423         regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL],
2424                            SW_START, SW_START);
2425
2426         return 0;
2427
2428 out_ptp_clock_unregister:
2429         ksz_ptp_clock_unregister(ds);
2430 out_ptpirq:
2431         if (dev->irq > 0)
2432                 dsa_switch_for_each_user_port(dp, dev->ds)
2433                         ksz_ptp_irq_free(ds, dp->index);
2434 out_pirq:
2435         if (dev->irq > 0)
2436                 dsa_switch_for_each_user_port(dp, dev->ds)
2437                         ksz_irq_free(&dev->ports[dp->index].pirq);
2438 out_girq:
2439         if (dev->irq > 0)
2440                 ksz_irq_free(&dev->girq);
2441
2442         return ret;
2443 }
2444
2445 static void ksz_teardown(struct dsa_switch *ds)
2446 {
2447         struct ksz_device *dev = ds->priv;
2448         struct dsa_port *dp;
2449
2450         ksz_ptp_clock_unregister(ds);
2451
2452         if (dev->irq > 0) {
2453                 dsa_switch_for_each_user_port(dp, dev->ds) {
2454                         ksz_ptp_irq_free(ds, dp->index);
2455
2456                         ksz_irq_free(&dev->ports[dp->index].pirq);
2457                 }
2458
2459                 ksz_irq_free(&dev->girq);
2460         }
2461
2462         if (dev->dev_ops->teardown)
2463                 dev->dev_ops->teardown(ds);
2464 }
2465
2466 static void port_r_cnt(struct ksz_device *dev, int port)
2467 {
2468         struct ksz_port_mib *mib = &dev->ports[port].mib;
2469         u64 *dropped;
2470
2471         /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
2472         while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
2473                 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
2474                                         &mib->counters[mib->cnt_ptr]);
2475                 ++mib->cnt_ptr;
2476         }
2477
2478         /* last one in storage */
2479         dropped = &mib->counters[dev->info->mib_cnt];
2480
2481         /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
2482         while (mib->cnt_ptr < dev->info->mib_cnt) {
2483                 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
2484                                         dropped, &mib->counters[mib->cnt_ptr]);
2485                 ++mib->cnt_ptr;
2486         }
2487         mib->cnt_ptr = 0;
2488 }
2489
2490 static void ksz_mib_read_work(struct work_struct *work)
2491 {
2492         struct ksz_device *dev = container_of(work, struct ksz_device,
2493                                               mib_read.work);
2494         struct ksz_port_mib *mib;
2495         struct ksz_port *p;
2496         int i;
2497
2498         for (i = 0; i < dev->info->port_cnt; i++) {
2499                 if (dsa_is_unused_port(dev->ds, i))
2500                         continue;
2501
2502                 p = &dev->ports[i];
2503                 mib = &p->mib;
2504                 mutex_lock(&mib->cnt_mutex);
2505
2506                 /* Only read MIB counters when the port is told to do.
2507                  * If not, read only dropped counters when link is not up.
2508                  */
2509                 if (!p->read) {
2510                         const struct dsa_port *dp = dsa_to_port(dev->ds, i);
2511
2512                         if (!netif_carrier_ok(dp->user))
2513                                 mib->cnt_ptr = dev->info->reg_mib_cnt;
2514                 }
2515                 port_r_cnt(dev, i);
2516                 p->read = false;
2517
2518                 if (dev->dev_ops->r_mib_stat64)
2519                         dev->dev_ops->r_mib_stat64(dev, i);
2520
2521                 mutex_unlock(&mib->cnt_mutex);
2522         }
2523
2524         schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
2525 }
2526
2527 void ksz_init_mib_timer(struct ksz_device *dev)
2528 {
2529         int i;
2530
2531         INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
2532
2533         for (i = 0; i < dev->info->port_cnt; i++) {
2534                 struct ksz_port_mib *mib = &dev->ports[i].mib;
2535
2536                 dev->dev_ops->port_init_cnt(dev, i);
2537
2538                 mib->cnt_ptr = 0;
2539                 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
2540         }
2541 }
2542
2543 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
2544 {
2545         struct ksz_device *dev = ds->priv;
2546         u16 val = 0xffff;
2547         int ret;
2548
2549         ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
2550         if (ret)
2551                 return ret;
2552
2553         return val;
2554 }
2555
2556 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
2557 {
2558         struct ksz_device *dev = ds->priv;
2559         int ret;
2560
2561         ret = dev->dev_ops->w_phy(dev, addr, reg, val);
2562         if (ret)
2563                 return ret;
2564
2565         return 0;
2566 }
2567
2568 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
2569 {
2570         struct ksz_device *dev = ds->priv;
2571
2572         switch (dev->chip_id) {
2573         case KSZ8830_CHIP_ID:
2574                 /* Silicon Errata Sheet (DS80000830A):
2575                  * Port 1 does not work with LinkMD Cable-Testing.
2576                  * Port 1 does not respond to received PAUSE control frames.
2577                  */
2578                 if (!port)
2579                         return MICREL_KSZ8_P1_ERRATA;
2580                 break;
2581         case KSZ8567_CHIP_ID:
2582         case KSZ9477_CHIP_ID:
2583         case KSZ9567_CHIP_ID:
2584         case KSZ9896_CHIP_ID:
2585         case KSZ9897_CHIP_ID:
2586                 /* KSZ9477 Errata DS80000754C
2587                  *
2588                  * Module 4: Energy Efficient Ethernet (EEE) feature select must
2589                  * be manually disabled
2590                  *   The EEE feature is enabled by default, but it is not fully
2591                  *   operational. It must be manually disabled through register
2592                  *   controls. If not disabled, the PHY ports can auto-negotiate
2593                  *   to enable EEE, and this feature can cause link drops when
2594                  *   linked to another device supporting EEE.
2595                  *
2596                  * The same item appears in the errata for the KSZ9567, KSZ9896,
2597                  * and KSZ9897.
2598                  *
2599                  * A similar item appears in the errata for the KSZ8567, but
2600                  * provides an alternative workaround. For now, use the simple
2601                  * workaround of disabling the EEE feature for this device too.
2602                  */
2603                 return MICREL_NO_EEE;
2604         }
2605
2606         return 0;
2607 }
2608
2609 static void ksz_phylink_mac_link_down(struct phylink_config *config,
2610                                       unsigned int mode,
2611                                       phy_interface_t interface)
2612 {
2613         struct dsa_port *dp = dsa_phylink_to_port(config);
2614         struct ksz_device *dev = dp->ds->priv;
2615
2616         /* Read all MIB counters when the link is going down. */
2617         dev->ports[dp->index].read = true;
2618         /* timer started */
2619         if (dev->mib_read_interval)
2620                 schedule_delayed_work(&dev->mib_read, 0);
2621 }
2622
2623 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
2624 {
2625         struct ksz_device *dev = ds->priv;
2626
2627         if (sset != ETH_SS_STATS)
2628                 return 0;
2629
2630         return dev->info->mib_cnt;
2631 }
2632
2633 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
2634                                   uint64_t *buf)
2635 {
2636         const struct dsa_port *dp = dsa_to_port(ds, port);
2637         struct ksz_device *dev = ds->priv;
2638         struct ksz_port_mib *mib;
2639
2640         mib = &dev->ports[port].mib;
2641         mutex_lock(&mib->cnt_mutex);
2642
2643         /* Only read dropped counters if no link. */
2644         if (!netif_carrier_ok(dp->user))
2645                 mib->cnt_ptr = dev->info->reg_mib_cnt;
2646         port_r_cnt(dev, port);
2647         memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
2648         mutex_unlock(&mib->cnt_mutex);
2649 }
2650
2651 static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
2652                                 struct dsa_bridge bridge,
2653                                 bool *tx_fwd_offload,
2654                                 struct netlink_ext_ack *extack)
2655 {
2656         /* port_stp_state_set() will be called after to put the port in
2657          * appropriate state so there is no need to do anything.
2658          */
2659
2660         return 0;
2661 }
2662
2663 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
2664                                   struct dsa_bridge bridge)
2665 {
2666         /* port_stp_state_set() will be called after to put the port in
2667          * forwarding state so there is no need to do anything.
2668          */
2669 }
2670
2671 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
2672 {
2673         struct ksz_device *dev = ds->priv;
2674
2675         dev->dev_ops->flush_dyn_mac_table(dev, port);
2676 }
2677
2678 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
2679 {
2680         struct ksz_device *dev = ds->priv;
2681
2682         if (!dev->dev_ops->set_ageing_time)
2683                 return -EOPNOTSUPP;
2684
2685         return dev->dev_ops->set_ageing_time(dev, msecs);
2686 }
2687
2688 static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
2689                             const unsigned char *addr, u16 vid,
2690                             struct dsa_db db)
2691 {
2692         struct ksz_device *dev = ds->priv;
2693
2694         if (!dev->dev_ops->fdb_add)
2695                 return -EOPNOTSUPP;
2696
2697         return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
2698 }
2699
2700 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
2701                             const unsigned char *addr,
2702                             u16 vid, struct dsa_db db)
2703 {
2704         struct ksz_device *dev = ds->priv;
2705
2706         if (!dev->dev_ops->fdb_del)
2707                 return -EOPNOTSUPP;
2708
2709         return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
2710 }
2711
2712 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
2713                              dsa_fdb_dump_cb_t *cb, void *data)
2714 {
2715         struct ksz_device *dev = ds->priv;
2716
2717         if (!dev->dev_ops->fdb_dump)
2718                 return -EOPNOTSUPP;
2719
2720         return dev->dev_ops->fdb_dump(dev, port, cb, data);
2721 }
2722
2723 static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
2724                             const struct switchdev_obj_port_mdb *mdb,
2725                             struct dsa_db db)
2726 {
2727         struct ksz_device *dev = ds->priv;
2728
2729         if (!dev->dev_ops->mdb_add)
2730                 return -EOPNOTSUPP;
2731
2732         return dev->dev_ops->mdb_add(dev, port, mdb, db);
2733 }
2734
2735 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
2736                             const struct switchdev_obj_port_mdb *mdb,
2737                             struct dsa_db db)
2738 {
2739         struct ksz_device *dev = ds->priv;
2740
2741         if (!dev->dev_ops->mdb_del)
2742                 return -EOPNOTSUPP;
2743
2744         return dev->dev_ops->mdb_del(dev, port, mdb, db);
2745 }
2746
2747 static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev,
2748                                                   int port)
2749 {
2750         u32 queue_map = 0;
2751         int ipm;
2752
2753         for (ipm = 0; ipm < dev->info->num_ipms; ipm++) {
2754                 int queue;
2755
2756                 /* Traffic Type (TT) is corresponding to the Internal Priority
2757                  * Map (IPM) in the switch. Traffic Class (TC) is
2758                  * corresponding to the queue in the switch.
2759                  */
2760                 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues);
2761                 if (queue < 0)
2762                         return queue;
2763
2764                 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S);
2765         }
2766
2767         return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
2768 }
2769
2770 static int ksz_port_setup(struct dsa_switch *ds, int port)
2771 {
2772         struct ksz_device *dev = ds->priv;
2773         int ret;
2774
2775         if (!dsa_is_user_port(ds, port))
2776                 return 0;
2777
2778         /* setup user port */
2779         dev->dev_ops->port_setup(dev, port, false);
2780
2781         if (!is_ksz8(dev)) {
2782                 ret = ksz9477_set_default_prio_queue_mapping(dev, port);
2783                 if (ret)
2784                         return ret;
2785         }
2786
2787         /* port_stp_state_set() will be called after to enable the port so
2788          * there is no need to do anything.
2789          */
2790
2791         return ksz_dcb_init_port(dev, port);
2792 }
2793
2794 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
2795 {
2796         struct ksz_device *dev = ds->priv;
2797         struct ksz_port *p;
2798         const u16 *regs;
2799         u8 data;
2800
2801         regs = dev->info->regs;
2802
2803         ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
2804         data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2805
2806         p = &dev->ports[port];
2807
2808         switch (state) {
2809         case BR_STATE_DISABLED:
2810                 data |= PORT_LEARN_DISABLE;
2811                 break;
2812         case BR_STATE_LISTENING:
2813                 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2814                 break;
2815         case BR_STATE_LEARNING:
2816                 data |= PORT_RX_ENABLE;
2817                 if (!p->learning)
2818                         data |= PORT_LEARN_DISABLE;
2819                 break;
2820         case BR_STATE_FORWARDING:
2821                 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2822                 if (!p->learning)
2823                         data |= PORT_LEARN_DISABLE;
2824                 break;
2825         case BR_STATE_BLOCKING:
2826                 data |= PORT_LEARN_DISABLE;
2827                 break;
2828         default:
2829                 dev_err(ds->dev, "invalid STP state: %d\n", state);
2830                 return;
2831         }
2832
2833         ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
2834
2835         p->stp_state = state;
2836
2837         ksz_update_port_member(dev, port);
2838 }
2839
2840 static void ksz_port_teardown(struct dsa_switch *ds, int port)
2841 {
2842         struct ksz_device *dev = ds->priv;
2843
2844         switch (dev->chip_id) {
2845         case KSZ8563_CHIP_ID:
2846         case KSZ8567_CHIP_ID:
2847         case KSZ9477_CHIP_ID:
2848         case KSZ9563_CHIP_ID:
2849         case KSZ9567_CHIP_ID:
2850         case KSZ9893_CHIP_ID:
2851         case KSZ9896_CHIP_ID:
2852         case KSZ9897_CHIP_ID:
2853                 if (dsa_is_user_port(ds, port))
2854                         ksz9477_port_acl_free(dev, port);
2855         }
2856 }
2857
2858 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2859                                      struct switchdev_brport_flags flags,
2860                                      struct netlink_ext_ack *extack)
2861 {
2862         if (flags.mask & ~(BR_LEARNING | BR_ISOLATED))
2863                 return -EINVAL;
2864
2865         return 0;
2866 }
2867
2868 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
2869                                  struct switchdev_brport_flags flags,
2870                                  struct netlink_ext_ack *extack)
2871 {
2872         struct ksz_device *dev = ds->priv;
2873         struct ksz_port *p = &dev->ports[port];
2874
2875         if (flags.mask & (BR_LEARNING | BR_ISOLATED)) {
2876                 if (flags.mask & BR_LEARNING)
2877                         p->learning = !!(flags.val & BR_LEARNING);
2878
2879                 if (flags.mask & BR_ISOLATED)
2880                         p->isolated = !!(flags.val & BR_ISOLATED);
2881
2882                 /* Make the change take effect immediately */
2883                 ksz_port_stp_state_set(ds, port, p->stp_state);
2884         }
2885
2886         return 0;
2887 }
2888
2889 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
2890                                                   int port,
2891                                                   enum dsa_tag_protocol mp)
2892 {
2893         struct ksz_device *dev = ds->priv;
2894         enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
2895
2896         if (dev->chip_id == KSZ8795_CHIP_ID ||
2897             dev->chip_id == KSZ8794_CHIP_ID ||
2898             dev->chip_id == KSZ8765_CHIP_ID)
2899                 proto = DSA_TAG_PROTO_KSZ8795;
2900
2901         if (dev->chip_id == KSZ8830_CHIP_ID ||
2902             dev->chip_id == KSZ8563_CHIP_ID ||
2903             dev->chip_id == KSZ9893_CHIP_ID ||
2904             dev->chip_id == KSZ9563_CHIP_ID)
2905                 proto = DSA_TAG_PROTO_KSZ9893;
2906
2907         if (dev->chip_id == KSZ8567_CHIP_ID ||
2908             dev->chip_id == KSZ9477_CHIP_ID ||
2909             dev->chip_id == KSZ9896_CHIP_ID ||
2910             dev->chip_id == KSZ9897_CHIP_ID ||
2911             dev->chip_id == KSZ9567_CHIP_ID)
2912                 proto = DSA_TAG_PROTO_KSZ9477;
2913
2914         if (is_lan937x(dev))
2915                 proto = DSA_TAG_PROTO_LAN937X;
2916
2917         return proto;
2918 }
2919
2920 static int ksz_connect_tag_protocol(struct dsa_switch *ds,
2921                                     enum dsa_tag_protocol proto)
2922 {
2923         struct ksz_tagger_data *tagger_data;
2924
2925         switch (proto) {
2926         case DSA_TAG_PROTO_KSZ8795:
2927                 return 0;
2928         case DSA_TAG_PROTO_KSZ9893:
2929         case DSA_TAG_PROTO_KSZ9477:
2930         case DSA_TAG_PROTO_LAN937X:
2931                 tagger_data = ksz_tagger_data(ds);
2932                 tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
2933                 return 0;
2934         default:
2935                 return -EPROTONOSUPPORT;
2936         }
2937 }
2938
2939 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
2940                                    bool flag, struct netlink_ext_ack *extack)
2941 {
2942         struct ksz_device *dev = ds->priv;
2943
2944         if (!dev->dev_ops->vlan_filtering)
2945                 return -EOPNOTSUPP;
2946
2947         return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
2948 }
2949
2950 static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
2951                              const struct switchdev_obj_port_vlan *vlan,
2952                              struct netlink_ext_ack *extack)
2953 {
2954         struct ksz_device *dev = ds->priv;
2955
2956         if (!dev->dev_ops->vlan_add)
2957                 return -EOPNOTSUPP;
2958
2959         return dev->dev_ops->vlan_add(dev, port, vlan, extack);
2960 }
2961
2962 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
2963                              const struct switchdev_obj_port_vlan *vlan)
2964 {
2965         struct ksz_device *dev = ds->priv;
2966
2967         if (!dev->dev_ops->vlan_del)
2968                 return -EOPNOTSUPP;
2969
2970         return dev->dev_ops->vlan_del(dev, port, vlan);
2971 }
2972
2973 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
2974                                struct dsa_mall_mirror_tc_entry *mirror,
2975                                bool ingress, struct netlink_ext_ack *extack)
2976 {
2977         struct ksz_device *dev = ds->priv;
2978
2979         if (!dev->dev_ops->mirror_add)
2980                 return -EOPNOTSUPP;
2981
2982         return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
2983 }
2984
2985 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
2986                                 struct dsa_mall_mirror_tc_entry *mirror)
2987 {
2988         struct ksz_device *dev = ds->priv;
2989
2990         if (dev->dev_ops->mirror_del)
2991                 dev->dev_ops->mirror_del(dev, port, mirror);
2992 }
2993
2994 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
2995 {
2996         struct ksz_device *dev = ds->priv;
2997
2998         if (!dev->dev_ops->change_mtu)
2999                 return -EOPNOTSUPP;
3000
3001         return dev->dev_ops->change_mtu(dev, port, mtu);
3002 }
3003
3004 static int ksz_max_mtu(struct dsa_switch *ds, int port)
3005 {
3006         struct ksz_device *dev = ds->priv;
3007
3008         switch (dev->chip_id) {
3009         case KSZ8795_CHIP_ID:
3010         case KSZ8794_CHIP_ID:
3011         case KSZ8765_CHIP_ID:
3012                 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3013         case KSZ8830_CHIP_ID:
3014                 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3015         case KSZ8563_CHIP_ID:
3016         case KSZ8567_CHIP_ID:
3017         case KSZ9477_CHIP_ID:
3018         case KSZ9563_CHIP_ID:
3019         case KSZ9567_CHIP_ID:
3020         case KSZ9893_CHIP_ID:
3021         case KSZ9896_CHIP_ID:
3022         case KSZ9897_CHIP_ID:
3023         case LAN9370_CHIP_ID:
3024         case LAN9371_CHIP_ID:
3025         case LAN9372_CHIP_ID:
3026         case LAN9373_CHIP_ID:
3027         case LAN9374_CHIP_ID:
3028                 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3029         }
3030
3031         return -EOPNOTSUPP;
3032 }
3033
3034 static int ksz_validate_eee(struct dsa_switch *ds, int port)
3035 {
3036         struct ksz_device *dev = ds->priv;
3037
3038         if (!dev->info->internal_phy[port])
3039                 return -EOPNOTSUPP;
3040
3041         switch (dev->chip_id) {
3042         case KSZ8563_CHIP_ID:
3043         case KSZ8567_CHIP_ID:
3044         case KSZ9477_CHIP_ID:
3045         case KSZ9563_CHIP_ID:
3046         case KSZ9567_CHIP_ID:
3047         case KSZ9893_CHIP_ID:
3048         case KSZ9896_CHIP_ID:
3049         case KSZ9897_CHIP_ID:
3050                 return 0;
3051         }
3052
3053         return -EOPNOTSUPP;
3054 }
3055
3056 static int ksz_get_mac_eee(struct dsa_switch *ds, int port,
3057                            struct ethtool_keee *e)
3058 {
3059         int ret;
3060
3061         ret = ksz_validate_eee(ds, port);
3062         if (ret)
3063                 return ret;
3064
3065         /* There is no documented control of Tx LPI configuration. */
3066         e->tx_lpi_enabled = true;
3067
3068         /* There is no documented control of Tx LPI timer. According to tests
3069          * Tx LPI timer seems to be set by default to minimal value.
3070          */
3071         e->tx_lpi_timer = 0;
3072
3073         return 0;
3074 }
3075
3076 static int ksz_set_mac_eee(struct dsa_switch *ds, int port,
3077                            struct ethtool_keee *e)
3078 {
3079         struct ksz_device *dev = ds->priv;
3080         int ret;
3081
3082         ret = ksz_validate_eee(ds, port);
3083         if (ret)
3084                 return ret;
3085
3086         if (!e->tx_lpi_enabled) {
3087                 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n");
3088                 return -EINVAL;
3089         }
3090
3091         if (e->tx_lpi_timer) {
3092                 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n");
3093                 return -EINVAL;
3094         }
3095
3096         return 0;
3097 }
3098
3099 static void ksz_set_xmii(struct ksz_device *dev, int port,
3100                          phy_interface_t interface)
3101 {
3102         const u8 *bitval = dev->info->xmii_ctrl1;
3103         struct ksz_port *p = &dev->ports[port];
3104         const u16 *regs = dev->info->regs;
3105         u8 data8;
3106
3107         ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3108
3109         data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
3110                    P_RGMII_ID_EG_ENABLE);
3111
3112         switch (interface) {
3113         case PHY_INTERFACE_MODE_MII:
3114                 data8 |= bitval[P_MII_SEL];
3115                 break;
3116         case PHY_INTERFACE_MODE_RMII:
3117                 data8 |= bitval[P_RMII_SEL];
3118                 break;
3119         case PHY_INTERFACE_MODE_GMII:
3120                 data8 |= bitval[P_GMII_SEL];
3121                 break;
3122         case PHY_INTERFACE_MODE_RGMII:
3123         case PHY_INTERFACE_MODE_RGMII_ID:
3124         case PHY_INTERFACE_MODE_RGMII_TXID:
3125         case PHY_INTERFACE_MODE_RGMII_RXID:
3126                 data8 |= bitval[P_RGMII_SEL];
3127                 /* On KSZ9893, disable RGMII in-band status support */
3128                 if (dev->chip_id == KSZ9893_CHIP_ID ||
3129                     dev->chip_id == KSZ8563_CHIP_ID ||
3130                     dev->chip_id == KSZ9563_CHIP_ID ||
3131                     is_lan937x(dev))
3132                         data8 &= ~P_MII_MAC_MODE;
3133                 break;
3134         default:
3135                 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
3136                         phy_modes(interface), port);
3137                 return;
3138         }
3139
3140         if (p->rgmii_tx_val)
3141                 data8 |= P_RGMII_ID_EG_ENABLE;
3142
3143         if (p->rgmii_rx_val)
3144                 data8 |= P_RGMII_ID_IG_ENABLE;
3145
3146         /* Write the updated value */
3147         ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
3148 }
3149
3150 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
3151 {
3152         const u8 *bitval = dev->info->xmii_ctrl1;
3153         const u16 *regs = dev->info->regs;
3154         phy_interface_t interface;
3155         u8 data8;
3156         u8 val;
3157
3158         ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3159
3160         val = FIELD_GET(P_MII_SEL_M, data8);
3161
3162         if (val == bitval[P_MII_SEL]) {
3163                 if (gbit)
3164                         interface = PHY_INTERFACE_MODE_GMII;
3165                 else
3166                         interface = PHY_INTERFACE_MODE_MII;
3167         } else if (val == bitval[P_RMII_SEL]) {
3168                 interface = PHY_INTERFACE_MODE_RMII;
3169         } else {
3170                 interface = PHY_INTERFACE_MODE_RGMII;
3171                 if (data8 & P_RGMII_ID_EG_ENABLE)
3172                         interface = PHY_INTERFACE_MODE_RGMII_TXID;
3173                 if (data8 & P_RGMII_ID_IG_ENABLE) {
3174                         interface = PHY_INTERFACE_MODE_RGMII_RXID;
3175                         if (data8 & P_RGMII_ID_EG_ENABLE)
3176                                 interface = PHY_INTERFACE_MODE_RGMII_ID;
3177                 }
3178         }
3179
3180         return interface;
3181 }
3182
3183 static void ksz8830_phylink_mac_config(struct phylink_config *config,
3184                                        unsigned int mode,
3185                                        const struct phylink_link_state *state)
3186 {
3187         struct dsa_port *dp = dsa_phylink_to_port(config);
3188         struct ksz_device *dev = dp->ds->priv;
3189
3190         dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN);
3191 }
3192
3193 static void ksz_phylink_mac_config(struct phylink_config *config,
3194                                    unsigned int mode,
3195                                    const struct phylink_link_state *state)
3196 {
3197         struct dsa_port *dp = dsa_phylink_to_port(config);
3198         struct ksz_device *dev = dp->ds->priv;
3199         int port = dp->index;
3200
3201         /* Internal PHYs */
3202         if (dev->info->internal_phy[port])
3203                 return;
3204
3205         if (phylink_autoneg_inband(mode)) {
3206                 dev_err(dev->dev, "In-band AN not supported!\n");
3207                 return;
3208         }
3209
3210         ksz_set_xmii(dev, port, state->interface);
3211
3212         if (dev->dev_ops->setup_rgmii_delay)
3213                 dev->dev_ops->setup_rgmii_delay(dev, port);
3214 }
3215
3216 bool ksz_get_gbit(struct ksz_device *dev, int port)
3217 {
3218         const u8 *bitval = dev->info->xmii_ctrl1;
3219         const u16 *regs = dev->info->regs;
3220         bool gbit = false;
3221         u8 data8;
3222         bool val;
3223
3224         ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3225
3226         val = FIELD_GET(P_GMII_1GBIT_M, data8);
3227
3228         if (val == bitval[P_GMII_1GBIT])
3229                 gbit = true;
3230
3231         return gbit;
3232 }
3233
3234 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
3235 {
3236         const u8 *bitval = dev->info->xmii_ctrl1;
3237         const u16 *regs = dev->info->regs;
3238         u8 data8;
3239
3240         ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3241
3242         data8 &= ~P_GMII_1GBIT_M;
3243
3244         if (gbit)
3245                 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
3246         else
3247                 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
3248
3249         /* Write the updated value */
3250         ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
3251 }
3252
3253 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
3254 {
3255         const u8 *bitval = dev->info->xmii_ctrl0;
3256         const u16 *regs = dev->info->regs;
3257         u8 data8;
3258
3259         ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
3260
3261         data8 &= ~P_MII_100MBIT_M;
3262
3263         if (speed == SPEED_100)
3264                 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
3265         else
3266                 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
3267
3268         /* Write the updated value */
3269         ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
3270 }
3271
3272 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
3273 {
3274         if (speed == SPEED_1000)
3275                 ksz_set_gbit(dev, port, true);
3276         else
3277                 ksz_set_gbit(dev, port, false);
3278
3279         if (speed == SPEED_100 || speed == SPEED_10)
3280                 ksz_set_100_10mbit(dev, port, speed);
3281 }
3282
3283 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
3284                                 bool tx_pause, bool rx_pause)
3285 {
3286         const u8 *bitval = dev->info->xmii_ctrl0;
3287         const u32 *masks = dev->info->masks;
3288         const u16 *regs = dev->info->regs;
3289         u8 mask;
3290         u8 val;
3291
3292         mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
3293                masks[P_MII_RX_FLOW_CTRL];
3294
3295         if (duplex == DUPLEX_FULL)
3296                 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
3297         else
3298                 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
3299
3300         if (tx_pause)
3301                 val |= masks[P_MII_TX_FLOW_CTRL];
3302
3303         if (rx_pause)
3304                 val |= masks[P_MII_RX_FLOW_CTRL];
3305
3306         ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
3307 }
3308
3309 static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
3310                                         struct phy_device *phydev,
3311                                         unsigned int mode,
3312                                         phy_interface_t interface,
3313                                         int speed, int duplex, bool tx_pause,
3314                                         bool rx_pause)
3315 {
3316         struct dsa_port *dp = dsa_phylink_to_port(config);
3317         struct ksz_device *dev = dp->ds->priv;
3318         int port = dp->index;
3319         struct ksz_port *p;
3320
3321         p = &dev->ports[port];
3322
3323         /* Internal PHYs */
3324         if (dev->info->internal_phy[port])
3325                 return;
3326
3327         p->phydev.speed = speed;
3328
3329         ksz_port_set_xmii_speed(dev, port, speed);
3330
3331         ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
3332 }
3333
3334 static int ksz_switch_detect(struct ksz_device *dev)
3335 {
3336         u8 id1, id2, id4;
3337         u16 id16;
3338         u32 id32;
3339         int ret;
3340
3341         /* read chip id */
3342         ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
3343         if (ret)
3344                 return ret;
3345
3346         id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
3347         id2 = FIELD_GET(SW_CHIP_ID_M, id16);
3348
3349         switch (id1) {
3350         case KSZ87_FAMILY_ID:
3351                 if (id2 == KSZ87_CHIP_ID_95) {
3352                         u8 val;
3353
3354                         dev->chip_id = KSZ8795_CHIP_ID;
3355
3356                         ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
3357                         if (val & KSZ8_PORT_FIBER_MODE)
3358                                 dev->chip_id = KSZ8765_CHIP_ID;
3359                 } else if (id2 == KSZ87_CHIP_ID_94) {
3360                         dev->chip_id = KSZ8794_CHIP_ID;
3361                 } else {
3362                         return -ENODEV;
3363                 }
3364                 break;
3365         case KSZ88_FAMILY_ID:
3366                 if (id2 == KSZ88_CHIP_ID_63)
3367                         dev->chip_id = KSZ8830_CHIP_ID;
3368                 else
3369                         return -ENODEV;
3370                 break;
3371         default:
3372                 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
3373                 if (ret)
3374                         return ret;
3375
3376                 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
3377                 id32 &= ~0xFF;
3378
3379                 switch (id32) {
3380                 case KSZ9477_CHIP_ID:
3381                 case KSZ9896_CHIP_ID:
3382                 case KSZ9897_CHIP_ID:
3383                 case KSZ9567_CHIP_ID:
3384                 case KSZ8567_CHIP_ID:
3385                 case LAN9370_CHIP_ID:
3386                 case LAN9371_CHIP_ID:
3387                 case LAN9372_CHIP_ID:
3388                 case LAN9373_CHIP_ID:
3389                 case LAN9374_CHIP_ID:
3390                         dev->chip_id = id32;
3391                         break;
3392                 case KSZ9893_CHIP_ID:
3393                         ret = ksz_read8(dev, REG_CHIP_ID4,
3394                                         &id4);
3395                         if (ret)
3396                                 return ret;
3397
3398                         if (id4 == SKU_ID_KSZ8563)
3399                                 dev->chip_id = KSZ8563_CHIP_ID;
3400                         else if (id4 == SKU_ID_KSZ9563)
3401                                 dev->chip_id = KSZ9563_CHIP_ID;
3402                         else
3403                                 dev->chip_id = KSZ9893_CHIP_ID;
3404
3405                         break;
3406                 default:
3407                         dev_err(dev->dev,
3408                                 "unsupported switch detected %x)\n", id32);
3409                         return -ENODEV;
3410                 }
3411         }
3412         return 0;
3413 }
3414
3415 static int ksz_cls_flower_add(struct dsa_switch *ds, int port,
3416                               struct flow_cls_offload *cls, bool ingress)
3417 {
3418         struct ksz_device *dev = ds->priv;
3419
3420         switch (dev->chip_id) {
3421         case KSZ8563_CHIP_ID:
3422         case KSZ8567_CHIP_ID:
3423         case KSZ9477_CHIP_ID:
3424         case KSZ9563_CHIP_ID:
3425         case KSZ9567_CHIP_ID:
3426         case KSZ9893_CHIP_ID:
3427         case KSZ9896_CHIP_ID:
3428         case KSZ9897_CHIP_ID:
3429                 return ksz9477_cls_flower_add(ds, port, cls, ingress);
3430         }
3431
3432         return -EOPNOTSUPP;
3433 }
3434
3435 static int ksz_cls_flower_del(struct dsa_switch *ds, int port,
3436                               struct flow_cls_offload *cls, bool ingress)
3437 {
3438         struct ksz_device *dev = ds->priv;
3439
3440         switch (dev->chip_id) {
3441         case KSZ8563_CHIP_ID:
3442         case KSZ8567_CHIP_ID:
3443         case KSZ9477_CHIP_ID:
3444         case KSZ9563_CHIP_ID:
3445         case KSZ9567_CHIP_ID:
3446         case KSZ9893_CHIP_ID:
3447         case KSZ9896_CHIP_ID:
3448         case KSZ9897_CHIP_ID:
3449                 return ksz9477_cls_flower_del(ds, port, cls, ingress);
3450         }
3451
3452         return -EOPNOTSUPP;
3453 }
3454
3455 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth
3456  * is converted to Hex-decimal using the successive multiplication method. On
3457  * every step, integer part is taken and decimal part is carry forwarded.
3458  */
3459 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw)
3460 {
3461         u32 cinc = 0;
3462         u32 txrate;
3463         u32 rate;
3464         u8 temp;
3465         u8 i;
3466
3467         txrate = idle_slope - send_slope;
3468
3469         if (!txrate)
3470                 return -EINVAL;
3471
3472         rate = idle_slope;
3473
3474         /* 24 bit register */
3475         for (i = 0; i < 6; i++) {
3476                 rate = rate * 16;
3477
3478                 temp = rate / txrate;
3479
3480                 rate %= txrate;
3481
3482                 cinc = ((cinc << 4) | temp);
3483         }
3484
3485         *bw = cinc;
3486
3487         return 0;
3488 }
3489
3490 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler,
3491                              u8 shaper)
3492 {
3493         return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
3494                            FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) |
3495                            FIELD_PREP(MTI_SHAPING_M, shaper));
3496 }
3497
3498 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
3499                             struct tc_cbs_qopt_offload *qopt)
3500 {
3501         struct ksz_device *dev = ds->priv;
3502         int ret;
3503         u32 bw;
3504
3505         if (!dev->info->tc_cbs_supported)
3506                 return -EOPNOTSUPP;
3507
3508         if (qopt->queue > dev->info->num_tx_queues)
3509                 return -EINVAL;
3510
3511         /* Queue Selection */
3512         ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue);
3513         if (ret)
3514                 return ret;
3515
3516         if (!qopt->enable)
3517                 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3518                                          MTI_SHAPING_OFF);
3519
3520         /* High Credit */
3521         ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK,
3522                            qopt->hicredit);
3523         if (ret)
3524                 return ret;
3525
3526         /* Low Credit */
3527         ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK,
3528                            qopt->locredit);
3529         if (ret)
3530                 return ret;
3531
3532         /* Credit Increment Register */
3533         ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw);
3534         if (ret)
3535                 return ret;
3536
3537         if (dev->dev_ops->tc_cbs_set_cinc) {
3538                 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw);
3539                 if (ret)
3540                         return ret;
3541         }
3542
3543         return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3544                                  MTI_SHAPING_SRP);
3545 }
3546
3547 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port)
3548 {
3549         int queue, ret;
3550
3551         /* Configuration will not take effect until the last Port Queue X
3552          * Egress Limit Control Register is written.
3553          */
3554         for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3555                 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue,
3556                                   KSZ9477_OUT_RATE_NO_LIMIT);
3557                 if (ret)
3558                         return ret;
3559         }
3560
3561         return 0;
3562 }
3563
3564 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p,
3565                                  int band)
3566 {
3567         /* Compared to queues, bands prioritize packets differently. In strict
3568          * priority mode, the lowest priority is assigned to Queue 0 while the
3569          * highest priority is given to Band 0.
3570          */
3571         return p->bands - 1 - band;
3572 }
3573
3574 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue)
3575 {
3576         int ret;
3577
3578         ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
3579         if (ret)
3580                 return ret;
3581
3582         return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3583                                  MTI_SHAPING_OFF);
3584 }
3585
3586 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue,
3587                              int weight)
3588 {
3589         int ret;
3590
3591         ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
3592         if (ret)
3593                 return ret;
3594
3595         ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3596                                 MTI_SHAPING_OFF);
3597         if (ret)
3598                 return ret;
3599
3600         return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight);
3601 }
3602
3603 static int ksz_tc_ets_add(struct ksz_device *dev, int port,
3604                           struct tc_ets_qopt_offload_replace_params *p)
3605 {
3606         int ret, band, tc_prio;
3607         u32 queue_map = 0;
3608
3609         /* In order to ensure proper prioritization, it is necessary to set the
3610          * rate limit for the related queue to zero. Otherwise strict priority
3611          * or WRR mode will not work. This is a hardware limitation.
3612          */
3613         ret = ksz_disable_egress_rate_limit(dev, port);
3614         if (ret)
3615                 return ret;
3616
3617         /* Configure queue scheduling mode for all bands. Currently only strict
3618          * prio mode is supported.
3619          */
3620         for (band = 0; band < p->bands; band++) {
3621                 int queue = ksz_ets_band_to_queue(p, band);
3622
3623                 ret = ksz_queue_set_strict(dev, port, queue);
3624                 if (ret)
3625                         return ret;
3626         }
3627
3628         /* Configure the mapping between traffic classes and queues. Note:
3629          * priomap variable support 16 traffic classes, but the chip can handle
3630          * only 8 classes.
3631          */
3632         for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) {
3633                 int queue;
3634
3635                 if (tc_prio >= dev->info->num_ipms)
3636                         break;
3637
3638                 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]);
3639                 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
3640         }
3641
3642         return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
3643 }
3644
3645 static int ksz_tc_ets_del(struct ksz_device *dev, int port)
3646 {
3647         int ret, queue;
3648
3649         /* To restore the default chip configuration, set all queues to use the
3650          * WRR scheduler with a weight of 1.
3651          */
3652         for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3653                 ret = ksz_queue_set_wrr(dev, port, queue,
3654                                         KSZ9477_DEFAULT_WRR_WEIGHT);
3655                 if (ret)
3656                         return ret;
3657         }
3658
3659         /* Revert the queue mapping for TC-priority to its default setting on
3660          * the chip.
3661          */
3662         return ksz9477_set_default_prio_queue_mapping(dev, port);
3663 }
3664
3665 static int ksz_tc_ets_validate(struct ksz_device *dev, int port,
3666                                struct tc_ets_qopt_offload_replace_params *p)
3667 {
3668         int band;
3669
3670         /* Since it is not feasible to share one port among multiple qdisc,
3671          * the user must configure all available queues appropriately.
3672          */
3673         if (p->bands != dev->info->num_tx_queues) {
3674                 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n",
3675                         dev->info->num_tx_queues);
3676                 return -EOPNOTSUPP;
3677         }
3678
3679         for (band = 0; band < p->bands; ++band) {
3680                 /* The KSZ switches utilize a weighted round robin configuration
3681                  * where a certain number of packets can be transmitted from a
3682                  * queue before the next queue is serviced. For more information
3683                  * on this, refer to section 5.2.8.4 of the KSZ8565R
3684                  * documentation on the Port Transmit Queue Control 1 Register.
3685                  * However, the current ETS Qdisc implementation (as of February
3686                  * 2023) assigns a weight to each queue based on the number of
3687                  * bytes or extrapolated bandwidth in percentages. Since this
3688                  * differs from the KSZ switches' method and we don't want to
3689                  * fake support by converting bytes to packets, it is better to
3690                  * return an error instead.
3691                  */
3692                 if (p->quanta[band]) {
3693                         dev_err(dev->dev, "Quanta/weights configuration is not supported.\n");
3694                         return -EOPNOTSUPP;
3695                 }
3696         }
3697
3698         return 0;
3699 }
3700
3701 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port,
3702                                   struct tc_ets_qopt_offload *qopt)
3703 {
3704         struct ksz_device *dev = ds->priv;
3705         int ret;
3706
3707         if (is_ksz8(dev))
3708                 return -EOPNOTSUPP;
3709
3710         if (qopt->parent != TC_H_ROOT) {
3711                 dev_err(dev->dev, "Parent should be \"root\"\n");
3712                 return -EOPNOTSUPP;
3713         }
3714
3715         switch (qopt->command) {
3716         case TC_ETS_REPLACE:
3717                 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params);
3718                 if (ret)
3719                         return ret;
3720
3721                 return ksz_tc_ets_add(dev, port, &qopt->replace_params);
3722         case TC_ETS_DESTROY:
3723                 return ksz_tc_ets_del(dev, port);
3724         case TC_ETS_STATS:
3725         case TC_ETS_GRAFT:
3726                 return -EOPNOTSUPP;
3727         }
3728
3729         return -EOPNOTSUPP;
3730 }
3731
3732 static int ksz_setup_tc(struct dsa_switch *ds, int port,
3733                         enum tc_setup_type type, void *type_data)
3734 {
3735         switch (type) {
3736         case TC_SETUP_QDISC_CBS:
3737                 return ksz_setup_tc_cbs(ds, port, type_data);
3738         case TC_SETUP_QDISC_ETS:
3739                 return ksz_tc_setup_qdisc_ets(ds, port, type_data);
3740         default:
3741                 return -EOPNOTSUPP;
3742         }
3743 }
3744
3745 static void ksz_get_wol(struct dsa_switch *ds, int port,
3746                         struct ethtool_wolinfo *wol)
3747 {
3748         struct ksz_device *dev = ds->priv;
3749
3750         if (dev->dev_ops->get_wol)
3751                 dev->dev_ops->get_wol(dev, port, wol);
3752 }
3753
3754 static int ksz_set_wol(struct dsa_switch *ds, int port,
3755                        struct ethtool_wolinfo *wol)
3756 {
3757         struct ksz_device *dev = ds->priv;
3758
3759         if (dev->dev_ops->set_wol)
3760                 return dev->dev_ops->set_wol(dev, port, wol);
3761
3762         return -EOPNOTSUPP;
3763 }
3764
3765 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port,
3766                                     const unsigned char *addr)
3767 {
3768         struct dsa_port *dp = dsa_to_port(ds, port);
3769         struct ethtool_wolinfo wol;
3770
3771         if (dp->hsr_dev) {
3772                 dev_err(ds->dev,
3773                         "Cannot change MAC address on port %d with active HSR offload\n",
3774                         port);
3775                 return -EBUSY;
3776         }
3777
3778         /* Need to initialize variable as the code to fill in settings may
3779          * not be executed.
3780          */
3781         wol.wolopts = 0;
3782
3783         ksz_get_wol(ds, dp->index, &wol);
3784         if (wol.wolopts & WAKE_MAGIC) {
3785                 dev_err(ds->dev,
3786                         "Cannot change MAC address on port %d with active Wake on Magic Packet\n",
3787                         port);
3788                 return -EBUSY;
3789         }
3790
3791         return 0;
3792 }
3793
3794 /**
3795  * ksz_is_port_mac_global_usable - Check if the MAC address on a given port
3796  *                                 can be used as a global address.
3797  * @ds: Pointer to the DSA switch structure.
3798  * @port: The port number on which the MAC address is to be checked.
3799  *
3800  * This function examines the MAC address set on the specified port and
3801  * determines if it can be used as a global address for the switch.
3802  *
3803  * Return: true if the port's MAC address can be used as a global address, false
3804  * otherwise.
3805  */
3806 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port)
3807 {
3808         struct net_device *user = dsa_to_port(ds, port)->user;
3809         const unsigned char *addr = user->dev_addr;
3810         struct ksz_switch_macaddr *switch_macaddr;
3811         struct ksz_device *dev = ds->priv;
3812
3813         ASSERT_RTNL();
3814
3815         switch_macaddr = dev->switch_macaddr;
3816         if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr))
3817                 return false;
3818
3819         return true;
3820 }
3821
3822 /**
3823  * ksz_switch_macaddr_get - Program the switch's MAC address register.
3824  * @ds: DSA switch instance.
3825  * @port: Port number.
3826  * @extack: Netlink extended acknowledgment.
3827  *
3828  * This function programs the switch's MAC address register with the MAC address
3829  * of the requesting user port. This single address is used by the switch for
3830  * multiple features like HSR self-address filtering and WoL. Other user ports
3831  * can share ownership of this address as long as their MAC address is the same.
3832  * The MAC addresses of user ports must not change while they have ownership of
3833  * the switch MAC address.
3834  *
3835  * Return: 0 on success, or other error codes on failure.
3836  */
3837 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
3838                            struct netlink_ext_ack *extack)
3839 {
3840         struct net_device *user = dsa_to_port(ds, port)->user;
3841         const unsigned char *addr = user->dev_addr;
3842         struct ksz_switch_macaddr *switch_macaddr;
3843         struct ksz_device *dev = ds->priv;
3844         const u16 *regs = dev->info->regs;
3845         int i, ret;
3846
3847         /* Make sure concurrent MAC address changes are blocked */
3848         ASSERT_RTNL();
3849
3850         switch_macaddr = dev->switch_macaddr;
3851         if (switch_macaddr) {
3852                 if (!ether_addr_equal(switch_macaddr->addr, addr)) {
3853                         NL_SET_ERR_MSG_FMT_MOD(extack,
3854                                                "Switch already configured for MAC address %pM",
3855                                                switch_macaddr->addr);
3856                         return -EBUSY;
3857                 }
3858
3859                 refcount_inc(&switch_macaddr->refcount);
3860                 return 0;
3861         }
3862
3863         switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL);
3864         if (!switch_macaddr)
3865                 return -ENOMEM;
3866
3867         ether_addr_copy(switch_macaddr->addr, addr);
3868         refcount_set(&switch_macaddr->refcount, 1);
3869         dev->switch_macaddr = switch_macaddr;
3870
3871         /* Program the switch MAC address to hardware */
3872         for (i = 0; i < ETH_ALEN; i++) {
3873                 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, addr[i]);
3874                 if (ret)
3875                         goto macaddr_drop;
3876         }
3877
3878         return 0;
3879
3880 macaddr_drop:
3881         dev->switch_macaddr = NULL;
3882         refcount_set(&switch_macaddr->refcount, 0);
3883         kfree(switch_macaddr);
3884
3885         return ret;
3886 }
3887
3888 void ksz_switch_macaddr_put(struct dsa_switch *ds)
3889 {
3890         struct ksz_switch_macaddr *switch_macaddr;
3891         struct ksz_device *dev = ds->priv;
3892         const u16 *regs = dev->info->regs;
3893         int i;
3894
3895         /* Make sure concurrent MAC address changes are blocked */
3896         ASSERT_RTNL();
3897
3898         switch_macaddr = dev->switch_macaddr;
3899         if (!refcount_dec_and_test(&switch_macaddr->refcount))
3900                 return;
3901
3902         for (i = 0; i < ETH_ALEN; i++)
3903                 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0);
3904
3905         dev->switch_macaddr = NULL;
3906         kfree(switch_macaddr);
3907 }
3908
3909 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr,
3910                         struct netlink_ext_ack *extack)
3911 {
3912         struct ksz_device *dev = ds->priv;
3913         enum hsr_version ver;
3914         int ret;
3915
3916         ret = hsr_get_version(hsr, &ver);
3917         if (ret)
3918                 return ret;
3919
3920         if (dev->chip_id != KSZ9477_CHIP_ID) {
3921                 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload");
3922                 return -EOPNOTSUPP;
3923         }
3924
3925         /* KSZ9477 can support HW offloading of only 1 HSR device */
3926         if (dev->hsr_dev && hsr != dev->hsr_dev) {
3927                 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR");
3928                 return -EOPNOTSUPP;
3929         }
3930
3931         /* KSZ9477 only supports HSR v0 and v1 */
3932         if (!(ver == HSR_V0 || ver == HSR_V1)) {
3933                 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported");
3934                 return -EOPNOTSUPP;
3935         }
3936
3937         /* KSZ9477 can only perform HSR offloading for up to two ports */
3938         if (hweight8(dev->hsr_ports) >= 2) {
3939                 NL_SET_ERR_MSG_MOD(extack,
3940                                    "Cannot offload more than two ports - using software HSR");
3941                 return -EOPNOTSUPP;
3942         }
3943
3944         /* Self MAC address filtering, to avoid frames traversing
3945          * the HSR ring more than once.
3946          */
3947         ret = ksz_switch_macaddr_get(ds, port, extack);
3948         if (ret)
3949                 return ret;
3950
3951         ksz9477_hsr_join(ds, port, hsr);
3952         dev->hsr_dev = hsr;
3953         dev->hsr_ports |= BIT(port);
3954
3955         return 0;
3956 }
3957
3958 static int ksz_hsr_leave(struct dsa_switch *ds, int port,
3959                          struct net_device *hsr)
3960 {
3961         struct ksz_device *dev = ds->priv;
3962
3963         WARN_ON(dev->chip_id != KSZ9477_CHIP_ID);
3964
3965         ksz9477_hsr_leave(ds, port, hsr);
3966         dev->hsr_ports &= ~BIT(port);
3967         if (!dev->hsr_ports)
3968                 dev->hsr_dev = NULL;
3969
3970         ksz_switch_macaddr_put(ds);
3971
3972         return 0;
3973 }
3974
3975 static const struct dsa_switch_ops ksz_switch_ops = {
3976         .get_tag_protocol       = ksz_get_tag_protocol,
3977         .connect_tag_protocol   = ksz_connect_tag_protocol,
3978         .get_phy_flags          = ksz_get_phy_flags,
3979         .setup                  = ksz_setup,
3980         .teardown               = ksz_teardown,
3981         .phy_read               = ksz_phy_read16,
3982         .phy_write              = ksz_phy_write16,
3983         .phylink_get_caps       = ksz_phylink_get_caps,
3984         .port_setup             = ksz_port_setup,
3985         .set_ageing_time        = ksz_set_ageing_time,
3986         .get_strings            = ksz_get_strings,
3987         .get_ethtool_stats      = ksz_get_ethtool_stats,
3988         .get_sset_count         = ksz_sset_count,
3989         .port_bridge_join       = ksz_port_bridge_join,
3990         .port_bridge_leave      = ksz_port_bridge_leave,
3991         .port_hsr_join          = ksz_hsr_join,
3992         .port_hsr_leave         = ksz_hsr_leave,
3993         .port_set_mac_address   = ksz_port_set_mac_address,
3994         .port_stp_state_set     = ksz_port_stp_state_set,
3995         .port_teardown          = ksz_port_teardown,
3996         .port_pre_bridge_flags  = ksz_port_pre_bridge_flags,
3997         .port_bridge_flags      = ksz_port_bridge_flags,
3998         .port_fast_age          = ksz_port_fast_age,
3999         .port_vlan_filtering    = ksz_port_vlan_filtering,
4000         .port_vlan_add          = ksz_port_vlan_add,
4001         .port_vlan_del          = ksz_port_vlan_del,
4002         .port_fdb_dump          = ksz_port_fdb_dump,
4003         .port_fdb_add           = ksz_port_fdb_add,
4004         .port_fdb_del           = ksz_port_fdb_del,
4005         .port_mdb_add           = ksz_port_mdb_add,
4006         .port_mdb_del           = ksz_port_mdb_del,
4007         .port_mirror_add        = ksz_port_mirror_add,
4008         .port_mirror_del        = ksz_port_mirror_del,
4009         .get_stats64            = ksz_get_stats64,
4010         .get_pause_stats        = ksz_get_pause_stats,
4011         .port_change_mtu        = ksz_change_mtu,
4012         .port_max_mtu           = ksz_max_mtu,
4013         .get_wol                = ksz_get_wol,
4014         .set_wol                = ksz_set_wol,
4015         .get_ts_info            = ksz_get_ts_info,
4016         .port_hwtstamp_get      = ksz_hwtstamp_get,
4017         .port_hwtstamp_set      = ksz_hwtstamp_set,
4018         .port_txtstamp          = ksz_port_txtstamp,
4019         .port_rxtstamp          = ksz_port_rxtstamp,
4020         .cls_flower_add         = ksz_cls_flower_add,
4021         .cls_flower_del         = ksz_cls_flower_del,
4022         .port_setup_tc          = ksz_setup_tc,
4023         .get_mac_eee            = ksz_get_mac_eee,
4024         .set_mac_eee            = ksz_set_mac_eee,
4025         .port_get_default_prio  = ksz_port_get_default_prio,
4026         .port_set_default_prio  = ksz_port_set_default_prio,
4027         .port_get_dscp_prio     = ksz_port_get_dscp_prio,
4028         .port_add_dscp_prio     = ksz_port_add_dscp_prio,
4029         .port_del_dscp_prio     = ksz_port_del_dscp_prio,
4030         .port_get_apptrust      = ksz_port_get_apptrust,
4031         .port_set_apptrust      = ksz_port_set_apptrust,
4032 };
4033
4034 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
4035 {
4036         struct dsa_switch *ds;
4037         struct ksz_device *swdev;
4038
4039         ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
4040         if (!ds)
4041                 return NULL;
4042
4043         ds->dev = base;
4044         ds->num_ports = DSA_MAX_PORTS;
4045         ds->ops = &ksz_switch_ops;
4046
4047         swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
4048         if (!swdev)
4049                 return NULL;
4050
4051         ds->priv = swdev;
4052         swdev->dev = base;
4053
4054         swdev->ds = ds;
4055         swdev->priv = priv;
4056
4057         return swdev;
4058 }
4059 EXPORT_SYMBOL(ksz_switch_alloc);
4060
4061 /**
4062  * ksz_switch_shutdown - Shutdown routine for the switch device.
4063  * @dev: The switch device structure.
4064  *
4065  * This function is responsible for initiating a shutdown sequence for the
4066  * switch device. It invokes the reset operation defined in the device
4067  * operations, if available, to reset the switch. Subsequently, it calls the
4068  * DSA framework's shutdown function to ensure a proper shutdown of the DSA
4069  * switch.
4070  */
4071 void ksz_switch_shutdown(struct ksz_device *dev)
4072 {
4073         bool wol_enabled = false;
4074
4075         if (dev->dev_ops->wol_pre_shutdown)
4076                 dev->dev_ops->wol_pre_shutdown(dev, &wol_enabled);
4077
4078         if (dev->dev_ops->reset && !wol_enabled)
4079                 dev->dev_ops->reset(dev);
4080
4081         dsa_switch_shutdown(dev->ds);
4082 }
4083 EXPORT_SYMBOL(ksz_switch_shutdown);
4084
4085 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
4086                                   struct device_node *port_dn)
4087 {
4088         phy_interface_t phy_mode = dev->ports[port_num].interface;
4089         int rx_delay = -1, tx_delay = -1;
4090
4091         if (!phy_interface_mode_is_rgmii(phy_mode))
4092                 return;
4093
4094         of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
4095         of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
4096
4097         if (rx_delay == -1 && tx_delay == -1) {
4098                 dev_warn(dev->dev,
4099                          "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
4100                          "please update device tree to specify \"rx-internal-delay-ps\" and "
4101                          "\"tx-internal-delay-ps\"",
4102                          port_num);
4103
4104                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
4105                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
4106                         rx_delay = 2000;
4107
4108                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
4109                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
4110                         tx_delay = 2000;
4111         }
4112
4113         if (rx_delay < 0)
4114                 rx_delay = 0;
4115         if (tx_delay < 0)
4116                 tx_delay = 0;
4117
4118         dev->ports[port_num].rgmii_rx_val = rx_delay;
4119         dev->ports[port_num].rgmii_tx_val = tx_delay;
4120 }
4121
4122 /**
4123  * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding
4124  *                               register value.
4125  * @array:      The array of drive strength values to search.
4126  * @array_size: The size of the array.
4127  * @microamp:   The drive strength value in microamp to be converted.
4128  *
4129  * This function searches the array of drive strength values for the given
4130  * microamp value and returns the corresponding register value for that drive.
4131  *
4132  * Returns: If found, the corresponding register value for that drive strength
4133  * is returned. Otherwise, -EINVAL is returned indicating an invalid value.
4134  */
4135 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array,
4136                                      size_t array_size, int microamp)
4137 {
4138         int i;
4139
4140         for (i = 0; i < array_size; i++) {
4141                 if (array[i].microamp == microamp)
4142                         return array[i].reg_val;
4143         }
4144
4145         return -EINVAL;
4146 }
4147
4148 /**
4149  * ksz_drive_strength_error() - Report invalid drive strength value
4150  * @dev:        ksz device
4151  * @array:      The array of drive strength values to search.
4152  * @array_size: The size of the array.
4153  * @microamp:   Invalid drive strength value in microamp
4154  *
4155  * This function logs an error message when an unsupported drive strength value
4156  * is detected. It lists out all the supported drive strength values for
4157  * reference in the error message.
4158  */
4159 static void ksz_drive_strength_error(struct ksz_device *dev,
4160                                      const struct ksz_drive_strength *array,
4161                                      size_t array_size, int microamp)
4162 {
4163         char supported_values[100];
4164         size_t remaining_size;
4165         int added_len;
4166         char *ptr;
4167         int i;
4168
4169         remaining_size = sizeof(supported_values);
4170         ptr = supported_values;
4171
4172         for (i = 0; i < array_size; i++) {
4173                 added_len = snprintf(ptr, remaining_size,
4174                                      i == 0 ? "%d" : ", %d", array[i].microamp);
4175
4176                 if (added_len >= remaining_size)
4177                         break;
4178
4179                 ptr += added_len;
4180                 remaining_size -= added_len;
4181         }
4182
4183         dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n",
4184                 microamp, supported_values);
4185 }
4186
4187 /**
4188  * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477
4189  *                                  chip variants.
4190  * @dev:       ksz device
4191  * @props:     Array of drive strength properties to be applied
4192  * @num_props: Number of properties in the array
4193  *
4194  * This function configures the drive strength for various KSZ9477 chip variants
4195  * based on the provided properties. It handles chip-specific nuances and
4196  * ensures only valid drive strengths are written to the respective chip.
4197  *
4198  * Return: 0 on successful configuration, a negative error code on failure.
4199  */
4200 static int ksz9477_drive_strength_write(struct ksz_device *dev,
4201                                         struct ksz_driver_strength_prop *props,
4202                                         int num_props)
4203 {
4204         size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths);
4205         int i, ret, reg;
4206         u8 mask = 0;
4207         u8 val = 0;
4208
4209         if (props[KSZ_DRIVER_STRENGTH_IO].value != -1)
4210                 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4211                          props[KSZ_DRIVER_STRENGTH_IO].name);
4212
4213         if (dev->chip_id == KSZ8795_CHIP_ID ||
4214             dev->chip_id == KSZ8794_CHIP_ID ||
4215             dev->chip_id == KSZ8765_CHIP_ID)
4216                 reg = KSZ8795_REG_SW_CTRL_20;
4217         else
4218                 reg = KSZ9477_REG_SW_IO_STRENGTH;
4219
4220         for (i = 0; i < num_props; i++) {
4221                 if (props[i].value == -1)
4222                         continue;
4223
4224                 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths,
4225                                                 array_size, props[i].value);
4226                 if (ret < 0) {
4227                         ksz_drive_strength_error(dev, ksz9477_drive_strengths,
4228                                                  array_size, props[i].value);
4229                         return ret;
4230                 }
4231
4232                 mask |= SW_DRIVE_STRENGTH_M << props[i].offset;
4233                 val |= ret << props[i].offset;
4234         }
4235
4236         return ksz_rmw8(dev, reg, mask, val);
4237 }
4238
4239 /**
4240  * ksz8830_drive_strength_write() - Set the drive strength configuration for
4241  *                                  KSZ8830 compatible chip variants.
4242  * @dev:       ksz device
4243  * @props:     Array of drive strength properties to be set
4244  * @num_props: Number of properties in the array
4245  *
4246  * This function applies the specified drive strength settings to KSZ8830 chip
4247  * variants (KSZ8873, KSZ8863).
4248  * It ensures the configurations align with what the chip variant supports and
4249  * warns or errors out on unsupported settings.
4250  *
4251  * Return: 0 on success, error code otherwise
4252  */
4253 static int ksz8830_drive_strength_write(struct ksz_device *dev,
4254                                         struct ksz_driver_strength_prop *props,
4255                                         int num_props)
4256 {
4257         size_t array_size = ARRAY_SIZE(ksz8830_drive_strengths);
4258         int microamp;
4259         int i, ret;
4260
4261         for (i = 0; i < num_props; i++) {
4262                 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO)
4263                         continue;
4264
4265                 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4266                          props[i].name);
4267         }
4268
4269         microamp = props[KSZ_DRIVER_STRENGTH_IO].value;
4270         ret = ksz_drive_strength_to_reg(ksz8830_drive_strengths, array_size,
4271                                         microamp);
4272         if (ret < 0) {
4273                 ksz_drive_strength_error(dev, ksz8830_drive_strengths,
4274                                          array_size, microamp);
4275                 return ret;
4276         }
4277
4278         return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12,
4279                         KSZ8873_DRIVE_STRENGTH_16MA, ret);
4280 }
4281
4282 /**
4283  * ksz_parse_drive_strength() - Extract and apply drive strength configurations
4284  *                              from device tree properties.
4285  * @dev:        ksz device
4286  *
4287  * This function reads the specified drive strength properties from the
4288  * device tree, validates against the supported chip variants, and sets
4289  * them accordingly. An error should be critical here, as the drive strength
4290  * settings are crucial for EMI compliance.
4291  *
4292  * Return: 0 on success, error code otherwise
4293  */
4294 static int ksz_parse_drive_strength(struct ksz_device *dev)
4295 {
4296         struct ksz_driver_strength_prop of_props[] = {
4297                 [KSZ_DRIVER_STRENGTH_HI] = {
4298                         .name = "microchip,hi-drive-strength-microamp",
4299                         .offset = SW_HI_SPEED_DRIVE_STRENGTH_S,
4300                         .value = -1,
4301                 },
4302                 [KSZ_DRIVER_STRENGTH_LO] = {
4303                         .name = "microchip,lo-drive-strength-microamp",
4304                         .offset = SW_LO_SPEED_DRIVE_STRENGTH_S,
4305                         .value = -1,
4306                 },
4307                 [KSZ_DRIVER_STRENGTH_IO] = {
4308                         .name = "microchip,io-drive-strength-microamp",
4309                         .offset = 0, /* don't care */
4310                         .value = -1,
4311                 },
4312         };
4313         struct device_node *np = dev->dev->of_node;
4314         bool have_any_prop = false;
4315         int i, ret;
4316
4317         for (i = 0; i < ARRAY_SIZE(of_props); i++) {
4318                 ret = of_property_read_u32(np, of_props[i].name,
4319                                            &of_props[i].value);
4320                 if (ret && ret != -EINVAL)
4321                         dev_warn(dev->dev, "Failed to read %s\n",
4322                                  of_props[i].name);
4323                 if (ret)
4324                         continue;
4325
4326                 have_any_prop = true;
4327         }
4328
4329         if (!have_any_prop)
4330                 return 0;
4331
4332         switch (dev->chip_id) {
4333         case KSZ8830_CHIP_ID:
4334                 return ksz8830_drive_strength_write(dev, of_props,
4335                                                     ARRAY_SIZE(of_props));
4336         case KSZ8795_CHIP_ID:
4337         case KSZ8794_CHIP_ID:
4338         case KSZ8765_CHIP_ID:
4339         case KSZ8563_CHIP_ID:
4340         case KSZ8567_CHIP_ID:
4341         case KSZ9477_CHIP_ID:
4342         case KSZ9563_CHIP_ID:
4343         case KSZ9567_CHIP_ID:
4344         case KSZ9893_CHIP_ID:
4345         case KSZ9896_CHIP_ID:
4346         case KSZ9897_CHIP_ID:
4347                 return ksz9477_drive_strength_write(dev, of_props,
4348                                                     ARRAY_SIZE(of_props));
4349         default:
4350                 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
4351                         if (of_props[i].value == -1)
4352                                 continue;
4353
4354                         dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4355                                  of_props[i].name);
4356                 }
4357         }
4358
4359         return 0;
4360 }
4361
4362 int ksz_switch_register(struct ksz_device *dev)
4363 {
4364         const struct ksz_chip_data *info;
4365         struct device_node *port, *ports;
4366         phy_interface_t interface;
4367         unsigned int port_num;
4368         int ret;
4369         int i;
4370
4371         dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
4372                                                   GPIOD_OUT_LOW);
4373         if (IS_ERR(dev->reset_gpio))
4374                 return PTR_ERR(dev->reset_gpio);
4375
4376         if (dev->reset_gpio) {
4377                 gpiod_set_value_cansleep(dev->reset_gpio, 1);
4378                 usleep_range(10000, 12000);
4379                 gpiod_set_value_cansleep(dev->reset_gpio, 0);
4380                 msleep(100);
4381         }
4382
4383         mutex_init(&dev->dev_mutex);
4384         mutex_init(&dev->regmap_mutex);
4385         mutex_init(&dev->alu_mutex);
4386         mutex_init(&dev->vlan_mutex);
4387
4388         ret = ksz_switch_detect(dev);
4389         if (ret)
4390                 return ret;
4391
4392         info = ksz_lookup_info(dev->chip_id);
4393         if (!info)
4394                 return -ENODEV;
4395
4396         /* Update the compatible info with the probed one */
4397         dev->info = info;
4398
4399         dev_info(dev->dev, "found switch: %s, rev %i\n",
4400                  dev->info->dev_name, dev->chip_rev);
4401
4402         ret = ksz_check_device_id(dev);
4403         if (ret)
4404                 return ret;
4405
4406         dev->dev_ops = dev->info->ops;
4407
4408         ret = dev->dev_ops->init(dev);
4409         if (ret)
4410                 return ret;
4411
4412         dev->ports = devm_kzalloc(dev->dev,
4413                                   dev->info->port_cnt * sizeof(struct ksz_port),
4414                                   GFP_KERNEL);
4415         if (!dev->ports)
4416                 return -ENOMEM;
4417
4418         for (i = 0; i < dev->info->port_cnt; i++) {
4419                 spin_lock_init(&dev->ports[i].mib.stats64_lock);
4420                 mutex_init(&dev->ports[i].mib.cnt_mutex);
4421                 dev->ports[i].mib.counters =
4422                         devm_kzalloc(dev->dev,
4423                                      sizeof(u64) * (dev->info->mib_cnt + 1),
4424                                      GFP_KERNEL);
4425                 if (!dev->ports[i].mib.counters)
4426                         return -ENOMEM;
4427
4428                 dev->ports[i].ksz_dev = dev;
4429                 dev->ports[i].num = i;
4430         }
4431
4432         /* set the real number of ports */
4433         dev->ds->num_ports = dev->info->port_cnt;
4434
4435         /* set the phylink ops */
4436         dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops;
4437
4438         /* Host port interface will be self detected, or specifically set in
4439          * device tree.
4440          */
4441         for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
4442                 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
4443         if (dev->dev->of_node) {
4444                 ret = of_get_phy_mode(dev->dev->of_node, &interface);
4445                 if (ret == 0)
4446                         dev->compat_interface = interface;
4447                 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
4448                 if (!ports)
4449                         ports = of_get_child_by_name(dev->dev->of_node, "ports");
4450                 if (ports) {
4451                         for_each_available_child_of_node(ports, port) {
4452                                 if (of_property_read_u32(port, "reg",
4453                                                          &port_num))
4454                                         continue;
4455                                 if (!(dev->port_mask & BIT(port_num))) {
4456                                         of_node_put(port);
4457                                         of_node_put(ports);
4458                                         return -EINVAL;
4459                                 }
4460                                 of_get_phy_mode(port,
4461                                                 &dev->ports[port_num].interface);
4462
4463                                 ksz_parse_rgmii_delay(dev, port_num, port);
4464                         }
4465                         of_node_put(ports);
4466                 }
4467                 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
4468                                                          "microchip,synclko-125");
4469                 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
4470                                                              "microchip,synclko-disable");
4471                 if (dev->synclko_125 && dev->synclko_disable) {
4472                         dev_err(dev->dev, "inconsistent synclko settings\n");
4473                         return -EINVAL;
4474                 }
4475
4476                 dev->wakeup_source = of_property_read_bool(dev->dev->of_node,
4477                                                            "wakeup-source");
4478         }
4479
4480         ret = dsa_register_switch(dev->ds);
4481         if (ret) {
4482                 dev->dev_ops->exit(dev);
4483                 return ret;
4484         }
4485
4486         /* Read MIB counters every 30 seconds to avoid overflow. */
4487         dev->mib_read_interval = msecs_to_jiffies(5000);
4488
4489         /* Start the MIB timer. */
4490         schedule_delayed_work(&dev->mib_read, 0);
4491
4492         return ret;
4493 }
4494 EXPORT_SYMBOL(ksz_switch_register);
4495
4496 void ksz_switch_remove(struct ksz_device *dev)
4497 {
4498         /* timer started */
4499         if (dev->mib_read_interval) {
4500                 dev->mib_read_interval = 0;
4501                 cancel_delayed_work_sync(&dev->mib_read);
4502         }
4503
4504         dev->dev_ops->exit(dev);
4505         dsa_unregister_switch(dev->ds);
4506
4507         if (dev->reset_gpio)
4508                 gpiod_set_value_cansleep(dev->reset_gpio, 1);
4509
4510 }
4511 EXPORT_SYMBOL(ksz_switch_remove);
4512
4513 MODULE_AUTHOR("Woojung Huh <[email protected]>");
4514 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
4515 MODULE_LICENSE("GPL");