drivers/media/i2c/gc08a3.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for GalaxyCore gc08a3 image sensor
   4  *
   5  * Copyright 2024 MediaTek
   6  *
   7  * Zhi Mao <[email protected]>
   8  */
   9 #include <linux/array_size.h>
  10 #include <linux/bits.h>
  11 #include <linux/clk.h>
  12 #include <linux/container_of.h>
  13 #include <linux/delay.h>
  14 #include <linux/device.h>
  15 #include <linux/err.h>
  16 #include <linux/gpio/consumer.h>
  17 #include <linux/math64.h>
  18 #include <linux/mod_devicetable.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/property.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/types.h>
  23 #include <linux/units.h>
  24
  25 #include <media/v4l2-cci.h>
  26 #include <media/v4l2-ctrls.h>
  27 #include <media/v4l2-event.h>
  28 #include <media/v4l2-fwnode.h>
  29 #include <media/v4l2-subdev.h>
  30
  31 #define GC08A3_REG_TEST_PATTERN_EN CCI_REG8(0x008c)
  32 #define GC08A3_REG_TEST_PATTERN_IDX CCI_REG8(0x008d)
  33 #define GC08A3_TEST_PATTERN_EN 0x01
  34
  35 #define GC08A3_STREAMING_REG CCI_REG8(0x0100)
  36
  37 #define GC08A3_FLIP_REG CCI_REG8(0x0101)
  38 #define GC08A3_FLIP_H_MASK BIT(0)
  39 #define GC08A3_FLIP_V_MASK BIT(1)
  40
  41 #define GC08A3_EXP_REG CCI_REG16(0x0202)
  42 #define GC08A3_EXP_MARGIN 16
  43 #define GC08A3_EXP_MIN 4
  44 #define GC08A3_EXP_STEP 1
  45
  46 #define GC08A3_AGAIN_REG CCI_REG16(0x0204)
  47 #define GC08A3_AGAIN_MIN 1024
  48 #define GC08A3_AGAIN_MAX (1024 * 16)
  49 #define GC08A3_AGAIN_STEP 1
  50
  51 #define GC08A3_FRAME_LENGTH_REG CCI_REG16(0x0340)
  52 #define GC08A3_VTS_MAX 0xfff0
  53
  54 #define GC08A3_REG_CHIP_ID CCI_REG16(0x03f0)
  55 #define GC08A3_CHIP_ID 0x08a3
  56
  57 #define GC08A3_NATIVE_WIDTH 3264
  58 #define GC08A3_NATIVE_HEIGHT 2448
  59
  60 #define GC08A3_DEFAULT_CLK_FREQ (24 * HZ_PER_MHZ)
  61 #define GC08A3_MBUS_CODE MEDIA_BUS_FMT_SRGGB10_1X10
  62 #define GC08A3_DATA_LANES 4
  63
  64 #define GC08A3_RGB_DEPTH 10
  65
  66 #define GC08A3_SLEEP_US  (2 * USEC_PER_MSEC)
  67
  68 static const char *const gc08a3_test_pattern_menu[] = {
  69         "No Pattern", "Solid Black", "Colour Bar", "Solid White",
  70         "Solid Red", "Solid Green", "Solid Blue", "Solid Yellow",
  71 };
  72
  73 static const s64 gc08a3_link_freq_menu_items[] = {
  74         (336 * HZ_PER_MHZ),
  75         (207 * HZ_PER_MHZ),
  76 };
  77
  78 static const char *const gc08a3_supply_name[] = {
  79         "avdd",
  80         "dvdd",
  81         "dovdd",
  82 };
  83
  84 struct gc08a3 {
  85         struct device *dev;
  86         struct v4l2_subdev sd;
  87         struct media_pad pad;
  88
  89         struct clk *xclk;
  90         struct regulator_bulk_data supplies[ARRAY_SIZE(gc08a3_supply_name)];
  91         struct gpio_desc *reset_gpio;
  92
  93         struct v4l2_ctrl_handler ctrls;
  94         struct v4l2_ctrl *pixel_rate;
  95         struct v4l2_ctrl *link_freq;
  96         struct v4l2_ctrl *exposure;
  97         struct v4l2_ctrl *vblank;
  98         struct v4l2_ctrl *hblank;
  99         struct v4l2_ctrl *hflip;
 100         struct v4l2_ctrl *vflip;
 101
 102         struct regmap *regmap;
 103         unsigned long link_freq_bitmap;
 104         const struct gc08a3_mode *cur_mode;
 105 };
 106
 107 struct gc08a3_reg_list {
 108         u32 num_of_regs;
 109         const struct cci_reg_sequence *regs;
 110 };
 111
 112 static const struct cci_reg_sequence mode_3264x2448[] = {
 113         /* system */
 114         { CCI_REG8(0x0336), 0x70 },
 115         { CCI_REG8(0x0383), 0xbb },
 116         { CCI_REG8(0x0344), 0x00 },
 117         { CCI_REG8(0x0345), 0x06 },
 118         { CCI_REG8(0x0346), 0x00 },
 119         { CCI_REG8(0x0347), 0x04 },
 120         { CCI_REG8(0x0348), 0x0c },
 121         { CCI_REG8(0x0349), 0xd0 },
 122         { CCI_REG8(0x034a), 0x09 },
 123         { CCI_REG8(0x034b), 0x9c },
 124         { CCI_REG8(0x0202), 0x09 },
 125         { CCI_REG8(0x0203), 0x04 },
 126         { CCI_REG8(0x0340), 0x09 },
 127         { CCI_REG8(0x0341), 0xf4 },
 128         { CCI_REG8(0x0342), 0x07 },
 129         { CCI_REG8(0x0343), 0x1c },
 130
 131         { CCI_REG8(0x0226), 0x00 },
 132         { CCI_REG8(0x0227), 0x28 },
 133         { CCI_REG8(0x0e38), 0x49 },
 134         { CCI_REG8(0x0210), 0x13 },
 135         { CCI_REG8(0x0218), 0x00 },
 136         { CCI_REG8(0x0241), 0x88 },
 137         { CCI_REG8(0x0392), 0x60 },
 138
 139         /* ISP */
 140         { CCI_REG8(0x00a2), 0x00 },
 141         { CCI_REG8(0x00a3), 0x00 },
 142         { CCI_REG8(0x00ab), 0x00 },
 143         { CCI_REG8(0x00ac), 0x00 },
 144
 145         /* GAIN */
 146         { CCI_REG8(0x0204), 0x04 },
 147         { CCI_REG8(0x0205), 0x00 },
 148         { CCI_REG8(0x0050), 0x5c },
 149         { CCI_REG8(0x0051), 0x44 },
 150
 151         /* out window */
 152         { CCI_REG8(0x009a), 0x66 },
 153         { CCI_REG8(0x0351), 0x00 },
 154         { CCI_REG8(0x0352), 0x06 },
 155         { CCI_REG8(0x0353), 0x00 },
 156         { CCI_REG8(0x0354), 0x08 },
 157         { CCI_REG8(0x034c), 0x0c },
 158         { CCI_REG8(0x034d), 0xc0 },
 159         { CCI_REG8(0x034e), 0x09 },
 160         { CCI_REG8(0x034f), 0x90 },
 161
 162         /* MIPI */
 163         { CCI_REG8(0x0114), 0x03 },
 164         { CCI_REG8(0x0180), 0x65 },
 165         { CCI_REG8(0x0181), 0xf0 },
 166         { CCI_REG8(0x0185), 0x01 },
 167         { CCI_REG8(0x0115), 0x30 },
 168         { CCI_REG8(0x011b), 0x12 },
 169         { CCI_REG8(0x011c), 0x12 },
 170         { CCI_REG8(0x0121), 0x06 },
 171         { CCI_REG8(0x0122), 0x06 },
 172         { CCI_REG8(0x0123), 0x15 },
 173         { CCI_REG8(0x0124), 0x01 },
 174         { CCI_REG8(0x0125), 0x0b },
 175         { CCI_REG8(0x0126), 0x08 },
 176         { CCI_REG8(0x0129), 0x06 },
 177         { CCI_REG8(0x012a), 0x08 },
 178         { CCI_REG8(0x012b), 0x08 },
 179
 180         { CCI_REG8(0x0a73), 0x60 },
 181         { CCI_REG8(0x0a70), 0x11 },
 182         { CCI_REG8(0x0313), 0x80 },
 183         { CCI_REG8(0x0aff), 0x00 },
 184         { CCI_REG8(0x0a70), 0x00 },
 185         { CCI_REG8(0x00a4), 0x80 },
 186         { CCI_REG8(0x0316), 0x01 },
 187         { CCI_REG8(0x0a67), 0x00 },
 188         { CCI_REG8(0x0084), 0x10 },
 189         { CCI_REG8(0x0102), 0x09 },
 190 };
 191
 192 static const struct cci_reg_sequence mode_1920x1080[] = {
 193         /* system */
 194         { CCI_REG8(0x0336), 0x45 },
 195         { CCI_REG8(0x0383), 0x8b },
 196         { CCI_REG8(0x0344), 0x02 },
 197         { CCI_REG8(0x0345), 0xa6 },
 198         { CCI_REG8(0x0346), 0x02 },
 199         { CCI_REG8(0x0347), 0xb0 },
 200         { CCI_REG8(0x0348), 0x07 },
 201         { CCI_REG8(0x0349), 0x90 },
 202         { CCI_REG8(0x034a), 0x04 },
 203         { CCI_REG8(0x034b), 0x44 },
 204         { CCI_REG8(0x0202), 0x03 },
 205         { CCI_REG8(0x0203), 0x00 },
 206         { CCI_REG8(0x0340), 0x04 },
 207         { CCI_REG8(0x0341), 0xfc },
 208         { CCI_REG8(0x0342), 0x07 },
 209         { CCI_REG8(0x0343), 0x1c },
 210         { CCI_REG8(0x0226), 0x00 },
 211         { CCI_REG8(0x0227), 0x88 },
 212         { CCI_REG8(0x0e38), 0x49 },
 213         { CCI_REG8(0x0210), 0x13 },
 214         { CCI_REG8(0x0218), 0x00 },
 215         { CCI_REG8(0x0241), 0x88 },
 216         { CCI_REG8(0x0392), 0x60 },
 217
 218         /* ISP */
 219         { CCI_REG8(0x00a2), 0xac },
 220         { CCI_REG8(0x00a3), 0x02 },
 221         { CCI_REG8(0x00ab), 0xa0 },
 222         { CCI_REG8(0x00ac), 0x02 },
 223
 224         /* GAIN */
 225         { CCI_REG8(0x0204), 0x04 },
 226         { CCI_REG8(0x0205), 0x00 },
 227         { CCI_REG8(0x0050), 0x38 },
 228         { CCI_REG8(0x0051), 0x20 },
 229
 230         /* out window */
 231         { CCI_REG8(0x009a), 0x66 },
 232         { CCI_REG8(0x0351), 0x00 },
 233         { CCI_REG8(0x0352), 0x06 },
 234         { CCI_REG8(0x0353), 0x00 },
 235         { CCI_REG8(0x0354), 0x08 },
 236         { CCI_REG8(0x034c), 0x07 },
 237         { CCI_REG8(0x034d), 0x80 },
 238         { CCI_REG8(0x034e), 0x04 },
 239         { CCI_REG8(0x034f), 0x38 },
 240
 241         /* MIPI */
 242         { CCI_REG8(0x0114), 0x03 },
 243         { CCI_REG8(0x0180), 0x65 },
 244         { CCI_REG8(0x0181), 0xf0 },
 245         { CCI_REG8(0x0185), 0x01 },
 246         { CCI_REG8(0x0115), 0x30 },
 247         { CCI_REG8(0x011b), 0x12 },
 248         { CCI_REG8(0x011c), 0x12 },
 249         { CCI_REG8(0x0121), 0x02 },
 250         { CCI_REG8(0x0122), 0x03 },
 251         { CCI_REG8(0x0123), 0x0c },
 252         { CCI_REG8(0x0124), 0x00 },
 253         { CCI_REG8(0x0125), 0x09 },
 254         { CCI_REG8(0x0126), 0x06 },
 255         { CCI_REG8(0x0129), 0x04 },
 256         { CCI_REG8(0x012a), 0x03 },
 257         { CCI_REG8(0x012b), 0x06 },
 258
 259         { CCI_REG8(0x0a73), 0x60 },
 260         { CCI_REG8(0x0a70), 0x11 },
 261         { CCI_REG8(0x0313), 0x80 },
 262         { CCI_REG8(0x0aff), 0x00 },
 263         { CCI_REG8(0x0a70), 0x00 },
 264         { CCI_REG8(0x00a4), 0x80 },
 265         { CCI_REG8(0x0316), 0x01 },
 266         { CCI_REG8(0x0a67), 0x00 },
 267         { CCI_REG8(0x0084), 0x10 },
 268         { CCI_REG8(0x0102), 0x09 },
 269 };
 270
 271 static const struct cci_reg_sequence mode_table_common[] = {
 272         { GC08A3_STREAMING_REG, 0x00 },
 273         /* system */
 274         { CCI_REG8(0x031c), 0x60 },
 275         { CCI_REG8(0x0337), 0x04 },
 276         { CCI_REG8(0x0335), 0x51 },
 277         { CCI_REG8(0x0336), 0x70 },
 278         { CCI_REG8(0x0383), 0xbb },
 279         { CCI_REG8(0x031a), 0x00 },
 280         { CCI_REG8(0x0321), 0x10 },
 281         { CCI_REG8(0x0327), 0x03 },
 282         { CCI_REG8(0x0325), 0x40 },
 283         { CCI_REG8(0x0326), 0x23 },
 284         { CCI_REG8(0x0314), 0x11 },
 285         { CCI_REG8(0x0315), 0xd6 },
 286         { CCI_REG8(0x0316), 0x01 },
 287         { CCI_REG8(0x0334), 0x40 },
 288         { CCI_REG8(0x0324), 0x42 },
 289         { CCI_REG8(0x031c), 0x00 },
 290         { CCI_REG8(0x031c), 0x9f },
 291         { CCI_REG8(0x039a), 0x13 },
 292         { CCI_REG8(0x0084), 0x30 },
 293         { CCI_REG8(0x02b3), 0x08 },
 294         { CCI_REG8(0x0057), 0x0c },
 295         { CCI_REG8(0x05c3), 0x50 },
 296         { CCI_REG8(0x0311), 0x90 },
 297         { CCI_REG8(0x05a0), 0x02 },
 298         { CCI_REG8(0x0074), 0x0a },
 299         { CCI_REG8(0x0059), 0x11 },
 300         { CCI_REG8(0x0070), 0x05 },
 301         { CCI_REG8(0x0101), 0x00 },
 302
 303         /* analog */
 304         { CCI_REG8(0x0344), 0x00 },
 305         { CCI_REG8(0x0345), 0x06 },
 306         { CCI_REG8(0x0346), 0x00 },
 307         { CCI_REG8(0x0347), 0x04 },
 308         { CCI_REG8(0x0348), 0x0c },
 309         { CCI_REG8(0x0349), 0xd0 },
 310         { CCI_REG8(0x034a), 0x09 },
 311         { CCI_REG8(0x034b), 0x9c },
 312         { CCI_REG8(0x0202), 0x09 },
 313         { CCI_REG8(0x0203), 0x04 },
 314
 315         { CCI_REG8(0x0219), 0x05 },
 316         { CCI_REG8(0x0226), 0x00 },
 317         { CCI_REG8(0x0227), 0x28 },
 318         { CCI_REG8(0x0e0a), 0x00 },
 319         { CCI_REG8(0x0e0b), 0x00 },
 320         { CCI_REG8(0x0e24), 0x04 },
 321         { CCI_REG8(0x0e25), 0x04 },
 322         { CCI_REG8(0x0e26), 0x00 },
 323         { CCI_REG8(0x0e27), 0x10 },
 324         { CCI_REG8(0x0e01), 0x74 },
 325         { CCI_REG8(0x0e03), 0x47 },
 326         { CCI_REG8(0x0e04), 0x33 },
 327         { CCI_REG8(0x0e05), 0x44 },
 328         { CCI_REG8(0x0e06), 0x44 },
 329         { CCI_REG8(0x0e0c), 0x1e },
 330         { CCI_REG8(0x0e17), 0x3a },
 331         { CCI_REG8(0x0e18), 0x3c },
 332         { CCI_REG8(0x0e19), 0x40 },
 333         { CCI_REG8(0x0e1a), 0x42 },
 334         { CCI_REG8(0x0e28), 0x21 },
 335         { CCI_REG8(0x0e2b), 0x68 },
 336         { CCI_REG8(0x0e2c), 0x0d },
 337         { CCI_REG8(0x0e2d), 0x08 },
 338         { CCI_REG8(0x0e34), 0xf4 },
 339         { CCI_REG8(0x0e35), 0x44 },
 340         { CCI_REG8(0x0e36), 0x07 },
 341         { CCI_REG8(0x0e38), 0x49 },
 342         { CCI_REG8(0x0210), 0x13 },
 343         { CCI_REG8(0x0218), 0x00 },
 344         { CCI_REG8(0x0241), 0x88 },
 345         { CCI_REG8(0x0e32), 0x00 },
 346         { CCI_REG8(0x0e33), 0x18 },
 347         { CCI_REG8(0x0e42), 0x03 },
 348         { CCI_REG8(0x0e43), 0x80 },
 349         { CCI_REG8(0x0e44), 0x04 },
 350         { CCI_REG8(0x0e45), 0x00 },
 351         { CCI_REG8(0x0e4f), 0x04 },
 352         { CCI_REG8(0x057a), 0x20 },
 353         { CCI_REG8(0x0381), 0x7c },
 354         { CCI_REG8(0x0382), 0x9b },
 355         { CCI_REG8(0x0384), 0xfb },
 356         { CCI_REG8(0x0389), 0x38 },
 357         { CCI_REG8(0x038a), 0x03 },
 358         { CCI_REG8(0x0390), 0x6a },
 359         { CCI_REG8(0x0391), 0x0b },
 360         { CCI_REG8(0x0392), 0x60 },
 361         { CCI_REG8(0x0393), 0xc1 },
 362         { CCI_REG8(0x0396), 0xff },
 363         { CCI_REG8(0x0398), 0x62 },
 364
 365         /* cisctl reset */
 366         { CCI_REG8(0x031c), 0x80 },
 367         { CCI_REG8(0x03fe), 0x10 },
 368         { CCI_REG8(0x03fe), 0x00 },
 369         { CCI_REG8(0x031c), 0x9f },
 370         { CCI_REG8(0x03fe), 0x00 },
 371         { CCI_REG8(0x03fe), 0x00 },
 372         { CCI_REG8(0x03fe), 0x00 },
 373         { CCI_REG8(0x03fe), 0x00 },
 374         { CCI_REG8(0x031c), 0x80 },
 375         { CCI_REG8(0x03fe), 0x10 },
 376         { CCI_REG8(0x03fe), 0x00 },
 377         { CCI_REG8(0x031c), 0x9f },
 378         { CCI_REG8(0x0360), 0x01 },
 379         { CCI_REG8(0x0360), 0x00 },
 380         { CCI_REG8(0x0316), 0x09 },
 381         { CCI_REG8(0x0a67), 0x80 },
 382         { CCI_REG8(0x0313), 0x00 },
 383         { CCI_REG8(0x0a53), 0x0e },
 384         { CCI_REG8(0x0a65), 0x17 },
 385         { CCI_REG8(0x0a68), 0xa1 },
 386         { CCI_REG8(0x0a58), 0x00 },
 387         { CCI_REG8(0x0ace), 0x0c },
 388         { CCI_REG8(0x00a4), 0x00 },
 389         { CCI_REG8(0x00a5), 0x01 },
 390         { CCI_REG8(0x00a7), 0x09 },
 391         { CCI_REG8(0x00a8), 0x9c },
 392         { CCI_REG8(0x00a9), 0x0c },
 393         { CCI_REG8(0x00aa), 0xd0 },
 394         { CCI_REG8(0x0a8a), 0x00 },
 395         { CCI_REG8(0x0a8b), 0xe0 },
 396         { CCI_REG8(0x0a8c), 0x13 },
 397         { CCI_REG8(0x0a8d), 0xe8 },
 398         { CCI_REG8(0x0a90), 0x0a },
 399         { CCI_REG8(0x0a91), 0x10 },
 400         { CCI_REG8(0x0a92), 0xf8 },
 401         { CCI_REG8(0x0a71), 0xf2 },
 402         { CCI_REG8(0x0a72), 0x12 },
 403         { CCI_REG8(0x0a73), 0x64 },
 404         { CCI_REG8(0x0a75), 0x41 },
 405         { CCI_REG8(0x0a70), 0x07 },
 406         { CCI_REG8(0x0313), 0x80 },
 407
 408         /* ISP */
 409         { CCI_REG8(0x00a0), 0x01 },
 410         { CCI_REG8(0x0080), 0xd2 },
 411         { CCI_REG8(0x0081), 0x3f },
 412         { CCI_REG8(0x0087), 0x51 },
 413         { CCI_REG8(0x0089), 0x03 },
 414         { CCI_REG8(0x009b), 0x40 },
 415         { CCI_REG8(0x05a0), 0x82 },
 416         { CCI_REG8(0x05ac), 0x00 },
 417         { CCI_REG8(0x05ad), 0x01 },
 418         { CCI_REG8(0x05ae), 0x00 },
 419         { CCI_REG8(0x0800), 0x0a },
 420         { CCI_REG8(0x0801), 0x14 },
 421         { CCI_REG8(0x0802), 0x28 },
 422         { CCI_REG8(0x0803), 0x34 },
 423         { CCI_REG8(0x0804), 0x0e },
 424         { CCI_REG8(0x0805), 0x33 },
 425         { CCI_REG8(0x0806), 0x03 },
 426         { CCI_REG8(0x0807), 0x8a },
 427         { CCI_REG8(0x0808), 0x50 },
 428         { CCI_REG8(0x0809), 0x00 },
 429         { CCI_REG8(0x080a), 0x34 },
 430         { CCI_REG8(0x080b), 0x03 },
 431         { CCI_REG8(0x080c), 0x26 },
 432         { CCI_REG8(0x080d), 0x03 },
 433         { CCI_REG8(0x080e), 0x18 },
 434         { CCI_REG8(0x080f), 0x03 },
 435         { CCI_REG8(0x0810), 0x10 },
 436         { CCI_REG8(0x0811), 0x03 },
 437         { CCI_REG8(0x0812), 0x00 },
 438         { CCI_REG8(0x0813), 0x00 },
 439         { CCI_REG8(0x0814), 0x01 },
 440         { CCI_REG8(0x0815), 0x00 },
 441         { CCI_REG8(0x0816), 0x01 },
 442         { CCI_REG8(0x0817), 0x00 },
 443         { CCI_REG8(0x0818), 0x00 },
 444         { CCI_REG8(0x0819), 0x0a },
 445         { CCI_REG8(0x081a), 0x01 },
 446         { CCI_REG8(0x081b), 0x6c },
 447         { CCI_REG8(0x081c), 0x00 },
 448         { CCI_REG8(0x081d), 0x0b },
 449         { CCI_REG8(0x081e), 0x02 },
 450         { CCI_REG8(0x081f), 0x00 },
 451         { CCI_REG8(0x0820), 0x00 },
 452         { CCI_REG8(0x0821), 0x0c },
 453         { CCI_REG8(0x0822), 0x02 },
 454         { CCI_REG8(0x0823), 0xd9 },
 455         { CCI_REG8(0x0824), 0x00 },
 456         { CCI_REG8(0x0825), 0x0d },
 457         { CCI_REG8(0x0826), 0x03 },
 458         { CCI_REG8(0x0827), 0xf0 },
 459         { CCI_REG8(0x0828), 0x00 },
 460         { CCI_REG8(0x0829), 0x0e },
 461         { CCI_REG8(0x082a), 0x05 },
 462         { CCI_REG8(0x082b), 0x94 },
 463         { CCI_REG8(0x082c), 0x09 },
 464         { CCI_REG8(0x082d), 0x6e },
 465         { CCI_REG8(0x082e), 0x07 },
 466         { CCI_REG8(0x082f), 0xe6 },
 467         { CCI_REG8(0x0830), 0x10 },
 468         { CCI_REG8(0x0831), 0x0e },
 469         { CCI_REG8(0x0832), 0x0b },
 470         { CCI_REG8(0x0833), 0x2c },
 471         { CCI_REG8(0x0834), 0x14 },
 472         { CCI_REG8(0x0835), 0xae },
 473         { CCI_REG8(0x0836), 0x0f },
 474         { CCI_REG8(0x0837), 0xc4 },
 475         { CCI_REG8(0x0838), 0x18 },
 476         { CCI_REG8(0x0839), 0x0e },
 477         { CCI_REG8(0x05ac), 0x01 },
 478         { CCI_REG8(0x059a), 0x00 },
 479         { CCI_REG8(0x059b), 0x00 },
 480         { CCI_REG8(0x059c), 0x01 },
 481         { CCI_REG8(0x0598), 0x00 },
 482         { CCI_REG8(0x0597), 0x14 },
 483         { CCI_REG8(0x05ab), 0x09 },
 484         { CCI_REG8(0x05a4), 0x02 },
 485         { CCI_REG8(0x05a3), 0x05 },
 486         { CCI_REG8(0x05a0), 0xc2 },
 487         { CCI_REG8(0x0207), 0xc4 },
 488
 489         /* GAIN */
 490         { CCI_REG8(0x0208), 0x01 },
 491         { CCI_REG8(0x0209), 0x72 },
 492         { CCI_REG8(0x0204), 0x04 },
 493         { CCI_REG8(0x0205), 0x00 },
 494
 495         { CCI_REG8(0x0040), 0x22 },
 496         { CCI_REG8(0x0041), 0x20 },
 497         { CCI_REG8(0x0043), 0x10 },
 498         { CCI_REG8(0x0044), 0x00 },
 499         { CCI_REG8(0x0046), 0x08 },
 500         { CCI_REG8(0x0047), 0xf0 },
 501         { CCI_REG8(0x0048), 0x0f },
 502         { CCI_REG8(0x004b), 0x0f },
 503         { CCI_REG8(0x004c), 0x00 },
 504         { CCI_REG8(0x0050), 0x5c },
 505         { CCI_REG8(0x0051), 0x44 },
 506         { CCI_REG8(0x005b), 0x03 },
 507         { CCI_REG8(0x00c0), 0x00 },
 508         { CCI_REG8(0x00c1), 0x80 },
 509         { CCI_REG8(0x00c2), 0x31 },
 510         { CCI_REG8(0x00c3), 0x00 },
 511         { CCI_REG8(0x0460), 0x04 },
 512         { CCI_REG8(0x0462), 0x08 },
 513         { CCI_REG8(0x0464), 0x0e },
 514         { CCI_REG8(0x0466), 0x0a },
 515         { CCI_REG8(0x0468), 0x12 },
 516         { CCI_REG8(0x046a), 0x12 },
 517         { CCI_REG8(0x046c), 0x10 },
 518         { CCI_REG8(0x046e), 0x0c },
 519         { CCI_REG8(0x0461), 0x03 },
 520         { CCI_REG8(0x0463), 0x03 },
 521         { CCI_REG8(0x0465), 0x03 },
 522         { CCI_REG8(0x0467), 0x03 },
 523         { CCI_REG8(0x0469), 0x04 },
 524         { CCI_REG8(0x046b), 0x04 },
 525         { CCI_REG8(0x046d), 0x04 },
 526         { CCI_REG8(0x046f), 0x04 },
 527         { CCI_REG8(0x0470), 0x04 },
 528         { CCI_REG8(0x0472), 0x10 },
 529         { CCI_REG8(0x0474), 0x26 },
 530         { CCI_REG8(0x0476), 0x38 },
 531         { CCI_REG8(0x0478), 0x20 },
 532         { CCI_REG8(0x047a), 0x30 },
 533         { CCI_REG8(0x047c), 0x38 },
 534         { CCI_REG8(0x047e), 0x60 },
 535         { CCI_REG8(0x0471), 0x05 },
 536         { CCI_REG8(0x0473), 0x05 },
 537         { CCI_REG8(0x0475), 0x05 },
 538         { CCI_REG8(0x0477), 0x05 },
 539         { CCI_REG8(0x0479), 0x04 },
 540         { CCI_REG8(0x047b), 0x04 },
 541         { CCI_REG8(0x047d), 0x04 },
 542         { CCI_REG8(0x047f), 0x04 },
 543 };
 544
 545 struct gc08a3_mode {
 546         u32 width;
 547         u32 height;
 548         const struct gc08a3_reg_list reg_list;
 549
 550         u32 hts; /* Horizontal timining size */
 551         u32 vts_def; /* Default vertical timining size */
 552         u32 vts_min; /* Min vertical timining size */
 553 };
 554
 555 /* Declare modes in order, from biggest to smallest height. */
 556 static const struct gc08a3_mode gc08a3_modes[] = {
 557         {
 558                 /* 3264*2448@30fps */
 559                 .width = GC08A3_NATIVE_WIDTH,
 560                 .height = GC08A3_NATIVE_HEIGHT,
 561                 .reg_list = {
 562                         .num_of_regs = ARRAY_SIZE(mode_3264x2448),
 563                         .regs = mode_3264x2448,
 564                 },
 565                 .hts = 3640,
 566                 .vts_def = 2548,
 567                 .vts_min = 2548,
 568         },
 569         {
 570                 /* 1920*1080@60fps */
 571                 .width = 1920,
 572                 .height = 1080,
 573                 .reg_list = {
 574                         .num_of_regs = ARRAY_SIZE(mode_1920x1080),
 575                         .regs = mode_1920x1080,
 576                 },
 577                 .hts = 3640,
 578                 .vts_def = 1276,
 579                 .vts_min = 1276,
 580         },
 581 };
 582
 583 static inline struct gc08a3 *to_gc08a3(struct v4l2_subdev *sd)
 584 {
 585         return container_of(sd, struct gc08a3, sd);
 586 }
 587
 588 static int gc08a3_power_on(struct device *dev)
 589 {
 590         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 591         struct gc08a3 *gc08a3 = to_gc08a3(sd);
 592         int ret;
 593
 594         ret = regulator_bulk_enable(ARRAY_SIZE(gc08a3_supply_name),
 595                                     gc08a3->supplies);
 596         if (ret < 0) {
 597                 dev_err(gc08a3->dev, "failed to enable regulators: %d\n", ret);
 598                 return ret;
 599         }
 600
 601         ret = clk_prepare_enable(gc08a3->xclk);
 602         if (ret < 0) {
 603                 regulator_bulk_disable(ARRAY_SIZE(gc08a3_supply_name),
 604                                        gc08a3->supplies);
 605                 dev_err(gc08a3->dev, "clk prepare enable failed\n");
 606                 return ret;
 607         }
 608
 609         fsleep(GC08A3_SLEEP_US);
 610
 611         gpiod_set_value_cansleep(gc08a3->reset_gpio, 0);
 612         fsleep(GC08A3_SLEEP_US);
 613
 614         return 0;
 615 }
 616
 617 static int gc08a3_power_off(struct device *dev)
 618 {
 619         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 620         struct gc08a3 *gc08a3 = to_gc08a3(sd);
 621
 622         clk_disable_unprepare(gc08a3->xclk);
 623         gpiod_set_value_cansleep(gc08a3->reset_gpio, 1);
 624         regulator_bulk_disable(ARRAY_SIZE(gc08a3_supply_name),
 625                                gc08a3->supplies);
 626
 627         return 0;
 628 }
 629
 630 static int gc08a3_enum_mbus_code(struct v4l2_subdev *sd,
 631                                  struct v4l2_subdev_state *sd_state,
 632                                  struct v4l2_subdev_mbus_code_enum *code)
 633 {
 634         if (code->index > 0)
 635                 return -EINVAL;
 636
 637         code->code = GC08A3_MBUS_CODE;
 638
 639         return 0;
 640 }
 641
 642 static int gc08a3_enum_frame_size(struct v4l2_subdev *subdev,
 643                                   struct v4l2_subdev_state *sd_state,
 644                                   struct v4l2_subdev_frame_size_enum *fse)
 645 {
 646         if (fse->code != GC08A3_MBUS_CODE)
 647                 return -EINVAL;
 648
 649         if (fse->index >= ARRAY_SIZE(gc08a3_modes))
 650                 return -EINVAL;
 651
 652         fse->min_width = gc08a3_modes[fse->index].width;
 653         fse->max_width = gc08a3_modes[fse->index].width;
 654         fse->min_height = gc08a3_modes[fse->index].height;
 655         fse->max_height = gc08a3_modes[fse->index].height;
 656
 657         return 0;
 658 }
 659
 660 static int gc08a3_update_cur_mode_controls(struct gc08a3 *gc08a3,
 661                                            const struct gc08a3_mode *mode)
 662 {
 663         s64 exposure_max, h_blank;
 664         int ret;
 665
 666         ret = __v4l2_ctrl_modify_range(gc08a3->vblank,
 667                                        mode->vts_min - mode->height,
 668                                        GC08A3_VTS_MAX - mode->height, 1,
 669                                        mode->vts_def - mode->height);
 670         if (ret) {
 671                 dev_err(gc08a3->dev, "VB ctrl range update failed\n");
 672                 return ret;
 673         }
 674
 675         h_blank = mode->hts - mode->width;
 676         ret = __v4l2_ctrl_modify_range(gc08a3->hblank, h_blank, h_blank, 1,
 677                                        h_blank);
 678         if (ret) {
 679                 dev_err(gc08a3->dev, "HB ctrl range update failed\n");
 680                 return ret;
 681         }
 682
 683         exposure_max = mode->vts_def - GC08A3_EXP_MARGIN;
 684         ret = __v4l2_ctrl_modify_range(gc08a3->exposure, GC08A3_EXP_MIN,
 685                                        exposure_max, GC08A3_EXP_STEP,
 686                                        exposure_max);
 687         if (ret) {
 688                 dev_err(gc08a3->dev, "exposure ctrl range update failed\n");
 689                 return ret;
 690         }
 691
 692         return 0;
 693 }
 694
 695 static void gc08a3_update_pad_format(struct gc08a3 *gc08a3,
 696                                      const struct gc08a3_mode *mode,
 697                                      struct v4l2_mbus_framefmt *fmt)
 698 {
 699         fmt->width = mode->width;
 700         fmt->height = mode->height;
 701         fmt->code = GC08A3_MBUS_CODE;
 702         fmt->field = V4L2_FIELD_NONE;
 703         fmt->colorspace = V4L2_COLORSPACE_RAW;
 704         fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
 705         fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
 706         fmt->xfer_func = V4L2_XFER_FUNC_NONE;
 707 }
 708
 709 static int gc08a3_set_format(struct v4l2_subdev *sd,
 710                              struct v4l2_subdev_state *state,
 711                              struct v4l2_subdev_format *fmt)
 712 {
 713         struct gc08a3 *gc08a3 = to_gc08a3(sd);
 714         struct v4l2_mbus_framefmt *mbus_fmt;
 715         struct v4l2_rect *crop;
 716         const struct gc08a3_mode *mode;
 717
 718         mode = v4l2_find_nearest_size(gc08a3_modes, ARRAY_SIZE(gc08a3_modes),
 719                                       width, height, fmt->format.width,
 720                                       fmt->format.height);
 721
 722         /* update crop info to subdev state */
 723         crop = v4l2_subdev_state_get_crop(state, 0);
 724         crop->width = mode->width;
 725         crop->height = mode->height;
 726
 727         /* update fmt info to subdev state */
 728         gc08a3_update_pad_format(gc08a3, mode, &fmt->format);
 729         mbus_fmt = v4l2_subdev_state_get_format(state, 0);
 730         *mbus_fmt = fmt->format;
 731
 732         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
 733                 return 0;
 734
 735         gc08a3->cur_mode = mode;
 736         gc08a3_update_cur_mode_controls(gc08a3, mode);
 737
 738         return 0;
 739 }
 740
 741 static int gc08a3_get_selection(struct v4l2_subdev *sd,
 742                                 struct v4l2_subdev_state *state,
 743                                 struct v4l2_subdev_selection *sel)
 744 {
 745         switch (sel->target) {
 746         case V4L2_SEL_TGT_CROP_DEFAULT:
 747         case V4L2_SEL_TGT_CROP:
 748                 sel->r = *v4l2_subdev_state_get_crop(state, 0);
 749                 break;
 750         case V4L2_SEL_TGT_CROP_BOUNDS:
 751                 sel->r.top = 0;
 752                 sel->r.left = 0;
 753                 sel->r.width = GC08A3_NATIVE_WIDTH;
 754                 sel->r.height = GC08A3_NATIVE_HEIGHT;
 755                 break;
 756         default:
 757                 return -EINVAL;
 758         }
 759
 760         return 0;
 761 }
 762
 763 static int gc08a3_init_state(struct v4l2_subdev *sd,
 764                              struct v4l2_subdev_state *state)
 765 {
 766         struct v4l2_subdev_format fmt = {
 767                 .which = V4L2_SUBDEV_FORMAT_TRY,
 768                 .pad = 0,
 769                 .format = {
 770                         .code = GC08A3_MBUS_CODE,
 771                         .width = gc08a3_modes[0].width,
 772                         .height = gc08a3_modes[0].height,
 773                 },
 774         };
 775
 776         gc08a3_set_format(sd, state, &fmt);
 777
 778         return 0;
 779 }
 780
 781 static int gc08a3_set_ctrl_hflip(struct gc08a3 *gc08a3, u32 ctrl_val)
 782 {
 783         int ret;
 784         u64 val;
 785
 786         ret = cci_read(gc08a3->regmap, GC08A3_FLIP_REG, &val, NULL);
 787         if (ret) {
 788                 dev_err(gc08a3->dev, "read hflip register failed: %d\n", ret);
 789                 return ret;
 790         }
 791
 792         return cci_update_bits(gc08a3->regmap, GC08A3_FLIP_REG,
 793                                GC08A3_FLIP_H_MASK,
 794                                ctrl_val ? GC08A3_FLIP_H_MASK : 0, NULL);
 795 }
 796
 797 static int gc08a3_set_ctrl_vflip(struct gc08a3 *gc08a3, u32 ctrl_val)
 798 {
 799         int ret;
 800         u64 val;
 801
 802         ret = cci_read(gc08a3->regmap, GC08A3_FLIP_REG, &val, NULL);
 803         if (ret) {
 804                 dev_err(gc08a3->dev, "read vflip register failed: %d\n", ret);
 805                 return ret;
 806         }
 807
 808         return cci_update_bits(gc08a3->regmap, GC08A3_FLIP_REG,
 809                                GC08A3_FLIP_V_MASK,
 810                                ctrl_val ? GC08A3_FLIP_V_MASK : 0, NULL);
 811 }
 812
 813 static int gc08a3_test_pattern(struct gc08a3 *gc08a3, u32 pattern_menu)
 814 {
 815         u32 pattern;
 816         int ret;
 817
 818         if (pattern_menu) {
 819                 switch (pattern_menu) {
 820                 case 1:
 821                         pattern = 0x00;
 822                         break;
 823                 case 2:
 824                         pattern = 0x10;
 825                         break;
 826                 case 3:
 827                 case 4:
 828                 case 5:
 829                 case 6:
 830                 case 7:
 831                         pattern = pattern_menu + 1;
 832                         break;
 833                 default:
 834                         pattern = 0x00;
 835                         break;
 836                 }
 837
 838                 ret = cci_write(gc08a3->regmap, GC08A3_REG_TEST_PATTERN_IDX,
 839                                 pattern, NULL);
 840                 if (ret)
 841                         return ret;
 842
 843                 return cci_write(gc08a3->regmap, GC08A3_REG_TEST_PATTERN_EN,
 844                                  GC08A3_TEST_PATTERN_EN, NULL);
 845         } else {
 846                 return cci_write(gc08a3->regmap, GC08A3_REG_TEST_PATTERN_EN,
 847                                  0x00, NULL);
 848         }
 849 }
 850
 851 static int gc08a3_set_ctrl(struct v4l2_ctrl *ctrl)
 852 {
 853         struct gc08a3 *gc08a3 =
 854                 container_of(ctrl->handler, struct gc08a3, ctrls);
 855         int ret = 0;
 856         s64 exposure_max;
 857         struct v4l2_subdev_state *state;
 858         const struct v4l2_mbus_framefmt *format;
 859
 860         state = v4l2_subdev_get_locked_active_state(&gc08a3->sd);
 861         format = v4l2_subdev_state_get_format(state, 0);
 862
 863         if (ctrl->id == V4L2_CID_VBLANK) {
 864                 /* Update max exposure while meeting expected vblanking */
 865                 exposure_max = format->height + ctrl->val - GC08A3_EXP_MARGIN;
 866                 __v4l2_ctrl_modify_range(gc08a3->exposure,
 867                                          gc08a3->exposure->minimum,
 868                                          exposure_max, gc08a3->exposure->step,
 869                                          exposure_max);
 870         }
 871
 872         /*
 873          * Applying V4L2 control value only happens
 874          * when power is on for streaming.
 875          */
 876         if (!pm_runtime_get_if_active(gc08a3->dev))
 877                 return 0;
 878
 879         switch (ctrl->id) {
 880         case V4L2_CID_EXPOSURE:
 881                 ret = cci_write(gc08a3->regmap, GC08A3_EXP_REG,
 882                                 ctrl->val, NULL);
 883                 break;
 884
 885         case V4L2_CID_ANALOGUE_GAIN:
 886                 ret = cci_write(gc08a3->regmap, GC08A3_AGAIN_REG,
 887                                 ctrl->val, NULL);
 888                 break;
 889
 890         case V4L2_CID_VBLANK:
 891                 ret = cci_write(gc08a3->regmap, GC08A3_FRAME_LENGTH_REG,
 892                                 gc08a3->cur_mode->height + ctrl->val, NULL);
 893                 break;
 894
 895         case V4L2_CID_HFLIP:
 896                 ret = gc08a3_set_ctrl_hflip(gc08a3, ctrl->val);
 897                 break;
 898
 899         case V4L2_CID_VFLIP:
 900                 ret = gc08a3_set_ctrl_vflip(gc08a3, ctrl->val);
 901                 break;
 902
 903         case V4L2_CID_TEST_PATTERN:
 904                 ret = gc08a3_test_pattern(gc08a3, ctrl->val);
 905                 break;
 906
 907         default:
 908                 break;
 909         }
 910
 911         pm_runtime_put(gc08a3->dev);
 912
 913         return ret;
 914 }
 915
 916 static const struct v4l2_ctrl_ops gc08a3_ctrl_ops = {
 917         .s_ctrl = gc08a3_set_ctrl,
 918 };
 919
 920 static int gc08a3_start_streaming(struct gc08a3 *gc08a3)
 921 {
 922         const struct gc08a3_mode *mode;
 923         const struct gc08a3_reg_list *reg_list;
 924         int ret;
 925
 926         ret = pm_runtime_resume_and_get(gc08a3->dev);
 927         if (ret < 0)
 928                 return ret;
 929
 930         ret = cci_multi_reg_write(gc08a3->regmap,
 931                                   mode_table_common,
 932                                   ARRAY_SIZE(mode_table_common), NULL);
 933         if (ret)
 934                 goto err_rpm_put;
 935
 936         mode = gc08a3->cur_mode;
 937         reg_list = &mode->reg_list;
 938         ret = cci_multi_reg_write(gc08a3->regmap,
 939                                   reg_list->regs, reg_list->num_of_regs, NULL);
 940         if (ret < 0)
 941                 goto err_rpm_put;
 942
 943         ret = __v4l2_ctrl_handler_setup(&gc08a3->ctrls);
 944         if (ret < 0) {
 945                 dev_err(gc08a3->dev, "could not sync v4l2 controls\n");
 946                 goto err_rpm_put;
 947         }
 948
 949         ret = cci_write(gc08a3->regmap, GC08A3_STREAMING_REG, 1, NULL);
 950         if (ret < 0) {
 951                 dev_err(gc08a3->dev, "write STRAEMING_REG failed: %d\n", ret);
 952                 goto err_rpm_put;
 953         }
 954
 955         return 0;
 956
 957 err_rpm_put:
 958         pm_runtime_put(gc08a3->dev);
 959         return ret;
 960 }
 961
 962 static int gc08a3_stop_streaming(struct gc08a3 *gc08a3)
 963 {
 964         int ret;
 965
 966         ret = cci_write(gc08a3->regmap, GC08A3_STREAMING_REG, 0, NULL);
 967         if (ret < 0)
 968                 dev_err(gc08a3->dev, "could not sent stop streaming %d\n", ret);
 969
 970         pm_runtime_put(gc08a3->dev);
 971         return ret;
 972 }
 973
 974 static int gc08a3_s_stream(struct v4l2_subdev *subdev, int enable)
 975 {
 976         struct gc08a3 *gc08a3 = to_gc08a3(subdev);
 977         struct v4l2_subdev_state *state;
 978         int ret;
 979
 980         state = v4l2_subdev_lock_and_get_active_state(subdev);
 981
 982         if (enable)
 983                 ret = gc08a3_start_streaming(gc08a3);
 984         else
 985                 ret = gc08a3_stop_streaming(gc08a3);
 986
 987         v4l2_subdev_unlock_state(state);
 988
 989         return ret;
 990 }
 991
 992 static const struct v4l2_subdev_video_ops gc08a3_video_ops = {
 993         .s_stream = gc08a3_s_stream,
 994 };
 995
 996 static const struct v4l2_subdev_pad_ops gc08a3_subdev_pad_ops = {
 997         .enum_mbus_code = gc08a3_enum_mbus_code,
 998         .enum_frame_size = gc08a3_enum_frame_size,
 999         .get_fmt = v4l2_subdev_get_fmt,
1000         .set_fmt = gc08a3_set_format,
1001         .get_selection = gc08a3_get_selection,
1002 };
1003
1004 static const struct v4l2_subdev_core_ops gc08a3_core_ops = {
1005         .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1006         .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1007 };
1008
1009 static const struct v4l2_subdev_ops gc08a3_subdev_ops = {
1010         .core = &gc08a3_core_ops,
1011         .video = &gc08a3_video_ops,
1012         .pad = &gc08a3_subdev_pad_ops,
1013 };
1014
1015 static const struct v4l2_subdev_internal_ops gc08a3_internal_ops = {
1016         .init_state = gc08a3_init_state,
1017 };
1018
1019 static int gc08a3_get_regulators(struct device *dev, struct gc08a3 *gc08a3)
1020 {
1021         unsigned int i;
1022
1023         for (i = 0; i < ARRAY_SIZE(gc08a3_supply_name); i++)
1024                 gc08a3->supplies[i].supply = gc08a3_supply_name[i];
1025
1026         return devm_regulator_bulk_get(dev, ARRAY_SIZE(gc08a3_supply_name),
1027                                        gc08a3->supplies);
1028 }
1029
1030 static int gc08a3_parse_fwnode(struct gc08a3 *gc08a3)
1031 {
1032         struct fwnode_handle *endpoint;
1033         struct v4l2_fwnode_endpoint bus_cfg = {
1034                 .bus_type = V4L2_MBUS_CSI2_DPHY,
1035         };
1036         int ret;
1037         struct device *dev = gc08a3->dev;
1038
1039         endpoint =
1040                 fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0,
1041                                                 FWNODE_GRAPH_ENDPOINT_NEXT);
1042         if (!endpoint) {
1043                 dev_err(dev, "endpoint node not found\n");
1044                 return -EINVAL;
1045         }
1046
1047         ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg);
1048         if (ret) {
1049                 dev_err(dev, "parsing endpoint node failed\n");
1050                 goto done;
1051         }
1052
1053         ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies,
1054                                        bus_cfg.nr_of_link_frequencies,
1055                                        gc08a3_link_freq_menu_items,
1056                                        ARRAY_SIZE(gc08a3_link_freq_menu_items),
1057                                        &gc08a3->link_freq_bitmap);
1058         if (ret)
1059                 goto done;
1060
1061 done:
1062         v4l2_fwnode_endpoint_free(&bus_cfg);
1063         fwnode_handle_put(endpoint);
1064         return ret;
1065 }
1066
1067 static u64 gc08a3_to_pixel_rate(u32 f_index)
1068 {
1069         u64 pixel_rate =
1070                 gc08a3_link_freq_menu_items[f_index] * 2 * GC08A3_DATA_LANES;
1071
1072         return div_u64(pixel_rate, GC08A3_RGB_DEPTH);
1073 }
1074
1075 static int gc08a3_init_controls(struct gc08a3 *gc08a3)
1076 {
1077         struct i2c_client *client = v4l2_get_subdevdata(&gc08a3->sd);
1078         const struct gc08a3_mode *mode = &gc08a3_modes[0];
1079         const struct v4l2_ctrl_ops *ops = &gc08a3_ctrl_ops;
1080         struct v4l2_fwnode_device_properties props;
1081         struct v4l2_ctrl_handler *ctrl_hdlr;
1082         s64 exposure_max, h_blank;
1083         int ret;
1084
1085         ctrl_hdlr = &gc08a3->ctrls;
1086         ret = v4l2_ctrl_handler_init(ctrl_hdlr, 9);
1087         if (ret)
1088                 return ret;
1089
1090         gc08a3->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &gc08a3_ctrl_ops,
1091                                           V4L2_CID_HFLIP, 0, 1, 1, 0);
1092         gc08a3->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &gc08a3_ctrl_ops,
1093                                           V4L2_CID_VFLIP, 0, 1, 1, 0);
1094         v4l2_ctrl_cluster(2, &gc08a3->hflip);
1095
1096         gc08a3->link_freq =
1097         v4l2_ctrl_new_int_menu(ctrl_hdlr,
1098                                &gc08a3_ctrl_ops,
1099                                V4L2_CID_LINK_FREQ,
1100                                ARRAY_SIZE(gc08a3_link_freq_menu_items) - 1,
1101                                0,
1102                                gc08a3_link_freq_menu_items);
1103         if (gc08a3->link_freq)
1104                 gc08a3->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1105
1106         gc08a3->pixel_rate =
1107                 v4l2_ctrl_new_std(ctrl_hdlr,
1108                                   &gc08a3_ctrl_ops,
1109                                   V4L2_CID_PIXEL_RATE, 0,
1110                                   gc08a3_to_pixel_rate(0),
1111                                   1,
1112                                   gc08a3_to_pixel_rate(0));
1113
1114         gc08a3->vblank =
1115                 v4l2_ctrl_new_std(ctrl_hdlr,
1116                                   &gc08a3_ctrl_ops, V4L2_CID_VBLANK,
1117                                   mode->vts_min - mode->height,
1118                                   GC08A3_VTS_MAX - mode->height, 1,
1119                                   mode->vts_def - mode->height);
1120
1121         h_blank = mode->hts - mode->width;
1122         gc08a3->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &gc08a3_ctrl_ops,
1123                                            V4L2_CID_HBLANK, h_blank, h_blank, 1,
1124                                            h_blank);
1125         if (gc08a3->hblank)
1126                 gc08a3->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1127
1128         v4l2_ctrl_new_std(ctrl_hdlr, &gc08a3_ctrl_ops,
1129                           V4L2_CID_ANALOGUE_GAIN, GC08A3_AGAIN_MIN,
1130                           GC08A3_AGAIN_MAX, GC08A3_AGAIN_STEP,
1131                           GC08A3_AGAIN_MIN);
1132
1133         exposure_max = mode->vts_def - GC08A3_EXP_MARGIN;
1134         gc08a3->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &gc08a3_ctrl_ops,
1135                                              V4L2_CID_EXPOSURE, GC08A3_EXP_MIN,
1136                                              exposure_max, GC08A3_EXP_STEP,
1137                                              exposure_max);
1138
1139         v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &gc08a3_ctrl_ops,
1140                                      V4L2_CID_TEST_PATTERN,
1141                                      ARRAY_SIZE(gc08a3_test_pattern_menu) - 1,
1142                                      0, 0, gc08a3_test_pattern_menu);
1143
1144         /* register properties to fwnode (e.g. rotation, orientation) */
1145         ret = v4l2_fwnode_device_parse(&client->dev, &props);
1146         if (ret)
1147                 goto error_ctrls;
1148
1149         ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, ops, &props);
1150         if (ret)
1151                 goto error_ctrls;
1152
1153         if (ctrl_hdlr->error) {
1154                 ret = ctrl_hdlr->error;
1155                 goto error_ctrls;
1156         }
1157
1158         gc08a3->sd.ctrl_handler = ctrl_hdlr;
1159
1160         return 0;
1161
1162 error_ctrls:
1163         v4l2_ctrl_handler_free(ctrl_hdlr);
1164
1165         return ret;
1166 }
1167
1168 static int gc08a3_identify_module(struct gc08a3 *gc08a3)
1169 {
1170         u64 val;
1171         int ret;
1172
1173         ret = cci_read(gc08a3->regmap, GC08A3_REG_CHIP_ID, &val, NULL);
1174         if (ret) {
1175                 dev_err(gc08a3->dev, "failed to read chip id");
1176                 return ret;
1177         }
1178
1179         if (val != GC08A3_CHIP_ID) {
1180                 dev_err(gc08a3->dev, "chip id mismatch: 0x%x!=0x%llx",
1181                         GC08A3_CHIP_ID, val);
1182                 return -ENXIO;
1183         }
1184
1185         return 0;
1186 }
1187
1188 static int gc08a3_probe(struct i2c_client *client)
1189 {
1190         struct device *dev = &client->dev;
1191         struct gc08a3 *gc08a3;
1192         int ret;
1193
1194         gc08a3 = devm_kzalloc(dev, sizeof(*gc08a3), GFP_KERNEL);
1195         if (!gc08a3)
1196                 return -ENOMEM;
1197
1198         gc08a3->dev = dev;
1199
1200         ret = gc08a3_parse_fwnode(gc08a3);
1201         if (ret)
1202                 return ret;
1203
1204         gc08a3->regmap = devm_cci_regmap_init_i2c(client, 16);
1205         if (IS_ERR(gc08a3->regmap))
1206                 return dev_err_probe(dev, PTR_ERR(gc08a3->regmap),
1207                                      "failed to init CCI\n");
1208
1209         gc08a3->xclk = devm_clk_get(dev, NULL);
1210         if (IS_ERR(gc08a3->xclk))
1211                 return dev_err_probe(dev, PTR_ERR(gc08a3->xclk),
1212                                      "failed to get xclk\n");
1213
1214         ret = clk_set_rate(gc08a3->xclk, GC08A3_DEFAULT_CLK_FREQ);
1215         if (ret)
1216                 return dev_err_probe(dev, ret,
1217                                      "failed to set xclk frequency\n");
1218
1219         ret = gc08a3_get_regulators(dev, gc08a3);
1220         if (ret < 0)
1221                 return dev_err_probe(dev, ret,
1222                                      "failed to get regulators\n");
1223
1224         gc08a3->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1225         if (IS_ERR(gc08a3->reset_gpio))
1226                 return dev_err_probe(dev, PTR_ERR(gc08a3->reset_gpio),
1227                                      "failed to get gpio\n");
1228
1229         v4l2_i2c_subdev_init(&gc08a3->sd, client, &gc08a3_subdev_ops);
1230         gc08a3->sd.internal_ops = &gc08a3_internal_ops;
1231         gc08a3->cur_mode = &gc08a3_modes[0];
1232
1233         ret = gc08a3_power_on(gc08a3->dev);
1234         if (ret)
1235                 return dev_err_probe(dev, ret,
1236                                      "failed to sensor power on\n");
1237
1238         ret = gc08a3_identify_module(gc08a3);
1239         if (ret) {
1240                 dev_err(&client->dev, "failed to find sensor: %d\n", ret);
1241                 goto err_power_off;
1242         }
1243
1244         ret = gc08a3_init_controls(gc08a3);
1245         if (ret) {
1246                 dev_err(&client->dev, "failed to init controls: %d", ret);
1247                 goto err_power_off;
1248         }
1249
1250         gc08a3->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1251                             V4L2_SUBDEV_FL_HAS_EVENTS;
1252         gc08a3->pad.flags = MEDIA_PAD_FL_SOURCE;
1253         gc08a3->sd.dev = &client->dev;
1254         gc08a3->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1255
1256         ret = media_entity_pads_init(&gc08a3->sd.entity, 1, &gc08a3->pad);
1257         if (ret < 0) {
1258                 dev_err(dev, "could not register media entity\n");
1259                 goto err_v4l2_ctrl_handler_free;
1260         }
1261
1262         gc08a3->sd.state_lock = gc08a3->ctrls.lock;
1263         ret = v4l2_subdev_init_finalize(&gc08a3->sd);
1264         if (ret < 0) {
1265                 dev_err(dev, "v4l2 subdev init error: %d\n", ret);
1266                 goto err_media_entity_cleanup;
1267         }
1268
1269         pm_runtime_set_active(gc08a3->dev);
1270         pm_runtime_enable(gc08a3->dev);
1271         pm_runtime_set_autosuspend_delay(gc08a3->dev, 1000);
1272         pm_runtime_use_autosuspend(gc08a3->dev);
1273         pm_runtime_idle(gc08a3->dev);
1274
1275         ret = v4l2_async_register_subdev_sensor(&gc08a3->sd);
1276         if (ret < 0) {
1277                 dev_err(dev, "could not register v4l2 device\n");
1278                 goto err_rpm;
1279         }
1280
1281         return 0;
1282
1283 err_rpm:
1284         pm_runtime_disable(gc08a3->dev);
1285         v4l2_subdev_cleanup(&gc08a3->sd);
1286
1287 err_media_entity_cleanup:
1288         media_entity_cleanup(&gc08a3->sd.entity);
1289
1290 err_v4l2_ctrl_handler_free:
1291         v4l2_ctrl_handler_free(gc08a3->sd.ctrl_handler);
1292
1293 err_power_off:
1294         gc08a3_power_off(gc08a3->dev);
1295
1296         return ret;
1297 }
1298
1299 static void gc08a3_remove(struct i2c_client *client)
1300 {
1301         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1302         struct gc08a3 *gc08a3 = to_gc08a3(sd);
1303
1304         v4l2_async_unregister_subdev(&gc08a3->sd);
1305         v4l2_subdev_cleanup(sd);
1306         media_entity_cleanup(&gc08a3->sd.entity);
1307         v4l2_ctrl_handler_free(&gc08a3->ctrls);
1308
1309         pm_runtime_disable(&client->dev);
1310         if (!pm_runtime_status_suspended(&client->dev))
1311                 gc08a3_power_off(gc08a3->dev);
1312         pm_runtime_set_suspended(&client->dev);
1313 }
1314
1315 static const struct of_device_id gc08a3_of_match[] = {
1316         { .compatible = "galaxycore,gc08a3" },
1317         {}
1318 };
1319 MODULE_DEVICE_TABLE(of, gc08a3_of_match);
1320
1321 static DEFINE_RUNTIME_DEV_PM_OPS(gc08a3_pm_ops,
1322                                  gc08a3_power_off,
1323                                  gc08a3_power_on,
1324                                  NULL);
1325
1326 static struct i2c_driver gc08a3_i2c_driver = {
1327         .driver = {
1328                 .of_match_table = gc08a3_of_match,
1329                 .pm = pm_ptr(&gc08a3_pm_ops),
1330                 .name  = "gc08a3",
1331         },
1332         .probe  = gc08a3_probe,
1333         .remove = gc08a3_remove,
1334 };
1335 module_i2c_driver(gc08a3_i2c_driver);
1336
1337 MODULE_DESCRIPTION("GalaxyCore gc08a3 Camera driver");
1338 MODULE_AUTHOR("Zhi Mao <[email protected]>");
1339 MODULE_LICENSE("GPL");