drivers/clk/rockchip/clk-rv1126.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
   4  * Author: Finley Xiao <[email protected]>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/syscore_ops.h>
  13 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
  14 #include "clk.h"
  15
  16 #define RV1126_GMAC_CON                 0x460
  17 #define RV1126_GRF_IOFUNC_CON1          0x10264
  18 #define RV1126_GRF_SOC_STATUS0          0x10
  19
  20 #define RV1126_FRAC_MAX_PRATE           1200000000
  21 #define RV1126_CSIOUT_FRAC_MAX_PRATE    300000000
  22
  23 enum rv1126_pmu_plls {
  24         gpll,
  25 };
  26
  27 enum rv1126_plls {
  28         apll, dpll, cpll, hpll,
  29 };
  30
  31 static struct rockchip_pll_rate_table rv1126_pll_rates[] = {
  32         /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
  33         RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
  34         RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
  35         RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
  36         RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
  37         RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
  38         RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
  39         RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
  40         RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
  41         RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
  42         RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
  43         RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
  44         RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
  45         RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
  46         RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
  47         RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
  48         RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
  49         RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
  50         RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
  51         RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
  52         RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
  53         RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
  54         RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
  55         RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
  56         RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
  57         RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
  58         RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
  59         RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
  60         RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
  61         RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
  62         RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
  63         RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
  64         RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
  65         RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
  66         RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
  67         RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
  68         RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
  69         RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0),
  70         RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
  71         RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
  72         RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0),
  73         RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
  74         RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
  75         RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
  76         RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
  77         RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
  78         { /* sentinel */ },
  79 };
  80
  81 #define RV1126_DIV_ACLK_CORE_MASK       0xf
  82 #define RV1126_DIV_ACLK_CORE_SHIFT      4
  83 #define RV1126_DIV_PCLK_DBG_MASK        0x7
  84 #define RV1126_DIV_PCLK_DBG_SHIFT       0
  85
  86 #define RV1126_CLKSEL1(_aclk_core, _pclk_dbg)                           \
  87 {                                                                       \
  88         .reg = RV1126_CLKSEL_CON(1),                                    \
  89         .val = HIWORD_UPDATE(_aclk_core, RV1126_DIV_ACLK_CORE_MASK,     \
  90                              RV1126_DIV_ACLK_CORE_SHIFT) |              \
  91                HIWORD_UPDATE(_pclk_dbg, RV1126_DIV_PCLK_DBG_MASK,       \
  92                              RV1126_DIV_PCLK_DBG_SHIFT),                \
  93 }
  94
  95 #define RV1126_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg)               \
  96 {                                                                       \
  97         .prate = _prate,                                                \
  98         .divs = {                                                       \
  99                 RV1126_CLKSEL1(_aclk_core, _pclk_dbg),                  \
 100         },                                                              \
 101 }
 102
 103 static struct rockchip_cpuclk_rate_table rv1126_cpuclk_rates[] __initdata = {
 104         RV1126_CPUCLK_RATE(1608000000, 1, 7),
 105         RV1126_CPUCLK_RATE(1584000000, 1, 7),
 106         RV1126_CPUCLK_RATE(1560000000, 1, 7),
 107         RV1126_CPUCLK_RATE(1536000000, 1, 7),
 108         RV1126_CPUCLK_RATE(1512000000, 1, 7),
 109         RV1126_CPUCLK_RATE(1488000000, 1, 5),
 110         RV1126_CPUCLK_RATE(1464000000, 1, 5),
 111         RV1126_CPUCLK_RATE(1440000000, 1, 5),
 112         RV1126_CPUCLK_RATE(1416000000, 1, 5),
 113         RV1126_CPUCLK_RATE(1392000000, 1, 5),
 114         RV1126_CPUCLK_RATE(1368000000, 1, 5),
 115         RV1126_CPUCLK_RATE(1344000000, 1, 5),
 116         RV1126_CPUCLK_RATE(1320000000, 1, 5),
 117         RV1126_CPUCLK_RATE(1296000000, 1, 5),
 118         RV1126_CPUCLK_RATE(1272000000, 1, 5),
 119         RV1126_CPUCLK_RATE(1248000000, 1, 5),
 120         RV1126_CPUCLK_RATE(1224000000, 1, 5),
 121         RV1126_CPUCLK_RATE(1200000000, 1, 5),
 122         RV1126_CPUCLK_RATE(1104000000, 1, 5),
 123         RV1126_CPUCLK_RATE(1008000000, 1, 5),
 124         RV1126_CPUCLK_RATE(912000000, 1, 5),
 125         RV1126_CPUCLK_RATE(816000000, 1, 3),
 126         RV1126_CPUCLK_RATE(696000000, 1, 3),
 127         RV1126_CPUCLK_RATE(600000000, 1, 3),
 128         RV1126_CPUCLK_RATE(408000000, 1, 1),
 129         RV1126_CPUCLK_RATE(312000000, 1, 1),
 130         RV1126_CPUCLK_RATE(216000000,  1, 1),
 131         RV1126_CPUCLK_RATE(96000000, 1, 1),
 132 };
 133
 134 static const struct rockchip_cpuclk_reg_data rv1126_cpuclk_data = {
 135         .core_reg[0] = RV1126_CLKSEL_CON(0),
 136         .div_core_shift[0] = 0,
 137         .div_core_mask[0] = 0x1f,
 138         .num_cores = 1,
 139         .mux_core_alt = 0,
 140         .mux_core_main = 2,
 141         .mux_core_shift = 6,
 142         .mux_core_mask = 0x3,
 143 };
 144
 145 PNAME(mux_pll_p)                        = { "xin24m" };
 146 PNAME(mux_rtc32k_p)                     = { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" };
 147 PNAME(mux_wifi_p)                       = { "clk_wifi_osc0", "clk_wifi_div" };
 148 PNAME(mux_gpll_usb480m_cpll_xin24m_p)   = { "gpll", "usb480m", "cpll", "xin24m" };
 149 PNAME(mux_uart1_p)                      = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
 150 PNAME(mux_xin24m_gpll_p)                = { "xin24m", "gpll" };
 151 PNAME(mux_gpll_xin24m_p)                = { "gpll", "xin24m" };
 152 PNAME(mux_xin24m_32k_p)                 = { "xin24m", "clk_rtc32k" };
 153 PNAME(mux_usbphy_otg_ref_p)             = { "clk_ref12m", "xin_osc0_div2_usbphyref_otg" };
 154 PNAME(mux_usbphy_host_ref_p)            = { "clk_ref12m", "xin_osc0_div2_usbphyref_host" };
 155 PNAME(mux_mipidsiphy_ref_p)             = { "clk_ref24m", "xin_osc0_mipiphyref" };
 156 PNAME(mux_usb480m_p)                    = { "xin24m", "usb480m_phy", "clk_rtc32k" };
 157 PNAME(mux_armclk_p)                     = { "gpll", "cpll", "apll" };
 158 PNAME(mux_gpll_cpll_dpll_p)             = { "gpll", "cpll", "dummy_dpll" };
 159 PNAME(mux_gpll_cpll_p)                  = { "gpll", "cpll" };
 160 PNAME(mux_hclk_pclk_pdbus_p)            = { "gpll", "dummy_cpll" };
 161 PNAME(mux_gpll_cpll_usb480m_xin24m_p)   = { "gpll", "cpll", "usb480m", "xin24m" };
 162 PNAME(mux_uart0_p)                      = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
 163 PNAME(mux_uart2_p)                      = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
 164 PNAME(mux_uart3_p)                      = { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" };
 165 PNAME(mux_uart4_p)                      = { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" };
 166 PNAME(mux_uart5_p)                      = { "sclk_uart5_div", "sclk_uart5_frac", "xin24m" };
 167 PNAME(mux_cpll_gpll_p)                  = { "cpll", "gpll" };
 168 PNAME(mux_i2s0_tx_p)                    = { "mclk_i2s0_tx_div", "mclk_i2s0_tx_fracdiv", "i2s0_mclkin", "xin12m" };
 169 PNAME(mux_i2s0_rx_p)                    = { "mclk_i2s0_rx_div", "mclk_i2s0_rx_fracdiv", "i2s0_mclkin", "xin12m" };
 170 PNAME(mux_i2s0_tx_out2io_p)             = { "mclk_i2s0_tx", "xin12m" };
 171 PNAME(mux_i2s0_rx_out2io_p)             = { "mclk_i2s0_rx", "xin12m" };
 172 PNAME(mux_i2s1_p)                       = { "mclk_i2s1_div", "mclk_i2s1_fracdiv", "i2s1_mclkin", "xin12m" };
 173 PNAME(mux_i2s1_out2io_p)                = { "mclk_i2s1", "xin12m" };
 174 PNAME(mux_i2s2_p)                       = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xin12m" };
 175 PNAME(mux_i2s2_out2io_p)                = { "mclk_i2s2", "xin12m" };
 176 PNAME(mux_gpll_cpll_xin24m_p)           = { "gpll", "cpll", "xin24m" };
 177 PNAME(mux_audpwm_p)                     = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
 178 PNAME(mux_dclk_vop_p)                   = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
 179 PNAME(mux_usb480m_gpll_p)               = { "usb480m", "gpll" };
 180 PNAME(clk_gmac_src_m0_p)                = { "clk_gmac_div", "clk_gmac_rgmii_m0" };
 181 PNAME(clk_gmac_src_m1_p)                = { "clk_gmac_div", "clk_gmac_rgmii_m1" };
 182 PNAME(mux_clk_gmac_src_p)               = { "clk_gmac_src_m0", "clk_gmac_src_m1" };
 183 PNAME(mux_rgmii_clk_p)                  = { "clk_gmac_tx_div50", "clk_gmac_tx_div5", "clk_gmac_tx_src", "clk_gmac_tx_src"};
 184 PNAME(mux_rmii_clk_p)                   = { "clk_gmac_rx_div20", "clk_gmac_rx_div2" };
 185 PNAME(mux_gmac_tx_rx_p)                 = { "rgmii_mode_clk", "rmii_mode_clk" };
 186 PNAME(mux_dpll_gpll_p)                  = { "dpll", "gpll" };
 187
 188 static u32 rgmii_mux_idx[]              = { 2, 3, 0, 1 };
 189
 190 static struct rockchip_pll_clock rv1126_pmu_pll_clks[] __initdata = {
 191         [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll",  mux_pll_p,
 192                      0, RV1126_PMU_PLL_CON(0),
 193                      RV1126_PMU_MODE, 0, 3, 0, rv1126_pll_rates),
 194 };
 195
 196 static struct rockchip_pll_clock rv1126_pll_clks[] __initdata = {
 197         [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
 198                      0, RV1126_PLL_CON(0),
 199                      RV1126_MODE_CON, 0, 0, 0, rv1126_pll_rates),
 200         [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
 201                      0, RV1126_PLL_CON(8),
 202                      RV1126_MODE_CON, 2, 1, 0, NULL),
 203         [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
 204                      0, RV1126_PLL_CON(16),
 205                      RV1126_MODE_CON, 4, 2, 0, rv1126_pll_rates),
 206         [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
 207                      0, RV1126_PLL_CON(24),
 208                      RV1126_MODE_CON, 6, 4, 0, rv1126_pll_rates),
 209 };
 210
 211 #define MFLAGS CLK_MUX_HIWORD_MASK
 212 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
 213 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
 214
 215 static struct rockchip_clk_branch rv1126_rtc32k_fracmux __initdata =
 216         MUX(CLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
 217                         RV1126_PMU_CLKSEL_CON(0), 7, 2, MFLAGS);
 218
 219 static struct rockchip_clk_branch rv1126_uart1_fracmux __initdata =
 220         MUX(SCLK_UART1_MUX, "sclk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
 221                         RV1126_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
 222
 223 static struct rockchip_clk_branch rv1126_uart0_fracmux __initdata =
 224         MUX(SCLK_UART0_MUX, "sclk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
 225                         RV1126_CLKSEL_CON(10), 10, 2, MFLAGS);
 226
 227 static struct rockchip_clk_branch rv1126_uart2_fracmux __initdata =
 228         MUX(SCLK_UART2_MUX, "sclk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
 229                         RV1126_CLKSEL_CON(12), 10, 2, MFLAGS);
 230
 231 static struct rockchip_clk_branch rv1126_uart3_fracmux __initdata =
 232         MUX(SCLK_UART3_MUX, "sclk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
 233                         RV1126_CLKSEL_CON(14), 10, 2, MFLAGS);
 234
 235 static struct rockchip_clk_branch rv1126_uart4_fracmux __initdata =
 236         MUX(SCLK_UART4_MUX, "sclk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
 237                         RV1126_CLKSEL_CON(16), 10, 2, MFLAGS);
 238
 239 static struct rockchip_clk_branch rv1126_uart5_fracmux __initdata =
 240         MUX(SCLK_UART5_MUX, "sclk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
 241                         RV1126_CLKSEL_CON(18), 10, 2, MFLAGS);
 242
 243 static struct rockchip_clk_branch rv1126_i2s0_tx_fracmux __initdata =
 244         MUX(MCLK_I2S0_TX_MUX, "mclk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
 245                         RV1126_CLKSEL_CON(30), 0, 2, MFLAGS);
 246
 247 static struct rockchip_clk_branch rv1126_i2s0_rx_fracmux __initdata =
 248         MUX(MCLK_I2S0_RX_MUX, "mclk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
 249                         RV1126_CLKSEL_CON(30), 2, 2, MFLAGS);
 250
 251 static struct rockchip_clk_branch rv1126_i2s1_fracmux __initdata =
 252         MUX(MCLK_I2S1_MUX, "mclk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
 253                         RV1126_CLKSEL_CON(31), 8, 2, MFLAGS);
 254
 255 static struct rockchip_clk_branch rv1126_i2s2_fracmux __initdata =
 256         MUX(MCLK_I2S2_MUX, "mclk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
 257                         RV1126_CLKSEL_CON(33), 8, 2, MFLAGS);
 258
 259 static struct rockchip_clk_branch rv1126_audpwm_fracmux __initdata =
 260         MUX(SCLK_AUDPWM_MUX, "mclk_audpwm_mux", mux_audpwm_p, CLK_SET_RATE_PARENT,
 261                         RV1126_CLKSEL_CON(36), 8, 2, MFLAGS);
 262
 263 static struct rockchip_clk_branch rv1126_dclk_vop_fracmux __initdata =
 264         MUX(DCLK_VOP_MUX, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
 265             RV1126_CLKSEL_CON(47), 10, 2, MFLAGS);
 266
 267 static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
 268         /*
 269          * Clock-Architecture Diagram 2
 270          */
 271         /* PD_PMU */
 272         COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "gpll", CLK_IGNORE_UNUSED,
 273                         RV1126_PMU_CLKSEL_CON(1), 0, 5, DFLAGS,
 274                         RV1126_PMU_CLKGATE_CON(0), 0, GFLAGS),
 275
 276         COMPOSITE_FRACMUX(CLK_OSC0_DIV32K, "clk_osc0_div32k", "xin24m", CLK_IGNORE_UNUSED,
 277                         RV1126_PMU_CLKSEL_CON(13), 0,
 278                         RV1126_PMU_CLKGATE_CON(2), 9, GFLAGS,
 279                         &rv1126_rtc32k_fracmux),
 280
 281         COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "gpll", 0,
 282                         RV1126_PMU_CLKSEL_CON(12), 0, 6, DFLAGS,
 283                         RV1126_PMU_CLKGATE_CON(2), 10, GFLAGS),
 284         GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
 285                         RV1126_PMU_CLKGATE_CON(2), 11, GFLAGS),
 286         MUX(CLK_WIFI, "clk_wifi", mux_wifi_p, CLK_SET_RATE_PARENT,
 287                         RV1126_PMU_CLKSEL_CON(12), 8, 1, MFLAGS),
 288
 289         GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
 290                         RV1126_PMU_CLKGATE_CON(0), 1, GFLAGS),
 291
 292         GATE(PCLK_UART1, "pclk_uart1", "pclk_pdpmu", 0,
 293                         RV1126_PMU_CLKGATE_CON(0), 11, GFLAGS),
 294         COMPOSITE(SCLK_UART1_DIV, "sclk_uart1_div", mux_gpll_usb480m_cpll_xin24m_p, 0,
 295                         RV1126_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
 296                         RV1126_PMU_CLKGATE_CON(0), 12, GFLAGS),
 297         COMPOSITE_FRACMUX(SCLK_UART1_FRACDIV, "sclk_uart1_fracdiv", "sclk_uart1_div",
 298                         CLK_SET_RATE_PARENT,
 299                         RV1126_PMU_CLKSEL_CON(5), 0,
 300                         RV1126_PMU_CLKGATE_CON(0), 13, GFLAGS,
 301                         &rv1126_uart1_fracmux),
 302         GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
 303                         RV1126_PMU_CLKGATE_CON(0), 14, GFLAGS),
 304
 305         GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
 306                         RV1126_PMU_CLKGATE_CON(0), 5, GFLAGS),
 307         COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "gpll", 0,
 308                         RV1126_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
 309                         RV1126_PMU_CLKGATE_CON(0), 6, GFLAGS),
 310         GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pdpmu", 0,
 311                         RV1126_PMU_CLKGATE_CON(0), 9, GFLAGS),
 312         COMPOSITE_NOMUX(CLK_I2C2, "clk_i2c2", "gpll", 0,
 313                         RV1126_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
 314                         RV1126_PMU_CLKGATE_CON(0), 10, GFLAGS),
 315
 316         GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
 317                         RV1126_PMU_CLKGATE_CON(1), 2, GFLAGS),
 318         GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
 319                         RV1126_PMU_CLKGATE_CON(1), 0, GFLAGS),
 320         COMPOSITE(CLK_PWM0, "clk_pwm0", mux_xin24m_gpll_p, 0,
 321                         RV1126_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
 322                         RV1126_PMU_CLKGATE_CON(1), 1, GFLAGS),
 323         GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
 324                         RV1126_PMU_CLKGATE_CON(1), 5, GFLAGS),
 325         GATE(PCLK_PWM1, "pclk_pwm1", "pclk_pdpmu", 0,
 326                         RV1126_PMU_CLKGATE_CON(1), 3, GFLAGS),
 327         COMPOSITE(CLK_PWM1, "clk_pwm1", mux_xin24m_gpll_p, 0,
 328                         RV1126_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 7, DFLAGS,
 329                         RV1126_PMU_CLKGATE_CON(1), 4, GFLAGS),
 330
 331         GATE(PCLK_SPI0, "pclk_spi0", "pclk_pdpmu", 0,
 332                         RV1126_PMU_CLKGATE_CON(1), 11, GFLAGS),
 333         COMPOSITE(CLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
 334                         RV1126_PMU_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 7, DFLAGS,
 335                         RV1126_PMU_CLKGATE_CON(1), 12, GFLAGS),
 336
 337         GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
 338                         RV1126_PMU_CLKGATE_CON(1), 9, GFLAGS),
 339         COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_xin24m_32k_p, 0,
 340                         RV1126_PMU_CLKSEL_CON(8), 15, 1, MFLAGS,
 341                         RV1126_PMU_CLKGATE_CON(1), 10, GFLAGS),
 342
 343         GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
 344                         RV1126_PMU_CLKGATE_CON(2), 6, GFLAGS),
 345         GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
 346                         RV1126_PMU_CLKGATE_CON(2), 5, GFLAGS),
 347         GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
 348                         RV1126_PMU_CLKGATE_CON(2), 7, GFLAGS),
 349
 350         COMPOSITE_NOMUX(CLK_REF12M, "clk_ref12m", "gpll", 0,
 351                         RV1126_PMU_CLKSEL_CON(7), 8, 7, DFLAGS,
 352                         RV1126_PMU_CLKGATE_CON(1), 15, GFLAGS),
 353         GATE(0, "xin_osc0_usbphyref_otg", "xin24m", 0,
 354                         RV1126_PMU_CLKGATE_CON(1), 6, GFLAGS),
 355         GATE(0, "xin_osc0_usbphyref_host", "xin24m", 0,
 356                         RV1126_PMU_CLKGATE_CON(1), 7, GFLAGS),
 357         FACTOR(0, "xin_osc0_div2_usbphyref_otg", "xin_osc0_usbphyref_otg", 0, 1, 2),
 358         FACTOR(0, "xin_osc0_div2_usbphyref_host", "xin_osc0_usbphyref_host", 0, 1, 2),
 359         MUX(CLK_USBPHY_OTG_REF, "clk_usbphy_otg_ref", mux_usbphy_otg_ref_p, CLK_SET_RATE_PARENT,
 360                         RV1126_PMU_CLKSEL_CON(7), 6, 1, MFLAGS),
 361         MUX(CLK_USBPHY_HOST_REF, "clk_usbphy_host_ref", mux_usbphy_host_ref_p, CLK_SET_RATE_PARENT,
 362                         RV1126_PMU_CLKSEL_CON(7), 7, 1, MFLAGS),
 363
 364         COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "gpll", 0,
 365                         RV1126_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
 366                         RV1126_PMU_CLKGATE_CON(1), 14, GFLAGS),
 367         GATE(0, "xin_osc0_mipiphyref", "xin24m", 0,
 368                         RV1126_PMU_CLKGATE_CON(1), 8, GFLAGS),
 369         MUX(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
 370                         RV1126_PMU_CLKSEL_CON(7), 15, 1, MFLAGS),
 371
 372         GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED,
 373                         RV1126_PMU_CLKGATE_CON(0), 15, GFLAGS),
 374
 375         GATE(PCLK_PMUSGRF, "pclk_pmusgrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
 376                         RV1126_PMU_CLKGATE_CON(0), 4, GFLAGS),
 377         GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
 378                         RV1126_PMU_CLKGATE_CON(1), 13, GFLAGS),
 379         GATE(PCLK_PMUCRU, "pclk_pmucru", "pclk_pdpmu", CLK_IGNORE_UNUSED,
 380                         RV1126_PMU_CLKGATE_CON(2), 4, GFLAGS),
 381         GATE(PCLK_CHIPVEROTP, "pclk_chipverotp", "pclk_pdpmu", CLK_IGNORE_UNUSED,
 382                         RV1126_PMU_CLKGATE_CON(2), 0, GFLAGS),
 383         GATE(PCLK_PDPMU_NIU, "pclk_pdpmu_niu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
 384                         RV1126_PMU_CLKGATE_CON(0), 2, GFLAGS),
 385
 386         GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pdpmu", 0,
 387                         RV1126_PMU_CLKGATE_CON(0), 7, GFLAGS),
 388 };
 389
 390 static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
 391         /*
 392          * Clock-Architecture Diagram 1
 393          */
 394         MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
 395                         RV1126_MODE_CON, 10, 2, MFLAGS),
 396         FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
 397
 398         /*
 399          * Clock-Architecture Diagram 3
 400          */
 401         /* PD_CORE */
 402         COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
 403                         RV1126_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 404                         RV1126_CLKGATE_CON(0), 6, GFLAGS),
 405         GATE(CLK_CORE_CPUPVTM, "clk_core_cpupvtm", "armclk", 0,
 406                         RV1126_CLKGATE_CON(0), 12, GFLAGS),
 407         GATE(PCLK_CPUPVTM, "pclk_cpupvtm", "pclk_dbg", 0,
 408                         RV1126_CLKGATE_CON(0), 10, GFLAGS),
 409         GATE(CLK_CPUPVTM, "clk_cpupvtm", "xin24m", 0,
 410                         RV1126_CLKGATE_CON(0), 11, GFLAGS),
 411         COMPOSITE_NOMUX(HCLK_PDCORE_NIU, "hclk_pdcore_niu", "gpll", CLK_IGNORE_UNUSED,
 412                         RV1126_CLKSEL_CON(0), 8, 5, DFLAGS,
 413                         RV1126_CLKGATE_CON(0), 8, GFLAGS),
 414
 415         /*
 416          * Clock-Architecture Diagram 4
 417          */
 418         /* PD_BUS */
 419         COMPOSITE(0, "aclk_pdbus_pre", mux_gpll_cpll_dpll_p, CLK_IGNORE_UNUSED,
 420                         RV1126_CLKSEL_CON(2), 6, 2, MFLAGS, 0, 5, DFLAGS,
 421                         RV1126_CLKGATE_CON(2), 0, GFLAGS),
 422         GATE(ACLK_PDBUS, "aclk_pdbus", "aclk_pdbus_pre", CLK_IGNORE_UNUSED,
 423                         RV1126_CLKGATE_CON(2), 11, GFLAGS),
 424         COMPOSITE(0, "hclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
 425                         RV1126_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 5, DFLAGS,
 426                         RV1126_CLKGATE_CON(2), 1, GFLAGS),
 427         GATE(HCLK_PDBUS, "hclk_pdbus", "hclk_pdbus_pre", CLK_IGNORE_UNUSED,
 428                         RV1126_CLKGATE_CON(2), 12, GFLAGS),
 429         COMPOSITE(0, "pclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
 430                         RV1126_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS,
 431                         RV1126_CLKGATE_CON(2), 2, GFLAGS),
 432         GATE(PCLK_PDBUS, "pclk_pdbus", "pclk_pdbus_pre", CLK_IGNORE_UNUSED,
 433                         RV1126_CLKGATE_CON(2), 13, GFLAGS),
 434         /* aclk_dmac is controlled by sgrf_clkgat_con. */
 435         SGRF_GATE(ACLK_DMAC, "aclk_dmac", "hclk_pdbus"),
 436         GATE(ACLK_DCF, "aclk_dcf", "hclk_pdbus", CLK_IGNORE_UNUSED,
 437                         RV1126_CLKGATE_CON(3), 6, GFLAGS),
 438         GATE(PCLK_DCF, "pclk_dcf", "pclk_pdbus", CLK_IGNORE_UNUSED,
 439                         RV1126_CLKGATE_CON(3), 7, GFLAGS),
 440         GATE(PCLK_WDT, "pclk_wdt", "pclk_pdbus", 0,
 441                         RV1126_CLKGATE_CON(6), 14, GFLAGS),
 442         GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_pdbus", 0,
 443                         RV1126_CLKGATE_CON(7), 10, GFLAGS),
 444
 445         COMPOSITE(CLK_SCR1, "clk_scr1", mux_gpll_cpll_p, 0,
 446                         RV1126_CLKSEL_CON(3), 15, 1, MFLAGS, 8, 5, DFLAGS,
 447                         RV1126_CLKGATE_CON(4), 7, GFLAGS),
 448         GATE(0, "clk_scr1_niu", "clk_scr1", CLK_IGNORE_UNUSED,
 449                         RV1126_CLKGATE_CON(2), 14, GFLAGS),
 450         GATE(CLK_SCR1_CORE, "clk_scr1_core", "clk_scr1", 0,
 451                         RV1126_CLKGATE_CON(4), 8, GFLAGS),
 452         GATE(CLK_SCR1_RTC, "clk_scr1_rtc", "xin24m", 0,
 453                         RV1126_CLKGATE_CON(4), 9, GFLAGS),
 454         GATE(CLK_SCR1_JTAG, "clk_scr1_jtag", "clk_scr1_jtag_io", 0,
 455                         RV1126_CLKGATE_CON(4), 10, GFLAGS),
 456
 457         GATE(PCLK_UART0, "pclk_uart0", "pclk_pdbus", 0,
 458                         RV1126_CLKGATE_CON(5), 0, GFLAGS),
 459         COMPOSITE(SCLK_UART0_DIV, "sclk_uart0_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
 460                         RV1126_CLKSEL_CON(10), 8, 2, MFLAGS, 0, 7, DFLAGS,
 461                         RV1126_CLKGATE_CON(5), 1, GFLAGS),
 462         COMPOSITE_FRACMUX(SCLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
 463                         RV1126_CLKSEL_CON(11), 0,
 464                         RV1126_CLKGATE_CON(5), 2, GFLAGS,
 465                         &rv1126_uart0_fracmux),
 466         GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
 467                         RV1126_CLKGATE_CON(5), 3, GFLAGS),
 468         GATE(PCLK_UART2, "pclk_uart2", "pclk_pdbus", 0,
 469                         RV1126_CLKGATE_CON(5), 4, GFLAGS),
 470         COMPOSITE(SCLK_UART2_DIV, "sclk_uart2_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
 471                         RV1126_CLKSEL_CON(12), 8, 2, MFLAGS, 0, 7, DFLAGS,
 472                         RV1126_CLKGATE_CON(5), 5, GFLAGS),
 473         COMPOSITE_FRACMUX(SCLK_UART2_FRAC, "sclk_uart2_frac", "sclk_uart2_div", CLK_SET_RATE_PARENT,
 474                         RV1126_CLKSEL_CON(13), 0,
 475                         RV1126_CLKGATE_CON(5), 6, GFLAGS,
 476                         &rv1126_uart2_fracmux),
 477         GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
 478                         RV1126_CLKGATE_CON(5), 7, GFLAGS),
 479         GATE(PCLK_UART3, "pclk_uart3", "pclk_pdbus", 0,
 480                         RV1126_CLKGATE_CON(5), 8, GFLAGS),
 481         COMPOSITE(SCLK_UART3_DIV, "sclk_uart3_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
 482                         RV1126_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
 483                         RV1126_CLKGATE_CON(5), 9, GFLAGS),
 484         COMPOSITE_FRACMUX(SCLK_UART3_FRAC, "sclk_uart3_frac", "sclk_uart3_div", CLK_SET_RATE_PARENT,
 485                         RV1126_CLKSEL_CON(15), 0,
 486                         RV1126_CLKGATE_CON(5), 10, GFLAGS,
 487                         &rv1126_uart3_fracmux),
 488         GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
 489                         RV1126_CLKGATE_CON(5), 11, GFLAGS),
 490         GATE(PCLK_UART4, "pclk_uart4", "pclk_pdbus", 0,
 491                         RV1126_CLKGATE_CON(5), 12, GFLAGS),
 492         COMPOSITE(SCLK_UART4_DIV, "sclk_uart4_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
 493                         RV1126_CLKSEL_CON(16), 8, 2, MFLAGS, 0, 7,
 494                         DFLAGS, RV1126_CLKGATE_CON(5), 13, GFLAGS),
 495         COMPOSITE_FRACMUX(SCLK_UART4_FRAC, "sclk_uart4_frac", "sclk_uart4_div", CLK_SET_RATE_PARENT,
 496                         RV1126_CLKSEL_CON(17), 0,
 497                         RV1126_CLKGATE_CON(5), 14, GFLAGS,
 498                         &rv1126_uart4_fracmux),
 499         GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
 500                         RV1126_CLKGATE_CON(5), 15, GFLAGS),
 501         GATE(PCLK_UART5, "pclk_uart5", "pclk_pdbus", 0,
 502                         RV1126_CLKGATE_CON(6), 0, GFLAGS),
 503         COMPOSITE(SCLK_UART5_DIV, "sclk_uart5_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
 504                         RV1126_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7,
 505                         DFLAGS, RV1126_CLKGATE_CON(6), 1, GFLAGS),
 506         COMPOSITE_FRACMUX(SCLK_UART5_FRAC, "sclk_uart5_frac", "sclk_uart5_div", CLK_SET_RATE_PARENT,
 507                         RV1126_CLKSEL_CON(19), 0,
 508                         RV1126_CLKGATE_CON(6), 2, GFLAGS,
 509                         &rv1126_uart5_fracmux),
 510         GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
 511                         RV1126_CLKGATE_CON(6), 3, GFLAGS),
 512
 513         GATE(PCLK_I2C1, "pclk_i2c1", "pclk_pdbus", 0,
 514                         RV1126_CLKGATE_CON(3), 10, GFLAGS),
 515         COMPOSITE_NOMUX(CLK_I2C1, "clk_i2c1", "gpll", 0,
 516                         RV1126_CLKSEL_CON(5), 0, 7, DFLAGS,
 517                         RV1126_CLKGATE_CON(3), 11, GFLAGS),
 518         GATE(PCLK_I2C3, "pclk_i2c3", "pclk_pdbus", 0,
 519                         RV1126_CLKGATE_CON(3), 12, GFLAGS),
 520         COMPOSITE_NOMUX(CLK_I2C3, "clk_i2c3", "gpll", 0,
 521                         RV1126_CLKSEL_CON(5), 8, 7, DFLAGS,
 522                         RV1126_CLKGATE_CON(3), 13, GFLAGS),
 523         GATE(PCLK_I2C4, "pclk_i2c4", "pclk_pdbus", 0,
 524                         RV1126_CLKGATE_CON(3), 14, GFLAGS),
 525         COMPOSITE_NOMUX(CLK_I2C4, "clk_i2c4", "gpll", 0,
 526                         RV1126_CLKSEL_CON(6), 0, 7, DFLAGS,
 527                         RV1126_CLKGATE_CON(3), 15, GFLAGS),
 528         GATE(PCLK_I2C5, "pclk_i2c5", "pclk_pdbus", 0,
 529                         RV1126_CLKGATE_CON(4), 0, GFLAGS),
 530         COMPOSITE_NOMUX(CLK_I2C5, "clk_i2c5", "gpll", 0,
 531                         RV1126_CLKSEL_CON(6), 8, 7, DFLAGS,
 532                         RV1126_CLKGATE_CON(4), 1, GFLAGS),
 533
 534         GATE(PCLK_SPI1, "pclk_spi1", "pclk_pdbus", 0,
 535                         RV1126_CLKGATE_CON(4), 2, GFLAGS),
 536         COMPOSITE(CLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
 537                         RV1126_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 7, DFLAGS,
 538                         RV1126_CLKGATE_CON(4), 3, GFLAGS),
 539
 540         GATE(CLK_CAPTURE_PWM2, "clk_capture_pwm2", "xin24m", 0,
 541                         RV1126_CLKGATE_CON(4), 6, GFLAGS),
 542         GATE(PCLK_PWM2, "pclk_pwm2", "pclk_pdbus", 0,
 543                         RV1126_CLKGATE_CON(4), 4, GFLAGS),
 544         COMPOSITE(CLK_PWM2, "clk_pwm2", mux_xin24m_gpll_p, 0,
 545                         RV1126_CLKSEL_CON(9), 15, 1, MFLAGS, 8, 7, DFLAGS,
 546                         RV1126_CLKGATE_CON(4), 5, GFLAGS),
 547
 548         GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pdbus", 0,
 549                         RV1126_CLKGATE_CON(7), 0, GFLAGS),
 550         COMPOSITE_NODIV(DBCLK_GPIO1, "dbclk_gpio1", mux_xin24m_32k_p, 0,
 551                         RV1126_CLKSEL_CON(21), 15, 1, MFLAGS,
 552                         RV1126_CLKGATE_CON(7), 1, GFLAGS),
 553         GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pdbus", 0,
 554                         RV1126_CLKGATE_CON(7), 2, GFLAGS),
 555         COMPOSITE_NODIV(DBCLK_GPIO2, "dbclk_gpio2", mux_xin24m_32k_p, 0,
 556                         RV1126_CLKSEL_CON(22), 15, 1, MFLAGS,
 557                         RV1126_CLKGATE_CON(7), 3, GFLAGS),
 558         GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pdbus", 0,
 559                         RV1126_CLKGATE_CON(7), 4, GFLAGS),
 560         COMPOSITE_NODIV(DBCLK_GPIO3, "dbclk_gpio3", mux_xin24m_32k_p, 0,
 561                         RV1126_CLKSEL_CON(23), 15, 1, MFLAGS,
 562                         RV1126_CLKGATE_CON(7), 5, GFLAGS),
 563         GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pdbus", 0,
 564                         RV1126_CLKGATE_CON(7), 6, GFLAGS),
 565         COMPOSITE_NODIV(DBCLK_GPIO4, "dbclk_gpio4", mux_xin24m_32k_p, 0,
 566                         RV1126_CLKSEL_CON(24), 15, 1, MFLAGS,
 567                         RV1126_CLKGATE_CON(7), 7, GFLAGS),
 568
 569         GATE(PCLK_SARADC, "pclk_saradc", "pclk_pdbus", 0,
 570                         RV1126_CLKGATE_CON(6), 4, GFLAGS),
 571         COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
 572                         RV1126_CLKSEL_CON(20), 0, 11, DFLAGS,
 573                         RV1126_CLKGATE_CON(6), 5, GFLAGS),
 574
 575         GATE(PCLK_TIMER, "pclk_timer", "pclk_pdbus", 0,
 576                         RV1126_CLKGATE_CON(6), 7, GFLAGS),
 577         GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
 578                         RV1126_CLKGATE_CON(6), 8, GFLAGS),
 579         GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
 580                         RV1126_CLKGATE_CON(6), 9, GFLAGS),
 581         GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
 582                         RV1126_CLKGATE_CON(6), 10, GFLAGS),
 583         GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
 584                         RV1126_CLKGATE_CON(6), 11, GFLAGS),
 585         GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
 586                         RV1126_CLKGATE_CON(6), 12, GFLAGS),
 587         GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
 588                         RV1126_CLKGATE_CON(6), 13, GFLAGS),
 589
 590         GATE(ACLK_SPINLOCK, "aclk_spinlock", "hclk_pdbus", 0,
 591                         RV1126_CLKGATE_CON(6), 6, GFLAGS),
 592
 593         GATE(ACLK_DECOM, "aclk_decom", "aclk_pdbus", 0,
 594                         RV1126_CLKGATE_CON(7), 11, GFLAGS),
 595         GATE(PCLK_DECOM, "pclk_decom", "pclk_pdbus", 0,
 596                         RV1126_CLKGATE_CON(7), 12, GFLAGS),
 597         COMPOSITE(DCLK_DECOM, "dclk_decom", mux_gpll_cpll_p, 0,
 598                         RV1126_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
 599                         RV1126_CLKGATE_CON(7), 13, GFLAGS),
 600
 601         GATE(PCLK_CAN, "pclk_can", "pclk_pdbus", 0,
 602                         RV1126_CLKGATE_CON(7), 8, GFLAGS),
 603         COMPOSITE(CLK_CAN, "clk_can", mux_gpll_xin24m_p, 0,
 604                         RV1126_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
 605                         RV1126_CLKGATE_CON(7), 9, GFLAGS),
 606         /* pclk_otp and clk_otp are controlled by sgrf_clkgat_con. */
 607         SGRF_GATE(CLK_OTP, "clk_otp", "xin24m"),
 608         SGRF_GATE(PCLK_OTP, "pclk_otp", "pclk_pdbus"),
 609
 610         GATE(PCLK_NPU_TSADC, "pclk_npu_tsadc", "pclk_pdbus", 0,
 611                         RV1126_CLKGATE_CON(24), 3, GFLAGS),
 612         COMPOSITE_NOMUX(CLK_NPU_TSADC, "clk_npu_tsadc", "xin24m", 0,
 613                         RV1126_CLKSEL_CON(71), 0, 11, DFLAGS,
 614                         RV1126_CLKGATE_CON(24), 4, GFLAGS),
 615         GATE(CLK_NPU_TSADCPHY, "clk_npu_tsadcphy", "clk_npu_tsadc", 0,
 616                         RV1126_CLKGATE_CON(24), 5, GFLAGS),
 617         GATE(PCLK_CPU_TSADC, "pclk_cpu_tsadc", "pclk_pdbus", 0,
 618                         RV1126_CLKGATE_CON(24), 0, GFLAGS),
 619         COMPOSITE_NOMUX(CLK_CPU_TSADC, "clk_cpu_tsadc", "xin24m", 0,
 620                         RV1126_CLKSEL_CON(70), 0, 11, DFLAGS,
 621                         RV1126_CLKGATE_CON(24), 1, GFLAGS),
 622         GATE(CLK_CPU_TSADCPHY, "clk_cpu_tsadcphy", "clk_cpu_tsadc", 0,
 623                         RV1126_CLKGATE_CON(24), 2, GFLAGS),
 624
 625         /*
 626          * Clock-Architecture Diagram 6
 627          */
 628         /* PD_AUDIO */
 629         COMPOSITE_NOMUX(HCLK_PDAUDIO, "hclk_pdaudio", "gpll", 0,
 630                         RV1126_CLKSEL_CON(26), 0, 5, DFLAGS,
 631                         RV1126_CLKGATE_CON(9), 0, GFLAGS),
 632
 633         GATE(HCLK_I2S0, "hclk_i2s0", "hclk_pdaudio", 0,
 634                         RV1126_CLKGATE_CON(9), 4, GFLAGS),
 635         COMPOSITE(MCLK_I2S0_TX_DIV, "mclk_i2s0_tx_div", mux_cpll_gpll_p, 0,
 636                         RV1126_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
 637                         RV1126_CLKGATE_CON(9), 5, GFLAGS),
 638         COMPOSITE_FRACMUX(MCLK_I2S0_TX_FRACDIV, "mclk_i2s0_tx_fracdiv", "mclk_i2s0_tx_div",
 639                         CLK_SET_RATE_PARENT,
 640                         RV1126_CLKSEL_CON(28), 0,
 641                         RV1126_CLKGATE_CON(9), 6, GFLAGS,
 642                         &rv1126_i2s0_tx_fracmux),
 643         GATE(MCLK_I2S0_TX, "mclk_i2s0_tx", "mclk_i2s0_tx_mux", 0,
 644                         RV1126_CLKGATE_CON(9), 9, GFLAGS),
 645         COMPOSITE(MCLK_I2S0_RX_DIV, "mclk_i2s0_rx_div", mux_cpll_gpll_p, 0,
 646                         RV1126_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 7, DFLAGS,
 647                         RV1126_CLKGATE_CON(9), 7, GFLAGS),
 648         COMPOSITE_FRACMUX(MCLK_I2S0_RX_FRACDIV, "mclk_i2s0_rx_fracdiv", "mclk_i2s0_rx_div",
 649                         CLK_SET_RATE_PARENT,
 650                         RV1126_CLKSEL_CON(29), 0,
 651                         RV1126_CLKGATE_CON(9), 8, GFLAGS,
 652                         &rv1126_i2s0_rx_fracmux),
 653         GATE(MCLK_I2S0_RX, "mclk_i2s0_rx", "mclk_i2s0_rx_mux", 0,
 654                         RV1126_CLKGATE_CON(9), 10, GFLAGS),
 655         COMPOSITE_NODIV(MCLK_I2S0_TX_OUT2IO, "mclk_i2s0_tx_out2io", mux_i2s0_tx_out2io_p, 0,
 656                         RV1126_CLKSEL_CON(30), 6, 1, MFLAGS,
 657                         RV1126_CLKGATE_CON(9), 13, GFLAGS),
 658         COMPOSITE_NODIV(MCLK_I2S0_RX_OUT2IO, "mclk_i2s0_rx_out2io", mux_i2s0_rx_out2io_p, 0,
 659                         RV1126_CLKSEL_CON(30), 8, 1, MFLAGS,
 660                         RV1126_CLKGATE_CON(9), 14, GFLAGS),
 661
 662         GATE(HCLK_I2S1, "hclk_i2s1", "hclk_pdaudio", 0,
 663                         RV1126_CLKGATE_CON(10), 0, GFLAGS),
 664         COMPOSITE(MCLK_I2S1_DIV, "mclk_i2s1_div", mux_cpll_gpll_p, 0,
 665                         RV1126_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 7, DFLAGS,
 666                         RV1126_CLKGATE_CON(10), 1, GFLAGS),
 667         COMPOSITE_FRACMUX(MCLK_I2S1_FRACDIV, "mclk_i2s1_fracdiv", "mclk_i2s1_div",
 668                         CLK_SET_RATE_PARENT,
 669                         RV1126_CLKSEL_CON(32), 0,
 670                         RV1126_CLKGATE_CON(10), 2, GFLAGS,
 671                         &rv1126_i2s1_fracmux),
 672         GATE(MCLK_I2S1, "mclk_i2s1", "mclk_i2s1_mux", 0,
 673                         RV1126_CLKGATE_CON(10), 3, GFLAGS),
 674         COMPOSITE_NODIV(MCLK_I2S1_OUT2IO, "mclk_i2s1_out2io", mux_i2s1_out2io_p, 0,
 675                         RV1126_CLKSEL_CON(31), 12, 1, MFLAGS,
 676                         RV1126_CLKGATE_CON(10), 4, GFLAGS),
 677         GATE(HCLK_I2S2, "hclk_i2s2", "hclk_pdaudio", 0,
 678                         RV1126_CLKGATE_CON(10), 5, GFLAGS),
 679         COMPOSITE(MCLK_I2S2_DIV, "mclk_i2s2_div", mux_cpll_gpll_p, 0,
 680                         RV1126_CLKSEL_CON(33), 7, 1, MFLAGS, 0, 7, DFLAGS,
 681                         RV1126_CLKGATE_CON(10), 6, GFLAGS),
 682         COMPOSITE_FRACMUX(MCLK_I2S2_FRACDIV, "mclk_i2s2_fracdiv", "mclk_i2s2_div",
 683                         CLK_SET_RATE_PARENT,
 684                         RV1126_CLKSEL_CON(34), 0,
 685                         RV1126_CLKGATE_CON(10), 7, GFLAGS,
 686                         &rv1126_i2s2_fracmux),
 687         GATE(MCLK_I2S2, "mclk_i2s2", "mclk_i2s2_mux", 0,
 688                         RV1126_CLKGATE_CON(10), 8, GFLAGS),
 689         COMPOSITE_NODIV(MCLK_I2S2_OUT2IO, "mclk_i2s2_out2io", mux_i2s2_out2io_p, 0,
 690                         RV1126_CLKSEL_CON(33), 10, 1, MFLAGS,
 691                         RV1126_CLKGATE_CON(10), 9, GFLAGS),
 692
 693         GATE(HCLK_PDM, "hclk_pdm", "hclk_pdaudio", 0,
 694                         RV1126_CLKGATE_CON(10), 10, GFLAGS),
 695         COMPOSITE(MCLK_PDM, "mclk_pdm", mux_gpll_cpll_xin24m_p, 0,
 696                         RV1126_CLKSEL_CON(35), 8, 2, MFLAGS, 0, 7, DFLAGS,
 697                         RV1126_CLKGATE_CON(10), 11, GFLAGS),
 698
 699         GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_pdaudio", 0,
 700                         RV1126_CLKGATE_CON(10), 12, GFLAGS),
 701         COMPOSITE(SCLK_ADUPWM_DIV, "sclk_audpwm_div", mux_gpll_cpll_p, 0,
 702                         RV1126_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS,
 703                         RV1126_CLKGATE_CON(10), 13, GFLAGS),
 704         COMPOSITE_FRACMUX(SCLK_AUDPWM_FRACDIV, "sclk_audpwm_fracdiv", "sclk_audpwm_div",
 705                         CLK_SET_RATE_PARENT,
 706                         RV1126_CLKSEL_CON(37), 0,
 707                         RV1126_CLKGATE_CON(10), 14, GFLAGS,
 708                         &rv1126_audpwm_fracmux),
 709         GATE(SCLK_AUDPWM, "sclk_audpwm", "mclk_audpwm_mux", 0,
 710                         RV1126_CLKGATE_CON(10), 15, GFLAGS),
 711
 712         GATE(PCLK_ACDCDIG, "pclk_acdcdig", "hclk_pdaudio", 0,
 713                         RV1126_CLKGATE_CON(11), 0, GFLAGS),
 714         GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s0_rx", 0,
 715                         RV1126_CLKGATE_CON(11), 2, GFLAGS),
 716         GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s0_tx", 0,
 717                         RV1126_CLKGATE_CON(11), 3, GFLAGS),
 718         COMPOSITE(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", mux_gpll_xin24m_p, 0,
 719                         RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
 720                         RV1126_CLKGATE_CON(11), 1, GFLAGS),
 721
 722         /*
 723          * Clock-Architecture Diagram 9
 724          */
 725         /* PD_VO */
 726         COMPOSITE(ACLK_PDVO, "aclk_pdvo", mux_gpll_cpll_p, 0,
 727                   RV1126_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 5, DFLAGS,
 728                   RV1126_CLKGATE_CON(14), 0, GFLAGS),
 729         COMPOSITE_NOMUX(HCLK_PDVO, "hclk_pdvo", "aclk_pdvo", 0,
 730                         RV1126_CLKSEL_CON(45), 8, 5, DFLAGS,
 731                         RV1126_CLKGATE_CON(14), 1, GFLAGS),
 732         COMPOSITE_NOMUX(PCLK_PDVO, "pclk_pdvo", "aclk_pdvo", 0,
 733                         RV1126_CLKSEL_CON(46), 8, 5, DFLAGS,
 734                         RV1126_CLKGATE_CON(14), 2, GFLAGS),
 735         GATE(ACLK_RGA, "aclk_rga", "aclk_pdvo", 0,
 736              RV1126_CLKGATE_CON(14), 6, GFLAGS),
 737         GATE(HCLK_RGA, "hclk_rga", "hclk_pdvo", 0,
 738              RV1126_CLKGATE_CON(14), 7, GFLAGS),
 739         COMPOSITE(CLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_p, 0,
 740                   RV1126_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 5, DFLAGS,
 741                   RV1126_CLKGATE_CON(14), 8, GFLAGS),
 742         GATE(ACLK_VOP, "aclk_vop", "aclk_pdvo", 0,
 743              RV1126_CLKGATE_CON(14), 9, GFLAGS),
 744         GATE(HCLK_VOP, "hclk_vop", "hclk_pdvo", 0,
 745              RV1126_CLKGATE_CON(14), 10, GFLAGS),
 746         COMPOSITE(DCLK_VOP_DIV, "dclk_vop_div", mux_gpll_cpll_p, 0,
 747                   RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,
 748                   RV1126_CLKGATE_CON(14), 11, GFLAGS),
 749         COMPOSITE_FRACMUX(DCLK_VOP_FRACDIV, "dclk_vop_fracdiv", "dclk_vop_div",
 750                           CLK_SET_RATE_PARENT, RV1126_CLKSEL_CON(48), 0,
 751                           RV1126_CLKGATE_CON(14), 12, GFLAGS,
 752                           &rv1126_dclk_vop_fracmux),
 753         GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
 754              RV1126_CLKGATE_CON(14), 13, GFLAGS),
 755         GATE(PCLK_DSIHOST, "pclk_dsihost", "pclk_pdvo", 0,
 756              RV1126_CLKGATE_CON(14), 14, GFLAGS),
 757         GATE(ACLK_IEP, "aclk_iep", "aclk_pdvo", 0,
 758              RV1126_CLKGATE_CON(12), 7, GFLAGS),
 759         GATE(HCLK_IEP, "hclk_iep", "hclk_pdvo", 0,
 760              RV1126_CLKGATE_CON(12), 8, GFLAGS),
 761         COMPOSITE(CLK_IEP_CORE, "clk_iep_core", mux_gpll_cpll_p, 0,
 762                   RV1126_CLKSEL_CON(54), 7, 1, MFLAGS, 0, 5, DFLAGS,
 763                   RV1126_CLKGATE_CON(12), 9, GFLAGS),
 764
 765         /*
 766          * Clock-Architecture Diagram 12
 767          */
 768         /* PD_PHP */
 769         COMPOSITE(ACLK_PDPHP, "aclk_pdphp", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
 770                         RV1126_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 5, DFLAGS,
 771                         RV1126_CLKGATE_CON(17), 0, GFLAGS),
 772         COMPOSITE_NOMUX(HCLK_PDPHP, "hclk_pdphp", "gpll", CLK_IGNORE_UNUSED,
 773                         RV1126_CLKSEL_CON(53), 8, 5, DFLAGS,
 774                         RV1126_CLKGATE_CON(17), 1, GFLAGS),
 775         /* PD_SDCARD */
 776         GATE(HCLK_PDSDMMC, "hclk_pdsdmmc", "hclk_pdphp", 0,
 777                         RV1126_CLKGATE_CON(17), 6, GFLAGS),
 778         GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_pdsdmmc", 0,
 779                         RV1126_CLKGATE_CON(18), 4, GFLAGS),
 780         COMPOSITE(CLK_SDMMC, "clk_sdmmc", mux_gpll_cpll_xin24m_p, 0,
 781                         RV1126_CLKSEL_CON(55), 14, 2, MFLAGS, 0, 8,
 782                         DFLAGS, RV1126_CLKGATE_CON(18), 5, GFLAGS),
 783         MMC(SCLK_SDMMC_DRV,     "sdmmc_drv",    "clk_sdmmc", RV1126_SDMMC_CON0, 1),
 784         MMC(SCLK_SDMMC_SAMPLE,  "sdmmc_sample", "clk_sdmmc", RV1126_SDMMC_CON1, 1),
 785
 786         /* PD_SDIO */
 787         GATE(HCLK_PDSDIO, "hclk_pdsdio", "hclk_pdphp", 0,
 788                         RV1126_CLKGATE_CON(17), 8, GFLAGS),
 789         GATE(HCLK_SDIO, "hclk_sdio", "hclk_pdsdio", 0,
 790                         RV1126_CLKGATE_CON(18), 6, GFLAGS),
 791         COMPOSITE(CLK_SDIO, "clk_sdio", mux_gpll_cpll_xin24m_p, 0,
 792                         RV1126_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 8, DFLAGS,
 793                         RV1126_CLKGATE_CON(18), 7, GFLAGS),
 794         MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RV1126_SDIO_CON0, 1),
 795         MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RV1126_SDIO_CON1, 1),
 796
 797         /* PD_NVM */
 798         GATE(HCLK_PDNVM, "hclk_pdnvm", "hclk_pdphp", 0,
 799                         RV1126_CLKGATE_CON(18), 1, GFLAGS),
 800         GATE(HCLK_EMMC, "hclk_emmc", "hclk_pdnvm", 0,
 801                         RV1126_CLKGATE_CON(18), 8, GFLAGS),
 802         COMPOSITE(CLK_EMMC, "clk_emmc", mux_gpll_cpll_xin24m_p, 0,
 803                         RV1126_CLKSEL_CON(57), 14, 2, MFLAGS, 0, 8, DFLAGS,
 804                         RV1126_CLKGATE_CON(18), 9, GFLAGS),
 805         GATE(HCLK_NANDC, "hclk_nandc", "hclk_pdnvm", 0,
 806                         RV1126_CLKGATE_CON(18), 13, GFLAGS),
 807         COMPOSITE(CLK_NANDC, "clk_nandc", mux_gpll_cpll_p, 0,
 808                         RV1126_CLKSEL_CON(59), 15, 1, MFLAGS, 0, 8, DFLAGS,
 809                         RV1126_CLKGATE_CON(18), 14, GFLAGS),
 810         GATE(HCLK_SFC, "hclk_sfc", "hclk_pdnvm", 0,
 811                         RV1126_CLKGATE_CON(18), 10, GFLAGS),
 812         GATE(HCLK_SFCXIP, "hclk_sfcxip", "hclk_pdnvm", 0,
 813                         RV1126_CLKGATE_CON(18), 11, GFLAGS),
 814         COMPOSITE(SCLK_SFC, "sclk_sfc", mux_cpll_gpll_p, 0,
 815                         RV1126_CLKSEL_CON(58), 15, 1, MFLAGS, 0, 8, DFLAGS,
 816                         RV1126_CLKGATE_CON(18), 12, GFLAGS),
 817         MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RV1126_EMMC_CON0, 1),
 818         MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RV1126_EMMC_CON1, 1),
 819
 820         /* PD_USB */
 821         GATE(ACLK_PDUSB, "aclk_pdusb", "aclk_pdphp", 0,
 822                         RV1126_CLKGATE_CON(19), 0, GFLAGS),
 823         GATE(HCLK_PDUSB, "hclk_pdusb", "hclk_pdphp", 0,
 824                         RV1126_CLKGATE_CON(19), 1, GFLAGS),
 825         GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_pdusb", 0,
 826                         RV1126_CLKGATE_CON(19), 4, GFLAGS),
 827         GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_pdusb", 0,
 828                         RV1126_CLKGATE_CON(19), 5, GFLAGS),
 829         COMPOSITE(CLK_USBHOST_UTMI_OHCI, "clk_usbhost_utmi_ohci", mux_usb480m_gpll_p, 0,
 830                         RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
 831                         RV1126_CLKGATE_CON(19), 6, GFLAGS),
 832         GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_pdusb", 0,
 833                         RV1126_CLKGATE_CON(19), 7, GFLAGS),
 834         GATE(CLK_USBOTG_REF, "clk_usbotg_ref", "xin24m", 0,
 835                         RV1126_CLKGATE_CON(19), 8, GFLAGS),
 836         /* PD_GMAC */
 837         GATE(ACLK_PDGMAC, "aclk_pdgmac", "aclk_pdphp", 0,
 838                         RV1126_CLKGATE_CON(20), 0, GFLAGS),
 839         COMPOSITE_NOMUX(PCLK_PDGMAC, "pclk_pdgmac", "aclk_pdgmac", 0,
 840                         RV1126_CLKSEL_CON(63), 8, 5, DFLAGS,
 841                         RV1126_CLKGATE_CON(20), 1, GFLAGS),
 842         GATE(ACLK_GMAC, "aclk_gmac", "aclk_pdgmac", 0,
 843                         RV1126_CLKGATE_CON(20), 4, GFLAGS),
 844         GATE(PCLK_GMAC, "pclk_gmac", "pclk_pdgmac", 0,
 845                         RV1126_CLKGATE_CON(20), 5, GFLAGS),
 846
 847         COMPOSITE(CLK_GMAC_DIV, "clk_gmac_div", mux_cpll_gpll_p, 0,
 848                         RV1126_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 5, DFLAGS,
 849                         RV1126_CLKGATE_CON(20), 6, GFLAGS),
 850         GATE(CLK_GMAC_RGMII_M0, "clk_gmac_rgmii_m0", "clk_gmac_rgmii_clkin_m0", 0,
 851                         RV1126_CLKGATE_CON(20), 12, GFLAGS),
 852         MUX(CLK_GMAC_SRC_M0, "clk_gmac_src_m0", clk_gmac_src_m0_p, CLK_SET_RATE_PARENT,
 853                         RV1126_GMAC_CON, 0, 1, MFLAGS),
 854         GATE(CLK_GMAC_RGMII_M1, "clk_gmac_rgmii_m1", "clk_gmac_rgmii_clkin_m1", 0,
 855                         RV1126_CLKGATE_CON(20), 13, GFLAGS),
 856         MUX(CLK_GMAC_SRC_M1, "clk_gmac_src_m1", clk_gmac_src_m1_p, CLK_SET_RATE_PARENT,
 857                         RV1126_GMAC_CON, 5, 1, MFLAGS),
 858         MUXGRF(CLK_GMAC_SRC, "clk_gmac_src", mux_clk_gmac_src_p, CLK_SET_RATE_PARENT |
 859                         CLK_SET_RATE_NO_REPARENT,
 860                         RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS),
 861
 862         GATE(CLK_GMAC_REF, "clk_gmac_ref", "clk_gmac_src", 0,
 863                         RV1126_CLKGATE_CON(20), 7, GFLAGS),
 864
 865         GATE(CLK_GMAC_TX_SRC, "clk_gmac_tx_src", "clk_gmac_src", 0,
 866                         RV1126_CLKGATE_CON(20), 9, GFLAGS),
 867         FACTOR(CLK_GMAC_TX_DIV5, "clk_gmac_tx_div5", "clk_gmac_tx_src", 0, 1, 5),
 868         FACTOR(CLK_GMAC_TX_DIV50, "clk_gmac_tx_div50", "clk_gmac_tx_src", 0, 1, 50),
 869         MUXTBL(RGMII_MODE_CLK, "rgmii_mode_clk", mux_rgmii_clk_p, CLK_SET_RATE_PARENT,
 870                         RV1126_GMAC_CON, 2, 2, MFLAGS, rgmii_mux_idx),
 871         GATE(CLK_GMAC_RX_SRC, "clk_gmac_rx_src", "clk_gmac_src", 0,
 872                         RV1126_CLKGATE_CON(20), 8, GFLAGS),
 873         FACTOR(CLK_GMAC_RX_DIV2, "clk_gmac_rx_div2", "clk_gmac_rx_src", 0, 1, 2),
 874         FACTOR(CLK_GMAC_RX_DIV20, "clk_gmac_rx_div20", "clk_gmac_rx_src", 0, 1, 20),
 875         MUX(RMII_MODE_CLK, "rmii_mode_clk", mux_rmii_clk_p, CLK_SET_RATE_PARENT,
 876                         RV1126_GMAC_CON, 1, 1, MFLAGS),
 877         MUX(CLK_GMAC_TX_RX, "clk_gmac_tx_rx", mux_gmac_tx_rx_p, CLK_SET_RATE_PARENT |
 878                         CLK_SET_RATE_NO_REPARENT,
 879                         RV1126_GMAC_CON, 4, 1, MFLAGS),
 880
 881         GATE(CLK_GMAC_PTPREF, "clk_gmac_ptpref", "xin24m", 0,
 882                         RV1126_CLKGATE_CON(20), 10, GFLAGS),
 883         COMPOSITE(CLK_GMAC_ETHERNET_OUT, "clk_gmac_ethernet_out2io", mux_cpll_gpll_p, 0,
 884                         RV1126_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 5, DFLAGS,
 885                         RV1126_CLKGATE_CON(20), 11, GFLAGS),
 886
 887         /*
 888          * Clock-Architecture Diagram 15
 889          */
 890         GATE(PCLK_PDTOP, "pclk_pdtop", "pclk_pdbus", CLK_IGNORE_UNUSED,
 891                         RV1126_CLKGATE_CON(23), 8, GFLAGS),
 892         GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_pdtop", 0,
 893                         RV1126_CLKGATE_CON(23), 4, GFLAGS),
 894         GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_pdtop", 0,
 895                         RV1126_CLKGATE_CON(23), 2, GFLAGS),
 896         GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_pdtop", 0,
 897                         RV1126_CLKGATE_CON(23), 3, GFLAGS),
 898         GATE(PCLK_USBPHY_HOST, "pclk_usbphy_host", "pclk_pdtop", 0,
 899                         RV1126_CLKGATE_CON(19), 13, GFLAGS),
 900         GATE(PCLK_USBPHY_OTG, "pclk_usbphy_otg", "pclk_pdtop", 0,
 901                         RV1126_CLKGATE_CON(19), 12, GFLAGS),
 902
 903         /*
 904          * Clock-Architecture Diagram 3
 905          */
 906         /* PD_CORE */
 907         COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
 908                         RV1126_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
 909                         RV1126_CLKGATE_CON(0), 2, GFLAGS),
 910         GATE(0, "pclk_dbg_daplite", "pclk_dbg", CLK_IGNORE_UNUSED,
 911                         RV1126_CLKGATE_CON(0), 5, GFLAGS),
 912         GATE(0, "clk_a7_jtag", "clk_jtag_ori", CLK_IGNORE_UNUSED,
 913                         RV1126_CLKGATE_CON(0), 9, GFLAGS),
 914         GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
 915                         RV1126_CLKGATE_CON(0), 3, GFLAGS),
 916         GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
 917                         RV1126_CLKGATE_CON(0), 4, GFLAGS),
 918         /*
 919          * Clock-Architecture Diagram 4
 920          */
 921         /* PD_BUS */
 922         GATE(0, "aclk_pdbus_hold_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
 923                         RV1126_CLKGATE_CON(2), 10, GFLAGS),
 924         GATE(0, "aclk_pdbus_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
 925                         RV1126_CLKGATE_CON(2), 3, GFLAGS),
 926         GATE(0, "hclk_pdbus_niu1", "hclk_pdbus", CLK_IGNORE_UNUSED,
 927                         RV1126_CLKGATE_CON(2), 4, GFLAGS),
 928         GATE(0, "pclk_pdbus_niu1", "pclk_pdbus", CLK_IGNORE_UNUSED,
 929                         RV1126_CLKGATE_CON(2), 5, GFLAGS),
 930         GATE(0, "aclk_pdbus_niu2", "aclk_pdbus", CLK_IGNORE_UNUSED,
 931                         RV1126_CLKGATE_CON(2), 6, GFLAGS),
 932         GATE(0, "hclk_pdbus_niu2", "hclk_pdbus", CLK_IGNORE_UNUSED,
 933                         RV1126_CLKGATE_CON(2), 7, GFLAGS),
 934         GATE(0, "aclk_pdbus_niu3", "aclk_pdbus", CLK_IGNORE_UNUSED,
 935                         RV1126_CLKGATE_CON(2), 8, GFLAGS),
 936         GATE(0, "hclk_pdbus_niu3", "hclk_pdbus", CLK_IGNORE_UNUSED,
 937                         RV1126_CLKGATE_CON(2), 9, GFLAGS),
 938         GATE(0, "pclk_grf", "pclk_pdbus", CLK_IGNORE_UNUSED,
 939                         RV1126_CLKGATE_CON(6), 15, GFLAGS),
 940         GATE(0, "pclk_sgrf", "pclk_pdbus", CLK_IGNORE_UNUSED,
 941                         RV1126_CLKGATE_CON(8), 4, GFLAGS),
 942         GATE(0, "aclk_sysram", "hclk_pdbus", CLK_IGNORE_UNUSED,
 943                         RV1126_CLKGATE_CON(3), 9, GFLAGS),
 944         GATE(0, "pclk_intmux", "pclk_pdbus", CLK_IGNORE_UNUSED,
 945                         RV1126_CLKGATE_CON(7), 14, GFLAGS),
 946
 947         /*
 948          * Clock-Architecture Diagram 6
 949          */
 950         /* PD_AUDIO */
 951         GATE(0, "hclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
 952                         RV1126_CLKGATE_CON(9), 2, GFLAGS),
 953         GATE(0, "pclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
 954                         RV1126_CLKGATE_CON(9), 3, GFLAGS),
 955
 956         /*
 957          * Clock-Architecture Diagram 9
 958          */
 959         /* PD_VO */
 960         GATE(0, "aclk_pdvo_niu", "aclk_pdvo", CLK_IGNORE_UNUSED,
 961              RV1126_CLKGATE_CON(14), 3, GFLAGS),
 962         GATE(0, "hclk_pdvo_niu", "hclk_pdvo", CLK_IGNORE_UNUSED,
 963              RV1126_CLKGATE_CON(14), 4, GFLAGS),
 964         GATE(0, "pclk_pdvo_niu", "pclk_pdvo", CLK_IGNORE_UNUSED,
 965              RV1126_CLKGATE_CON(14), 5, GFLAGS),
 966
 967         /*
 968          * Clock-Architecture Diagram 12
 969          */
 970         /* PD_PHP */
 971         GATE(0, "aclk_pdphpmid", "aclk_pdphp", CLK_IGNORE_UNUSED,
 972                         RV1126_CLKGATE_CON(17), 2, GFLAGS),
 973         GATE(0, "hclk_pdphpmid", "hclk_pdphp", CLK_IGNORE_UNUSED,
 974                         RV1126_CLKGATE_CON(17), 3, GFLAGS),
 975         GATE(0, "aclk_pdphpmid_niu", "aclk_pdphpmid", CLK_IGNORE_UNUSED,
 976                         RV1126_CLKGATE_CON(17), 4, GFLAGS),
 977         GATE(0, "hclk_pdphpmid_niu", "hclk_pdphpmid", CLK_IGNORE_UNUSED,
 978                         RV1126_CLKGATE_CON(17), 5, GFLAGS),
 979
 980         /* PD_SDCARD */
 981         GATE(0, "hclk_pdsdmmc_niu", "hclk_pdsdmmc", CLK_IGNORE_UNUSED,
 982                         RV1126_CLKGATE_CON(17), 7, GFLAGS),
 983
 984         /* PD_SDIO */
 985         GATE(0, "hclk_pdsdio_niu", "hclk_pdsdio", CLK_IGNORE_UNUSED,
 986                         RV1126_CLKGATE_CON(17), 9, GFLAGS),
 987
 988         /* PD_NVM */
 989         GATE(0, "hclk_pdnvm_niu", "hclk_pdnvm", CLK_IGNORE_UNUSED,
 990                         RV1126_CLKGATE_CON(18), 3, GFLAGS),
 991
 992         /* PD_USB */
 993         GATE(0, "aclk_pdusb_niu", "aclk_pdusb", CLK_IGNORE_UNUSED,
 994                         RV1126_CLKGATE_CON(19), 2, GFLAGS),
 995         GATE(0, "hclk_pdusb_niu", "hclk_pdusb", CLK_IGNORE_UNUSED,
 996                         RV1126_CLKGATE_CON(19), 3, GFLAGS),
 997
 998         /* PD_GMAC */
 999         GATE(0, "aclk_pdgmac_niu", "aclk_pdgmac", CLK_IGNORE_UNUSED,
1000                         RV1126_CLKGATE_CON(20), 2, GFLAGS),
1001         GATE(0, "pclk_pdgmac_niu", "pclk_pdgmac", CLK_IGNORE_UNUSED,
1002                         RV1126_CLKGATE_CON(20), 3, GFLAGS),
1003
1004         /*
1005          * Clock-Architecture Diagram 13
1006          */
1007         /* PD_DDR */
1008         COMPOSITE_NOMUX(0, "pclk_pdddr_pre", "gpll", CLK_IGNORE_UNUSED,
1009                         RV1126_CLKSEL_CON(64), 0, 5, DFLAGS,
1010                         RV1126_CLKGATE_CON(21), 0, GFLAGS),
1011         GATE(PCLK_PDDDR, "pclk_pdddr", "pclk_pdddr_pre", CLK_IGNORE_UNUSED,
1012                         RV1126_CLKGATE_CON(21), 15, GFLAGS),
1013         GATE(0, "pclk_ddr_msch", "pclk_pdddr", CLK_IGNORE_UNUSED,
1014                         RV1126_CLKGATE_CON(21), 6, GFLAGS),
1015         COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_dpll_gpll_p, CLK_IGNORE_UNUSED,
1016                          RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS |
1017                          CLK_DIVIDER_POWER_OF_TWO),
1018         COMPOSITE(CLK_DDRPHY, "clk_ddrphy", mux_dpll_gpll_p, CLK_IGNORE_UNUSED,
1019                         RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
1020                         RV1126_CLKGATE_CON(21), 8, GFLAGS),
1021         GATE(0, "clk1x_phy", "clk_ddrphy", CLK_IGNORE_UNUSED,
1022                         RV1126_CLKGATE_CON(23), 1, GFLAGS),
1023         GATE(0, "clk_ddr_msch", "clk_ddrphy", CLK_IGNORE_UNUSED,
1024                         RV1126_CLKGATE_CON(21), 10, GFLAGS),
1025         GATE(0, "pclk_ddr_dfictl", "pclk_pdddr", CLK_IGNORE_UNUSED,
1026                         RV1126_CLKGATE_CON(21), 2, GFLAGS),
1027         GATE(0, "clk_ddr_dfictl", "clk_ddrphy", CLK_IGNORE_UNUSED,
1028                         RV1126_CLKGATE_CON(21), 13, GFLAGS),
1029         GATE(0, "pclk_ddr_standby", "pclk_pdddr", CLK_IGNORE_UNUSED,
1030                         RV1126_CLKGATE_CON(21), 4, GFLAGS),
1031         GATE(0, "clk_ddr_standby", "clk_ddrphy", CLK_IGNORE_UNUSED,
1032                         RV1126_CLKGATE_CON(21), 14, GFLAGS),
1033         GATE(0, "aclk_ddr_split", "clk_ddrphy", CLK_IGNORE_UNUSED,
1034                         RV1126_CLKGATE_CON(21), 9, GFLAGS),
1035         GATE(0, "pclk_ddr_grf", "pclk_pdddr", CLK_IGNORE_UNUSED,
1036                         RV1126_CLKGATE_CON(21), 5, GFLAGS),
1037         GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_pdddr", CLK_IGNORE_UNUSED,
1038                         RV1126_CLKGATE_CON(21), 3, GFLAGS),
1039         GATE(CLK_DDR_MON, "clk_ddr_mon", "clk_ddrphy", CLK_IGNORE_UNUSED,
1040                         RV1126_CLKGATE_CON(20), 15, GFLAGS),
1041         GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED,
1042                         RV1126_CLKGATE_CON(21), 7, GFLAGS),
1043
1044         /*
1045          * Clock-Architecture Diagram 15
1046          */
1047         GATE(0, "pclk_topniu", "pclk_pdtop", CLK_IGNORE_UNUSED,
1048                         RV1126_CLKGATE_CON(23), 9, GFLAGS),
1049         GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_pdtop", CLK_IGNORE_UNUSED,
1050                         RV1126_CLKGATE_CON(23), 10, GFLAGS),
1051         GATE(PCLK_TOPGRF, "pclk_topgrf", "pclk_pdtop", CLK_IGNORE_UNUSED,
1052                         RV1126_CLKGATE_CON(23), 11, GFLAGS),
1053         GATE(PCLK_CPUEMADET, "pclk_cpuemadet", "pclk_pdtop", CLK_IGNORE_UNUSED,
1054                         RV1126_CLKGATE_CON(23), 12, GFLAGS),
1055         GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_pdtop", CLK_IGNORE_UNUSED,
1056                         RV1126_CLKGATE_CON(23), 0, GFLAGS),
1057 };
1058
1059 static const char *const rv1126_cru_critical_clocks[] __initconst = {
1060         "gpll",
1061         "cpll",
1062         "hpll",
1063         "armclk",
1064         "pclk_dbg",
1065         "pclk_pdpmu",
1066         "aclk_pdbus",
1067         "hclk_pdbus",
1068         "pclk_pdbus",
1069         "aclk_pdphp",
1070         "hclk_pdphp",
1071         "clk_ddrphy",
1072         "pclk_pdddr",
1073         "pclk_pdtop",
1074         "clk_usbhost_utmi_ohci",
1075         "aclk_pdjpeg_niu",
1076         "hclk_pdjpeg_niu",
1077         "aclk_pdvdec_niu",
1078         "hclk_pdvdec_niu",
1079 };
1080
1081 static void __init rv1126_pmu_clk_init(struct device_node *np)
1082 {
1083         struct rockchip_clk_provider *ctx;
1084         void __iomem *reg_base;
1085
1086         reg_base = of_iomap(np, 0);
1087         if (!reg_base) {
1088                 pr_err("%s: could not map cru pmu region\n", __func__);
1089                 return;
1090         }
1091
1092         ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1093         if (IS_ERR(ctx)) {
1094                 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1095                 return;
1096         }
1097
1098         rockchip_clk_register_plls(ctx, rv1126_pmu_pll_clks,
1099                                    ARRAY_SIZE(rv1126_pmu_pll_clks),
1100                                    RV1126_GRF_SOC_STATUS0);
1101
1102         rockchip_clk_register_branches(ctx, rv1126_clk_pmu_branches,
1103                                        ARRAY_SIZE(rv1126_clk_pmu_branches));
1104
1105         rockchip_register_softrst(np, 2, reg_base + RV1126_PMU_SOFTRST_CON(0),
1106                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
1107
1108         rockchip_clk_of_add_provider(np, ctx);
1109 }
1110
1111 static void __init rv1126_clk_init(struct device_node *np)
1112 {
1113         struct rockchip_clk_provider *ctx;
1114         void __iomem *reg_base;
1115
1116         reg_base = of_iomap(np, 0);
1117         if (!reg_base) {
1118                 pr_err("%s: could not map cru region\n", __func__);
1119                 return;
1120         }
1121
1122         ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1123         if (IS_ERR(ctx)) {
1124                 pr_err("%s: rockchip clk init failed\n", __func__);
1125                 iounmap(reg_base);
1126                 return;
1127         }
1128
1129         rockchip_clk_register_plls(ctx, rv1126_pll_clks,
1130                                    ARRAY_SIZE(rv1126_pll_clks),
1131                                    RV1126_GRF_SOC_STATUS0);
1132
1133         rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1134                                      mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
1135                                      &rv1126_cpuclk_data, rv1126_cpuclk_rates,
1136                                      ARRAY_SIZE(rv1126_cpuclk_rates));
1137
1138         rockchip_clk_register_branches(ctx, rv1126_clk_branches,
1139                                        ARRAY_SIZE(rv1126_clk_branches));
1140
1141         rockchip_register_softrst(np, 15, reg_base + RV1126_SOFTRST_CON(0),
1142                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
1143
1144         rockchip_register_restart_notifier(ctx, RV1126_GLB_SRST_FST, NULL);
1145
1146         rockchip_clk_protect_critical(rv1126_cru_critical_clocks,
1147                                       ARRAY_SIZE(rv1126_cru_critical_clocks));
1148
1149         rockchip_clk_of_add_provider(np, ctx);
1150 }
1151
1152 struct clk_rv1126_inits {
1153         void (*inits)(struct device_node *np);
1154 };
1155
1156 static const struct clk_rv1126_inits clk_rv1126_pmucru_init = {
1157         .inits = rv1126_pmu_clk_init,
1158 };
1159
1160 static const struct clk_rv1126_inits clk_rv1126_cru_init = {
1161         .inits = rv1126_clk_init,
1162 };
1163
1164 static const struct of_device_id clk_rv1126_match_table[] = {
1165         {
1166                 .compatible = "rockchip,rv1126-cru",
1167                 .data = &clk_rv1126_cru_init,
1168         },  {
1169                 .compatible = "rockchip,rv1126-pmucru",
1170                 .data = &clk_rv1126_pmucru_init,
1171         },
1172         { }
1173 };
1174
1175 static int __init clk_rv1126_probe(struct platform_device *pdev)
1176 {
1177         struct device_node *np = pdev->dev.of_node;
1178         const struct clk_rv1126_inits *init_data;
1179
1180         init_data = (struct clk_rv1126_inits *)of_device_get_match_data(&pdev->dev);
1181         if (!init_data)
1182                 return -EINVAL;
1183
1184         if (init_data->inits)
1185                 init_data->inits(np);
1186
1187         return 0;
1188 }
1189
1190 static struct platform_driver clk_rv1126_driver = {
1191         .driver         = {
1192                 .name   = "clk-rv1126",
1193                 .of_match_table = clk_rv1126_match_table,
1194                 .suppress_bind_attrs = true,
1195         },
1196 };
1197 builtin_platform_driver_probe(clk_rv1126_driver, clk_rv1126_probe);