drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <asm/unaligned.h>
  18 #include "hw.h"
  19 #include "ar9003_phy.h"
  20 #include "ar9003_eeprom.h"
  21
  22 #define COMP_HDR_LEN 4
  23 #define COMP_CKSUM_LEN 2
  24
  25 #define LE16(x) __constant_cpu_to_le16(x)
  26 #define LE32(x) __constant_cpu_to_le32(x)
  27
  28 /* Local defines to distinguish between extension and control CTL's */
  29 #define EXT_ADDITIVE (0x8000)
  30 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  31 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  32 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  33 #define PWRINCR_3_TO_1_CHAIN      9             /* 10*log(3)*2 */
  34 #define PWRINCR_3_TO_2_CHAIN      3             /* floor(10*log(3/2)*2) */
  35 #define PWRINCR_2_TO_1_CHAIN      6             /* 10*log(2)*2 */
  36
  37 #define SUB_NUM_CTL_MODES_AT_5G_40 2    /* excluding HT40, EXT-OFDM */
  38 #define SUB_NUM_CTL_MODES_AT_2G_40 3    /* excluding HT40, EXT-OFDM, EXT-CCK */
  39
  40 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
  41
  42 #define EEPROM_DATA_LEN_9485    1088
  43
  44 static int ar9003_hw_power_interpolate(int32_t x,
  45                                        int32_t *px, int32_t *py, u_int16_t np);
  46
  47
  48 static const struct ar9300_eeprom ar9300_default = {
  49         .eepromVersion = 2,
  50         .templateVersion = 2,
  51         .macAddr = {0, 2, 3, 4, 5, 6},
  52         .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  53                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
  54         .baseEepHeader = {
  55                 .regDmn = { LE16(0), LE16(0x1f) },
  56                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
  57                 .opCapFlags = {
  58                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
  59                         .eepMisc = 0,
  60                 },
  61                 .rfSilent = 0,
  62                 .blueToothOptions = 0,
  63                 .deviceCap = 0,
  64                 .deviceType = 5, /* takes lower byte in eeprom location */
  65                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
  66                 .params_for_tuning_caps = {0, 0},
  67                 .featureEnable = 0x0c,
  68                  /*
  69                   * bit0 - enable tx temp comp - disabled
  70                   * bit1 - enable tx volt comp - disabled
  71                   * bit2 - enable fastClock - enabled
  72                   * bit3 - enable doubling - enabled
  73                   * bit4 - enable internal regulator - disabled
  74                   * bit5 - enable pa predistortion - disabled
  75                   */
  76                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
  77                 .eepromWriteEnableGpio = 3,
  78                 .wlanDisableGpio = 0,
  79                 .wlanLedGpio = 8,
  80                 .rxBandSelectGpio = 0xff,
  81                 .txrxgain = 0,
  82                 .swreg = 0,
  83          },
  84         .modalHeader2G = {
  85         /* ar9300_modal_eep_header  2g */
  86                 /* 4 idle,t1,t2,b(4 bits per setting) */
  87                 .antCtrlCommon = LE32(0x110),
  88                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
  89                 .antCtrlCommon2 = LE32(0x22222),
  90
  91                 /*
  92                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
  93                  * rx1, rx12, b (2 bits each)
  94                  */
  95                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
  96
  97                 /*
  98                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
  99                  * for ar9280 (0xa20c/b20c 5:0)
 100                  */
 101                 .xatten1DB = {0, 0, 0},
 102
 103                 /*
 104                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 105                  * for ar9280 (0xa20c/b20c 16:12
 106                  */
 107                 .xatten1Margin = {0, 0, 0},
 108                 .tempSlope = 36,
 109                 .voltSlope = 0,
 110
 111                 /*
 112                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 113                  * channels in usual fbin coding format
 114                  */
 115                 .spurChans = {0, 0, 0, 0, 0},
 116
 117                 /*
 118                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 119                  * if the register is per chain
 120                  */
 121                 .noiseFloorThreshCh = {-1, 0, 0},
 122                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 123                 .quick_drop = 0,
 124                 .xpaBiasLvl = 0,
 125                 .txFrameToDataStart = 0x0e,
 126                 .txFrameToPaOn = 0x0e,
 127                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 128                 .antennaGain = 0,
 129                 .switchSettling = 0x2c,
 130                 .adcDesiredSize = -30,
 131                 .txEndToXpaOff = 0,
 132                 .txEndToRxOn = 0x2,
 133                 .txFrameToXpaOn = 0xe,
 134                 .thresh62 = 28,
 135                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 136                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 137                 .futureModal = {
 138                         0, 0, 0, 0, 0, 0, 0, 0,
 139                 },
 140          },
 141         .base_ext1 = {
 142                 .ant_div_control = 0,
 143                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 144         },
 145         .calFreqPier2G = {
 146                 FREQ2FBIN(2412, 1),
 147                 FREQ2FBIN(2437, 1),
 148                 FREQ2FBIN(2472, 1),
 149          },
 150         /* ar9300_cal_data_per_freq_op_loop 2g */
 151         .calPierData2G = {
 152                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 153                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 154                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 155          },
 156         .calTarget_freqbin_Cck = {
 157                 FREQ2FBIN(2412, 1),
 158                 FREQ2FBIN(2484, 1),
 159          },
 160         .calTarget_freqbin_2G = {
 161                 FREQ2FBIN(2412, 1),
 162                 FREQ2FBIN(2437, 1),
 163                 FREQ2FBIN(2472, 1)
 164          },
 165         .calTarget_freqbin_2GHT20 = {
 166                 FREQ2FBIN(2412, 1),
 167                 FREQ2FBIN(2437, 1),
 168                 FREQ2FBIN(2472, 1)
 169          },
 170         .calTarget_freqbin_2GHT40 = {
 171                 FREQ2FBIN(2412, 1),
 172                 FREQ2FBIN(2437, 1),
 173                 FREQ2FBIN(2472, 1)
 174          },
 175         .calTargetPowerCck = {
 176                  /* 1L-5L,5S,11L,11S */
 177                  { {36, 36, 36, 36} },
 178                  { {36, 36, 36, 36} },
 179         },
 180         .calTargetPower2G = {
 181                  /* 6-24,36,48,54 */
 182                  { {32, 32, 28, 24} },
 183                  { {32, 32, 28, 24} },
 184                  { {32, 32, 28, 24} },
 185         },
 186         .calTargetPower2GHT20 = {
 187                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 188                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 189                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 190         },
 191         .calTargetPower2GHT40 = {
 192                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 193                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 194                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 195         },
 196         .ctlIndex_2G =  {
 197                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 198                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 199         },
 200         .ctl_freqbin_2G = {
 201                 {
 202                         FREQ2FBIN(2412, 1),
 203                         FREQ2FBIN(2417, 1),
 204                         FREQ2FBIN(2457, 1),
 205                         FREQ2FBIN(2462, 1)
 206                 },
 207                 {
 208                         FREQ2FBIN(2412, 1),
 209                         FREQ2FBIN(2417, 1),
 210                         FREQ2FBIN(2462, 1),
 211                         0xFF,
 212                 },
 213
 214                 {
 215                         FREQ2FBIN(2412, 1),
 216                         FREQ2FBIN(2417, 1),
 217                         FREQ2FBIN(2462, 1),
 218                         0xFF,
 219                 },
 220                 {
 221                         FREQ2FBIN(2422, 1),
 222                         FREQ2FBIN(2427, 1),
 223                         FREQ2FBIN(2447, 1),
 224                         FREQ2FBIN(2452, 1)
 225                 },
 226
 227                 {
 228                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 229                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 230                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 231                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 232                 },
 233
 234                 {
 235                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 236                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 237                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 238                         0,
 239                 },
 240
 241                 {
 242                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 243                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 244                         FREQ2FBIN(2472, 1),
 245                         0,
 246                 },
 247
 248                 {
 249                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 250                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 251                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 252                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 253                 },
 254
 255                 {
 256                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 257                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 258                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 259                 },
 260
 261                 {
 262                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 263                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 264                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 265                         0
 266                 },
 267
 268                 {
 269                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 270                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 271                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 272                         0
 273                 },
 274
 275                 {
 276                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 277                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 278                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 279                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 280                 }
 281          },
 282         .ctlPowerData_2G = {
 283                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 284                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 285                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 286
 287                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
 288                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 289                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 290
 291                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 292                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 293                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 294
 295                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 296                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 297                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 298          },
 299         .modalHeader5G = {
 300                 /* 4 idle,t1,t2,b (4 bits per setting) */
 301                 .antCtrlCommon = LE32(0x110),
 302                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 303                 .antCtrlCommon2 = LE32(0x22222),
 304                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 305                 .antCtrlChain = {
 306                         LE16(0x000), LE16(0x000), LE16(0x000),
 307                 },
 308                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 309                 .xatten1DB = {0, 0, 0},
 310
 311                 /*
 312                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 313                  * for merlin (0xa20c/b20c 16:12
 314                  */
 315                 .xatten1Margin = {0, 0, 0},
 316                 .tempSlope = 68,
 317                 .voltSlope = 0,
 318                 /* spurChans spur channels in usual fbin coding format */
 319                 .spurChans = {0, 0, 0, 0, 0},
 320                 /* noiseFloorThreshCh Check if the register is per chain */
 321                 .noiseFloorThreshCh = {-1, 0, 0},
 322                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 323                 .quick_drop = 0,
 324                 .xpaBiasLvl = 0,
 325                 .txFrameToDataStart = 0x0e,
 326                 .txFrameToPaOn = 0x0e,
 327                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 328                 .antennaGain = 0,
 329                 .switchSettling = 0x2d,
 330                 .adcDesiredSize = -30,
 331                 .txEndToXpaOff = 0,
 332                 .txEndToRxOn = 0x2,
 333                 .txFrameToXpaOn = 0xe,
 334                 .thresh62 = 28,
 335                 .papdRateMaskHt20 = LE32(0x0c80c080),
 336                 .papdRateMaskHt40 = LE32(0x0080c080),
 337                 .futureModal = {
 338                         0, 0, 0, 0, 0, 0, 0, 0,
 339                 },
 340          },
 341         .base_ext2 = {
 342                 .tempSlopeLow = 0,
 343                 .tempSlopeHigh = 0,
 344                 .xatten1DBLow = {0, 0, 0},
 345                 .xatten1MarginLow = {0, 0, 0},
 346                 .xatten1DBHigh = {0, 0, 0},
 347                 .xatten1MarginHigh = {0, 0, 0}
 348         },
 349         .calFreqPier5G = {
 350                 FREQ2FBIN(5180, 0),
 351                 FREQ2FBIN(5220, 0),
 352                 FREQ2FBIN(5320, 0),
 353                 FREQ2FBIN(5400, 0),
 354                 FREQ2FBIN(5500, 0),
 355                 FREQ2FBIN(5600, 0),
 356                 FREQ2FBIN(5725, 0),
 357                 FREQ2FBIN(5825, 0)
 358         },
 359         .calPierData5G = {
 360                         {
 361                                 {0, 0, 0, 0, 0},
 362                                 {0, 0, 0, 0, 0},
 363                                 {0, 0, 0, 0, 0},
 364                                 {0, 0, 0, 0, 0},
 365                                 {0, 0, 0, 0, 0},
 366                                 {0, 0, 0, 0, 0},
 367                                 {0, 0, 0, 0, 0},
 368                                 {0, 0, 0, 0, 0},
 369                         },
 370                         {
 371                                 {0, 0, 0, 0, 0},
 372                                 {0, 0, 0, 0, 0},
 373                                 {0, 0, 0, 0, 0},
 374                                 {0, 0, 0, 0, 0},
 375                                 {0, 0, 0, 0, 0},
 376                                 {0, 0, 0, 0, 0},
 377                                 {0, 0, 0, 0, 0},
 378                                 {0, 0, 0, 0, 0},
 379                         },
 380                         {
 381                                 {0, 0, 0, 0, 0},
 382                                 {0, 0, 0, 0, 0},
 383                                 {0, 0, 0, 0, 0},
 384                                 {0, 0, 0, 0, 0},
 385                                 {0, 0, 0, 0, 0},
 386                                 {0, 0, 0, 0, 0},
 387                                 {0, 0, 0, 0, 0},
 388                                 {0, 0, 0, 0, 0},
 389                         },
 390
 391         },
 392         .calTarget_freqbin_5G = {
 393                 FREQ2FBIN(5180, 0),
 394                 FREQ2FBIN(5220, 0),
 395                 FREQ2FBIN(5320, 0),
 396                 FREQ2FBIN(5400, 0),
 397                 FREQ2FBIN(5500, 0),
 398                 FREQ2FBIN(5600, 0),
 399                 FREQ2FBIN(5725, 0),
 400                 FREQ2FBIN(5825, 0)
 401         },
 402         .calTarget_freqbin_5GHT20 = {
 403                 FREQ2FBIN(5180, 0),
 404                 FREQ2FBIN(5240, 0),
 405                 FREQ2FBIN(5320, 0),
 406                 FREQ2FBIN(5500, 0),
 407                 FREQ2FBIN(5700, 0),
 408                 FREQ2FBIN(5745, 0),
 409                 FREQ2FBIN(5725, 0),
 410                 FREQ2FBIN(5825, 0)
 411         },
 412         .calTarget_freqbin_5GHT40 = {
 413                 FREQ2FBIN(5180, 0),
 414                 FREQ2FBIN(5240, 0),
 415                 FREQ2FBIN(5320, 0),
 416                 FREQ2FBIN(5500, 0),
 417                 FREQ2FBIN(5700, 0),
 418                 FREQ2FBIN(5745, 0),
 419                 FREQ2FBIN(5725, 0),
 420                 FREQ2FBIN(5825, 0)
 421          },
 422         .calTargetPower5G = {
 423                 /* 6-24,36,48,54 */
 424                 { {20, 20, 20, 10} },
 425                 { {20, 20, 20, 10} },
 426                 { {20, 20, 20, 10} },
 427                 { {20, 20, 20, 10} },
 428                 { {20, 20, 20, 10} },
 429                 { {20, 20, 20, 10} },
 430                 { {20, 20, 20, 10} },
 431                 { {20, 20, 20, 10} },
 432          },
 433         .calTargetPower5GHT20 = {
 434                 /*
 435                  * 0_8_16,1-3_9-11_17-19,
 436                  * 4,5,6,7,12,13,14,15,20,21,22,23
 437                  */
 438                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 439                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 440                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 441                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 442                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 443                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 444                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 445                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 446          },
 447         .calTargetPower5GHT40 =  {
 448                 /*
 449                  * 0_8_16,1-3_9-11_17-19,
 450                  * 4,5,6,7,12,13,14,15,20,21,22,23
 451                  */
 452                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 453                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 454                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 455                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 456                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 457                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 458                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 459                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 460          },
 461         .ctlIndex_5G =  {
 462                 0x10, 0x16, 0x18, 0x40, 0x46,
 463                 0x48, 0x30, 0x36, 0x38
 464         },
 465         .ctl_freqbin_5G =  {
 466                 {
 467                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 468                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 469                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 470                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 471                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
 472                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 473                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 474                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 475                 },
 476                 {
 477                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 478                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 479                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 480                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 481                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
 482                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 483                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 484                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 485                 },
 486
 487                 {
 488                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 489                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 490                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 491                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
 492                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
 493                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
 494                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
 495                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
 496                 },
 497
 498                 {
 499                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 500                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 501                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
 502                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
 503                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 504                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 505                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
 506                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
 507                 },
 508
 509                 {
 510                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 511                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 512                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
 513                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
 514                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
 515                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
 516                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
 517                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
 518                 },
 519
 520                 {
 521                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 522                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
 523                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
 524                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 525                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
 526                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 527                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
 528                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
 529                 },
 530
 531                 {
 532                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 533                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 534                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
 535                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
 536                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 537                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
 538                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
 539                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
 540                 },
 541
 542                 {
 543                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 544                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 545                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
 546                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 547                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
 548                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 549                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 550                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 551                 },
 552
 553                 {
 554                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 555                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 556                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 557                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 558                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
 559                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 560                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
 561                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
 562                 }
 563          },
 564         .ctlPowerData_5G = {
 565                 {
 566                         {
 567                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 568                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 569                         }
 570                 },
 571                 {
 572                         {
 573                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 574                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 575                         }
 576                 },
 577                 {
 578                         {
 579                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 580                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 581                         }
 582                 },
 583                 {
 584                         {
 585                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 586                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 587                         }
 588                 },
 589                 {
 590                         {
 591                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 592                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 593                         }
 594                 },
 595                 {
 596                         {
 597                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 598                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 599                         }
 600                 },
 601                 {
 602                         {
 603                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 604                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 605                         }
 606                 },
 607                 {
 608                         {
 609                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 610                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 611                         }
 612                 },
 613                 {
 614                         {
 615                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
 616                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 617                         }
 618                 },
 619          }
 620 };
 621
 622 static const struct ar9300_eeprom ar9300_x113 = {
 623         .eepromVersion = 2,
 624         .templateVersion = 6,
 625         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
 626         .custData = {"x113-023-f0000"},
 627         .baseEepHeader = {
 628                 .regDmn = { LE16(0), LE16(0x1f) },
 629                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
 630                 .opCapFlags = {
 631                         .opFlags = AR5416_OPFLAGS_11A,
 632                         .eepMisc = 0,
 633                 },
 634                 .rfSilent = 0,
 635                 .blueToothOptions = 0,
 636                 .deviceCap = 0,
 637                 .deviceType = 5, /* takes lower byte in eeprom location */
 638                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
 639                 .params_for_tuning_caps = {0, 0},
 640                 .featureEnable = 0x0d,
 641                  /*
 642                   * bit0 - enable tx temp comp - disabled
 643                   * bit1 - enable tx volt comp - disabled
 644                   * bit2 - enable fastClock - enabled
 645                   * bit3 - enable doubling - enabled
 646                   * bit4 - enable internal regulator - disabled
 647                   * bit5 - enable pa predistortion - disabled
 648                   */
 649                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
 650                 .eepromWriteEnableGpio = 6,
 651                 .wlanDisableGpio = 0,
 652                 .wlanLedGpio = 8,
 653                 .rxBandSelectGpio = 0xff,
 654                 .txrxgain = 0x21,
 655                 .swreg = 0,
 656          },
 657         .modalHeader2G = {
 658         /* ar9300_modal_eep_header  2g */
 659                 /* 4 idle,t1,t2,b(4 bits per setting) */
 660                 .antCtrlCommon = LE32(0x110),
 661                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 662                 .antCtrlCommon2 = LE32(0x44444),
 663
 664                 /*
 665                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 666                  * rx1, rx12, b (2 bits each)
 667                  */
 668                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 669
 670                 /*
 671                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 672                  * for ar9280 (0xa20c/b20c 5:0)
 673                  */
 674                 .xatten1DB = {0, 0, 0},
 675
 676                 /*
 677                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 678                  * for ar9280 (0xa20c/b20c 16:12
 679                  */
 680                 .xatten1Margin = {0, 0, 0},
 681                 .tempSlope = 25,
 682                 .voltSlope = 0,
 683
 684                 /*
 685                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 686                  * channels in usual fbin coding format
 687                  */
 688                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
 689
 690                 /*
 691                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 692                  * if the register is per chain
 693                  */
 694                 .noiseFloorThreshCh = {-1, 0, 0},
 695                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 696                 .quick_drop = 0,
 697                 .xpaBiasLvl = 0,
 698                 .txFrameToDataStart = 0x0e,
 699                 .txFrameToPaOn = 0x0e,
 700                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 701                 .antennaGain = 0,
 702                 .switchSettling = 0x2c,
 703                 .adcDesiredSize = -30,
 704                 .txEndToXpaOff = 0,
 705                 .txEndToRxOn = 0x2,
 706                 .txFrameToXpaOn = 0xe,
 707                 .thresh62 = 28,
 708                 .papdRateMaskHt20 = LE32(0x0c80c080),
 709                 .papdRateMaskHt40 = LE32(0x0080c080),
 710                 .futureModal = {
 711                         0, 0, 0, 0, 0, 0, 0, 0,
 712                 },
 713          },
 714          .base_ext1 = {
 715                 .ant_div_control = 0,
 716                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 717          },
 718         .calFreqPier2G = {
 719                 FREQ2FBIN(2412, 1),
 720                 FREQ2FBIN(2437, 1),
 721                 FREQ2FBIN(2472, 1),
 722          },
 723         /* ar9300_cal_data_per_freq_op_loop 2g */
 724         .calPierData2G = {
 725                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 726                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 727                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 728          },
 729         .calTarget_freqbin_Cck = {
 730                 FREQ2FBIN(2412, 1),
 731                 FREQ2FBIN(2472, 1),
 732          },
 733         .calTarget_freqbin_2G = {
 734                 FREQ2FBIN(2412, 1),
 735                 FREQ2FBIN(2437, 1),
 736                 FREQ2FBIN(2472, 1)
 737          },
 738         .calTarget_freqbin_2GHT20 = {
 739                 FREQ2FBIN(2412, 1),
 740                 FREQ2FBIN(2437, 1),
 741                 FREQ2FBIN(2472, 1)
 742          },
 743         .calTarget_freqbin_2GHT40 = {
 744                 FREQ2FBIN(2412, 1),
 745                 FREQ2FBIN(2437, 1),
 746                 FREQ2FBIN(2472, 1)
 747          },
 748         .calTargetPowerCck = {
 749                  /* 1L-5L,5S,11L,11S */
 750                  { {34, 34, 34, 34} },
 751                  { {34, 34, 34, 34} },
 752         },
 753         .calTargetPower2G = {
 754                  /* 6-24,36,48,54 */
 755                  { {34, 34, 32, 32} },
 756                  { {34, 34, 32, 32} },
 757                  { {34, 34, 32, 32} },
 758         },
 759         .calTargetPower2GHT20 = {
 760                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 761                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 762                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 763         },
 764         .calTargetPower2GHT40 = {
 765                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 766                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 767                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 768         },
 769         .ctlIndex_2G =  {
 770                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 771                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 772         },
 773         .ctl_freqbin_2G = {
 774                 {
 775                         FREQ2FBIN(2412, 1),
 776                         FREQ2FBIN(2417, 1),
 777                         FREQ2FBIN(2457, 1),
 778                         FREQ2FBIN(2462, 1)
 779                 },
 780                 {
 781                         FREQ2FBIN(2412, 1),
 782                         FREQ2FBIN(2417, 1),
 783                         FREQ2FBIN(2462, 1),
 784                         0xFF,
 785                 },
 786
 787                 {
 788                         FREQ2FBIN(2412, 1),
 789                         FREQ2FBIN(2417, 1),
 790                         FREQ2FBIN(2462, 1),
 791                         0xFF,
 792                 },
 793                 {
 794                         FREQ2FBIN(2422, 1),
 795                         FREQ2FBIN(2427, 1),
 796                         FREQ2FBIN(2447, 1),
 797                         FREQ2FBIN(2452, 1)
 798                 },
 799
 800                 {
 801                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 802                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 803                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 804                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 805                 },
 806
 807                 {
 808                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 809                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 810                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 811                         0,
 812                 },
 813
 814                 {
 815                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 816                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 817                         FREQ2FBIN(2472, 1),
 818                         0,
 819                 },
 820
 821                 {
 822                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 823                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 824                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 825                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 826                 },
 827
 828                 {
 829                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 830                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 831                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 832                 },
 833
 834                 {
 835                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 836                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 837                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 838                         0
 839                 },
 840
 841                 {
 842                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 843                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 844                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 845                         0
 846                 },
 847
 848                 {
 849                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 850                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 851                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 852                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 853                 }
 854          },
 855         .ctlPowerData_2G = {
 856                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 857                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 858                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 859
 860                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
 861                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 862                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 863
 864                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 865                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 866                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 867
 868                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 869                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 870                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 871          },
 872         .modalHeader5G = {
 873                 /* 4 idle,t1,t2,b (4 bits per setting) */
 874                 .antCtrlCommon = LE32(0x220),
 875                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 876                 .antCtrlCommon2 = LE32(0x11111),
 877                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 878                 .antCtrlChain = {
 879                         LE16(0x150), LE16(0x150), LE16(0x150),
 880                 },
 881                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 882                 .xatten1DB = {0, 0, 0},
 883
 884                 /*
 885                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 886                  * for merlin (0xa20c/b20c 16:12
 887                  */
 888                 .xatten1Margin = {0, 0, 0},
 889                 .tempSlope = 68,
 890                 .voltSlope = 0,
 891                 /* spurChans spur channels in usual fbin coding format */
 892                 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
 893                 /* noiseFloorThreshCh Check if the register is per chain */
 894                 .noiseFloorThreshCh = {-1, 0, 0},
 895                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 896                 .quick_drop = 0,
 897                 .xpaBiasLvl = 0xf,
 898                 .txFrameToDataStart = 0x0e,
 899                 .txFrameToPaOn = 0x0e,
 900                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 901                 .antennaGain = 0,
 902                 .switchSettling = 0x2d,
 903                 .adcDesiredSize = -30,
 904                 .txEndToXpaOff = 0,
 905                 .txEndToRxOn = 0x2,
 906                 .txFrameToXpaOn = 0xe,
 907                 .thresh62 = 28,
 908                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 909                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 910                 .futureModal = {
 911                         0, 0, 0, 0, 0, 0, 0, 0,
 912                 },
 913          },
 914         .base_ext2 = {
 915                 .tempSlopeLow = 72,
 916                 .tempSlopeHigh = 105,
 917                 .xatten1DBLow = {0, 0, 0},
 918                 .xatten1MarginLow = {0, 0, 0},
 919                 .xatten1DBHigh = {0, 0, 0},
 920                 .xatten1MarginHigh = {0, 0, 0}
 921          },
 922         .calFreqPier5G = {
 923                 FREQ2FBIN(5180, 0),
 924                 FREQ2FBIN(5240, 0),
 925                 FREQ2FBIN(5320, 0),
 926                 FREQ2FBIN(5400, 0),
 927                 FREQ2FBIN(5500, 0),
 928                 FREQ2FBIN(5600, 0),
 929                 FREQ2FBIN(5745, 0),
 930                 FREQ2FBIN(5785, 0)
 931         },
 932         .calPierData5G = {
 933                         {
 934                                 {0, 0, 0, 0, 0},
 935                                 {0, 0, 0, 0, 0},
 936                                 {0, 0, 0, 0, 0},
 937                                 {0, 0, 0, 0, 0},
 938                                 {0, 0, 0, 0, 0},
 939                                 {0, 0, 0, 0, 0},
 940                                 {0, 0, 0, 0, 0},
 941                                 {0, 0, 0, 0, 0},
 942                         },
 943                         {
 944                                 {0, 0, 0, 0, 0},
 945                                 {0, 0, 0, 0, 0},
 946                                 {0, 0, 0, 0, 0},
 947                                 {0, 0, 0, 0, 0},
 948                                 {0, 0, 0, 0, 0},
 949                                 {0, 0, 0, 0, 0},
 950                                 {0, 0, 0, 0, 0},
 951                                 {0, 0, 0, 0, 0},
 952                         },
 953                         {
 954                                 {0, 0, 0, 0, 0},
 955                                 {0, 0, 0, 0, 0},
 956                                 {0, 0, 0, 0, 0},
 957                                 {0, 0, 0, 0, 0},
 958                                 {0, 0, 0, 0, 0},
 959                                 {0, 0, 0, 0, 0},
 960                                 {0, 0, 0, 0, 0},
 961                                 {0, 0, 0, 0, 0},
 962                         },
 963
 964         },
 965         .calTarget_freqbin_5G = {
 966                 FREQ2FBIN(5180, 0),
 967                 FREQ2FBIN(5220, 0),
 968                 FREQ2FBIN(5320, 0),
 969                 FREQ2FBIN(5400, 0),
 970                 FREQ2FBIN(5500, 0),
 971                 FREQ2FBIN(5600, 0),
 972                 FREQ2FBIN(5745, 0),
 973                 FREQ2FBIN(5785, 0)
 974         },
 975         .calTarget_freqbin_5GHT20 = {
 976                 FREQ2FBIN(5180, 0),
 977                 FREQ2FBIN(5240, 0),
 978                 FREQ2FBIN(5320, 0),
 979                 FREQ2FBIN(5400, 0),
 980                 FREQ2FBIN(5500, 0),
 981                 FREQ2FBIN(5700, 0),
 982                 FREQ2FBIN(5745, 0),
 983                 FREQ2FBIN(5825, 0)
 984         },
 985         .calTarget_freqbin_5GHT40 = {
 986                 FREQ2FBIN(5190, 0),
 987                 FREQ2FBIN(5230, 0),
 988                 FREQ2FBIN(5320, 0),
 989                 FREQ2FBIN(5410, 0),
 990                 FREQ2FBIN(5510, 0),
 991                 FREQ2FBIN(5670, 0),
 992                 FREQ2FBIN(5755, 0),
 993                 FREQ2FBIN(5825, 0)
 994          },
 995         .calTargetPower5G = {
 996                 /* 6-24,36,48,54 */
 997                 { {42, 40, 40, 34} },
 998                 { {42, 40, 40, 34} },
 999                 { {42, 40, 40, 34} },
1000                 { {42, 40, 40, 34} },
1001                 { {42, 40, 40, 34} },
1002                 { {42, 40, 40, 34} },
1003                 { {42, 40, 40, 34} },
1004                 { {42, 40, 40, 34} },
1005          },
1006         .calTargetPower5GHT20 = {
1007                 /*
1008                  * 0_8_16,1-3_9-11_17-19,
1009                  * 4,5,6,7,12,13,14,15,20,21,22,23
1010                  */
1011                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1012                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1013                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1014                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1015                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1016                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1017                 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1018                 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1019          },
1020         .calTargetPower5GHT40 =  {
1021                 /*
1022                  * 0_8_16,1-3_9-11_17-19,
1023                  * 4,5,6,7,12,13,14,15,20,21,22,23
1024                  */
1025                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1026                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1027                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1028                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1029                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1030                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1031                 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1032                 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1033          },
1034         .ctlIndex_5G =  {
1035                 0x10, 0x16, 0x18, 0x40, 0x46,
1036                 0x48, 0x30, 0x36, 0x38
1037         },
1038         .ctl_freqbin_5G =  {
1039                 {
1040                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1041                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1042                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1043                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1044                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1045                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1046                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1047                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1048                 },
1049                 {
1050                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1051                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1052                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1053                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1054                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1055                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1056                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1057                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1058                 },
1059
1060                 {
1061                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1062                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1063                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1064                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1065                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1066                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1067                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1068                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1069                 },
1070
1071                 {
1072                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1073                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1074                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1075                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1076                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1077                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1078                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1079                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1080                 },
1081
1082                 {
1083                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1084                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1085                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1086                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1087                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1088                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1089                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1090                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1091                 },
1092
1093                 {
1094                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1095                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1096                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1097                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1098                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1099                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1100                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1101                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1102                 },
1103
1104                 {
1105                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1106                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1107                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1108                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1109                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1110                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1111                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1112                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1113                 },
1114
1115                 {
1116                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1117                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1118                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1119                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1120                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1121                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1122                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1123                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1124                 },
1125
1126                 {
1127                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1128                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1129                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1130                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1131                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1132                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1133                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1134                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1135                 }
1136          },
1137         .ctlPowerData_5G = {
1138                 {
1139                         {
1140                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1141                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1142                         }
1143                 },
1144                 {
1145                         {
1146                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1147                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1148                         }
1149                 },
1150                 {
1151                         {
1152                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1153                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1154                         }
1155                 },
1156                 {
1157                         {
1158                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1159                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1160                         }
1161                 },
1162                 {
1163                         {
1164                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1165                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1166                         }
1167                 },
1168                 {
1169                         {
1170                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1171                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1172                         }
1173                 },
1174                 {
1175                         {
1176                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1177                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1178                         }
1179                 },
1180                 {
1181                         {
1182                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1183                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1184                         }
1185                 },
1186                 {
1187                         {
1188                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1189                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1190                         }
1191                 },
1192          }
1193 };
1194
1195
1196 static const struct ar9300_eeprom ar9300_h112 = {
1197         .eepromVersion = 2,
1198         .templateVersion = 3,
1199         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1200         .custData = {"h112-241-f0000"},
1201         .baseEepHeader = {
1202                 .regDmn = { LE16(0), LE16(0x1f) },
1203                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1204                 .opCapFlags = {
1205                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1206                         .eepMisc = 0,
1207                 },
1208                 .rfSilent = 0,
1209                 .blueToothOptions = 0,
1210                 .deviceCap = 0,
1211                 .deviceType = 5, /* takes lower byte in eeprom location */
1212                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1213                 .params_for_tuning_caps = {0, 0},
1214                 .featureEnable = 0x0d,
1215                 /*
1216                  * bit0 - enable tx temp comp - disabled
1217                  * bit1 - enable tx volt comp - disabled
1218                  * bit2 - enable fastClock - enabled
1219                  * bit3 - enable doubling - enabled
1220                  * bit4 - enable internal regulator - disabled
1221                  * bit5 - enable pa predistortion - disabled
1222                  */
1223                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1224                 .eepromWriteEnableGpio = 6,
1225                 .wlanDisableGpio = 0,
1226                 .wlanLedGpio = 8,
1227                 .rxBandSelectGpio = 0xff,
1228                 .txrxgain = 0x10,
1229                 .swreg = 0,
1230         },
1231         .modalHeader2G = {
1232                 /* ar9300_modal_eep_header  2g */
1233                 /* 4 idle,t1,t2,b(4 bits per setting) */
1234                 .antCtrlCommon = LE32(0x110),
1235                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1236                 .antCtrlCommon2 = LE32(0x44444),
1237
1238                 /*
1239                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1240                  * rx1, rx12, b (2 bits each)
1241                  */
1242                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1243
1244                 /*
1245                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
1246                  * for ar9280 (0xa20c/b20c 5:0)
1247                  */
1248                 .xatten1DB = {0, 0, 0},
1249
1250                 /*
1251                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1252                  * for ar9280 (0xa20c/b20c 16:12
1253                  */
1254                 .xatten1Margin = {0, 0, 0},
1255                 .tempSlope = 25,
1256                 .voltSlope = 0,
1257
1258                 /*
1259                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1260                  * channels in usual fbin coding format
1261                  */
1262                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1263
1264                 /*
1265                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1266                  * if the register is per chain
1267                  */
1268                 .noiseFloorThreshCh = {-1, 0, 0},
1269                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1270                 .quick_drop = 0,
1271                 .xpaBiasLvl = 0,
1272                 .txFrameToDataStart = 0x0e,
1273                 .txFrameToPaOn = 0x0e,
1274                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1275                 .antennaGain = 0,
1276                 .switchSettling = 0x2c,
1277                 .adcDesiredSize = -30,
1278                 .txEndToXpaOff = 0,
1279                 .txEndToRxOn = 0x2,
1280                 .txFrameToXpaOn = 0xe,
1281                 .thresh62 = 28,
1282                 .papdRateMaskHt20 = LE32(0x0c80c080),
1283                 .papdRateMaskHt40 = LE32(0x0080c080),
1284                 .futureModal = {
1285                         0, 0, 0, 0, 0, 0, 0, 0,
1286                 },
1287         },
1288         .base_ext1 = {
1289                 .ant_div_control = 0,
1290                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1291         },
1292         .calFreqPier2G = {
1293                 FREQ2FBIN(2412, 1),
1294                 FREQ2FBIN(2437, 1),
1295                 FREQ2FBIN(2462, 1),
1296         },
1297         /* ar9300_cal_data_per_freq_op_loop 2g */
1298         .calPierData2G = {
1299                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1300                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1301                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1302         },
1303         .calTarget_freqbin_Cck = {
1304                 FREQ2FBIN(2412, 1),
1305                 FREQ2FBIN(2472, 1),
1306         },
1307         .calTarget_freqbin_2G = {
1308                 FREQ2FBIN(2412, 1),
1309                 FREQ2FBIN(2437, 1),
1310                 FREQ2FBIN(2472, 1)
1311         },
1312         .calTarget_freqbin_2GHT20 = {
1313                 FREQ2FBIN(2412, 1),
1314                 FREQ2FBIN(2437, 1),
1315                 FREQ2FBIN(2472, 1)
1316         },
1317         .calTarget_freqbin_2GHT40 = {
1318                 FREQ2FBIN(2412, 1),
1319                 FREQ2FBIN(2437, 1),
1320                 FREQ2FBIN(2472, 1)
1321         },
1322         .calTargetPowerCck = {
1323                 /* 1L-5L,5S,11L,11S */
1324                 { {34, 34, 34, 34} },
1325                 { {34, 34, 34, 34} },
1326         },
1327         .calTargetPower2G = {
1328                 /* 6-24,36,48,54 */
1329                 { {34, 34, 32, 32} },
1330                 { {34, 34, 32, 32} },
1331                 { {34, 34, 32, 32} },
1332         },
1333         .calTargetPower2GHT20 = {
1334                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1335                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1336                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1337         },
1338         .calTargetPower2GHT40 = {
1339                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1340                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1341                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1342         },
1343         .ctlIndex_2G =  {
1344                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1345                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1346         },
1347         .ctl_freqbin_2G = {
1348                 {
1349                         FREQ2FBIN(2412, 1),
1350                         FREQ2FBIN(2417, 1),
1351                         FREQ2FBIN(2457, 1),
1352                         FREQ2FBIN(2462, 1)
1353                 },
1354                 {
1355                         FREQ2FBIN(2412, 1),
1356                         FREQ2FBIN(2417, 1),
1357                         FREQ2FBIN(2462, 1),
1358                         0xFF,
1359                 },
1360
1361                 {
1362                         FREQ2FBIN(2412, 1),
1363                         FREQ2FBIN(2417, 1),
1364                         FREQ2FBIN(2462, 1),
1365                         0xFF,
1366                 },
1367                 {
1368                         FREQ2FBIN(2422, 1),
1369                         FREQ2FBIN(2427, 1),
1370                         FREQ2FBIN(2447, 1),
1371                         FREQ2FBIN(2452, 1)
1372                 },
1373
1374                 {
1375                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1376                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1377                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1378                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1379                 },
1380
1381                 {
1382                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1383                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1384                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1385                         0,
1386                 },
1387
1388                 {
1389                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1390                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1391                         FREQ2FBIN(2472, 1),
1392                         0,
1393                 },
1394
1395                 {
1396                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1397                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1398                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1399                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1400                 },
1401
1402                 {
1403                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1404                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1405                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1406                 },
1407
1408                 {
1409                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1410                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1411                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1412                         0
1413                 },
1414
1415                 {
1416                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1417                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1418                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1419                         0
1420                 },
1421
1422                 {
1423                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1424                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1425                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1426                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1427                 }
1428         },
1429         .ctlPowerData_2G = {
1430                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1431                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1432                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1433
1434                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
1435                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1436                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1437
1438                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1439                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1440                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1441
1442                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1443                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1444                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1445         },
1446         .modalHeader5G = {
1447                 /* 4 idle,t1,t2,b (4 bits per setting) */
1448                 .antCtrlCommon = LE32(0x220),
1449                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1450                 .antCtrlCommon2 = LE32(0x44444),
1451                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1452                 .antCtrlChain = {
1453                         LE16(0x150), LE16(0x150), LE16(0x150),
1454                 },
1455                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1456                 .xatten1DB = {0, 0, 0},
1457
1458                 /*
1459                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1460                  * for merlin (0xa20c/b20c 16:12
1461                  */
1462                 .xatten1Margin = {0, 0, 0},
1463                 .tempSlope = 45,
1464                 .voltSlope = 0,
1465                 /* spurChans spur channels in usual fbin coding format */
1466                 .spurChans = {0, 0, 0, 0, 0},
1467                 /* noiseFloorThreshCh Check if the register is per chain */
1468                 .noiseFloorThreshCh = {-1, 0, 0},
1469                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1470                 .quick_drop = 0,
1471                 .xpaBiasLvl = 0,
1472                 .txFrameToDataStart = 0x0e,
1473                 .txFrameToPaOn = 0x0e,
1474                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1475                 .antennaGain = 0,
1476                 .switchSettling = 0x2d,
1477                 .adcDesiredSize = -30,
1478                 .txEndToXpaOff = 0,
1479                 .txEndToRxOn = 0x2,
1480                 .txFrameToXpaOn = 0xe,
1481                 .thresh62 = 28,
1482                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1483                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1484                 .futureModal = {
1485                         0, 0, 0, 0, 0, 0, 0, 0,
1486                 },
1487         },
1488         .base_ext2 = {
1489                 .tempSlopeLow = 40,
1490                 .tempSlopeHigh = 50,
1491                 .xatten1DBLow = {0, 0, 0},
1492                 .xatten1MarginLow = {0, 0, 0},
1493                 .xatten1DBHigh = {0, 0, 0},
1494                 .xatten1MarginHigh = {0, 0, 0}
1495         },
1496         .calFreqPier5G = {
1497                 FREQ2FBIN(5180, 0),
1498                 FREQ2FBIN(5220, 0),
1499                 FREQ2FBIN(5320, 0),
1500                 FREQ2FBIN(5400, 0),
1501                 FREQ2FBIN(5500, 0),
1502                 FREQ2FBIN(5600, 0),
1503                 FREQ2FBIN(5700, 0),
1504                 FREQ2FBIN(5785, 0)
1505         },
1506         .calPierData5G = {
1507                 {
1508                         {0, 0, 0, 0, 0},
1509                         {0, 0, 0, 0, 0},
1510                         {0, 0, 0, 0, 0},
1511                         {0, 0, 0, 0, 0},
1512                         {0, 0, 0, 0, 0},
1513                         {0, 0, 0, 0, 0},
1514                         {0, 0, 0, 0, 0},
1515                         {0, 0, 0, 0, 0},
1516                 },
1517                 {
1518                         {0, 0, 0, 0, 0},
1519                         {0, 0, 0, 0, 0},
1520                         {0, 0, 0, 0, 0},
1521                         {0, 0, 0, 0, 0},
1522                         {0, 0, 0, 0, 0},
1523                         {0, 0, 0, 0, 0},
1524                         {0, 0, 0, 0, 0},
1525                         {0, 0, 0, 0, 0},
1526                 },
1527                 {
1528                         {0, 0, 0, 0, 0},
1529                         {0, 0, 0, 0, 0},
1530                         {0, 0, 0, 0, 0},
1531                         {0, 0, 0, 0, 0},
1532                         {0, 0, 0, 0, 0},
1533                         {0, 0, 0, 0, 0},
1534                         {0, 0, 0, 0, 0},
1535                         {0, 0, 0, 0, 0},
1536                 },
1537
1538         },
1539         .calTarget_freqbin_5G = {
1540                 FREQ2FBIN(5180, 0),
1541                 FREQ2FBIN(5240, 0),
1542                 FREQ2FBIN(5320, 0),
1543                 FREQ2FBIN(5400, 0),
1544                 FREQ2FBIN(5500, 0),
1545                 FREQ2FBIN(5600, 0),
1546                 FREQ2FBIN(5700, 0),
1547                 FREQ2FBIN(5825, 0)
1548         },
1549         .calTarget_freqbin_5GHT20 = {
1550                 FREQ2FBIN(5180, 0),
1551                 FREQ2FBIN(5240, 0),
1552                 FREQ2FBIN(5320, 0),
1553                 FREQ2FBIN(5400, 0),
1554                 FREQ2FBIN(5500, 0),
1555                 FREQ2FBIN(5700, 0),
1556                 FREQ2FBIN(5745, 0),
1557                 FREQ2FBIN(5825, 0)
1558         },
1559         .calTarget_freqbin_5GHT40 = {
1560                 FREQ2FBIN(5180, 0),
1561                 FREQ2FBIN(5240, 0),
1562                 FREQ2FBIN(5320, 0),
1563                 FREQ2FBIN(5400, 0),
1564                 FREQ2FBIN(5500, 0),
1565                 FREQ2FBIN(5700, 0),
1566                 FREQ2FBIN(5745, 0),
1567                 FREQ2FBIN(5825, 0)
1568         },
1569         .calTargetPower5G = {
1570                 /* 6-24,36,48,54 */
1571                 { {30, 30, 28, 24} },
1572                 { {30, 30, 28, 24} },
1573                 { {30, 30, 28, 24} },
1574                 { {30, 30, 28, 24} },
1575                 { {30, 30, 28, 24} },
1576                 { {30, 30, 28, 24} },
1577                 { {30, 30, 28, 24} },
1578                 { {30, 30, 28, 24} },
1579         },
1580         .calTargetPower5GHT20 = {
1581                 /*
1582                  * 0_8_16,1-3_9-11_17-19,
1583                  * 4,5,6,7,12,13,14,15,20,21,22,23
1584                  */
1585                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1586                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1587                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1588                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1589                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1590                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1591                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1592                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1593         },
1594         .calTargetPower5GHT40 =  {
1595                 /*
1596                  * 0_8_16,1-3_9-11_17-19,
1597                  * 4,5,6,7,12,13,14,15,20,21,22,23
1598                  */
1599                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1600                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1601                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1602                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1603                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1604                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1605                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1606                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1607         },
1608         .ctlIndex_5G =  {
1609                 0x10, 0x16, 0x18, 0x40, 0x46,
1610                 0x48, 0x30, 0x36, 0x38
1611         },
1612         .ctl_freqbin_5G =  {
1613                 {
1614                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1615                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1616                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1617                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1618                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1619                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1620                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1621                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1622                 },
1623                 {
1624                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1625                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1626                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1627                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1628                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1629                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1630                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1631                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1632                 },
1633
1634                 {
1635                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1636                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1637                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1638                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1639                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1640                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1641                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1642                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1643                 },
1644
1645                 {
1646                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1647                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1648                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1649                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1650                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1651                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1652                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1653                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1654                 },
1655
1656                 {
1657                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1658                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1659                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1660                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1661                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1662                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1663                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1664                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1665                 },
1666
1667                 {
1668                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1669                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1670                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1671                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1672                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1673                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1674                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1675                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1676                 },
1677
1678                 {
1679                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1680                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1681                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1682                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1683                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1684                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1685                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1686                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1687                 },
1688
1689                 {
1690                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1691                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1692                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1693                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1694                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1695                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1696                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1697                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1698                 },
1699
1700                 {
1701                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1702                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1703                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1704                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1705                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1706                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1707                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1708                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1709                 }
1710         },
1711         .ctlPowerData_5G = {
1712                 {
1713                         {
1714                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1715                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1716                         }
1717                 },
1718                 {
1719                         {
1720                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1721                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1722                         }
1723                 },
1724                 {
1725                         {
1726                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1727                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1728                         }
1729                 },
1730                 {
1731                         {
1732                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1733                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1734                         }
1735                 },
1736                 {
1737                         {
1738                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1739                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1740                         }
1741                 },
1742                 {
1743                         {
1744                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1745                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1746                         }
1747                 },
1748                 {
1749                         {
1750                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1751                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1752                         }
1753                 },
1754                 {
1755                         {
1756                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1757                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1758                         }
1759                 },
1760                 {
1761                         {
1762                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1763                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1764                         }
1765                 },
1766         }
1767 };
1768
1769
1770 static const struct ar9300_eeprom ar9300_x112 = {
1771         .eepromVersion = 2,
1772         .templateVersion = 5,
1773         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1774         .custData = {"x112-041-f0000"},
1775         .baseEepHeader = {
1776                 .regDmn = { LE16(0), LE16(0x1f) },
1777                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1778                 .opCapFlags = {
1779                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1780                         .eepMisc = 0,
1781                 },
1782                 .rfSilent = 0,
1783                 .blueToothOptions = 0,
1784                 .deviceCap = 0,
1785                 .deviceType = 5, /* takes lower byte in eeprom location */
1786                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1787                 .params_for_tuning_caps = {0, 0},
1788                 .featureEnable = 0x0d,
1789                 /*
1790                  * bit0 - enable tx temp comp - disabled
1791                  * bit1 - enable tx volt comp - disabled
1792                  * bit2 - enable fastclock - enabled
1793                  * bit3 - enable doubling - enabled
1794                  * bit4 - enable internal regulator - disabled
1795                  * bit5 - enable pa predistortion - disabled
1796                  */
1797                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1798                 .eepromWriteEnableGpio = 6,
1799                 .wlanDisableGpio = 0,
1800                 .wlanLedGpio = 8,
1801                 .rxBandSelectGpio = 0xff,
1802                 .txrxgain = 0x0,
1803                 .swreg = 0,
1804         },
1805         .modalHeader2G = {
1806                 /* ar9300_modal_eep_header  2g */
1807                 /* 4 idle,t1,t2,b(4 bits per setting) */
1808                 .antCtrlCommon = LE32(0x110),
1809                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1810                 .antCtrlCommon2 = LE32(0x22222),
1811
1812                 /*
1813                  * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1814                  * rx1, rx12, b (2 bits each)
1815                  */
1816                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1817
1818                 /*
1819                  * xatten1DB[AR9300_max_chains];  3 xatten1_db
1820                  * for ar9280 (0xa20c/b20c 5:0)
1821                  */
1822                 .xatten1DB = {0x1b, 0x1b, 0x1b},
1823
1824                 /*
1825                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1826                  * for ar9280 (0xa20c/b20c 16:12
1827                  */
1828                 .xatten1Margin = {0x15, 0x15, 0x15},
1829                 .tempSlope = 50,
1830                 .voltSlope = 0,
1831
1832                 /*
1833                  * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1834                  * channels in usual fbin coding format
1835                  */
1836                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1837
1838                 /*
1839                  * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1840                  * if the register is per chain
1841                  */
1842                 .noiseFloorThreshCh = {-1, 0, 0},
1843                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1844                 .quick_drop = 0,
1845                 .xpaBiasLvl = 0,
1846                 .txFrameToDataStart = 0x0e,
1847                 .txFrameToPaOn = 0x0e,
1848                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1849                 .antennaGain = 0,
1850                 .switchSettling = 0x2c,
1851                 .adcDesiredSize = -30,
1852                 .txEndToXpaOff = 0,
1853                 .txEndToRxOn = 0x2,
1854                 .txFrameToXpaOn = 0xe,
1855                 .thresh62 = 28,
1856                 .papdRateMaskHt20 = LE32(0x0c80c080),
1857                 .papdRateMaskHt40 = LE32(0x0080c080),
1858                 .futureModal = {
1859                         0, 0, 0, 0, 0, 0, 0, 0,
1860                 },
1861         },
1862         .base_ext1 = {
1863                 .ant_div_control = 0,
1864                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1865         },
1866         .calFreqPier2G = {
1867                 FREQ2FBIN(2412, 1),
1868                 FREQ2FBIN(2437, 1),
1869                 FREQ2FBIN(2472, 1),
1870         },
1871         /* ar9300_cal_data_per_freq_op_loop 2g */
1872         .calPierData2G = {
1873                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1874                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1875                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1876         },
1877         .calTarget_freqbin_Cck = {
1878                 FREQ2FBIN(2412, 1),
1879                 FREQ2FBIN(2472, 1),
1880         },
1881         .calTarget_freqbin_2G = {
1882                 FREQ2FBIN(2412, 1),
1883                 FREQ2FBIN(2437, 1),
1884                 FREQ2FBIN(2472, 1)
1885         },
1886         .calTarget_freqbin_2GHT20 = {
1887                 FREQ2FBIN(2412, 1),
1888                 FREQ2FBIN(2437, 1),
1889                 FREQ2FBIN(2472, 1)
1890         },
1891         .calTarget_freqbin_2GHT40 = {
1892                 FREQ2FBIN(2412, 1),
1893                 FREQ2FBIN(2437, 1),
1894                 FREQ2FBIN(2472, 1)
1895         },
1896         .calTargetPowerCck = {
1897                 /* 1L-5L,5S,11L,11s */
1898                 { {38, 38, 38, 38} },
1899                 { {38, 38, 38, 38} },
1900         },
1901         .calTargetPower2G = {
1902                 /* 6-24,36,48,54 */
1903                 { {38, 38, 36, 34} },
1904                 { {38, 38, 36, 34} },
1905                 { {38, 38, 34, 32} },
1906         },
1907         .calTargetPower2GHT20 = {
1908                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1909                 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1910                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1911         },
1912         .calTargetPower2GHT40 = {
1913                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1914                 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1915                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1916         },
1917         .ctlIndex_2G =  {
1918                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1919                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1920         },
1921         .ctl_freqbin_2G = {
1922                 {
1923                         FREQ2FBIN(2412, 1),
1924                         FREQ2FBIN(2417, 1),
1925                         FREQ2FBIN(2457, 1),
1926                         FREQ2FBIN(2462, 1)
1927                 },
1928                 {
1929                         FREQ2FBIN(2412, 1),
1930                         FREQ2FBIN(2417, 1),
1931                         FREQ2FBIN(2462, 1),
1932                         0xFF,
1933                 },
1934
1935                 {
1936                         FREQ2FBIN(2412, 1),
1937                         FREQ2FBIN(2417, 1),
1938                         FREQ2FBIN(2462, 1),
1939                         0xFF,
1940                 },
1941                 {
1942                         FREQ2FBIN(2422, 1),
1943                         FREQ2FBIN(2427, 1),
1944                         FREQ2FBIN(2447, 1),
1945                         FREQ2FBIN(2452, 1)
1946                 },
1947
1948                 {
1949                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1950                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1951                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1952                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1953                 },
1954
1955                 {
1956                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1957                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1958                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1959                         0,
1960                 },
1961
1962                 {
1963                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1964                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1965                         FREQ2FBIN(2472, 1),
1966                         0,
1967                 },
1968
1969                 {
1970                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1971                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1972                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1973                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1974                 },
1975
1976                 {
1977                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1978                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1979                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1980                 },
1981
1982                 {
1983                         /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1984                         /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1985                         /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1986                         0
1987                 },
1988
1989                 {
1990                         /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1991                         /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1992                         /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1993                         0
1994                 },
1995
1996                 {
1997                         /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1998                         /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1999                         /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2000                         /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2001                 }
2002         },
2003         .ctlPowerData_2G = {
2004                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2005                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2006                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2007
2008                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2009                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2010                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2011
2012                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2013                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2014                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2015
2016                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2017                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2018                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2019         },
2020         .modalHeader5G = {
2021                 /* 4 idle,t1,t2,b (4 bits per setting) */
2022                 .antCtrlCommon = LE32(0x110),
2023                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2024                 .antCtrlCommon2 = LE32(0x22222),
2025                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2026                 .antCtrlChain = {
2027                         LE16(0x0), LE16(0x0), LE16(0x0),
2028                 },
2029                 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2030                 .xatten1DB = {0x13, 0x19, 0x17},
2031
2032                 /*
2033                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2034                  * for merlin (0xa20c/b20c 16:12
2035                  */
2036                 .xatten1Margin = {0x19, 0x19, 0x19},
2037                 .tempSlope = 70,
2038                 .voltSlope = 15,
2039                 /* spurChans spur channels in usual fbin coding format */
2040                 .spurChans = {0, 0, 0, 0, 0},
2041                 /* noiseFloorThreshch check if the register is per chain */
2042                 .noiseFloorThreshCh = {-1, 0, 0},
2043                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2044                 .quick_drop = 0,
2045                 .xpaBiasLvl = 0,
2046                 .txFrameToDataStart = 0x0e,
2047                 .txFrameToPaOn = 0x0e,
2048                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2049                 .antennaGain = 0,
2050                 .switchSettling = 0x2d,
2051                 .adcDesiredSize = -30,
2052                 .txEndToXpaOff = 0,
2053                 .txEndToRxOn = 0x2,
2054                 .txFrameToXpaOn = 0xe,
2055                 .thresh62 = 28,
2056                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2057                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2058                 .futureModal = {
2059                         0, 0, 0, 0, 0, 0, 0, 0,
2060                 },
2061         },
2062         .base_ext2 = {
2063                 .tempSlopeLow = 72,
2064                 .tempSlopeHigh = 105,
2065                 .xatten1DBLow = {0x10, 0x14, 0x10},
2066                 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2067                 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2068                 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2069         },
2070         .calFreqPier5G = {
2071                 FREQ2FBIN(5180, 0),
2072                 FREQ2FBIN(5220, 0),
2073                 FREQ2FBIN(5320, 0),
2074                 FREQ2FBIN(5400, 0),
2075                 FREQ2FBIN(5500, 0),
2076                 FREQ2FBIN(5600, 0),
2077                 FREQ2FBIN(5700, 0),
2078                 FREQ2FBIN(5785, 0)
2079         },
2080         .calPierData5G = {
2081                 {
2082                         {0, 0, 0, 0, 0},
2083                         {0, 0, 0, 0, 0},
2084                         {0, 0, 0, 0, 0},
2085                         {0, 0, 0, 0, 0},
2086                         {0, 0, 0, 0, 0},
2087                         {0, 0, 0, 0, 0},
2088                         {0, 0, 0, 0, 0},
2089                         {0, 0, 0, 0, 0},
2090                 },
2091                 {
2092                         {0, 0, 0, 0, 0},
2093                         {0, 0, 0, 0, 0},
2094                         {0, 0, 0, 0, 0},
2095                         {0, 0, 0, 0, 0},
2096                         {0, 0, 0, 0, 0},
2097                         {0, 0, 0, 0, 0},
2098                         {0, 0, 0, 0, 0},
2099                         {0, 0, 0, 0, 0},
2100                 },
2101                 {
2102                         {0, 0, 0, 0, 0},
2103                         {0, 0, 0, 0, 0},
2104                         {0, 0, 0, 0, 0},
2105                         {0, 0, 0, 0, 0},
2106                         {0, 0, 0, 0, 0},
2107                         {0, 0, 0, 0, 0},
2108                         {0, 0, 0, 0, 0},
2109                         {0, 0, 0, 0, 0},
2110                 },
2111
2112         },
2113         .calTarget_freqbin_5G = {
2114                 FREQ2FBIN(5180, 0),
2115                 FREQ2FBIN(5220, 0),
2116                 FREQ2FBIN(5320, 0),
2117                 FREQ2FBIN(5400, 0),
2118                 FREQ2FBIN(5500, 0),
2119                 FREQ2FBIN(5600, 0),
2120                 FREQ2FBIN(5725, 0),
2121                 FREQ2FBIN(5825, 0)
2122         },
2123         .calTarget_freqbin_5GHT20 = {
2124                 FREQ2FBIN(5180, 0),
2125                 FREQ2FBIN(5220, 0),
2126                 FREQ2FBIN(5320, 0),
2127                 FREQ2FBIN(5400, 0),
2128                 FREQ2FBIN(5500, 0),
2129                 FREQ2FBIN(5600, 0),
2130                 FREQ2FBIN(5725, 0),
2131                 FREQ2FBIN(5825, 0)
2132         },
2133         .calTarget_freqbin_5GHT40 = {
2134                 FREQ2FBIN(5180, 0),
2135                 FREQ2FBIN(5220, 0),
2136                 FREQ2FBIN(5320, 0),
2137                 FREQ2FBIN(5400, 0),
2138                 FREQ2FBIN(5500, 0),
2139                 FREQ2FBIN(5600, 0),
2140                 FREQ2FBIN(5725, 0),
2141                 FREQ2FBIN(5825, 0)
2142         },
2143         .calTargetPower5G = {
2144                 /* 6-24,36,48,54 */
2145                 { {32, 32, 28, 26} },
2146                 { {32, 32, 28, 26} },
2147                 { {32, 32, 28, 26} },
2148                 { {32, 32, 26, 24} },
2149                 { {32, 32, 26, 24} },
2150                 { {32, 32, 24, 22} },
2151                 { {30, 30, 24, 22} },
2152                 { {30, 30, 24, 22} },
2153         },
2154         .calTargetPower5GHT20 = {
2155                 /*
2156                  * 0_8_16,1-3_9-11_17-19,
2157                  * 4,5,6,7,12,13,14,15,20,21,22,23
2158                  */
2159                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2160                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2161                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2162                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2163                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2164                 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2165                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2166                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2167         },
2168         .calTargetPower5GHT40 =  {
2169                 /*
2170                  * 0_8_16,1-3_9-11_17-19,
2171                  * 4,5,6,7,12,13,14,15,20,21,22,23
2172                  */
2173                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2174                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2175                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2176                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2177                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2178                 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2179                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2180                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2181         },
2182         .ctlIndex_5G =  {
2183                 0x10, 0x16, 0x18, 0x40, 0x46,
2184                 0x48, 0x30, 0x36, 0x38
2185         },
2186         .ctl_freqbin_5G =  {
2187                 {
2188                         /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2189                         /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2190                         /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2191                         /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2192                         /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2193                         /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2194                         /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2195                         /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2196                 },
2197                 {
2198                         /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2199                         /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2200                         /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2201                         /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2202                         /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2203                         /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2204                         /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2205                         /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2206                 },
2207
2208                 {
2209                         /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2210                         /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2211                         /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2212                         /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2213                         /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2214                         /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2215                         /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2216                         /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2217                 },
2218
2219                 {
2220                         /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2221                         /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2222                         /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2223                         /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2224                         /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2225                         /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2226                         /* Data[3].ctledges[6].bchannel */ 0xFF,
2227                         /* Data[3].ctledges[7].bchannel */ 0xFF,
2228                 },
2229
2230                 {
2231                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2232                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2233                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2234                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2235                         /* Data[4].ctledges[4].bchannel */ 0xFF,
2236                         /* Data[4].ctledges[5].bchannel */ 0xFF,
2237                         /* Data[4].ctledges[6].bchannel */ 0xFF,
2238                         /* Data[4].ctledges[7].bchannel */ 0xFF,
2239                 },
2240
2241                 {
2242                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2243                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2244                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2245                         /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2246                         /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2247                         /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2248                         /* Data[5].ctledges[6].bchannel */ 0xFF,
2249                         /* Data[5].ctledges[7].bchannel */ 0xFF
2250                 },
2251
2252                 {
2253                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2254                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2255                         /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2256                         /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2257                         /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2258                         /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2259                         /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2260                         /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2261                 },
2262
2263                 {
2264                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2265                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2266                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2267                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2268                         /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2269                         /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2270                         /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2271                         /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2272                 },
2273
2274                 {
2275                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2276                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2277                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2278                         /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2279                         /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2280                         /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2281                         /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2282                         /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2283                 }
2284         },
2285         .ctlPowerData_5G = {
2286                 {
2287                         {
2288                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2289                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2290                         }
2291                 },
2292                 {
2293                         {
2294                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2295                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2296                         }
2297                 },
2298                 {
2299                         {
2300                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2301                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2302                         }
2303                 },
2304                 {
2305                         {
2306                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2307                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2308                         }
2309                 },
2310                 {
2311                         {
2312                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2313                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2314                         }
2315                 },
2316                 {
2317                         {
2318                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2319                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2320                         }
2321                 },
2322                 {
2323                         {
2324                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2325                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2326                         }
2327                 },
2328                 {
2329                         {
2330                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2331                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2332                         }
2333                 },
2334                 {
2335                         {
2336                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2337                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2338                         }
2339                 },
2340         }
2341 };
2342
2343 static const struct ar9300_eeprom ar9300_h116 = {
2344         .eepromVersion = 2,
2345         .templateVersion = 4,
2346         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2347         .custData = {"h116-041-f0000"},
2348         .baseEepHeader = {
2349                 .regDmn = { LE16(0), LE16(0x1f) },
2350                 .txrxMask =  0x33, /* 4 bits tx and 4 bits rx */
2351                 .opCapFlags = {
2352                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2353                         .eepMisc = 0,
2354                 },
2355                 .rfSilent = 0,
2356                 .blueToothOptions = 0,
2357                 .deviceCap = 0,
2358                 .deviceType = 5, /* takes lower byte in eeprom location */
2359                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2360                 .params_for_tuning_caps = {0, 0},
2361                 .featureEnable = 0x0d,
2362                  /*
2363                   * bit0 - enable tx temp comp - disabled
2364                   * bit1 - enable tx volt comp - disabled
2365                   * bit2 - enable fastClock - enabled
2366                   * bit3 - enable doubling - enabled
2367                   * bit4 - enable internal regulator - disabled
2368                   * bit5 - enable pa predistortion - disabled
2369                   */
2370                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2371                 .eepromWriteEnableGpio = 6,
2372                 .wlanDisableGpio = 0,
2373                 .wlanLedGpio = 8,
2374                 .rxBandSelectGpio = 0xff,
2375                 .txrxgain = 0x10,
2376                 .swreg = 0,
2377          },
2378         .modalHeader2G = {
2379         /* ar9300_modal_eep_header  2g */
2380                 /* 4 idle,t1,t2,b(4 bits per setting) */
2381                 .antCtrlCommon = LE32(0x110),
2382                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2383                 .antCtrlCommon2 = LE32(0x44444),
2384
2385                 /*
2386                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2387                  * rx1, rx12, b (2 bits each)
2388                  */
2389                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2390
2391                 /*
2392                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
2393                  * for ar9280 (0xa20c/b20c 5:0)
2394                  */
2395                 .xatten1DB = {0x1f, 0x1f, 0x1f},
2396
2397                 /*
2398                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2399                  * for ar9280 (0xa20c/b20c 16:12
2400                  */
2401                 .xatten1Margin = {0x12, 0x12, 0x12},
2402                 .tempSlope = 25,
2403                 .voltSlope = 0,
2404
2405                 /*
2406                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2407                  * channels in usual fbin coding format
2408                  */
2409                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2410
2411                 /*
2412                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2413                  * if the register is per chain
2414                  */
2415                 .noiseFloorThreshCh = {-1, 0, 0},
2416                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2417                 .quick_drop = 0,
2418                 .xpaBiasLvl = 0,
2419                 .txFrameToDataStart = 0x0e,
2420                 .txFrameToPaOn = 0x0e,
2421                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2422                 .antennaGain = 0,
2423                 .switchSettling = 0x2c,
2424                 .adcDesiredSize = -30,
2425                 .txEndToXpaOff = 0,
2426                 .txEndToRxOn = 0x2,
2427                 .txFrameToXpaOn = 0xe,
2428                 .thresh62 = 28,
2429                 .papdRateMaskHt20 = LE32(0x0c80C080),
2430                 .papdRateMaskHt40 = LE32(0x0080C080),
2431                 .futureModal = {
2432                         0, 0, 0, 0, 0, 0, 0, 0,
2433                 },
2434          },
2435          .base_ext1 = {
2436                 .ant_div_control = 0,
2437                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2438          },
2439         .calFreqPier2G = {
2440                 FREQ2FBIN(2412, 1),
2441                 FREQ2FBIN(2437, 1),
2442                 FREQ2FBIN(2462, 1),
2443          },
2444         /* ar9300_cal_data_per_freq_op_loop 2g */
2445         .calPierData2G = {
2446                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2447                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2448                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2449          },
2450         .calTarget_freqbin_Cck = {
2451                 FREQ2FBIN(2412, 1),
2452                 FREQ2FBIN(2472, 1),
2453          },
2454         .calTarget_freqbin_2G = {
2455                 FREQ2FBIN(2412, 1),
2456                 FREQ2FBIN(2437, 1),
2457                 FREQ2FBIN(2472, 1)
2458          },
2459         .calTarget_freqbin_2GHT20 = {
2460                 FREQ2FBIN(2412, 1),
2461                 FREQ2FBIN(2437, 1),
2462                 FREQ2FBIN(2472, 1)
2463          },
2464         .calTarget_freqbin_2GHT40 = {
2465                 FREQ2FBIN(2412, 1),
2466                 FREQ2FBIN(2437, 1),
2467                 FREQ2FBIN(2472, 1)
2468          },
2469         .calTargetPowerCck = {
2470                  /* 1L-5L,5S,11L,11S */
2471                  { {34, 34, 34, 34} },
2472                  { {34, 34, 34, 34} },
2473         },
2474         .calTargetPower2G = {
2475                  /* 6-24,36,48,54 */
2476                  { {34, 34, 32, 32} },
2477                  { {34, 34, 32, 32} },
2478                  { {34, 34, 32, 32} },
2479         },
2480         .calTargetPower2GHT20 = {
2481                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2482                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2483                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2484         },
2485         .calTargetPower2GHT40 = {
2486                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2487                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2488                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2489         },
2490         .ctlIndex_2G =  {
2491                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2492                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2493         },
2494         .ctl_freqbin_2G = {
2495                 {
2496                         FREQ2FBIN(2412, 1),
2497                         FREQ2FBIN(2417, 1),
2498                         FREQ2FBIN(2457, 1),
2499                         FREQ2FBIN(2462, 1)
2500                 },
2501                 {
2502                         FREQ2FBIN(2412, 1),
2503                         FREQ2FBIN(2417, 1),
2504                         FREQ2FBIN(2462, 1),
2505                         0xFF,
2506                 },
2507
2508                 {
2509                         FREQ2FBIN(2412, 1),
2510                         FREQ2FBIN(2417, 1),
2511                         FREQ2FBIN(2462, 1),
2512                         0xFF,
2513                 },
2514                 {
2515                         FREQ2FBIN(2422, 1),
2516                         FREQ2FBIN(2427, 1),
2517                         FREQ2FBIN(2447, 1),
2518                         FREQ2FBIN(2452, 1)
2519                 },
2520
2521                 {
2522                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2523                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2524                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2525                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2526                 },
2527
2528                 {
2529                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2530                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2531                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2532                         0,
2533                 },
2534
2535                 {
2536                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2537                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2538                         FREQ2FBIN(2472, 1),
2539                         0,
2540                 },
2541
2542                 {
2543                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2544                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2545                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2546                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2547                 },
2548
2549                 {
2550                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2551                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2552                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2553                 },
2554
2555                 {
2556                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2557                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2558                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2559                         0
2560                 },
2561
2562                 {
2563                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2564                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2565                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2566                         0
2567                 },
2568
2569                 {
2570                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2571                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2572                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2573                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2574                 }
2575          },
2576         .ctlPowerData_2G = {
2577                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2578                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2579                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2580
2581                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2582                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2583                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2584
2585                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2586                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2587                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2588
2589                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2590                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2591                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2592          },
2593         .modalHeader5G = {
2594                 /* 4 idle,t1,t2,b (4 bits per setting) */
2595                 .antCtrlCommon = LE32(0x220),
2596                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2597                 .antCtrlCommon2 = LE32(0x44444),
2598                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2599                 .antCtrlChain = {
2600                         LE16(0x150), LE16(0x150), LE16(0x150),
2601                 },
2602                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2603                 .xatten1DB = {0x19, 0x19, 0x19},
2604
2605                 /*
2606                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2607                  * for merlin (0xa20c/b20c 16:12
2608                  */
2609                 .xatten1Margin = {0x14, 0x14, 0x14},
2610                 .tempSlope = 70,
2611                 .voltSlope = 0,
2612                 /* spurChans spur channels in usual fbin coding format */
2613                 .spurChans = {0, 0, 0, 0, 0},
2614                 /* noiseFloorThreshCh Check if the register is per chain */
2615                 .noiseFloorThreshCh = {-1, 0, 0},
2616                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2617                 .quick_drop = 0,
2618                 .xpaBiasLvl = 0,
2619                 .txFrameToDataStart = 0x0e,
2620                 .txFrameToPaOn = 0x0e,
2621                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2622                 .antennaGain = 0,
2623                 .switchSettling = 0x2d,
2624                 .adcDesiredSize = -30,
2625                 .txEndToXpaOff = 0,
2626                 .txEndToRxOn = 0x2,
2627                 .txFrameToXpaOn = 0xe,
2628                 .thresh62 = 28,
2629                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2630                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2631                 .futureModal = {
2632                         0, 0, 0, 0, 0, 0, 0, 0,
2633                 },
2634          },
2635         .base_ext2 = {
2636                 .tempSlopeLow = 35,
2637                 .tempSlopeHigh = 50,
2638                 .xatten1DBLow = {0, 0, 0},
2639                 .xatten1MarginLow = {0, 0, 0},
2640                 .xatten1DBHigh = {0, 0, 0},
2641                 .xatten1MarginHigh = {0, 0, 0}
2642          },
2643         .calFreqPier5G = {
2644                 FREQ2FBIN(5160, 0),
2645                 FREQ2FBIN(5220, 0),
2646                 FREQ2FBIN(5320, 0),
2647                 FREQ2FBIN(5400, 0),
2648                 FREQ2FBIN(5500, 0),
2649                 FREQ2FBIN(5600, 0),
2650                 FREQ2FBIN(5700, 0),
2651                 FREQ2FBIN(5785, 0)
2652         },
2653         .calPierData5G = {
2654                         {
2655                                 {0, 0, 0, 0, 0},
2656                                 {0, 0, 0, 0, 0},
2657                                 {0, 0, 0, 0, 0},
2658                                 {0, 0, 0, 0, 0},
2659                                 {0, 0, 0, 0, 0},
2660                                 {0, 0, 0, 0, 0},
2661                                 {0, 0, 0, 0, 0},
2662                                 {0, 0, 0, 0, 0},
2663                         },
2664                         {
2665                                 {0, 0, 0, 0, 0},
2666                                 {0, 0, 0, 0, 0},
2667                                 {0, 0, 0, 0, 0},
2668                                 {0, 0, 0, 0, 0},
2669                                 {0, 0, 0, 0, 0},
2670                                 {0, 0, 0, 0, 0},
2671                                 {0, 0, 0, 0, 0},
2672                                 {0, 0, 0, 0, 0},
2673                         },
2674                         {
2675                                 {0, 0, 0, 0, 0},
2676                                 {0, 0, 0, 0, 0},
2677                                 {0, 0, 0, 0, 0},
2678                                 {0, 0, 0, 0, 0},
2679                                 {0, 0, 0, 0, 0},
2680                                 {0, 0, 0, 0, 0},
2681                                 {0, 0, 0, 0, 0},
2682                                 {0, 0, 0, 0, 0},
2683                         },
2684
2685         },
2686         .calTarget_freqbin_5G = {
2687                 FREQ2FBIN(5180, 0),
2688                 FREQ2FBIN(5240, 0),
2689                 FREQ2FBIN(5320, 0),
2690                 FREQ2FBIN(5400, 0),
2691                 FREQ2FBIN(5500, 0),
2692                 FREQ2FBIN(5600, 0),
2693                 FREQ2FBIN(5700, 0),
2694                 FREQ2FBIN(5825, 0)
2695         },
2696         .calTarget_freqbin_5GHT20 = {
2697                 FREQ2FBIN(5180, 0),
2698                 FREQ2FBIN(5240, 0),
2699                 FREQ2FBIN(5320, 0),
2700                 FREQ2FBIN(5400, 0),
2701                 FREQ2FBIN(5500, 0),
2702                 FREQ2FBIN(5700, 0),
2703                 FREQ2FBIN(5745, 0),
2704                 FREQ2FBIN(5825, 0)
2705         },
2706         .calTarget_freqbin_5GHT40 = {
2707                 FREQ2FBIN(5180, 0),
2708                 FREQ2FBIN(5240, 0),
2709                 FREQ2FBIN(5320, 0),
2710                 FREQ2FBIN(5400, 0),
2711                 FREQ2FBIN(5500, 0),
2712                 FREQ2FBIN(5700, 0),
2713                 FREQ2FBIN(5745, 0),
2714                 FREQ2FBIN(5825, 0)
2715          },
2716         .calTargetPower5G = {
2717                 /* 6-24,36,48,54 */
2718                 { {30, 30, 28, 24} },
2719                 { {30, 30, 28, 24} },
2720                 { {30, 30, 28, 24} },
2721                 { {30, 30, 28, 24} },
2722                 { {30, 30, 28, 24} },
2723                 { {30, 30, 28, 24} },
2724                 { {30, 30, 28, 24} },
2725                 { {30, 30, 28, 24} },
2726          },
2727         .calTargetPower5GHT20 = {
2728                 /*
2729                  * 0_8_16,1-3_9-11_17-19,
2730                  * 4,5,6,7,12,13,14,15,20,21,22,23
2731                  */
2732                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2733                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2734                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2735                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2736                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2737                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2738                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2739                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2740          },
2741         .calTargetPower5GHT40 =  {
2742                 /*
2743                  * 0_8_16,1-3_9-11_17-19,
2744                  * 4,5,6,7,12,13,14,15,20,21,22,23
2745                  */
2746                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2747                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2748                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2749                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2750                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2751                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2752                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2753                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2754          },
2755         .ctlIndex_5G =  {
2756                 0x10, 0x16, 0x18, 0x40, 0x46,
2757                 0x48, 0x30, 0x36, 0x38
2758         },
2759         .ctl_freqbin_5G =  {
2760                 {
2761                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2762                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2763                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2764                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2765                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2766                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2767                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2768                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2769                 },
2770                 {
2771                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2772                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2773                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2774                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2775                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2776                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2777                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2778                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2779                 },
2780
2781                 {
2782                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2783                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2784                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2785                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2786                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2787                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2788                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2789                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2790                 },
2791
2792                 {
2793                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2794                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2795                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2796                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2797                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2798                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2799                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2800                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2801                 },
2802
2803                 {
2804                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2805                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2806                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2807                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2808                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2809                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2810                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2811                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2812                 },
2813
2814                 {
2815                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2816                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2817                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2818                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2819                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2820                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2821                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2822                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
2823                 },
2824
2825                 {
2826                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2827                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2828                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2829                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2830                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2831                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2832                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2833                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2834                 },
2835
2836                 {
2837                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2838                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2839                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2840                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2841                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2842                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2843                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2844                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2845                 },
2846
2847                 {
2848                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2849                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2850                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2851                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2852                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2853                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2854                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2855                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2856                 }
2857          },
2858         .ctlPowerData_5G = {
2859                 {
2860                         {
2861                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2862                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2863                         }
2864                 },
2865                 {
2866                         {
2867                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2868                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2869                         }
2870                 },
2871                 {
2872                         {
2873                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2874                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2875                         }
2876                 },
2877                 {
2878                         {
2879                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2880                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2881                         }
2882                 },
2883                 {
2884                         {
2885                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2886                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2887                         }
2888                 },
2889                 {
2890                         {
2891                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2892                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2893                         }
2894                 },
2895                 {
2896                         {
2897                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2898                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2899                         }
2900                 },
2901                 {
2902                         {
2903                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2904                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2905                         }
2906                 },
2907                 {
2908                         {
2909                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2910                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2911                         }
2912                 },
2913          }
2914 };
2915
2916
2917 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2918         &ar9300_default,
2919         &ar9300_x112,
2920         &ar9300_h116,
2921         &ar9300_h112,
2922         &ar9300_x113,
2923 };
2924
2925 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2926 {
2927 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2928         int it;
2929
2930         for (it = 0; it < N_LOOP; it++)
2931                 if (ar9300_eep_templates[it]->templateVersion == id)
2932                         return ar9300_eep_templates[it];
2933         return NULL;
2934 #undef N_LOOP
2935 }
2936
2937
2938 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2939 {
2940         if (fbin == AR5416_BCHAN_UNUSED)
2941                 return fbin;
2942
2943         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2944 }
2945
2946 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2947 {
2948         return 0;
2949 }
2950
2951 static int interpolate(int x, int xa, int xb, int ya, int yb)
2952 {
2953         int bf, factor, plus;
2954
2955         bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2956         factor = bf / 2;
2957         plus = bf % 2;
2958         return ya + factor + plus;
2959 }
2960
2961 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2962                                       enum eeprom_param param)
2963 {
2964         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2965         struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2966
2967         switch (param) {
2968         case EEP_MAC_LSW:
2969                 return get_unaligned_be16(eep->macAddr);
2970         case EEP_MAC_MID:
2971                 return get_unaligned_be16(eep->macAddr + 2);
2972         case EEP_MAC_MSW:
2973                 return get_unaligned_be16(eep->macAddr + 4);
2974         case EEP_REG_0:
2975                 return le16_to_cpu(pBase->regDmn[0]);
2976         case EEP_OP_CAP:
2977                 return pBase->deviceCap;
2978         case EEP_OP_MODE:
2979                 return pBase->opCapFlags.opFlags;
2980         case EEP_RF_SILENT:
2981                 return pBase->rfSilent;
2982         case EEP_TX_MASK:
2983                 return (pBase->txrxMask >> 4) & 0xf;
2984         case EEP_RX_MASK:
2985                 return pBase->txrxMask & 0xf;
2986         case EEP_DRIVE_STRENGTH:
2987 #define AR9300_EEP_BASE_DRIV_STRENGTH   0x1
2988                 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
2989         case EEP_INTERNAL_REGULATOR:
2990                 /* Bit 4 is internal regulator flag */
2991                 return (pBase->featureEnable & 0x10) >> 4;
2992         case EEP_SWREG:
2993                 return le32_to_cpu(pBase->swreg);
2994         case EEP_PAPRD:
2995                 return !!(pBase->featureEnable & BIT(5));
2996         case EEP_CHAIN_MASK_REDUCE:
2997                 return (pBase->miscConfiguration >> 0x3) & 0x1;
2998         case EEP_ANT_DIV_CTL1:
2999                 return eep->base_ext1.ant_div_control;
3000         case EEP_ANTENNA_GAIN_5G:
3001                 return eep->modalHeader5G.antennaGain;
3002         case EEP_ANTENNA_GAIN_2G:
3003                 return eep->modalHeader2G.antennaGain;
3004         case EEP_QUICK_DROP:
3005                 return pBase->miscConfiguration & BIT(1);
3006         default:
3007                 return 0;
3008         }
3009 }
3010
3011 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3012                                     u8 *buffer)
3013 {
3014         u16 val;
3015
3016         if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3017                 return false;
3018
3019         *buffer = (val >> (8 * (address % 2))) & 0xff;
3020         return true;
3021 }
3022
3023 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3024                                     u8 *buffer)
3025 {
3026         u16 val;
3027
3028         if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3029                 return false;
3030
3031         buffer[0] = val >> 8;
3032         buffer[1] = val & 0xff;
3033
3034         return true;
3035 }
3036
3037 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3038                                int count)
3039 {
3040         struct ath_common *common = ath9k_hw_common(ah);
3041         int i;
3042
3043         if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3044                 ath_dbg(common, EEPROM, "eeprom address not in range\n");
3045                 return false;
3046         }
3047
3048         /*
3049          * Since we're reading the bytes in reverse order from a little-endian
3050          * word stream, an even address means we only use the lower half of
3051          * the 16-bit word at that address
3052          */
3053         if (address % 2 == 0) {
3054                 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3055                         goto error;
3056
3057                 count--;
3058         }
3059
3060         for (i = 0; i < count / 2; i++) {
3061                 if (!ar9300_eeprom_read_word(common, address, buffer))
3062                         goto error;
3063
3064                 address -= 2;
3065                 buffer += 2;
3066         }
3067
3068         if (count % 2)
3069                 if (!ar9300_eeprom_read_byte(common, address, buffer))
3070                         goto error;
3071
3072         return true;
3073
3074 error:
3075         ath_dbg(common, EEPROM, "unable to read eeprom region at offset %d\n",
3076                 address);
3077         return false;
3078 }
3079
3080 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3081 {
3082         REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3083
3084         if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3085                            AR9300_OTP_STATUS_VALID, 1000))
3086                 return false;
3087
3088         *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3089         return true;
3090 }
3091
3092 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3093                             int count)
3094 {
3095         u32 data;
3096         int i;
3097
3098         for (i = 0; i < count; i++) {
3099                 int offset = 8 * ((address - i) % 4);
3100                 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3101                         return false;
3102
3103                 buffer[i] = (data >> offset) & 0xff;
3104         }
3105
3106         return true;
3107 }
3108
3109
3110 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3111                                    int *length, int *major, int *minor)
3112 {
3113         unsigned long value[4];
3114
3115         value[0] = best[0];
3116         value[1] = best[1];
3117         value[2] = best[2];
3118         value[3] = best[3];
3119         *code = ((value[0] >> 5) & 0x0007);
3120         *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3121         *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3122         *major = (value[2] & 0x000f);
3123         *minor = (value[3] & 0x00ff);
3124 }
3125
3126 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3127 {
3128         int it, checksum = 0;
3129
3130         for (it = 0; it < dsize; it++) {
3131                 checksum += data[it];
3132                 checksum &= 0xffff;
3133         }
3134
3135         return checksum;
3136 }
3137
3138 static bool ar9300_uncompress_block(struct ath_hw *ah,
3139                                     u8 *mptr,
3140                                     int mdataSize,
3141                                     u8 *block,
3142                                     int size)
3143 {
3144         int it;
3145         int spot;
3146         int offset;
3147         int length;
3148         struct ath_common *common = ath9k_hw_common(ah);
3149
3150         spot = 0;
3151
3152         for (it = 0; it < size; it += (length+2)) {
3153                 offset = block[it];
3154                 offset &= 0xff;
3155                 spot += offset;
3156                 length = block[it+1];
3157                 length &= 0xff;
3158
3159                 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3160                         ath_dbg(common, EEPROM,
3161                                 "Restore at %d: spot=%d offset=%d length=%d\n",
3162                                 it, spot, offset, length);
3163                         memcpy(&mptr[spot], &block[it+2], length);
3164                         spot += length;
3165                 } else if (length > 0) {
3166                         ath_dbg(common, EEPROM,
3167                                 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3168                                 it, spot, offset, length);
3169                         return false;
3170                 }
3171         }
3172         return true;
3173 }
3174
3175 static int ar9300_compress_decision(struct ath_hw *ah,
3176                                     int it,
3177                                     int code,
3178                                     int reference,
3179                                     u8 *mptr,
3180                                     u8 *word, int length, int mdata_size)
3181 {
3182         struct ath_common *common = ath9k_hw_common(ah);
3183         const struct ar9300_eeprom *eep = NULL;
3184
3185         switch (code) {
3186         case _CompressNone:
3187                 if (length != mdata_size) {
3188                         ath_dbg(common, EEPROM,
3189                                 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3190                                 mdata_size, length);
3191                         return -1;
3192                 }
3193                 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3194                 ath_dbg(common, EEPROM,
3195                         "restored eeprom %d: uncompressed, length %d\n",
3196                         it, length);
3197                 break;
3198         case _CompressBlock:
3199                 if (reference == 0) {
3200                 } else {
3201                         eep = ar9003_eeprom_struct_find_by_id(reference);
3202                         if (eep == NULL) {
3203                                 ath_dbg(common, EEPROM,
3204                                         "can't find reference eeprom struct %d\n",
3205                                         reference);
3206                                 return -1;
3207                         }
3208                         memcpy(mptr, eep, mdata_size);
3209                 }
3210                 ath_dbg(common, EEPROM,
3211                         "restore eeprom %d: block, reference %d, length %d\n",
3212                         it, reference, length);
3213                 ar9300_uncompress_block(ah, mptr, mdata_size,
3214                                         (u8 *) (word + COMP_HDR_LEN), length);
3215                 break;
3216         default:
3217                 ath_dbg(common, EEPROM, "unknown compression code %d\n", code);
3218                 return -1;
3219         }
3220         return 0;
3221 }
3222
3223 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3224                                int count);
3225
3226 static bool ar9300_check_header(void *data)
3227 {
3228         u32 *word = data;
3229         return !(*word == 0 || *word == ~0);
3230 }
3231
3232 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3233                                        int base_addr)
3234 {
3235         u8 header[4];
3236
3237         if (!read(ah, base_addr, header, 4))
3238                 return false;
3239
3240         return ar9300_check_header(header);
3241 }
3242
3243 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3244                                        int mdata_size)
3245 {
3246         struct ath_common *common = ath9k_hw_common(ah);
3247         u16 *data = (u16 *) mptr;
3248         int i;
3249
3250         for (i = 0; i < mdata_size / 2; i++, data++)
3251                 ath9k_hw_nvram_read(common, i, data);
3252
3253         return 0;
3254 }
3255 /*
3256  * Read the configuration data from the eeprom.
3257  * The data can be put in any specified memory buffer.
3258  *
3259  * Returns -1 on error.
3260  * Returns address of next memory location on success.
3261  */
3262 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3263                                           u8 *mptr, int mdata_size)
3264 {
3265 #define MDEFAULT 15
3266 #define MSTATE 100
3267         int cptr;
3268         u8 *word;
3269         int code;
3270         int reference, length, major, minor;
3271         int osize;
3272         int it;
3273         u16 checksum, mchecksum;
3274         struct ath_common *common = ath9k_hw_common(ah);
3275         eeprom_read_op read;
3276
3277         if (ath9k_hw_use_flash(ah))
3278                 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3279
3280         word = kzalloc(2048, GFP_KERNEL);
3281         if (!word)
3282                 return -ENOMEM;
3283
3284         memcpy(mptr, &ar9300_default, mdata_size);
3285
3286         read = ar9300_read_eeprom;
3287         if (AR_SREV_9485(ah))
3288                 cptr = AR9300_BASE_ADDR_4K;
3289         else if (AR_SREV_9330(ah))
3290                 cptr = AR9300_BASE_ADDR_512;
3291         else
3292                 cptr = AR9300_BASE_ADDR;
3293         ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3294                 cptr);
3295         if (ar9300_check_eeprom_header(ah, read, cptr))
3296                 goto found;
3297
3298         cptr = AR9300_BASE_ADDR_512;
3299         ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3300                 cptr);
3301         if (ar9300_check_eeprom_header(ah, read, cptr))
3302                 goto found;
3303
3304         read = ar9300_read_otp;
3305         cptr = AR9300_BASE_ADDR;
3306         ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3307         if (ar9300_check_eeprom_header(ah, read, cptr))
3308                 goto found;
3309
3310         cptr = AR9300_BASE_ADDR_512;
3311         ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3312         if (ar9300_check_eeprom_header(ah, read, cptr))
3313                 goto found;
3314
3315         goto fail;
3316
3317 found:
3318         ath_dbg(common, EEPROM, "Found valid EEPROM data\n");
3319
3320         for (it = 0; it < MSTATE; it++) {
3321                 if (!read(ah, cptr, word, COMP_HDR_LEN))
3322                         goto fail;
3323
3324                 if (!ar9300_check_header(word))
3325                         break;
3326
3327                 ar9300_comp_hdr_unpack(word, &code, &reference,
3328                                        &length, &major, &minor);
3329                 ath_dbg(common, EEPROM,
3330                         "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3331                         cptr, code, reference, length, major, minor);
3332                 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3333                     (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
3334                         ath_dbg(common, EEPROM, "Skipping bad header\n");
3335                         cptr -= COMP_HDR_LEN;
3336                         continue;
3337                 }
3338
3339                 osize = length;
3340                 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3341                 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3342                 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
3343                 ath_dbg(common, EEPROM, "checksum %x %x\n",
3344                         checksum, mchecksum);
3345                 if (checksum == mchecksum) {
3346                         ar9300_compress_decision(ah, it, code, reference, mptr,
3347                                                  word, length, mdata_size);
3348                 } else {
3349                         ath_dbg(common, EEPROM,
3350                                 "skipping block with bad checksum\n");
3351                 }
3352                 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3353         }
3354
3355         kfree(word);
3356         return cptr;
3357
3358 fail:
3359         kfree(word);
3360         return -1;
3361 }
3362
3363 /*
3364  * Restore the configuration structure by reading the eeprom.
3365  * This function destroys any existing in-memory structure
3366  * content.
3367  */
3368 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3369 {
3370         u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3371
3372         if (ar9300_eeprom_restore_internal(ah, mptr,
3373                         sizeof(struct ar9300_eeprom)) < 0)
3374                 return false;
3375
3376         return true;
3377 }
3378
3379 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3380 static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3381                                     struct ar9300_modal_eep_header *modal_hdr)
3382 {
3383         PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3384         PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3385         PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3386         PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3387         PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3388         PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3389         PR_EEP("Switch Settle", modal_hdr->switchSettling);
3390         PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3391         PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3392         PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3393         PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3394         PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3395         PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3396         PR_EEP("Temp Slope", modal_hdr->tempSlope);
3397         PR_EEP("Volt Slope", modal_hdr->voltSlope);
3398         PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3399         PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3400         PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3401         PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3402         PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3403         PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3404         PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3405         PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
3406         PR_EEP("Quick Drop", modal_hdr->quick_drop);
3407         PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
3408         PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3409         PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3410         PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3411         PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3412         PR_EEP("txClip", modal_hdr->txClip);
3413         PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
3414
3415         return len;
3416 }
3417
3418 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3419                                        u8 *buf, u32 len, u32 size)
3420 {
3421         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3422         struct ar9300_base_eep_hdr *pBase;
3423
3424         if (!dump_base_hdr) {
3425                 len += snprintf(buf + len, size - len,
3426                                 "%20s :\n", "2GHz modal Header");
3427                 len += ar9003_dump_modal_eeprom(buf, len, size,
3428                                                 &eep->modalHeader2G);
3429                 len += snprintf(buf + len, size - len,
3430                                 "%20s :\n", "5GHz modal Header");
3431                 len += ar9003_dump_modal_eeprom(buf, len, size,
3432                                                 &eep->modalHeader5G);
3433                 goto out;
3434         }
3435
3436         pBase = &eep->baseEepHeader;
3437
3438         PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3439         PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3440         PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3441         PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3442         PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3443         PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3444                                 AR5416_OPFLAGS_11A));
3445         PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3446                                 AR5416_OPFLAGS_11G));
3447         PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3448                                         AR5416_OPFLAGS_N_2G_HT20));
3449         PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3450                                         AR5416_OPFLAGS_N_2G_HT40));
3451         PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3452                                         AR5416_OPFLAGS_N_5G_HT20));
3453         PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3454                                         AR5416_OPFLAGS_N_5G_HT40));
3455         PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
3456         PR_EEP("RF Silent", pBase->rfSilent);
3457         PR_EEP("BT option", pBase->blueToothOptions);
3458         PR_EEP("Device Cap", pBase->deviceCap);
3459         PR_EEP("Device Type", pBase->deviceType);
3460         PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3461         PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3462         PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3463         PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3464         PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3465         PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3466         PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3467         PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3468         PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3469         PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
3470         PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1)));
3471         PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3472         PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3473         PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3474         PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3475         PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3476         PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3477         PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3478         PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3479
3480         len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3481                         ah->eeprom.ar9300_eep.macAddr);
3482 out:
3483         if (len > size)
3484                 len = size;
3485
3486         return len;
3487 }
3488 #else
3489 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3490                                        u8 *buf, u32 len, u32 size)
3491 {
3492         return 0;
3493 }
3494 #endif
3495
3496 /* XXX: review hardware docs */
3497 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3498 {
3499         return ah->eeprom.ar9300_eep.eepromVersion;
3500 }
3501
3502 /* XXX: could be read from the eepromVersion, not sure yet */
3503 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3504 {
3505         return 0;
3506 }
3507
3508 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3509 {
3510         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3511
3512         if (is2ghz)
3513                 return eep->modalHeader2G.xpaBiasLvl;
3514         else
3515                 return eep->modalHeader5G.xpaBiasLvl;
3516 }
3517
3518 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3519 {
3520         int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3521
3522         if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3523                 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3524         else if (AR_SREV_9462(ah))
3525                 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3526         else {
3527                 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3528                 REG_RMW_FIELD(ah, AR_CH0_THERM,
3529                                 AR_CH0_THERM_XPABIASLVL_MSB,
3530                                 bias >> 2);
3531                 REG_RMW_FIELD(ah, AR_CH0_THERM,
3532                                 AR_CH0_THERM_XPASHORT2GND, 1);
3533         }
3534 }
3535
3536 static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz)
3537 {
3538         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3539         __le16 val;
3540
3541         if (is_2ghz)
3542                 val = eep->modalHeader2G.switchcomspdt;
3543         else
3544                 val = eep->modalHeader5G.switchcomspdt;
3545         return le16_to_cpu(val);
3546 }
3547
3548
3549 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3550 {
3551         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3552         __le32 val;
3553
3554         if (is2ghz)
3555                 val = eep->modalHeader2G.antCtrlCommon;
3556         else
3557                 val = eep->modalHeader5G.antCtrlCommon;
3558         return le32_to_cpu(val);
3559 }
3560
3561 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3562 {
3563         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3564         __le32 val;
3565
3566         if (is2ghz)
3567                 val = eep->modalHeader2G.antCtrlCommon2;
3568         else
3569                 val = eep->modalHeader5G.antCtrlCommon2;
3570         return le32_to_cpu(val);
3571 }
3572
3573 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3574                                         int chain,
3575                                         bool is2ghz)
3576 {
3577         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3578         __le16 val = 0;
3579
3580         if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3581                 if (is2ghz)
3582                         val = eep->modalHeader2G.antCtrlChain[chain];
3583                 else
3584                         val = eep->modalHeader5G.antCtrlChain[chain];
3585         }
3586
3587         return le16_to_cpu(val);
3588 }
3589
3590 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3591 {
3592         int chain;
3593         u32 regval;
3594         u32 ant_div_ctl1;
3595         static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3596                         AR_PHY_SWITCH_CHAIN_0,
3597                         AR_PHY_SWITCH_CHAIN_1,
3598                         AR_PHY_SWITCH_CHAIN_2,
3599         };
3600
3601         u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3602
3603         if (AR_SREV_9462(ah)) {
3604                 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3605                                 AR_SWITCH_TABLE_COM_AR9462_ALL, value);
3606         } else
3607                 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3608                               AR_SWITCH_TABLE_COM_ALL, value);
3609
3610
3611         /*
3612          *   AR9462 defines new switch table for BT/WLAN,
3613          *       here's new field name in XXX.ref for both 2G and 5G.
3614          *   Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3615          *   15:12   R/W     SWITCH_TABLE_COM_SPDT_WLAN_RX
3616          * SWITCH_TABLE_COM_SPDT_WLAN_RX
3617          *
3618          *   11:8     R/W     SWITCH_TABLE_COM_SPDT_WLAN_TX
3619          * SWITCH_TABLE_COM_SPDT_WLAN_TX
3620          *
3621          *   7:4 R/W  SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3622          * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3623          */
3624         if (AR_SREV_9462_20_OR_LATER(ah)) {
3625                 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3626                 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3627                                 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
3628         }
3629
3630         value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3631         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3632
3633         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3634                 if ((ah->rxchainmask & BIT(chain)) ||
3635                     (ah->txchainmask & BIT(chain))) {
3636                         value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3637                                                              is2ghz);
3638                         REG_RMW_FIELD(ah, switch_chain_reg[chain],
3639                                       AR_SWITCH_TABLE_ALL, value);
3640                 }
3641         }
3642
3643         if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3644                 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3645                 /*
3646                  * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3647                  * are the fields present
3648                  */
3649                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3650                 regval &= (~AR_ANT_DIV_CTRL_ALL);
3651                 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3652                 /* enable_lnadiv */
3653                 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3654                 regval |= ((value >> 6) & 0x1) <<
3655                                 AR_PHY_9485_ANT_DIV_LNADIV_S;
3656                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3657
3658                 /*enable fast_div */
3659                 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3660                 regval &= (~AR_FAST_DIV_ENABLE);
3661                 regval |= ((value >> 7) & 0x1) <<
3662                                 AR_FAST_DIV_ENABLE_S;
3663                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3664                 ant_div_ctl1 =
3665                         ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3666                 /* check whether antenna diversity is enabled */
3667                 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3668                         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3669                         /*
3670                          * clear bits 25-30 main_lnaconf, alt_lnaconf,
3671                          * main_tb, alt_tb
3672                          */
3673                         regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3674                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF |
3675                                         AR_PHY_9485_ANT_DIV_ALT_GAINTB |
3676                                         AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
3677                         /* by default use LNA1 for the main antenna */
3678                         regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3679                                         AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
3680                         regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3681                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
3682                         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3683                 }
3684
3685
3686         }
3687
3688 }
3689
3690 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3691 {
3692         int drive_strength;
3693         unsigned long reg;
3694
3695         drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3696
3697         if (!drive_strength)
3698                 return;
3699
3700         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3701         reg &= ~0x00ffffc0;
3702         reg |= 0x5 << 21;
3703         reg |= 0x5 << 18;
3704         reg |= 0x5 << 15;
3705         reg |= 0x5 << 12;
3706         reg |= 0x5 << 9;
3707         reg |= 0x5 << 6;
3708         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3709
3710         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3711         reg &= ~0xffffffe0;
3712         reg |= 0x5 << 29;
3713         reg |= 0x5 << 26;
3714         reg |= 0x5 << 23;
3715         reg |= 0x5 << 20;
3716         reg |= 0x5 << 17;
3717         reg |= 0x5 << 14;
3718         reg |= 0x5 << 11;
3719         reg |= 0x5 << 8;
3720         reg |= 0x5 << 5;
3721         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3722
3723         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3724         reg &= ~0xff800000;
3725         reg |= 0x5 << 29;
3726         reg |= 0x5 << 26;
3727         reg |= 0x5 << 23;
3728         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3729 }
3730
3731 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3732                                      struct ath9k_channel *chan)
3733 {
3734         int f[3], t[3];
3735         u16 value;
3736         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3737
3738         if (chain >= 0 && chain < 3) {
3739                 if (IS_CHAN_2GHZ(chan))
3740                         return eep->modalHeader2G.xatten1DB[chain];
3741                 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3742                         t[0] = eep->base_ext2.xatten1DBLow[chain];
3743                         f[0] = 5180;
3744                         t[1] = eep->modalHeader5G.xatten1DB[chain];
3745                         f[1] = 5500;
3746                         t[2] = eep->base_ext2.xatten1DBHigh[chain];
3747                         f[2] = 5785;
3748                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3749                                                             f, t, 3);
3750                         return value;
3751                 } else
3752                         return eep->modalHeader5G.xatten1DB[chain];
3753         }
3754
3755         return 0;
3756 }
3757
3758
3759 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3760                                             struct ath9k_channel *chan)
3761 {
3762         int f[3], t[3];
3763         u16 value;
3764         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3765
3766         if (chain >= 0 && chain < 3) {
3767                 if (IS_CHAN_2GHZ(chan))
3768                         return eep->modalHeader2G.xatten1Margin[chain];
3769                 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3770                         t[0] = eep->base_ext2.xatten1MarginLow[chain];
3771                         f[0] = 5180;
3772                         t[1] = eep->modalHeader5G.xatten1Margin[chain];
3773                         f[1] = 5500;
3774                         t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3775                         f[2] = 5785;
3776                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3777                                                             f, t, 3);
3778                         return value;
3779                 } else
3780                         return eep->modalHeader5G.xatten1Margin[chain];
3781         }
3782
3783         return 0;
3784 }
3785
3786 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3787 {
3788         int i;
3789         u16 value;
3790         unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3791                                           AR_PHY_EXT_ATTEN_CTL_1,
3792                                           AR_PHY_EXT_ATTEN_CTL_2,
3793                                          };
3794
3795         /* Test value. if 0 then attenuation is unused. Don't load anything. */
3796         for (i = 0; i < 3; i++) {
3797                 if (ah->txchainmask & BIT(i)) {
3798                         value = ar9003_hw_atten_chain_get(ah, i, chan);
3799                         REG_RMW_FIELD(ah, ext_atten_reg[i],
3800                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3801
3802                         value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3803                         REG_RMW_FIELD(ah, ext_atten_reg[i],
3804                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3805                                       value);
3806                 }
3807         }
3808 }
3809
3810 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3811 {
3812         int timeout = 100;
3813
3814         while (pmu_set != REG_READ(ah, pmu_reg)) {
3815                 if (timeout-- == 0)
3816                         return false;
3817                 REG_WRITE(ah, pmu_reg, pmu_set);
3818                 udelay(10);
3819         }
3820
3821         return true;
3822 }
3823
3824 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3825 {
3826         int internal_regulator =
3827                 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3828         u32 reg_val;
3829
3830         if (internal_regulator) {
3831                 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3832                         int reg_pmu_set;
3833
3834                         reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3835                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3836                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3837                                 return;
3838
3839                         if (AR_SREV_9330(ah)) {
3840                                 if (ah->is_clk_25mhz) {
3841                                         reg_pmu_set = (3 << 1) | (8 << 4) |
3842                                                       (3 << 8) | (1 << 14) |
3843                                                       (6 << 17) | (1 << 20) |
3844                                                       (3 << 24);
3845                                 } else {
3846                                         reg_pmu_set = (4 << 1)  | (7 << 4) |
3847                                                       (3 << 8)  | (1 << 14) |
3848                                                       (6 << 17) | (1 << 20) |
3849                                                       (3 << 24);
3850                                 }
3851                         } else {
3852                                 reg_pmu_set = (5 << 1) | (7 << 4) |
3853                                               (2 << 8) | (2 << 14) |
3854                                               (6 << 17) | (1 << 20) |
3855                                               (3 << 24) | (1 << 28);
3856                         }
3857
3858                         REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3859                         if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3860                                 return;
3861
3862                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3863                                         | (4 << 26);
3864                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3865                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3866                                 return;
3867
3868                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3869                                         | (1 << 21);
3870                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3871                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3872                                 return;
3873                 } else if (AR_SREV_9462(ah)) {
3874                         reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3875                         REG_WRITE(ah, AR_PHY_PMU1, reg_val);
3876                 } else {
3877                         /* Internal regulator is ON. Write swreg register. */
3878                         reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3879                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3880                                   REG_READ(ah, AR_RTC_REG_CONTROL1) &
3881                                   (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3882                         REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
3883                         /* Set REG_CONTROL1.SWREG_PROGRAM */
3884                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3885                                   REG_READ(ah,
3886                                            AR_RTC_REG_CONTROL1) |
3887                                            AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3888                 }
3889         } else {
3890                 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3891                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3892                         while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3893                                                 AR_PHY_PMU2_PGM))
3894                                 udelay(10);
3895
3896                         REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3897                         while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3898                                                 AR_PHY_PMU1_PWD))
3899                                 udelay(10);
3900                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3901                         while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3902                                                 AR_PHY_PMU2_PGM))
3903                                 udelay(10);
3904                 } else if (AR_SREV_9462(ah))
3905                         REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3906                 else {
3907                         reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
3908                                 AR_RTC_FORCE_SWREG_PRD;
3909                         REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val);
3910                 }
3911         }
3912
3913 }
3914
3915 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3916 {
3917         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3918         u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3919
3920         if (eep->baseEepHeader.featureEnable & 0x40) {
3921                 tuning_caps_param &= 0x7f;
3922                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3923                               tuning_caps_param);
3924                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3925                               tuning_caps_param);
3926         }
3927 }
3928
3929 static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
3930 {
3931         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3932         int quick_drop = ath9k_hw_ar9300_get_eeprom(ah, EEP_QUICK_DROP);
3933         s32 t[3], f[3] = {5180, 5500, 5785};
3934
3935         if (!quick_drop)
3936                 return;
3937
3938         if (freq < 4000)
3939                 quick_drop = eep->modalHeader2G.quick_drop;
3940         else {
3941                 t[0] = eep->base_ext1.quick_drop_low;
3942                 t[1] = eep->modalHeader5G.quick_drop;
3943                 t[2] = eep->base_ext1.quick_drop_high;
3944                 quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
3945         }
3946         REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
3947 }
3948
3949 static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, u16 freq)
3950 {
3951         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3952         u32 value;
3953
3954         value = (freq < 4000) ? eep->modalHeader2G.txEndToXpaOff :
3955                                 eep->modalHeader5G.txEndToXpaOff;
3956
3957         REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3958                       AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
3959         REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3960                       AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
3961 }
3962
3963 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3964                                              struct ath9k_channel *chan)
3965 {
3966         ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3967         ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3968         ar9003_hw_drive_strength_apply(ah);
3969         ar9003_hw_atten_apply(ah, chan);
3970         ar9003_hw_quick_drop_apply(ah, chan->channel);
3971         if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
3972                 ar9003_hw_internal_regulator_apply(ah);
3973         if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3974                 ar9003_hw_apply_tuning_caps(ah);
3975         ar9003_hw_txend_to_xpa_off_apply(ah, chan->channel);
3976 }
3977
3978 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3979                                       struct ath9k_channel *chan)
3980 {
3981 }
3982
3983 /*
3984  * Returns the interpolated y value corresponding to the specified x value
3985  * from the np ordered pairs of data (px,py).
3986  * The pairs do not have to be in any order.
3987  * If the specified x value is less than any of the px,
3988  * the returned y value is equal to the py for the lowest px.
3989  * If the specified x value is greater than any of the px,
3990  * the returned y value is equal to the py for the highest px.
3991  */
3992 static int ar9003_hw_power_interpolate(int32_t x,
3993                                        int32_t *px, int32_t *py, u_int16_t np)
3994 {
3995         int ip = 0;
3996         int lx = 0, ly = 0, lhave = 0;
3997         int hx = 0, hy = 0, hhave = 0;
3998         int dx = 0;
3999         int y = 0;
4000
4001         lhave = 0;
4002         hhave = 0;
4003
4004         /* identify best lower and higher x calibration measurement */
4005         for (ip = 0; ip < np; ip++) {
4006                 dx = x - px[ip];
4007
4008                 /* this measurement is higher than our desired x */
4009                 if (dx <= 0) {
4010                         if (!hhave || dx > (x - hx)) {
4011                                 /* new best higher x measurement */
4012                                 hx = px[ip];
4013                                 hy = py[ip];
4014                                 hhave = 1;
4015                         }
4016                 }
4017                 /* this measurement is lower than our desired x */
4018                 if (dx >= 0) {
4019                         if (!lhave || dx < (x - lx)) {
4020                                 /* new best lower x measurement */
4021                                 lx = px[ip];
4022                                 ly = py[ip];
4023                                 lhave = 1;
4024                         }
4025                 }
4026         }
4027
4028         /* the low x is good */
4029         if (lhave) {
4030                 /* so is the high x */
4031                 if (hhave) {
4032                         /* they're the same, so just pick one */
4033                         if (hx == lx)
4034                                 y = ly;
4035                         else    /* interpolate  */
4036                                 y = interpolate(x, lx, hx, ly, hy);
4037                 } else          /* only low is good, use it */
4038                         y = ly;
4039         } else if (hhave)       /* only high is good, use it */
4040                 y = hy;
4041         else /* nothing is good,this should never happen unless np=0, ???? */
4042                 y = -(1 << 30);
4043         return y;
4044 }
4045
4046 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4047                                        u16 rateIndex, u16 freq, bool is2GHz)
4048 {
4049         u16 numPiers, i;
4050         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4051         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4052         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4053         struct cal_tgt_pow_legacy *pEepromTargetPwr;
4054         u8 *pFreqBin;
4055
4056         if (is2GHz) {
4057                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4058                 pEepromTargetPwr = eep->calTargetPower2G;
4059                 pFreqBin = eep->calTarget_freqbin_2G;
4060         } else {
4061                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4062                 pEepromTargetPwr = eep->calTargetPower5G;
4063                 pFreqBin = eep->calTarget_freqbin_5G;
4064         }
4065
4066         /*
4067          * create array of channels and targetpower from
4068          * targetpower piers stored on eeprom
4069          */
4070         for (i = 0; i < numPiers; i++) {
4071                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4072                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4073         }
4074
4075         /* interpolate to get target power for given frequency */
4076         return (u8) ar9003_hw_power_interpolate((s32) freq,
4077                                                  freqArray,
4078                                                  targetPowerArray, numPiers);
4079 }
4080
4081 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4082                                             u16 rateIndex,
4083                                             u16 freq, bool is2GHz)
4084 {
4085         u16 numPiers, i;
4086         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4087         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4088         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4089         struct cal_tgt_pow_ht *pEepromTargetPwr;
4090         u8 *pFreqBin;
4091
4092         if (is2GHz) {
4093                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4094                 pEepromTargetPwr = eep->calTargetPower2GHT20;
4095                 pFreqBin = eep->calTarget_freqbin_2GHT20;
4096         } else {
4097                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4098                 pEepromTargetPwr = eep->calTargetPower5GHT20;
4099                 pFreqBin = eep->calTarget_freqbin_5GHT20;
4100         }
4101
4102         /*
4103          * create array of channels and targetpower
4104          * from targetpower piers stored on eeprom
4105          */
4106         for (i = 0; i < numPiers; i++) {
4107                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4108                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4109         }
4110
4111         /* interpolate to get target power for given frequency */
4112         return (u8) ar9003_hw_power_interpolate((s32) freq,
4113                                                  freqArray,
4114                                                  targetPowerArray, numPiers);
4115 }
4116
4117 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4118                                             u16 rateIndex,
4119                                             u16 freq, bool is2GHz)
4120 {
4121         u16 numPiers, i;
4122         s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4123         s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4124         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4125         struct cal_tgt_pow_ht *pEepromTargetPwr;
4126         u8 *pFreqBin;
4127
4128         if (is2GHz) {
4129                 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4130                 pEepromTargetPwr = eep->calTargetPower2GHT40;
4131                 pFreqBin = eep->calTarget_freqbin_2GHT40;
4132         } else {
4133                 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4134                 pEepromTargetPwr = eep->calTargetPower5GHT40;
4135                 pFreqBin = eep->calTarget_freqbin_5GHT40;
4136         }
4137
4138         /*
4139          * create array of channels and targetpower from
4140          * targetpower piers stored on eeprom
4141          */
4142         for (i = 0; i < numPiers; i++) {
4143                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4144                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4145         }
4146
4147         /* interpolate to get target power for given frequency */
4148         return (u8) ar9003_hw_power_interpolate((s32) freq,
4149                                                  freqArray,
4150                                                  targetPowerArray, numPiers);
4151 }
4152
4153 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4154                                            u16 rateIndex, u16 freq)
4155 {
4156         u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4157         s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4158         s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4159         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4160         struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4161         u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4162
4163         /*
4164          * create array of channels and targetpower from
4165          * targetpower piers stored on eeprom
4166          */
4167         for (i = 0; i < numPiers; i++) {
4168                 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
4169                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4170         }
4171
4172         /* interpolate to get target power for given frequency */
4173         return (u8) ar9003_hw_power_interpolate((s32) freq,
4174                                                  freqArray,
4175                                                  targetPowerArray, numPiers);
4176 }
4177
4178 /* Set tx power registers to array of values passed in */
4179 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4180 {
4181 #define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))
4182         /* make sure forced gain is not set */
4183         REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4184
4185         /* Write the OFDM power per rate set */
4186
4187         /* 6 (LSB), 9, 12, 18 (MSB) */
4188         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4189                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4190                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4191                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4192                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4193
4194         /* 24 (LSB), 36, 48, 54 (MSB) */
4195         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4196                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4197                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4198                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4199                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4200
4201         /* Write the CCK power per rate set */
4202
4203         /* 1L (LSB), reserved, 2L, 2S (MSB) */
4204         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4205                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4206                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4207                   /* POW_SM(txPowerTimes2,  8) | this is reserved for AR9003 */
4208                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4209
4210         /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4211         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4212                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4213                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4214                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4215                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4216             );
4217
4218         /* Write the power for duplicated frames - HT40 */
4219
4220         /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4221         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
4222                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4223                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4224                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24],  8) |
4225                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L],  0)
4226             );
4227
4228         /* Write the HT20 power per rate set */
4229
4230         /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4231         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4232                   POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4233                   POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4234                   POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4235                   POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4236             );
4237
4238         /* 6 (LSB), 7, 12, 13 (MSB) */
4239         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4240                   POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4241                   POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4242                   POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4243                   POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4244             );
4245
4246         /* 14 (LSB), 15, 20, 21 */
4247         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4248                   POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4249                   POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4250                   POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4251                   POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4252             );
4253
4254         /* Mixed HT20 and HT40 rates */
4255
4256         /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4257         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4258                   POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4259                   POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4260                   POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4261                   POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4262             );
4263
4264         /*
4265          * Write the HT40 power per rate set
4266          * correct PAR difference between HT40 and HT20/LEGACY
4267          * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4268          */
4269         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4270                   POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4271                   POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4272                   POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4273                   POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4274             );
4275
4276         /* 6 (LSB), 7, 12, 13 (MSB) */
4277         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4278                   POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4279                   POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4280                   POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4281                   POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4282             );
4283
4284         /* 14 (LSB), 15, 20, 21 */
4285         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4286                   POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4287                   POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4288                   POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4289                   POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4290             );
4291
4292         return 0;
4293 #undef POW_SM
4294 }
4295
4296 static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
4297                                               u8 *targetPowerValT2)
4298 {
4299         /* XXX: hard code for now, need to get from eeprom struct */
4300         u8 ht40PowerIncForPdadc = 0;
4301         bool is2GHz = false;
4302         unsigned int i = 0;
4303         struct ath_common *common = ath9k_hw_common(ah);
4304
4305         if (freq < 4000)
4306                 is2GHz = true;
4307
4308         targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4309             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4310                                          is2GHz);
4311         targetPowerValT2[ALL_TARGET_LEGACY_36] =
4312             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4313                                          is2GHz);
4314         targetPowerValT2[ALL_TARGET_LEGACY_48] =
4315             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4316                                          is2GHz);
4317         targetPowerValT2[ALL_TARGET_LEGACY_54] =
4318             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4319                                          is2GHz);
4320         targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4321             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4322                                              freq);
4323         targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4324             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4325         targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4326             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4327         targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4328             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4329         targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4330             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4331                                               is2GHz);
4332         targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4333             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4334                                               freq, is2GHz);
4335         targetPowerValT2[ALL_TARGET_HT20_4] =
4336             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4337                                               is2GHz);
4338         targetPowerValT2[ALL_TARGET_HT20_5] =
4339             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4340                                               is2GHz);
4341         targetPowerValT2[ALL_TARGET_HT20_6] =
4342             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4343                                               is2GHz);
4344         targetPowerValT2[ALL_TARGET_HT20_7] =
4345             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4346                                               is2GHz);
4347         targetPowerValT2[ALL_TARGET_HT20_12] =
4348             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4349                                               is2GHz);
4350         targetPowerValT2[ALL_TARGET_HT20_13] =
4351             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4352                                               is2GHz);
4353         targetPowerValT2[ALL_TARGET_HT20_14] =
4354             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4355                                               is2GHz);
4356         targetPowerValT2[ALL_TARGET_HT20_15] =
4357             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4358                                               is2GHz);
4359         targetPowerValT2[ALL_TARGET_HT20_20] =
4360             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4361                                               is2GHz);
4362         targetPowerValT2[ALL_TARGET_HT20_21] =
4363             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4364                                               is2GHz);
4365         targetPowerValT2[ALL_TARGET_HT20_22] =
4366             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4367                                               is2GHz);
4368         targetPowerValT2[ALL_TARGET_HT20_23] =
4369             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4370                                               is2GHz);
4371         targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4372             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4373                                               is2GHz) + ht40PowerIncForPdadc;
4374         targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4375             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4376                                               freq,
4377                                               is2GHz) + ht40PowerIncForPdadc;
4378         targetPowerValT2[ALL_TARGET_HT40_4] =
4379             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4380                                               is2GHz) + ht40PowerIncForPdadc;
4381         targetPowerValT2[ALL_TARGET_HT40_5] =
4382             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4383                                               is2GHz) + ht40PowerIncForPdadc;
4384         targetPowerValT2[ALL_TARGET_HT40_6] =
4385             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4386                                               is2GHz) + ht40PowerIncForPdadc;
4387         targetPowerValT2[ALL_TARGET_HT40_7] =
4388             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4389                                               is2GHz) + ht40PowerIncForPdadc;
4390         targetPowerValT2[ALL_TARGET_HT40_12] =
4391             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4392                                               is2GHz) + ht40PowerIncForPdadc;
4393         targetPowerValT2[ALL_TARGET_HT40_13] =
4394             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4395                                               is2GHz) + ht40PowerIncForPdadc;
4396         targetPowerValT2[ALL_TARGET_HT40_14] =
4397             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4398                                               is2GHz) + ht40PowerIncForPdadc;
4399         targetPowerValT2[ALL_TARGET_HT40_15] =
4400             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4401                                               is2GHz) + ht40PowerIncForPdadc;
4402         targetPowerValT2[ALL_TARGET_HT40_20] =
4403             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4404                                               is2GHz) + ht40PowerIncForPdadc;
4405         targetPowerValT2[ALL_TARGET_HT40_21] =
4406             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4407                                               is2GHz) + ht40PowerIncForPdadc;
4408         targetPowerValT2[ALL_TARGET_HT40_22] =
4409             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4410                                               is2GHz) + ht40PowerIncForPdadc;
4411         targetPowerValT2[ALL_TARGET_HT40_23] =
4412             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4413                                               is2GHz) + ht40PowerIncForPdadc;
4414
4415         for (i = 0; i < ar9300RateSize; i++) {
4416                 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
4417                         i, targetPowerValT2[i]);
4418         }
4419 }
4420
4421 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4422                                   int mode,
4423                                   int ipier,
4424                                   int ichain,
4425                                   int *pfrequency,
4426                                   int *pcorrection,
4427                                   int *ptemperature, int *pvoltage)
4428 {
4429         u8 *pCalPier;
4430         struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4431         int is2GHz;
4432         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4433         struct ath_common *common = ath9k_hw_common(ah);
4434
4435         if (ichain >= AR9300_MAX_CHAINS) {
4436                 ath_dbg(common, EEPROM,
4437                         "Invalid chain index, must be less than %d\n",
4438                         AR9300_MAX_CHAINS);
4439                 return -1;
4440         }
4441
4442         if (mode) {             /* 5GHz */
4443                 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4444                         ath_dbg(common, EEPROM,
4445                                 "Invalid 5GHz cal pier index, must be less than %d\n",
4446                                 AR9300_NUM_5G_CAL_PIERS);
4447                         return -1;
4448                 }
4449                 pCalPier = &(eep->calFreqPier5G[ipier]);
4450                 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4451                 is2GHz = 0;
4452         } else {
4453                 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4454                         ath_dbg(common, EEPROM,
4455                                 "Invalid 2GHz cal pier index, must be less than %d\n",
4456                                 AR9300_NUM_2G_CAL_PIERS);
4457                         return -1;
4458                 }
4459
4460                 pCalPier = &(eep->calFreqPier2G[ipier]);
4461                 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4462                 is2GHz = 1;
4463         }
4464
4465         *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4466         *pcorrection = pCalPierStruct->refPower;
4467         *ptemperature = pCalPierStruct->tempMeas;
4468         *pvoltage = pCalPierStruct->voltMeas;
4469
4470         return 0;
4471 }
4472
4473 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4474                                             int frequency,
4475                                             int *correction,
4476                                             int *voltage, int *temperature)
4477 {
4478         int tempSlope = 0;
4479         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4480         int f[3], t[3];
4481
4482         REG_RMW(ah, AR_PHY_TPC_11_B0,
4483                 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4484                 AR_PHY_TPC_OLPC_GAIN_DELTA);
4485         if (ah->caps.tx_chainmask & BIT(1))
4486                 REG_RMW(ah, AR_PHY_TPC_11_B1,
4487                         (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4488                         AR_PHY_TPC_OLPC_GAIN_DELTA);
4489         if (ah->caps.tx_chainmask & BIT(2))
4490                 REG_RMW(ah, AR_PHY_TPC_11_B2,
4491                         (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4492                         AR_PHY_TPC_OLPC_GAIN_DELTA);
4493
4494         /* enable open loop power control on chip */
4495         REG_RMW(ah, AR_PHY_TPC_6_B0,
4496                 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4497                 AR_PHY_TPC_6_ERROR_EST_MODE);
4498         if (ah->caps.tx_chainmask & BIT(1))
4499                 REG_RMW(ah, AR_PHY_TPC_6_B1,
4500                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4501                         AR_PHY_TPC_6_ERROR_EST_MODE);
4502         if (ah->caps.tx_chainmask & BIT(2))
4503                 REG_RMW(ah, AR_PHY_TPC_6_B2,
4504                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4505                         AR_PHY_TPC_6_ERROR_EST_MODE);
4506
4507         /*
4508          * enable temperature compensation
4509          * Need to use register names
4510          */
4511         if (frequency < 4000)
4512                 tempSlope = eep->modalHeader2G.tempSlope;
4513         else if (eep->base_ext2.tempSlopeLow != 0) {
4514                 t[0] = eep->base_ext2.tempSlopeLow;
4515                 f[0] = 5180;
4516                 t[1] = eep->modalHeader5G.tempSlope;
4517                 f[1] = 5500;
4518                 t[2] = eep->base_ext2.tempSlopeHigh;
4519                 f[2] = 5785;
4520                 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4521                                                         f, t, 3);
4522         } else
4523                 tempSlope = eep->modalHeader5G.tempSlope;
4524
4525         REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4526
4527         if (AR_SREV_9462_20(ah))
4528                 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4529                               AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
4530
4531
4532         REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4533                       temperature[0]);
4534
4535         return 0;
4536 }
4537
4538 /* Apply the recorded correction values. */
4539 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4540 {
4541         int ichain, ipier, npier;
4542         int mode;
4543         int lfrequency[AR9300_MAX_CHAINS],
4544             lcorrection[AR9300_MAX_CHAINS],
4545             ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4546         int hfrequency[AR9300_MAX_CHAINS],
4547             hcorrection[AR9300_MAX_CHAINS],
4548             htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4549         int fdiff;
4550         int correction[AR9300_MAX_CHAINS],
4551             voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4552         int pfrequency, pcorrection, ptemperature, pvoltage;
4553         struct ath_common *common = ath9k_hw_common(ah);
4554
4555         mode = (frequency >= 4000);
4556         if (mode)
4557                 npier = AR9300_NUM_5G_CAL_PIERS;
4558         else
4559                 npier = AR9300_NUM_2G_CAL_PIERS;
4560
4561         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4562                 lfrequency[ichain] = 0;
4563                 hfrequency[ichain] = 100000;
4564         }
4565         /* identify best lower and higher frequency calibration measurement */
4566         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4567                 for (ipier = 0; ipier < npier; ipier++) {
4568                         if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4569                                                     &pfrequency, &pcorrection,
4570                                                     &ptemperature, &pvoltage)) {
4571                                 fdiff = frequency - pfrequency;
4572
4573                                 /*
4574                                  * this measurement is higher than
4575                                  * our desired frequency
4576                                  */
4577                                 if (fdiff <= 0) {
4578                                         if (hfrequency[ichain] <= 0 ||
4579                                             hfrequency[ichain] >= 100000 ||
4580                                             fdiff >
4581                                             (frequency - hfrequency[ichain])) {
4582                                                 /*
4583                                                  * new best higher
4584                                                  * frequency measurement
4585                                                  */
4586                                                 hfrequency[ichain] = pfrequency;
4587                                                 hcorrection[ichain] =
4588                                                     pcorrection;
4589                                                 htemperature[ichain] =
4590                                                     ptemperature;
4591                                                 hvoltage[ichain] = pvoltage;
4592                                         }
4593                                 }
4594                                 if (fdiff >= 0) {
4595                                         if (lfrequency[ichain] <= 0
4596                                             || fdiff <
4597                                             (frequency - lfrequency[ichain])) {
4598                                                 /*
4599                                                  * new best lower
4600                                                  * frequency measurement
4601                                                  */
4602                                                 lfrequency[ichain] = pfrequency;
4603                                                 lcorrection[ichain] =
4604                                                     pcorrection;
4605                                                 ltemperature[ichain] =
4606                                                     ptemperature;
4607                                                 lvoltage[ichain] = pvoltage;
4608                                         }
4609                                 }
4610                         }
4611                 }
4612         }
4613
4614         /* interpolate  */
4615         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4616                 ath_dbg(common, EEPROM, "ch=%d f=%d low=%d %d h=%d %d\n",
4617                         ichain, frequency, lfrequency[ichain],
4618                         lcorrection[ichain], hfrequency[ichain],
4619                         hcorrection[ichain]);
4620                 /* they're the same, so just pick one */
4621                 if (hfrequency[ichain] == lfrequency[ichain]) {
4622                         correction[ichain] = lcorrection[ichain];
4623                         voltage[ichain] = lvoltage[ichain];
4624                         temperature[ichain] = ltemperature[ichain];
4625                 }
4626                 /* the low frequency is good */
4627                 else if (frequency - lfrequency[ichain] < 1000) {
4628                         /* so is the high frequency, interpolate */
4629                         if (hfrequency[ichain] - frequency < 1000) {
4630
4631                                 correction[ichain] = interpolate(frequency,
4632                                                 lfrequency[ichain],
4633                                                 hfrequency[ichain],
4634                                                 lcorrection[ichain],
4635                                                 hcorrection[ichain]);
4636
4637                                 temperature[ichain] = interpolate(frequency,
4638                                                 lfrequency[ichain],
4639                                                 hfrequency[ichain],
4640                                                 ltemperature[ichain],
4641                                                 htemperature[ichain]);
4642
4643                                 voltage[ichain] = interpolate(frequency,
4644                                                 lfrequency[ichain],
4645                                                 hfrequency[ichain],
4646                                                 lvoltage[ichain],
4647                                                 hvoltage[ichain]);
4648                         }
4649                         /* only low is good, use it */
4650                         else {
4651                                 correction[ichain] = lcorrection[ichain];
4652                                 temperature[ichain] = ltemperature[ichain];
4653                                 voltage[ichain] = lvoltage[ichain];
4654                         }
4655                 }
4656                 /* only high is good, use it */
4657                 else if (hfrequency[ichain] - frequency < 1000) {
4658                         correction[ichain] = hcorrection[ichain];
4659                         temperature[ichain] = htemperature[ichain];
4660                         voltage[ichain] = hvoltage[ichain];
4661                 } else {        /* nothing is good, presume 0???? */
4662                         correction[ichain] = 0;
4663                         temperature[ichain] = 0;
4664                         voltage[ichain] = 0;
4665                 }
4666         }
4667
4668         ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4669                                          temperature);
4670
4671         ath_dbg(common, EEPROM,
4672                 "for frequency=%d, calibration correction = %d %d %d\n",
4673                 frequency, correction[0], correction[1], correction[2]);
4674
4675         return 0;
4676 }
4677
4678 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4679                                            int idx,
4680                                            int edge,
4681                                            bool is2GHz)
4682 {
4683         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4684         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4685
4686         if (is2GHz)
4687                 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4688         else
4689                 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4690 }
4691
4692 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4693                                              int idx,
4694                                              unsigned int edge,
4695                                              u16 freq,
4696                                              bool is2GHz)
4697 {
4698         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4699         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4700
4701         u8 *ctl_freqbin = is2GHz ?
4702                 &eep->ctl_freqbin_2G[idx][0] :
4703                 &eep->ctl_freqbin_5G[idx][0];
4704
4705         if (is2GHz) {
4706                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4707                     CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4708                         return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4709         } else {
4710                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4711                     CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4712                         return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4713         }
4714
4715         return MAX_RATE_POWER;
4716 }
4717
4718 /*
4719  * Find the maximum conformance test limit for the given channel and CTL info
4720  */
4721 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4722                                         u16 freq, int idx, bool is2GHz)
4723 {
4724         u16 twiceMaxEdgePower = MAX_RATE_POWER;
4725         u8 *ctl_freqbin = is2GHz ?
4726                 &eep->ctl_freqbin_2G[idx][0] :
4727                 &eep->ctl_freqbin_5G[idx][0];
4728         u16 num_edges = is2GHz ?
4729                 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4730         unsigned int edge;
4731
4732         /* Get the edge power */
4733         for (edge = 0;
4734              (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4735              edge++) {
4736                 /*
4737                  * If there's an exact channel match or an inband flag set
4738                  * on the lower channel use the given rdEdgePower
4739                  */
4740                 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4741                         twiceMaxEdgePower =
4742                                 ar9003_hw_get_direct_edge_power(eep, idx,
4743                                                                 edge, is2GHz);
4744                         break;
4745                 } else if ((edge > 0) &&
4746                            (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4747                                                       is2GHz))) {
4748                         twiceMaxEdgePower =
4749                                 ar9003_hw_get_indirect_edge_power(eep, idx,
4750                                                                   edge, freq,
4751                                                                   is2GHz);
4752                         /*
4753                          * Leave loop - no more affecting edges possible in
4754                          * this monotonic increasing list
4755                          */
4756                         break;
4757                 }
4758         }
4759         return twiceMaxEdgePower;
4760 }
4761
4762 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4763                                                struct ath9k_channel *chan,
4764                                                u8 *pPwrArray, u16 cfgCtl,
4765                                                u8 antenna_reduction,
4766                                                u16 powerLimit)
4767 {
4768         struct ath_common *common = ath9k_hw_common(ah);
4769         struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4770         u16 twiceMaxEdgePower;
4771         int i;
4772         u16 scaledPower = 0, minCtlPower;
4773         static const u16 ctlModesFor11a[] = {
4774                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4775         };
4776         static const u16 ctlModesFor11g[] = {
4777                 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4778                 CTL_11G_EXT, CTL_2GHT40
4779         };
4780         u16 numCtlModes;
4781         const u16 *pCtlMode;
4782         u16 ctlMode, freq;
4783         struct chan_centers centers;
4784         u8 *ctlIndex;
4785         u8 ctlNum;
4786         u16 twiceMinEdgePower;
4787         bool is2ghz = IS_CHAN_2GHZ(chan);
4788
4789         ath9k_hw_get_channel_centers(ah, chan, &centers);
4790         scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
4791                                                 antenna_reduction);
4792
4793         /*
4794          * Get target powers from EEPROM - our baseline for TX Power
4795          */
4796         if (is2ghz) {
4797                 /* Setup for CTL modes */
4798                 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4799                 numCtlModes =
4800                         ARRAY_SIZE(ctlModesFor11g) -
4801                                    SUB_NUM_CTL_MODES_AT_2G_40;
4802                 pCtlMode = ctlModesFor11g;
4803                 if (IS_CHAN_HT40(chan))
4804                         /* All 2G CTL's */
4805                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4806         } else {
4807                 /* Setup for CTL modes */
4808                 /* CTL_11A, CTL_5GHT20 */
4809                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4810                                          SUB_NUM_CTL_MODES_AT_5G_40;
4811                 pCtlMode = ctlModesFor11a;
4812                 if (IS_CHAN_HT40(chan))
4813                         /* All 5G CTL's */
4814                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4815         }
4816
4817         /*
4818          * For MIMO, need to apply regulatory caps individually across
4819          * dynamically running modes: CCK, OFDM, HT20, HT40
4820          *
4821          * The outer loop walks through each possible applicable runtime mode.
4822          * The inner loop walks through each ctlIndex entry in EEPROM.
4823          * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4824          */
4825         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4826                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4827                         (pCtlMode[ctlMode] == CTL_2GHT40);
4828                 if (isHt40CtlMode)
4829                         freq = centers.synth_center;
4830                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4831                         freq = centers.ext_center;
4832                 else
4833                         freq = centers.ctl_center;
4834
4835                 ath_dbg(common, REGULATORY,
4836                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4837                         ctlMode, numCtlModes, isHt40CtlMode,
4838                         (pCtlMode[ctlMode] & EXT_ADDITIVE));
4839
4840                 /* walk through each CTL index stored in EEPROM */
4841                 if (is2ghz) {
4842                         ctlIndex = pEepData->ctlIndex_2G;
4843                         ctlNum = AR9300_NUM_CTLS_2G;
4844                 } else {
4845                         ctlIndex = pEepData->ctlIndex_5G;
4846                         ctlNum = AR9300_NUM_CTLS_5G;
4847                 }
4848
4849                 twiceMaxEdgePower = MAX_RATE_POWER;
4850                 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4851                         ath_dbg(common, REGULATORY,
4852                                 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4853                                 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4854                                 chan->channel);
4855
4856                                 /*
4857                                  * compare test group from regulatory
4858                                  * channel list with test mode from pCtlMode
4859                                  * list
4860                                  */
4861                                 if ((((cfgCtl & ~CTL_MODE_M) |
4862                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4863                                         ctlIndex[i]) ||
4864                                     (((cfgCtl & ~CTL_MODE_M) |
4865                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4866                                      ((ctlIndex[i] & CTL_MODE_M) |
4867                                        SD_NO_CTL))) {
4868                                         twiceMinEdgePower =
4869                                           ar9003_hw_get_max_edge_power(pEepData,
4870                                                                        freq, i,
4871                                                                        is2ghz);
4872
4873                                         if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4874                                                 /*
4875                                                  * Find the minimum of all CTL
4876                                                  * edge powers that apply to
4877                                                  * this channel
4878                                                  */
4879                                                 twiceMaxEdgePower =
4880                                                         min(twiceMaxEdgePower,
4881                                                             twiceMinEdgePower);
4882                                                 else {
4883                                                         /* specific */
4884                                                         twiceMaxEdgePower =
4885                                                           twiceMinEdgePower;
4886                                                         break;
4887                                                 }
4888                                 }
4889                         }
4890
4891                         minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4892
4893                         ath_dbg(common, REGULATORY,
4894                                 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4895                                 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4896                                 scaledPower, minCtlPower);
4897
4898                         /* Apply ctl mode to correct target power set */
4899                         switch (pCtlMode[ctlMode]) {
4900                         case CTL_11B:
4901                                 for (i = ALL_TARGET_LEGACY_1L_5L;
4902                                      i <= ALL_TARGET_LEGACY_11S; i++)
4903                                         pPwrArray[i] =
4904                                           (u8)min((u16)pPwrArray[i],
4905                                                   minCtlPower);
4906                                 break;
4907                         case CTL_11A:
4908                         case CTL_11G:
4909                                 for (i = ALL_TARGET_LEGACY_6_24;
4910                                      i <= ALL_TARGET_LEGACY_54; i++)
4911                                         pPwrArray[i] =
4912                                           (u8)min((u16)pPwrArray[i],
4913                                                   minCtlPower);
4914                                 break;
4915                         case CTL_5GHT20:
4916                         case CTL_2GHT20:
4917                                 for (i = ALL_TARGET_HT20_0_8_16;
4918                                      i <= ALL_TARGET_HT20_21; i++)
4919                                         pPwrArray[i] =
4920                                           (u8)min((u16)pPwrArray[i],
4921                                                   minCtlPower);
4922                                 pPwrArray[ALL_TARGET_HT20_22] =
4923                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4924                                           minCtlPower);
4925                                 pPwrArray[ALL_TARGET_HT20_23] =
4926                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4927                                            minCtlPower);
4928                                 break;
4929                         case CTL_5GHT40:
4930                         case CTL_2GHT40:
4931                                 for (i = ALL_TARGET_HT40_0_8_16;
4932                                      i <= ALL_TARGET_HT40_23; i++)
4933                                         pPwrArray[i] =
4934                                           (u8)min((u16)pPwrArray[i],
4935                                                   minCtlPower);
4936                                 break;
4937                         default:
4938                             break;
4939                         }
4940         } /* end ctl mode checking */
4941 }
4942
4943 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4944 {
4945         u8 mod_idx = mcs_idx % 8;
4946
4947         if (mod_idx <= 3)
4948                 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4949         else
4950                 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4951 }
4952
4953 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4954                                         struct ath9k_channel *chan, u16 cfgCtl,
4955                                         u8 twiceAntennaReduction,
4956                                         u8 powerLimit, bool test)
4957 {
4958         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4959         struct ath_common *common = ath9k_hw_common(ah);
4960         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4961         struct ar9300_modal_eep_header *modal_hdr;
4962         u8 targetPowerValT2[ar9300RateSize];
4963         u8 target_power_val_t2_eep[ar9300RateSize];
4964         unsigned int i = 0, paprd_scale_factor = 0;
4965         u8 pwr_idx, min_pwridx = 0;
4966
4967         ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
4968
4969         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4970                 if (IS_CHAN_2GHZ(chan))
4971                         modal_hdr = &eep->modalHeader2G;
4972                 else
4973                         modal_hdr = &eep->modalHeader5G;
4974
4975                 ah->paprd_ratemask =
4976                         le32_to_cpu(modal_hdr->papdRateMaskHt20) &
4977                         AR9300_PAPRD_RATE_MASK;
4978
4979                 ah->paprd_ratemask_ht40 =
4980                         le32_to_cpu(modal_hdr->papdRateMaskHt40) &
4981                         AR9300_PAPRD_RATE_MASK;
4982
4983                 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
4984                 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
4985                                                   ALL_TARGET_HT20_0_8_16;
4986
4987                 if (!ah->paprd_table_write_done) {
4988                         memcpy(target_power_val_t2_eep, targetPowerValT2,
4989                                sizeof(targetPowerValT2));
4990                         for (i = 0; i < 24; i++) {
4991                                 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
4992                                 if (ah->paprd_ratemask & (1 << i)) {
4993                                         if (targetPowerValT2[pwr_idx] &&
4994                                             targetPowerValT2[pwr_idx] ==
4995                                             target_power_val_t2_eep[pwr_idx])
4996                                                 targetPowerValT2[pwr_idx] -=
4997                                                         paprd_scale_factor;
4998                                 }
4999                         }
5000                 }
5001                 memcpy(target_power_val_t2_eep, targetPowerValT2,
5002                        sizeof(targetPowerValT2));
5003         }
5004
5005         ar9003_hw_set_power_per_rate_table(ah, chan,
5006                                            targetPowerValT2, cfgCtl,
5007                                            twiceAntennaReduction,
5008                                            powerLimit);
5009
5010         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5011                 for (i = 0; i < ar9300RateSize; i++) {
5012                         if ((ah->paprd_ratemask & (1 << i)) &&
5013                             (abs(targetPowerValT2[i] -
5014                                 target_power_val_t2_eep[i]) >
5015                             paprd_scale_factor)) {
5016                                 ah->paprd_ratemask &= ~(1 << i);
5017                                 ath_dbg(common, EEPROM,
5018                                         "paprd disabled for mcs %d\n", i);
5019                         }
5020                 }
5021         }
5022
5023         regulatory->max_power_level = 0;
5024         for (i = 0; i < ar9300RateSize; i++) {
5025                 if (targetPowerValT2[i] > regulatory->max_power_level)
5026                         regulatory->max_power_level = targetPowerValT2[i];
5027         }
5028
5029         ath9k_hw_update_regulatory_maxpower(ah);
5030
5031         if (test)
5032                 return;
5033
5034         for (i = 0; i < ar9300RateSize; i++) {
5035                 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
5036                         i, targetPowerValT2[i]);
5037         }
5038
5039         /* Write target power array to registers */
5040         ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
5041         ar9003_hw_calibration_apply(ah, chan->channel);
5042
5043         if (IS_CHAN_2GHZ(chan)) {
5044                 if (IS_CHAN_HT40(chan))
5045                         i = ALL_TARGET_HT40_0_8_16;
5046                 else
5047                         i = ALL_TARGET_HT20_0_8_16;
5048         } else {
5049                 if (IS_CHAN_HT40(chan))
5050                         i = ALL_TARGET_HT40_7;
5051                 else
5052                         i = ALL_TARGET_HT20_7;
5053         }
5054         ah->paprd_target_power = targetPowerValT2[i];
5055 }
5056
5057 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5058                                             u16 i, bool is2GHz)
5059 {
5060         return AR_NO_SPUR;
5061 }
5062
5063 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5064 {
5065         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5066
5067         return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5068 }
5069
5070 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5071 {
5072         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5073
5074         return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5075 }
5076
5077 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
5078 {
5079         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5080
5081         if (is_2ghz)
5082                 return eep->modalHeader2G.spurChans;
5083         else
5084                 return eep->modalHeader5G.spurChans;
5085 }
5086
5087 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5088                                            struct ath9k_channel *chan)
5089 {
5090         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5091
5092         if (IS_CHAN_2GHZ(chan))
5093                 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5094                           AR9300_PAPRD_SCALE_1);
5095         else {
5096                 if (chan->channel >= 5700)
5097                 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5098                           AR9300_PAPRD_SCALE_1);
5099                 else if (chan->channel >= 5400)
5100                         return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5101                                    AR9300_PAPRD_SCALE_2);
5102                 else
5103                         return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5104                                   AR9300_PAPRD_SCALE_1);
5105         }
5106 }
5107
5108 const struct eeprom_ops eep_ar9300_ops = {
5109         .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5110         .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5111         .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
5112         .dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
5113         .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5114         .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
5115         .set_board_values = ath9k_hw_ar9300_set_board_values,
5116         .set_addac = ath9k_hw_ar9300_set_addac,
5117         .set_txpower = ath9k_hw_ar9300_set_txpower,
5118         .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
5119 };